Verification apparatus, verification system, verification method, and verification program

Abstract

To detect an abnormal operation of a preceding test instruction without significantly increasing test execution time in a random test of a system including a processor.SOLUTION: A verification apparatus includes: an acquisition unit which acquires a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor; a detection unit which detects, in the test instruction sequence, a to-be-saved instruction, which is a preceding test instruction for a storage region which has been updated by the preceding test instruction and is to be updated by a subsequent test instruction without being referred to; an execution unit which causes the system to sequentially execute the test instruction sequence; and a verification unit which verifies the result executed by the system. The result of executing the to-be-saved instruction by the system is stored, before the system executes a test instruction next to the to-be-saved instruction executed by the system, in result storage means which stores the results of executing the to-be-saved instruction. The verification unit verifies the storage region updated by the test instruction sequence and the result storage means.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a verification device, a verification system, a verification method, and a verification program. [Background technology]

[0002] In recent years, the increasing integration density of LSIs (Large Scale Integration) has led to higher LSI manufacturing costs. Furthermore, manufacturing lead times have also become longer. Under these circumstances, poor quality LSIs can lead to increased rework costs and longer manufacturing TAT (Turn Around Time). For this reason, it is becoming increasingly important to improve LSI quality before manufacturing.

[0003] Random testing is known as a method for ensuring the quality of LSIs, etc. Random testing is a method for detecting illegal behavior by having a system including a processor execute a randomly generated test instruction sequence. Detection of illegal behavior in random testing is determined by the result of executing the test instruction sequence to the end.

[0004] However, in a typical random test, the sequence of test instructions is determined randomly. Therefore, the execution result of a preceding test instruction may be overwritten by a subsequent test instruction without being referenced. In such a case, even if a preceding test instruction causes an illegal operation, the illegal operation is hidden by the subsequent test instruction. Thus, a typical random test may not be able to detect an illegal operation caused by a preceding test instruction.

[0005] In contrast, the method described in Patent Document 1 detects a test instruction that overwrites the execution result of a preceding test instruction without referencing the execution result of the preceding test instruction as a checkpoint, executes the test instruction sequence from the beginning to just before the checkpoint, and verifies the execution result. In the method described in Patent Document 1, the execution result is verified before the unreferenced data is overwritten, so that it is possible to detect incorrect behavior caused by a preceding test instruction without compromising the randomness of the test. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6900661 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the method described in Patent Document 1, the test instruction sequence from the beginning to just before the checkpoint is executed, the execution result is verified, and then the test instruction sequence from the beginning to just before the checkpoint is executed and the execution result is verified. In this method, the test instructions from the beginning to just before the checkpoint are executed multiple times. Therefore, in this method, the execution time of the test becomes longer than when the test instructions from the beginning to the end of the test instruction sequence are executed once each. Furthermore, in this method, the execution time of the test becomes longer as the number of checkpoints increases. Also, in this method, if a test is to be performed in the same time as when the test instructions from the beginning to the end of the test instruction sequence are executed once each, the number of test instructions that can be executed becomes smaller. If the number of test instructions becomes smaller, the quality of the system under test may be affected.

[0008] In consideration of the above-mentioned problems, an object of the present disclosure is to provide a verification device, a verification system, a verification method, and a verification program that enable detection of unauthorized operation of a preceding test instruction in random testing of a system including a processor without significantly increasing the execution time of the test. [Means for solving the problem]

[0009] In one aspect of the present disclosure, a verification device includes an acquisition unit that acquires a test instruction sequence, which is a sequence of test instructions to be executed by a system including a processor, a detection unit that detects a to-be-saved instruction that is a preceding test instruction in the test instruction sequence when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without referencing it, an execution unit that causes the system to execute the test instruction sequence sequentially, and a verification unit that verifies the execution results by the system, wherein the execution results of the to-be-saved instructions by the system are stored in a result storage means that stores the execution results of the to-be-saved instructions before a test instruction next to the to-be-saved instructions executed by the system is executed by the system, and the verification unit performs the verification on the memory area updated by the test instruction sequence and the result storage means.

[0010] In another aspect of the present disclosure, a verification method is a verification method by a verification device, which obtains a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor, detects a save target instruction in the test instruction sequence which is a preceding test instruction when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without referencing it, has the system execute the test instruction sequence sequentially, and verifies the execution results by the system, and the execution results of the save target instructions by the system are stored in a result storage means which stores the execution results of the save target instructions before a test instruction next to the save target instruction executed by the system is executed by the system, and the verification device performs the verification on the memory area updated by the test instruction sequence and the result storage means.

[0011] In another aspect of the present disclosure, the verification program causes a computer to realize an acquisition function for acquiring a test instruction sequence, which is a sequence of test instructions to be executed by a system including a processor, a detection function for detecting a save target instruction, which is a preceding test instruction in the test instruction sequence, when a memory area updated by the preceding test instruction is updated by a subsequent test instruction without referencing it, an execution function for causing the system to execute the test instruction sequence sequentially, and a verification function for verifying the execution results by the system, wherein the execution results of the save target instructions by the system are stored in a result storage means that stores the execution results of the save target instructions before the next test instruction after the save target instruction executed by the system is executed by the system, and the verification function performs the verification on the memory area updated by the test instruction sequence and the result storage means. Effect of the Invention

[0012] According to the present disclosure, in random testing of a system including a processor, it is possible to detect incorrect operations of a preceding test instruction without significantly increasing the execution time of the test. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a verification device according to the present disclosure. [Diagram 2] FIG. 13 is a diagram illustrating an example of an operation flow of a verification device according to the present disclosure. [Diagram 3] FIG. 2 illustrates an example of a device that can be connected to a verification device of the present disclosure. [Figure 4] FIG. 1 is a diagram illustrating an example of the configuration of a system that is the subject of verification of the present disclosure. [Diagram 5] FIG. 2 is a diagram illustrating an example of the configuration of a verification device according to the present disclosure. [Figure 6] FIG. 13 is a diagram illustrating an example of a test instruction sequence. [Figure 7] FIG. 13 is a diagram illustrating an example of an update list. [Figure 8] FIG. 13 is a diagram illustrating an example of an update list. [Figure 9]FIG. 13 is a diagram illustrating an example of a list of instructions to be saved. [Figure 10] FIG. 13 is a diagram showing an example of information stored in a result storage means. [Figure 11] FIG. 13 is a diagram showing an example of a format of a test command. [Figure 12] FIG. 11 is a diagram illustrating an example of an operation flow of a detection unit. [Figure 13] FIG. 13 is a diagram illustrating an example of an operational flow of the verification device according to the present disclosure with respect to storing execution results. [Figure 14] FIG. 13 is a diagram illustrating an example of an operational flow of the verification device according to the present disclosure with respect to storing execution results. [Figure 15] FIG. 13 is a diagram illustrating an example of an operational flow of the verification device according to the present disclosure with respect to storing execution results. [Figure 16] FIG. 13 is a diagram illustrating an example of an operational flow of the verification device according to the present disclosure with respect to storing execution results. [Figure 17] FIG. 2 is a diagram illustrating an example of a hardware configuration according to each embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] [First embodiment] A first embodiment of the present disclosure will be described.

[0015] A specific example of the verification device 10 in the first embodiment is a verification device 20 in a second embodiment described later.

[0016] First, a description will be given of an example of the configuration of the verification device 10. Fig. 1 shows an example of the configuration of the verification device 10. The verification device 10 includes an acquisition unit 11, a detection unit 12, an execution unit 13, and a verification unit 14.

[0017] The acquiring unit 11 acquires a test instruction sequence. The test instruction sequence is a sequence of test instructions to be executed by a system including a processor.

[0018] The detection unit 12 detects a save target instruction. The save target instruction is a preceding test instruction in a test instruction sequence in which a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced.

[0019] The execution unit 13 causes the system to execute the test instruction sequence in sequence. The execution results of the save target instructions by the system are stored in the result storage means before the system executes the test instruction next to the save target instruction executed by the system. The result storage means stores the execution results of the save target instructions.

[0020] The verification unit 14 verifies the results of execution by the system. The verification unit 14 verifies the storage area updated by the test instruction sequence and the result storage means.

[0021] Next, a description will be given of an example of the operation flow of the verification device 10. An example of the operation flow of the verification device 10 is shown in FIG.

[0022] The acquiring unit 11 acquires a test instruction sequence (step S101). The test instruction sequence is a sequence of test instructions to be executed by a system including a processor.

[0023] The detection unit 12 detects a save target instruction (step S102). The save target instruction is a preceding test instruction in a test instruction sequence when a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced.

[0024] The execution unit 13 causes the system to execute the test instruction sequence in sequence (step S103). The execution results of the save target instructions by the system are stored in the result storage means before the system executes a test instruction next to the save target instruction executed by the system.

[0025] The verification unit 14 verifies the execution results by the system (step S104). The verification unit 14 verifies the storage area updated by the test instruction sequence and the result storage means.

[0026] As described above, in the first embodiment of the present disclosure, the verification device 10 includes an acquisition unit 11, a detection unit 12, an execution unit 13, and a verification unit 14. The acquisition unit 11 acquires a test instruction sequence. The test instruction sequence is a sequence of test instructions to be executed by a system including a processor. The detection unit 12 detects a save target instruction. The save target instruction is a preceding test instruction in the test instruction sequence when a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced. The execution unit 13 causes the system to execute the test instruction sequence sequentially. The execution result of the save target instruction by the system is stored in the result storage means before the system executes the test instruction next to the save target instruction executed by the system. The result storage means stores the execution result of the save target instruction. The verification unit 14 verifies the execution result by the system. The verification unit 14 performs verification on the memory area updated by the test instruction sequence and the result storage means.

[0027] This allows the verification device 10 to verify the execution result of a preceding test instruction when a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced. Also, the verification device 10 can realize a test by having the system execute each test instruction in the test instruction sequence once. Therefore, in a random test of a system including a processor, it becomes possible to detect an incorrect operation of a preceding test instruction without significantly increasing the execution time of the test.

[0028] [Second embodiment] Next, a description will be given of the verification device 20 according to the second embodiment of the present disclosure. Note that a specific example of the verification device 10 according to the first embodiment is the verification device 20 according to the second embodiment.

[0029] First, FIG. 3 shows an example of devices connected to the verification device 20. The verification device 20 and the system 50 are connected to each other. The system 50 is a system to be verified. The verification device 20 verifies the system 50. The verification device 20 and the result storage means 30 are also connected to each other. The result storage means 30 may be included in the verification device 20. The result storage means 30 may be included in the system 50. The verification device 20 may be included in the system 50. The result storage means 30 will be described later.

[0030] 4 shows an example of the configuration of a system 50. The system 50 includes at least a processor 51. In the example of FIG. 4, the system 50 also includes a register 52 and a memory 53. In this embodiment, the processor 51 executes a test command specified by the verification device 20, and stores the execution result of the test command in the register 52 or the memory 53.

[0031] 5 shows an example of the configuration of the verification device 20. The verification device includes an acquisition unit 21, a detection unit 22, an execution unit 23, and a verification unit 24.

[0032] The acquiring unit 21 acquires a test instruction sequence. The test instruction sequence is a sequence of test instructions to be executed by the system 50. The test instruction sequence is preferably generated randomly. Specifically, in the test instruction sequence, test instructions, the type of which and the allocation of memory areas accessed by the instructions are randomly selected, are arranged in a randomly determined order. For example, the memory areas accessed by the test instructions are selected and allocated from either or both of the register 52 and the memory 53.

[0033] The acquiring unit 21 also stores the acquired test instruction sequence in a storage means (not shown) inside or outside the verification device 20. The storage means in which the acquiring unit 21 stores the test instruction sequence may be the memory 53. For example, the acquiring unit 21 may acquire the test instruction sequence by generating a test instruction sequence, and store the acquired test instruction sequence in the storage means. Alternatively, the acquiring unit 21 may acquire information indicating a position on the storage means where a test instruction sequence generated by an external test instruction sequence generation program or the like is stored.

[0034] An example of a test instruction string is shown in Figure 6. This test instruction string consists of 10 test instructions. Each test instruction is assigned identification information C1 to C10, starting from the top. The instruction address written on the line of each test instruction indicates the address in the storage means where that test instruction is stored. The operation is a simplified representation of the behavior of each test instruction.

[0035] Each test command is a command to write a value read from an assigned memory area, or a result of performing arithmetic operations on the read value, to the assigned memory area. Here, there are eight registers 52 to be allocated, and REG#n (n is an integer from 0 to 7) represents the value of the nth register 52. Also, MEM(x) represents the value of address x in memory 53. Here, the size of the value stored in each register 52 and the size of the value accessed by MEM(x) are assumed to be equal, for example, 8 bytes. Also, "<-" represents a command to update the memory area on the left side with the value on the right side. Also, "+", "-", "*", and "÷" represent addition, subtraction, multiplication, and division, respectively.

[0036] The detection unit 22 detects a save target instruction from the test instruction sequence. The save target instruction is a test instruction whose execution result is to be saved in the result storage means 30. The detection unit 22 detects, as a save target instruction, a preceding test instruction in which a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced. The method of detecting a save target instruction will be described later.

[0037] The execution unit 23 causes the system 50 to sequentially execute the test instruction sequence. Furthermore, the execution results of the save target instruction by the system 50 are stored in the result storage means 30 before the system 50 executes the test instruction next to the save target instruction executed by the system 50. The result storage means stores the execution results of the save target instruction. The execution results may be, for example, values ​​stored in a storage area accessed by the test instruction.

[0038] The verification unit 24 verifies the execution results of the system 50. The verification unit 24 performs verification on the storage area updated by the test instruction sequence. The verification unit 24 also performs verification on the result storage means 30.

[0039] In this manner, in this embodiment, the execution result of the save target instruction is stored in the result storage means 30, and the verification unit 24 verifies the execution result stored in the result storage means 30. The execution result stored in the result storage means 30 is the execution result of the preceding test instruction (the save target instruction) in the case where the memory area updated by the preceding test instruction is updated by the subsequent test instruction without being referenced. In other words, the execution result of the preceding test instruction in the case where the memory area updated by the preceding test instruction is updated by the subsequent test instruction without being referenced is saved in the result storage means 30. Therefore, in this embodiment, it is possible to verify the execution result of the preceding test instruction in the case where the memory area updated by the preceding test instruction is updated by the subsequent test instruction without being referenced.

[0040] Specifically, the verification unit 24 performs verification by comparing the execution result with an expected value. Note that the expected value expected as the execution result of the test instruction sequence may be calculated in advance based on the test instruction sequence. If the value stored in the memory area to be accessed by the test instruction as the execution result of the test instruction sequence is not the expected value, it is detected that an incorrect operation may have occurred due to the preceding test instruction.

[0041] Furthermore, the expected value expected as the execution result of the save target instruction may be calculated in advance based on the test instruction sequence. In this case, since it is not clear which test instruction is the save target instruction until the detection unit 22 detects the save target instruction, the expected value of the execution result of each test instruction included in the test instruction sequence may be calculated in advance.

[0042] Furthermore, the expected value of the execution result of the save target instruction may be generated by a software simulator or the like based on the detection result of the save target instruction by the detection unit 22. In this case, for example, the detection unit 22 or the execution unit 23 may input the test instruction sequence and the save target instruction list to a software simulator inside or outside the verification device 20. Then, the software simulator may output the expected value of the execution result of the test instruction sequence and the save target instruction.

[0043] Furthermore, the verification unit 24 may output an error if the execution result does not match the expected value as a result of the verification.

[0044] Next, a description will be given of an example of a method for detecting save target instructions by the detection unit 22. The detection unit 22 generates a save target instruction list. The save target instruction list is a list of save target instructions detected from the test instruction sequence.

[0045] In the process of generating the list of instructions to be saved, the detection unit 22 uses, for example, an update list. The update list is a list of memory areas that have been updated before the execution of a certain test instruction and that have not been referenced and have not been saved. The update list also includes identification information of the memory area and identification information of the test instruction that has updated the memory area. At the start of detection of instructions to be saved, no information is stored in the update list and the list of instructions to be saved.

[0046] Here, saving refers to storing values ​​in the result storage means 30. A memory area targeted for saving is a memory area for which the test instruction that updated the memory area has been added to the list of instructions to be saved. In other words, a memory area not targeted for saving is a memory area for which the test instruction that updated the memory area has not been added to the list of instructions to be saved. Also, a memory area that remains in the update list is a memory area that is not targeted for saving and may be overwritten by a subsequent test instruction without being referenced.

[0047] The detection unit 22 reads one test command in sequence from the beginning of the test command string. Then, the detection unit 22 judges whether or not the identification information of the storage area referenced by this test command is already stored in the update list. If the corresponding identification information is already stored, the detection unit 22 deletes the identification information of the corresponding storage area from the update list. As a result, the identification information of the storage area referenced by the test command is deleted from the update list.

[0048] Furthermore, the detection unit 22 judges whether the identification information of the storage area to be updated by this test command is already stored in the update list. If the identification information of the storage area to be updated by this test command is not stored in the update list, the detection unit 22 adds the identification information to be updated by this test command and the identification information of this test command to the update list. As a result, the identification information of the storage area to be updated by the test command is added to the update list.

[0049] If the identification information of the memory area to be updated by this test instruction is already stored in the update list, the memory area to be updated by this test instruction is updated without being referenced. In other words, the preceding test instruction that updates the memory area to be updated by this test instruction is the save target instruction. Therefore, the detection unit 22 adds information of the (preceding) test instruction whose identification information is stored in the update list in association with the memory area to be updated by this test instruction to the save target instruction list. Furthermore, the detection unit 22 adds the identification information of the memory area to be updated by this test instruction and the identification information of this test instruction to the update list. Furthermore, the detection unit 22 deletes from the update list the identification information of the memory area associated with the test instruction added to the save target instruction list. As a result, the update list contains the identification information of the memory area that is not updated by the save target instruction and is not referenced.

[0050] Examples of update lists are shown in Figures 7 and 8. The update lists shown in Figures 7 and 8 are examples of the case where instructions to be saved are detected from the test instruction sequence shown in Figure 6. Figure 7 is an example of an update list reflecting each of instructions C1 to C6 from the test instruction sequence shown in Figure 6. Also, Figure 8 is an example of an update list reflecting each of instructions C7 to C10.

[0051] First, the detection unit 22 reads the command C1. Then, the detection unit 22 judges whether or not the identification information "MEM (0x20000)" of the memory area referenced by the command C1 is already stored in the update list. Since the identification information "MEM (0x20000)" of the memory area is not stored in the update list, the detection unit 22 then judges whether or not the identification information "REG#0" of the memory area to be updated by the command C1 is already stored in the update list. Since the identification information "REG#0" of the memory area is not stored in the update list, the detection unit 22 adds the identification information "REG#0" of the memory area to the update list. Furthermore, the detection unit 22 stores the identification information "C1" of the command C1 in the update list in association with the identification information "REG#0" of the memory area.

[0052] Next, the detection unit 22 reads the command C2, and similarly stores the identification information "REG#3" of the storage area updated by the command C2 and the identification information "C2" of the command C2 in the update list.

[0053] Furthermore, the detection unit 22 reads the command C3, and similarly stores the identification information "MEM(0x20100)" of the memory area updated by the command C3 and the identification information "C3" of the command C3 in the update list.

[0054] Next, the detection unit 22 reads the instruction C4. Then, the detection unit 22 judges whether or not the identification information "REG#3" of the memory area referenced by the instruction C4 is already stored in the update list. Since the identification information "REG#3" of the memory area is already stored in the update list, the detection unit 22 deletes the identification information "REG#3" of the memory area and the identification information "C2" of the instruction associated therewith from the update list. Furthermore, the detection unit 22 judges whether or not the identification information "REG#0" of the memory area referenced by the instruction C4 is already stored in the update list. Since the identification information "REG#0" of the memory area is already stored in the update list, the detection unit 22 deletes the identification information "REG#0" of the memory area and the identification information "C1" of the instruction associated therewith from the update list.

[0055] Next, the detection unit 22 determines whether the identification information "REG#4" of the memory area to be updated by the command C4 is stored in the update list. Since the identification information "REG#4" of the memory area is not stored in the update list, the detection unit 22 adds the identification information "REG#4" of the memory area to the update list. The detection unit 22 also stores the identification information "C4" of the command C4 in the update list in association with the identification information "REG#4" of the memory area.

[0056] Next, the detection unit 22 similarly updates the update list for the instructions C5 and C6.

[0057] Next, the detection unit 22 reads the command C7. Since the identification information "REG#5" of the memory area referenced by the command C7 is not stored in the update list, the detection unit 22 next judges whether the identification information "MEM(0x20100)" of the memory area to be updated by the command C7 is stored in the update list. The identification information "MEM(0x20100)" of the memory area is already stored in the update list. Since the identification information "MEM(0x20100)" of the test command is associated with the identification information "C3" of the test command, the detection unit 22 adds the information of the command C3 to the list of commands to be saved. Then, the detection unit 22 deletes the identification information "MEM(0x20100)" of the memory area associated with the identification information "C3" of the test command from the update list. Furthermore, the detection unit 22 adds the identification information "MEM(0x20100)" of the memory area to the update list in association with the identification information "C7" of the command C7.

[0058] Next, the detection unit 22 reads the instruction C8. Since the identification information "REG#2" and "REG#0" of the storage areas referenced by the instruction C8 are not stored in the update list, the detection unit 22 next determines whether or not the identification information "REG#7" of the storage area to be updated by the instruction C8 is stored in the update list. Since the identification information "REG#7" of the storage area is not stored in the update list, the detection unit 22 adds the identification information "REG#7" of the storage area to the update list. Also, the detection unit 22 stores the identification information "C8" of the instruction C8 in the update list.

[0059] Next, the detection unit 22 reads the instruction C9. Since the identification information "MEM (0x20020)" of the memory area referenced by the instruction C9 is not stored in the update list, the detection unit 22 next determines whether or not the identification information "REG#4" of the memory area to be updated by the instruction C9 is stored in the update list. The identification information "REG#4" of the memory area is already stored in the update list. Since the identification information "REG#4" already stored is associated with the identification information "C4" of the test instruction, the detection unit 22 adds the information of the instruction C4 to the list of instructions to be saved. Then, the detection unit 22 deletes the identification information "REG#4" of the memory area associated with the identification information "C4" of the instruction C4. Furthermore, the detection unit 22 adds the identification information "REG#4" of the memory area to the update list in association with the identification information "C9" of the instruction C9.

[0060] Next, the detection unit 22 reads the instruction C10. Since the identification information "REG#7" of the memory area referenced by the instruction C10 is already stored in the update list, the detection unit 22 deletes the identification information "REG#7" of the memory area and the identification information "C8" of the instruction associated therewith from the update list.

[0061] Next, the detection unit 22 determines whether the identification information "MEM(0x20050)" of the memory area to be updated by the command C10 is stored in the update list. Since the identification information "MEM(0x20050)" of the memory area is not stored in the update list, the detection unit 22 adds the identification information "MEM(0x20050)" of the memory area to the update list. The detection unit 22 also stores the identification information "C10" of the command C10 in the update list, in association with the identification information "MEM(0x20050)" of the memory area.

[0062] Then, since the instruction C10 is the last instruction in the test instruction sequence, the detection unit 22 ends the detection of instructions to be saved.

[0063] An example of the generated save target instruction list is shown in Fig. 9. In the example of Fig. 9, the save target instruction list includes identification information of the save target instructions. The save target instruction list may also include identification information of a memory area to be updated with the save target instructions. The save target instruction list may also include information of the instruction addresses of the save target instructions. The pointer is information indicating an area on the result storage means 30 where the execution result of the corresponding test instruction is stored.

[0064] 6, a list of instructions to be saved is generated, including information on instructions C3 and C4. The execution results of instructions C3 and C4 by system 50 are stored in result storage means 30.

[0065] 10 shows an example of information stored in the result storage means 30. The information stored in the result storage means 30 is called save information. The save information includes the execution results of the save target instructions by the system 50. The save information may also include the type of memory area (register or memory) updated by the save target instructions and identification information of the memory area updated by the save target instructions. The correspondence between each execution result and the save target instructions may be indicated by a pointer.

[0066] Next, an example of a method for storing the execution result (saving information) of the saving test command in the result storage means 30 will be described.

[0067] For example, the execution result of the save target instruction may be stored in the memory area and the result storage means 30 by the processor 51 included in the system 50. For example, when the test instruction to be executed by the system 50 is an instruction to be saved, the execution unit 23 may cause the system 50 to execute a test instruction having a value in a test bit indicating that the test instruction is an instruction to be saved. The test bit is included in the test instruction and indicates whether the test instruction is an instruction to be saved. When a value indicative of the test instruction to be executed is stored in the test bit of the test instruction, the system 50 stores the execution result of the test instruction in the memory area and the result storage means 30.

[0068] FIG. 11 shows an example of the format of a test command. In the example shown in FIG. 11, the test command is 32-bit data. The eighth bit is a test bit. For example, an unused area in the format of the test command may be defined as the test bit. In the example shown in FIG. 11, if the test command is a command to be saved, "1" is stored in the test bit. If the test command is not a command to be saved, the test bit is "0". The value is stored in the test bit by the detection unit 22 or the execution unit 23. For example, after detecting the command to be saved, the detection unit 22 rewrites the test bit of the command to be saved in the test command sequence stored in the storage means to "1". Alternatively, the execution unit 23 rewrites the test bit of the command to be saved to "1" before causing the system 50 to execute the command to be saved, and causes the system 50 to execute the command.

[0069] Furthermore, the execution unit 23 may receive the execution result of the command to be saved from the system 50 and store the received execution result in the result storage means 30 .

[0070] In this case, for example, when the test instruction to be executed by the system 50 is an instruction to be saved, the execution unit 23 may cause the system 50 to execute a test instruction having a value indicating that the test instruction is an instruction to be saved stored in the test bit. Then, when a value indicating that the test instruction is an instruction to be saved is stored in the test bit of the test instruction instructed to be executed, the system 50 transmits the execution result of the test instruction to the verification device 20.

[0071] Furthermore, for example, when the execution unit 23 causes the system 50 to execute the command to be saved, the execution unit 23 may read the execution result of the system 50 from the storage area and store the read execution result in the result storage means 30. In this case, the system 50 stores the execution result of the test command that has been instructed to be executed in the storage area.

[0072] In this way, the execution result of the save target instruction by the system 50 is stored in the result storage means 30 before the system 50 executes the test instruction next to the save target instruction executed by the system 50 .

[0073] Next, an example of the operation flow of the verification device 20 will be described with reference to FIG.

[0074] The acquiring unit 21 acquires a test instruction sequence to be executed by the system 50 including the processor 51 (step S101).

[0075] The detection unit 22 detects a save target instruction in the test instruction sequence (step S102). The save target instruction is a preceding test instruction in the case where a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced.

[0076] The execution unit 23 causes the system 50 to sequentially execute the test instruction sequence (step S103). The execution results of the save target instruction by the system 50 are stored in the result storage means 30, which stores the execution results of the save target instruction, before the system 50 executes the test instruction next to the save target instruction executed by the system 50.

[0077] The verification unit 24 verifies the execution result by the system 50 (step S104). The verification unit 24 verifies the storage area updated by the test instruction sequence and the result storage means 30.

[0078] Next, an example of the operation flow of the detection unit 22 in step S102 will be described.

[0079] The detection unit 22 reads one test instruction in sequence from the top of the test instruction string (step S201). Then, the detection unit 22 judges whether or not the identification information of the storage area referenced by this test instruction has already been stored in the update list (step S202). If the corresponding identification information has already been stored (YES in step S202), the detection unit 22 deletes the identification information of the corresponding storage area from the update list (step S203). As a result, the identification information of the storage area referenced by the test instruction is deleted from the update list.

[0080] Furthermore, the detection unit 22 judges whether the identification information of the storage area to be updated by this test command is already stored in the update list (step S204). If the identification information of the storage area to be updated by this test command is not stored in the update list (NO in step S204), the detection unit 22 adds the identification information to be updated by this test command and the identification information of this test command to the update list (step S206). As a result, the identification information of the storage area to be updated by the test command is added to the update list.

[0081] If the identification information of the memory area to be updated by this test instruction is already stored in the update list (YES in step S204), the memory area to be updated by this test instruction is updated without being referenced. In other words, the preceding test instruction that updates the memory area to be updated by this test instruction is the save target instruction. Therefore, the detection unit 22 adds information of the (preceding) test instruction whose identification information is stored in association with the memory area to be updated by this test instruction to the save target instruction list (step S205). The detection unit 22 also adds the identification information of the memory area to be updated by this test instruction and the identification information of this test instruction to the update list (step S206). The detection unit 22 also deletes from the update list the identification information of the memory area associated with the test instruction added to the save target instruction list (step S205). As a result, the update list contains the identification information of the memory area that is not updated by the save target instruction and is not referenced.

[0082] When the detection unit 22 performs the operations from step S201 to step S206 up to the last test instruction (YES in step S207), it ends the detection operation for the instruction to be saved.

[0083] Next, an example of the operation flow of the verification device 20 regarding the storage of the execution results in the result storage means 30 and the storage area (register 52 / memory 53) will be described. Figures 13 to 16 are diagrams showing an example of the operation flow of the verification device 20 regarding the storage of the execution results.

[0084] 2, the execution unit 23 sequentially executes the test instruction sequence in the system 50. At this time, the execution results of the save target instructions by the system 50 are stored in the result storage means 30 that stores the execution results of the save target instructions.

[0085] 13, the execution result of the save target instruction may be stored in the memory area and the result storage means 30 by the processor 51 included in the system 50. The processor 51 stores the execution result of the test instruction in the memory area in accordance with the test instruction (step S301). If the test instruction is a save target instruction, the processor 51 also stores the execution result in the result storage means 30 (step S302). The processor 51 can determine whether the test instruction is a save target instruction by, for example, the above-mentioned test bit.

[0086] In this case, the processor 51 is implemented with a function of storing the execution result in the result storage means 30 when the test instruction is a save target instruction. The system 50 may also be configured with information of an area on the result storage means 30 in which the execution result of the save target instruction is to be stored. For example, the system 50 stores information on which area on the result storage means 30 the save target instruction is to be stored in. Alternatively, the processor 51 may refer to the save target instruction list to ascertain the storage destination of the execution result of the save target instruction. Alternatively, the processor 51 may store information of the storage destination of the execution result of the save target instruction in the save target instruction list.

[0087] 14 or 15, the execution unit 23 may receive the execution result of the instruction to be saved from the system 50.

[0088] 14, the execution unit 23 receives the execution result of the test command from the system 50 (step S401). Then, the execution unit 23 stores the received execution result in a storage area in accordance with the test command. Furthermore, if the test command is a command to be saved, the execution unit 23 also stores the execution result in the result storage means 30 (step S402). In this case, the processor 51 is implemented with a function of returning the execution result of the test command to the verification device 20.

[0089] In the example shown in FIG. 15, the processor 51 stores the execution result in a storage area in accordance with the test command (step S501). If the test command is a command to be saved, the processor 51 returns the execution result to the verification device 20 (step S502). The execution unit 23 then stores the received execution result in the result storage means 30 (step S503). In this case, the processor 51 is implemented with a function of returning the execution result of the test command to the verification device 20 if the test command is a command to be saved. The processor 51 can determine whether the test command is a command to be saved, for example, by the above-mentioned test bit.

[0090] 16, when the execution unit 23 causes the system 50 to execute a save target instruction, the execution unit 23 may read the execution result of the system 50 from the storage area and store the read execution result in the result storage means 30. For example, the processor 51 stores the execution result in the storage area in accordance with a test instruction (step S601). When the execution unit 23 causes the system 50 to execute a save target instruction, the execution unit 23 reads the execution result of the system 50 from the storage area (step S602). Then, the execution unit 23 stores the read execution result in the result storage means 30 (step S603).

[0091] As described above, in the second embodiment of the present disclosure, the verification device 20 includes the acquisition unit 21, the detection unit 22, the execution unit 23, and the verification unit 24. The acquisition unit 21 acquires a test instruction sequence. The test instruction sequence is a sequence of test instructions to be executed by a system including a processor. The detection unit 22 detects a save target instruction. The save target instruction is a preceding test instruction in the test instruction sequence when a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced. The execution unit 23 causes the system to execute the test instruction sequence sequentially. The execution result of the save target instruction by the system is stored in the result storage means before the system executes the test instruction next to the save target instruction executed by the system. The result storage means stores the execution result of the save target instruction. The verification unit 24 verifies the execution result by the system. The verification unit 24 performs verification on the memory area updated by the test instruction sequence and the result storage means.

[0092] This allows the verification device 20 to verify the execution result of a preceding test instruction when a memory area updated by the preceding test instruction is updated by a subsequent test instruction without being referenced. Also, the verification device 20 can realize a test by having the system execute each test instruction in the test instruction sequence once. Therefore, in a random test of a system including a processor, it becomes possible to detect an incorrect operation of a preceding test instruction without significantly increasing the execution time of the test.

[0093] Furthermore, in this embodiment, the test can be performed without compromising the randomness of the random test.

[0094] [Hardware configuration example] An example of the configuration of hardware resources for implementing the verification device (10, 20) in each embodiment of the present disclosure described above using one information processing device (computer) will be described. The verification device may be physically or functionally implemented using at least two information processing devices. The verification device may also be implemented as a dedicated device. Only some of the functions of the verification device may also be implemented using an information processing device.

[0095] 17 is a diagram illustrating an example of a hardware configuration of an information processing device capable of implementing the verification device according to each embodiment of the present disclosure. The information processing device 90 includes a communication interface 91, an input / output interface 92, a computing device 93, a storage device 94, a non-volatile storage device 95, and a drive device 96.

[0096] For example, the acquisition unit 11, the detection unit 12, the execution unit 13 and the verification unit 14 in FIG.

[0097] The communication interface 91 is a communication means for the verification device of each embodiment to communicate with an external device via wired and / or wireless communication. When the verification device is realized using at least two information processing devices, the devices may be connected to each other via the communication interface 91 so as to be able to communicate with each other.

[0098] The input / output interface 92 is a man-machine interface including a keyboard as an example of an input device and a display as an output device.

[0099] The arithmetic device 93 is realized by an arithmetic processing device such as a general-purpose CPU (Central Processing Unit) or a microprocessor, and a plurality of electric circuits. The arithmetic device 93 can, for example, read various programs stored in a non-volatile storage device 95 into the storage device 94 and execute processing according to the read programs.

[0100] The storage device 94 is a memory device such as a RAM (Random Access Memory) that can be referenced by the arithmetic device 93, and stores programs, various data, etc. The storage device 94 may be a volatile memory device.

[0101] The non-volatile storage device 95 is, for example, a non-volatile storage device such as a ROM (Read Only Memory) or a flash memory, and is capable of storing various programs, data, and the like.

[0102] The drive device 96 is, for example, a device that processes reading and writing of data from and to a recording medium 97, which will be described later.

[0103] The recording medium 97 is any recording medium capable of recording data, such as an optical disk, a magneto-optical disk, or a semiconductor flash memory.

[0104] Each embodiment of the present disclosure may be realized, for example, by configuring a verification device using an information processing device 90 illustrated in FIG. 17 and supplying a program capable of realizing the functions described in each of the above embodiments to this verification device.

[0105] In this case, the embodiment can be realized by having the calculation device 93 execute the program supplied to the verification device. Also, it is possible to configure some, but not all, of the functions of the verification device in the information processing device 90.

[0106] Furthermore, the verification device may be configured so that the above program is recorded on a recording medium 97 and is appropriately stored in the non-volatile storage device 95 at the shipping stage or operation stage of the verification device. In this case, the method of supplying the above program may be a method of installing the program in the verification device using an appropriate tool at the manufacturing stage before shipping or at the operation stage. The method of supplying the above program may also be a general method such as downloading the program from an external source via a communication line such as the Internet.

[0107] A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes.

[0108] (Appendix 1) an acquisition unit that acquires a test instruction sequence, which is a sequence of test instructions to be executed by a system including a processor; a detection unit for detecting a save target instruction, which is a preceding test instruction in the test instruction sequence, when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without being referenced; an execution unit that causes the system to sequentially execute the test instruction sequence; A verification unit that verifies an execution result of the system; Equipped with the execution result of the save target instruction by the system is stored in a result storage means for storing the execution result of the save target instruction before a test instruction next to the save target instruction executed by the system is executed by the system; the verification unit performs the verification on a storage area updated by the test instruction sequence and on the result storage means; Verification device.

[0109] (Appendix 2) the execution result of the instruction to be saved is stored in the storage area and the result storage means by the processor included in the system; 2. A verification device as described in claim 1.

[0110] (Appendix 3) the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; when the test instruction to be executed by the system is a save target instruction, the execution unit causes the system to execute a test instruction in which a value indicating that the test instruction is a save target instruction is stored in the test bit; when a value indicating that the test instruction is a save target instruction is stored in a test bit of the test instruction instructed to be executed, the system stores an execution result of the test instruction in a storage area and in the result storage means; 3. A verification device as described in appended claim 2.

[0111] (Appendix 4) the execution unit receives an execution result of the instruction to be saved from the system, and stores the received execution result in the result storage means; 2. A verification device as described in claim 1.

[0112] (Appendix 5) the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; when the test instruction to be executed by the system is a save target instruction, the execution unit causes the system to execute a test instruction in which a value indicating that the test instruction is a save target instruction is stored in the test bit; the system transmits an execution result of the test instruction to the verification device when a value indicating that the test instruction is a save target instruction is stored in a test bit of the test instruction that has been instructed to be executed. 5. A verification device as described in claim 4.

[0113] (Appendix 6) when the execution unit causes the system to execute the save target instruction, the execution unit reads an execution result of the system from the storage area and stores the read execution result in the result storage means; 5. A verification device as described in claim 4.

[0114] (Appendix 7) The system transmits the execution result of the test command to the verification device; the execution unit receives an execution result of a test command from the system, stores the received execution result in the storage area, and, if the executed command is a command to be saved, stores the execution result in the result storage means. 2. A verification device as described in claim 1.

[0115] (Appendix 8) the detection unit generates a list of save target instructions that is a list of save target instructions detected from the test instruction sequence, and uses an update list in the process of generating the save target instruction list; the update list is a list of memory areas that have been updated before the execution of a certain test instruction, and that are to be updated by a test instruction that has not been referenced and has not been added to the save target instruction list; 8. A verification device according to any one of claims 1 to 7.

[0116] (Appendix 9) In the test instruction sequence, test instructions in which the types of instructions and the allocation of memory areas to be accessed by the instructions are randomly selected are arranged in a randomly determined order. 9. A verification device according to any one of claims 1 to 8.

[0117] (Appendix 10) A verification device according to any one of claims 1 to 9; The system; The result storage means; A verification system comprising:

[0118] (Appendix 11) A verification method using a verification device, comprising: obtaining a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor; Detecting a save target instruction, which is a preceding test instruction in the test instruction sequence, when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without being referenced; causing the system to execute the test instruction sequence in sequence; Verifying the results of execution by the system; the execution result of the save target instruction by the system is stored in a result storage means for storing the execution result of the save target instruction before a test instruction next to the save target instruction executed by the system is executed by the system; the verification device performs the verification on the storage area updated by the test instruction sequence and on the result storage means; Verification method.

[0119] (Appendix 12) the execution result of the instruction to be saved is stored in the storage area and the result storage means by the processor included in the system; Verification method described in Appendix 11.

[0120] (Appendix 13) the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; when the test instruction to be executed by the system is a save target instruction, the verification device causes the system to execute a test instruction in which a value indicating that the test instruction is a save target instruction is stored in the test bit; when a value indicating that the test instruction is a save target instruction is stored in a test bit of the test instruction instructed to be executed, the system stores an execution result of the test instruction in a storage area and in the result storage means; Verification method described in Appendix 12.

[0121] (Appendix 14) receiving an execution result of the instruction to be saved from the system, and storing the received execution result in the result storage means; Verification method described in Appendix 11.

[0122] (Appendix 15) the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; when the test instruction to be executed by the system is a save target instruction, the verification device causes the system to execute a test instruction in which a value indicating that the test instruction is a save target instruction is stored in the test bit; the system transmits an execution result of a test instruction when a value indicating that the test instruction is an instruction to be saved is stored in a test bit of the test instruction that has been instructed to be executed. Verification method described in Appendix 14.

[0123] (Appendix 16) when the save target instruction is executed by the system, an execution result of the system is read from the storage area, and the read execution result is stored in the result storage means; Verification method described in Appendix 14.

[0124] (Appendix 17) The system transmits a result of executing the test command; the verification device receives an execution result of a test command from the system, stores the received execution result in the storage area, and, if the executed command is a command to be saved, stores the execution result in the result storage means; Verification method described in Appendix 11.

[0125] (Appendix 18) generating a list of save-target instructions detected from the test instruction sequence, and using an update list in the process of generating the save-target instruction list; the update list is a list of memory areas that have been updated before the execution of a certain test instruction, and that are to be updated by a test instruction that has not been referenced and has not been added to the save target instruction list; 18. A method for verification according to any one of claims 11 to 17.

[0126] (Appendix 19) In the test instruction sequence, test instructions in which the types of instructions and the allocation of memory areas to be accessed by the instructions are randomly selected are arranged in a randomly determined order. 19. The verification method according to any one of claims 11 to 18.

[0127] (Appendix 20) On the computer, an acquisition function for acquiring a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor; a detection function for detecting a save target instruction, which is a preceding test instruction, in the test instruction sequence when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without being referenced; an execution function for causing the system to sequentially execute the test instruction sequence; A verification function for verifying an execution result of the system; Realize this, the execution result of the save target instruction by the system is stored in a result storage means for storing the execution result of the save target instruction before a test instruction next to the save target instruction executed by the system is executed by the system; the verification function performs the verification on the storage area updated by the test instruction sequence and on the result storage means; Verification program.

[0128] (Appendix 21) the execution result of the instruction to be saved is stored in the storage area and in the result storage means by the processor included in the system; 20. A verification program as described in Appendix 20.

[0129] (Appendix 22) the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; the execution function, when a test instruction to be executed by the system is an instruction to be saved, causes the system to execute a test instruction in which a value indicating that the test instruction is an instruction to be saved is stored in the test bit; when a value indicating that the test instruction is a save target instruction is stored in a test bit of the test instruction instructed to be executed, the system stores an execution result of the test instruction in a storage area and in the result storage means; 22. The validation program described in Appendix 21.

[0130] (Appendix 23) the execution function receives an execution result of the command to be saved from the system, and stores the received execution result in the result storage means; 20. A verification program as described in Appendix 20.

[0131] (Appendix 24) the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; the execution function, when a test instruction to be executed by the system is an instruction to be saved, causes the system to execute a test instruction in which a value indicating that the test instruction is an instruction to be saved is stored in the test bit; the system transmits an execution result of a test instruction when a value indicating that the test instruction is an instruction to be saved is stored in a test bit of the test instruction that has been instructed to be executed. 23. A verification program as described in Appendix 23.

[0132] (Appendix 25) the execution function, when causing the system to execute the save target command, reads an execution result of the system from the storage area and stores the read execution result in the result storage means; 23. A verification program as described in Appendix 23.

[0133] (Appendix 26) The system transmits a result of executing the test command; the execution function receives an execution result of a test command from the system, stores the received execution result in the storage area, and, if the executed command is a command to be saved, stores the execution result in the result storage means; 20. A verification program as described in Appendix 20.

[0134] (Appendix 27) the detection function generates a list of save target instructions that is a list of save target instructions detected from the test instruction sequence, and uses an update list in the process of generating the save target instruction list; the update list is a list of memory areas that have been updated before the execution of a certain test instruction, and that are to be updated by a test instruction that has not been referenced and has not been added to the save target instruction list; 27. A verification program according to any one of appendices 20 to 26.

[0135] (Appendix 28) In the test instruction sequence, test instructions in which the types of instructions and the allocation of memory areas to be accessed by the instructions are randomly selected are arranged in a randomly determined order. 28. A verification program according to any one of appendices 20 to 27.

[0136] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-mentioned embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be appropriately combined with other embodiments. [Explanation of symbols]

[0137] 10, 20 Verification device 11, 21 Acquisition Department 12, 22 Detector 13, 23 Executive Division 14, 24 Verification Department 30 Result storage means 50 Systems 51 Processors 52 Registers 53 Memory 90 Information processing equipment 91 Communication Interface 92 Input / Output Interface 93 Arithmetic unit 94 Storage device 95 Non-volatile storage devices 96 Drive device 97 Recording media

Claims

1. an acquisition unit that acquires a test instruction sequence, which is a sequence of test instructions to be executed by a system including a processor; a detection unit for detecting a save target instruction, which is a preceding test instruction in the test instruction sequence, when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without being referenced; an execution unit that causes the system to sequentially execute the test instruction sequence; A verification unit that verifies an execution result of the system; Equipped with the execution result of the save target instruction by the system is stored in a result storage means for storing the execution result of the save target instruction before a test instruction next to the save target instruction executed by the system is executed by the system; the verification unit performs the verification on a storage area updated by the test instruction sequence and on the result storage means; Verification device.

2. the execution result of the instruction to be saved is stored in the storage area and in the result storage means by the processor included in the system; The verification device according to claim 1 .

3. the test instruction includes a test bit indicating whether the test instruction is an instruction to be saved; when the test instruction to be executed by the system is a save target instruction, the execution unit causes the system to execute a test instruction in which a value indicating that the test instruction is a save target instruction is stored in the test bit; when a value indicating that the test instruction is a save target instruction is stored in a test bit of the test instruction instructed to be executed, the system stores an execution result of the test instruction in a storage area and in the result storage means; The verification device according to claim 2 .

4. the execution unit receives an execution result of the instruction to be saved from the system, and stores the received execution result in the result storage means; The verification device according to claim 1 .

5. The system transmits the execution result of the test command to the verification device; the execution unit receives an execution result of a test command from the system, stores the received execution result in the storage area, and, if the executed command is a command to be saved, stores the execution result in the result storage means. The verification device according to claim 1 .

6. the detection unit generates a list of save target instructions that is a list of save target instructions detected from the test instruction sequence, and uses an update list in the process of generating the save target instruction list; the update list is a list of memory areas that have been updated before the execution of a certain test instruction, and that are to be updated by a test instruction that has not been referenced and has not been added to the save target instruction list; The verification device according to claim 1 .

7. In the test instruction sequence, test instructions in which the types of instructions and the allocation of memory areas to be accessed by the instructions are randomly selected are arranged in a randomly determined order. The verification device according to claim 1 .

8. A verification device according to any one of claims 1 to 7, The system; The result storage means; A verification system comprising:

9. A verification method using a verification device, comprising: obtaining a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor; Detecting a save target instruction, which is a preceding test instruction in the test instruction sequence, when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without being referenced; causing the system to execute the test instruction sequence in sequence; Verifying the results of execution by the system; the execution result of the save target instruction by the system is stored in a result storage means for storing the execution result of the save target instruction before a test instruction next to the save target instruction executed by the system is executed by the system; the verification device performs the verification on the storage area updated by the test instruction sequence and on the result storage means; Verification method.

10. On the computer, an acquisition function for acquiring a test instruction sequence which is a sequence of test instructions to be executed by a system including a processor; a detection function for detecting a save target instruction, which is a preceding test instruction, in the test instruction sequence when a memory area updated by a preceding test instruction is updated by a subsequent test instruction without being referenced; an execution function for causing the system to sequentially execute the test instruction sequence; A verification function for verifying an execution result of the system; Realize this, the execution result of the save target instruction by the system is stored in a result storage means for storing the execution result of the save target instruction before a test instruction next to the save target instruction executed by the system is executed by the system; the verification function performs the verification on the storage area updated by the test instruction sequence and on the result storage means; Verification program.

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