Display device

Abstract

To provide a display device preventing moisture penetration from a position on top of an insulating layer through the insulating layer near the open area.SOLUTION: A display device according to an embodiment of the present disclosure comprises: a substrate including a display area, an open area positioned in the display area, and an intermediate area positioned between the display area and the open area; and a capping layer disposed in the intermediate area and extending in a closed loop surrounding the open area. The capping layer contains a metal material and is connected to the ground or to a power source having a given voltage.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present specification relates to a display device that includes an aperture region within a display region. [Background technology]

[0002] Display devices are configured in a wide variety of forms, including televisions, monitors, smartphones, tablet PCs, laptops, and wearable devices.

[0003] A display device can realize an image by a large number of pixels included in a display area.

[0004] With technological advances, display devices can now provide not only a function for realizing images, but also a function for capturing images or a sensing function using various optical sensors.

[0005] To accomplish this function, the display device may include various optical devices such as a camera or detection sensors.

[0006] The display device may include a bezel area outside the display area, and the camera, detection sensor, etc. may be arranged in the bezel area. Summary of the Invention [Problem to be solved by the invention]

[0007] Meanwhile, as users increasingly demand display devices with bezel-less or bezel-free designs that can minimize the bezel area and maximize the display area, it may become difficult to place cameras, detection sensors, etc. in the bezel area.

[0008] As a result, various techniques have been devised for arranging cameras, detection sensors, and the like inside the display area of ​​a display device.

[0009] A technology has been devised in which an open area such as a hole is located within the display area where a camera and detection sensor can be placed, and this technology can be called Hole-in Display (HID) or Hole-in Active Area (HiAA).

[0010] In the case of an opening area formed within the display area, not only various insulating layers and light-emitting layers but also the substrate of the display panel can be removed to prevent interference with cameras and detection sensors located in the opening area.

[0011] One method for removing the substrate of the display panel to form the opening area is typically a micro-cutting process using a laser.

[0012] When a fine cutting process using a laser is performed in this manner, a large amount of energy accumulates locally on the substrate due to the localized thermal energy received from the laser, which can cause cracks to occur in the substrate.

[0013] Cracks generated at the cut portion of the substrate may spread to surrounding areas due to stress generated during subsequent processes.

[0014] For example, a crack that occurs at the cut portion of the substrate may extend inside the display area, and the crack may be more likely to propagate through the light-emitting layer and insulating layer disposed near the opening area.

[0015] In this way, cracks that occur at the cut portions of the substrate in the opening regions can become a kind of penetration path for moisture.

[0016] The light emitting element located in the display area and containing an organic material is particularly vulnerable to moisture, and if moisture penetrates into the light emitting element, it may lead to a defect in the light emitting element.

[0017] In order to prevent moisture penetration through such cracks, a crack propagation prevention structure can be placed between the display area and the opening area to prevent cracks that occur at the cut portion of the opening area from propagating.

[0018] For example, the light-emitting layer disposed on the crack propagation prevention structure is discontinuous due to the step structure formed by the crack propagation prevention structure, and therefore the path along which cracks propagate can be blocked.

[0019] However, the step structure formed by the crack propagation prevention structures may cause defects such as seams in the inorganic insulating layer having a thin thickness at the boundary portions between the crack propagation prevention structures.

[0020] When a defect such as a seam occurs in the inorganic insulating layer, the inorganic insulating layer in the area where the seam occurs may not be able to sufficiently cover the underlying structure and may become discontinuous.

[0021] The defects in the inorganic insulating layer that occur in this way can act as paths for moisture permeation to the upper part.

[0022] Meanwhile, when a fine cutting process using a laser is performed, static electricity may be generated.

[0023] The static electricity generated in this way can damage the circuitry within the display panel by opening electrodes within the display panel or shorting adjacent electrodes together.

[0024] Through various experiments, the inventors of this specification have invented a display device that, when an opening region is formed within the display region, can prevent moisture penetration near the opening region and form a static electricity discharge path.

[0025] The problem to be solved by the embodiments of the present specification is to provide a display device that can prevent moisture from penetrating through an upper part of an insulating layer near an opening region in a display region.

[0026] Furthermore, a problem to be solved by the embodiments of the present specification is to provide a display device that provides a structure that is resistant to cracks that occur near the opening region in the display region.

[0027] Furthermore, a problem to be solved by the embodiments of the present specification is to provide a display device that can block cracks from propagating through an insulating layer near an opening region in a display region.

[0028] Furthermore, a problem to be solved by the embodiments of the present specification is to provide a display device that provides a path for discharging static electricity to the outside near an opening region within the display region.

[0029] Another problem to be solved by the embodiments of the present specification is to provide a touch display device capable of reducing the generation of touch noise.

[0030] The problems to be solved by the embodiments of this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0031] A display device according to an embodiment of the present specification includes a substrate including a display area, an opening area located within the display area, and an intermediate area located between the display area and the opening area, and a capping layer including a metal material, which is disposed in the intermediate area and surrounds the opening area in a closed loop, and the capping layer is connected to ground or to a power supply having a predetermined voltage.

[0032] Furthermore, a display device according to an embodiment of the present specification includes a substrate including a display area, an opening area located within the display area, and an intermediate area located between the display area and the opening area, one or more blocking portions arranged in the intermediate area, one or more insulating layers arranged to cover the one or more blocking portions, and a capping layer including a metal material arranged in the intermediate area to cover at least one or more of the blocking portions and surround the opening area, wherein the capping layer is connected to ground or to a power source having a predetermined voltage. [Effects of the Invention]

[0033] According to an embodiment of the present specification, by surrounding the opening area in the intermediate region between the display area and the opening area and disposing a capping layer containing a metal material, moisture penetration can be prevented through the top of the insulating layer near the opening area.

[0034] According to an embodiment of the present specification, by disposing a capping layer containing a metal material in an intermediate region between the display region and the opening region, surrounding the opening region, the capping layer can reduce the propagation of cracks through the insulating layer, thereby providing a crack-resistant structure.

[0035] In addition, according to the embodiments of the present specification, the insulating layer can be blocked by using a structure in which a capping layer containing a metal material is surrounded in an intermediate region between the display region and the opening region and connected to a power connection wiring arranged below via a power connection electrode, thereby preventing cracks from propagating through the insulating layer.

[0036] In addition, according to an embodiment of the present specification, by surrounding the opening region in the intermediate region between the display region and the opening region and connecting a capping layer containing a metal material to ground or supplying a power source having a constant voltage, static electricity generated during the cutting process to form the opening region can be discharged to the outside, thereby reducing the occurrence of pixel defects.

[0037] In this way, the occurrence of pixel defects can be reduced, which improves the lifespan of the display device, and by configuring a low-power display device, there is an effect of reducing power consumption.

[0038] In addition, according to the embodiments of the present specification, by surrounding the opening region in the intermediate region between the display region and the opening region and connecting a capping layer containing a metal material to ground or supplying a power source having a constant voltage, the voltage of the capping layer can be made constant and not fluctuate, thereby reducing the occurrence of touch noise in the touch display device.

[0039] The above-mentioned effects and specific effects of the present invention will be described in conjunction with the following description of the preferred embodiment of the invention. [Brief explanation of the drawings]

[0040] [Figure 1] 1 is a schematic plan view of a display device according to an embodiment of the present disclosure; [Figure 2] 1 is a schematic plan view of a display device including anti-static wiring and crack detection wiring according to an embodiment of the present disclosure; [Figure 3] 1 is a cross-sectional view of one subpixel of a display device according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is an enlarged plan view of an opening region within a display region. [Figure 5] FIG. 5 is a cross-sectional view of the AA′ region in FIG. [Figure 6] FIG. 5 is a cross-sectional view of the BB′ region in FIG. [Figure 7] FIG. 5 is a cross-sectional view of the BB′ region in FIG. [Figure 8] FIG. 1 is a circuit diagram in the vicinity of an aperture region of a display device according to an embodiment of the present specification. [Figure 9] FIG. 2 is a plan view of a display device according to an embodiment of the present specification in the vicinity of an opening region. [Figure 10] 1 is a cross-sectional view of a display device according to an embodiment of the present specification in the vicinity of an opening region. [Figure 11] FIG. 10 is a circuit diagram in the vicinity of an opening region of a display device according to another embodiment of the present specification. [Figure 12] FIG. 10 is a plan view of a display device according to another embodiment of the present specification in the vicinity of an opening region. [Figure 13] FIG. 10 is a cross-sectional view of a display device according to another embodiment of the present specification in the vicinity of an opening region. [Figure 14] FIG. 1 is a circuit diagram in the vicinity of an aperture region of a display device according to an embodiment of the present specification. [Figure 15] FIG. 2 is a plan view of a display device according to an embodiment of the present specification in the vicinity of an opening region. [Figure 16] 1 is a cross-sectional view of a display device according to an embodiment of the present specification in the vicinity of an opening region. DETAILED DESCRIPTION OF THE INVENTION

[0041] The advantages and features of the present specification, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be configured in various different forms. However, the present embodiments are provided to complete the disclosure of the specification and to fully convey the scope of the invention to those skilled in the art to which the specification pertains, and the specification is defined only by the scope of the claims.

[0042] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative only, and the specification is not limited to the illustrated matters. The same reference symbols throughout the specification refer to the same components. Furthermore, in explaining this specification, if a detailed description of related publicly known technology is deemed to obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be," other parts can be added unless "only" is used. When a component is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0043] When interpreting elements, they are interpreted as including a margin of error, even if there is no explicit statement otherwise.

[0044] When describing the positional relationship between two parts, for example, when using "above," "at the top," "below," "to the side," etc., one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0045] When describing temporal relationships, for example, when describing temporal precedence using "after," "following," "next to," or "before," non-sequential cases may also be included, unless "immediately" or "directly" is used.

[0046] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0047] The features of the multiple embodiments of this specification can be partially or wholly combined or combined with each other, and various technical interlocking and driving mechanisms are possible, and each embodiment can be implemented independently of each other or can be implemented together in a linked relationship.

[0048] A display device according to an embodiment of the present specification will be described in detail below with reference to FIGS.

[0049] FIG. 1 is a schematic plan view of a display device according to an embodiment of the present specification.

[0050] The display device 1 described below will be described as an organic light emitting diode (ELD) display device as an example, but is not limited thereto.

[0051] The display device 1 may include a substrate 10 including a display area (AA) and a non-display area (NA) surrounding the display area (AA).

[0052] In the display area (AA) on the substrate 10, a plurality of data lines (DL) extending in a first direction and a plurality of gate lines (GL) extending in a second direction intersecting the first direction may be arranged.

[0053] Each of the areas partitioned by the intersection of the data lines (DL) and the gate lines (GL) can be defined as one sub-pixel (SP1, SP2, SP3).

[0054] Each sub-pixel (SP1, SP2, SP3) may be configured to emit light of the same color, such as white (W) light, or may be configured to emit different colors, such as red (R), green (G), or blue (B) light.

[0055] A single pixel (P) may be configured by combining a plurality of sub-pixels (SP1, SP2, SP3) as described above.

[0056] The plurality of sub-pixels (SP1, SP2, SP3) may be arranged in a matrix with a plurality of rows and columns.

[0057] In this specification, the first direction is the column direction and can be defined as the Y-axis direction, and the second direction is the row direction and can be defined as the X-axis direction.

[0058] In the non-display area (NA) on the substrate 10, a large number of wirings and pads may be arranged to supply various signals, power sources, and the like to the inside of the pixels.

[0059] A data driving circuit (D-IC) 20 may be arranged on one side of the non-display area (NA).

[0060] The data driving circuit 20 can apply a data signal to the data line (DL) and a driving voltage such as a high potential voltage (VDD) or a low potential voltage (VSS) to the pixel (P).

[0061] The power supply wiring 30 may be arranged along the edge of the display area (AA) except for one side of the non-display area (NA) where the data driving circuit 20 is arranged.

[0062] For example, in the non-display areas (NA) located on both sides of the display area (AA), a gate driver 40 that applies a gate signal to the gate line (GL) may be arranged, and a power supply line 30 that can apply a voltage to the anode electrode or cathode electrode in the pixel (P) may be arranged along the outer periphery of the gate driver 40.

[0063] The gate driver 40 formed on the substrate 10 in a gate-in-panel (GIP) manner can be called a GIP driver.

[0064] The power supply wiring 30 may be a low potential voltage wiring capable of applying a low potential voltage (VSS) to the cathode electrode of the pixel (P), but is not limited to this, and a high potential voltage wiring capable of applying a high potential voltage (VDD) to the thin film transistor of the pixel (P) may also be arranged.

[0065] In the display area (AA), a plurality of power supply connection wirings 31 may be arranged to electrically connect the power supply wiring 30 to the plurality of sub-pixels (SP1, SP2, SP3) so as to apply a low potential voltage (VSS) to the plurality of sub-pixels (SP1, SP2, SP3).

[0066] For example, the plurality of power supply connection lines 31 may extend in the same first direction as the plurality of data lines (DL).

[0067] Referring to FIG. 2, one or more optical areas (OA1, OA2) may be formed within the display area (AA).

[0068] For example, a first area (A1) including a first optical area (OA1) and a second area (A2) including a second optical area (OA2) may be formed in the display area (AA).

[0069] The first optical area (OA1) and the second optical area (OA2) may be located in an upper area of ​​the display area (AA).

[0070] The first optical area (OA1) and the second optical area (OA2) may be formed to have various patterns, such as a circle, an ellipse, a square, a hexagon, or an octagon.

[0071] A first optical-electronic device may be arranged in the first optical area (OA1), and a second optical-electronic device may be arranged in the second optical area (OA2).

[0072] In one example, the first optical-electronic device may be a camera, and the second optical-electronic device may be a detection sensor such as a proximity sensor, an illuminance sensor, an infrared sensor, or the like.

[0073] The first optical area (OA1) may also be referred to as a camera aperture, and the second optical area (OA2) may also be referred to as a sensor aperture.

[0074] A flexible circuit board 50 and a printed circuit board 51 may be disposed in the lower region of the substrate 10 .

[0075] One side of the flexible circuit board 50 may be connected to the substrate 10 , and the other side of the flexible circuit board 50 may be connected to the printed circuit board 51 .

[0076] The flexible circuit board 50 may be a chip-on-film (COF) or a flexible printed circuit board (FPC).

[0077] The flexible circuit board 50 may have a data driver 20 disposed thereon, which supplies data signals to the pixels to cause them to emit light.

[0078] The printed circuit board 51 may have various components arranged thereon that can supply various signals to the data driver 20 and the gate driver 40, such as high voltage, low voltage, scan signal, data signal, or touch detection signal.

[0079] On the substrate 10, a crack detection wiring 60 may be arranged.

[0080] The crack detection wiring 60 may be formed in a form that substantially surrounds the outer periphery of the display area (AA) of the substrate 10, and may be formed to extend so as to pass through the non-display area (NA).

[0081] The crack detection wiring 60 passing through the upper region of the substrate 10 may be formed so as to pass through the peripheral portions of the first optical region (OA1) and the second optical region (OA2) and to substantially surround the first optical region (OA1) and the second optical region (OA2).

[0082] The first region (A1) may be a region including the crack detection wiring 60 surrounding the first optical region (OA1) and the peripheral periphery of the first optical region (OA1), and the second region (A2) may be a region including the crack detection wiring 60 surrounding the second optical region (OA2) and the peripheral periphery of the second optical region (OA2).

[0083] The crack detection wiring 60 may be made up of a single wiring, but is not limited to this and may be made up of a plurality of wirings.

[0084] The crack detection wiring 60 passing through the lower region of the substrate 10 may be connected to a crack detection pad portion 61 .

[0085] The crack detection pad portion 61 may be disposed on the substrate 10, but is not limited to this, and may also be disposed on the flexible circuit board 50.

[0086] The crack detection wiring 60 connected to the crack detection pad portion 61 may be formed so as to form a closed loop as a whole.

[0087] As mentioned above, the crack detection wiring 60 can be arranged to extend to the peripheral portions of the first optical area (OA1) and the second optical area (OA2), thereby making it possible to check whether cracks occur in the first optical area (OA1) and the second optical area (OA2).

[0088] The method of checking whether or not a crack occurs via the crack detection wiring 60 is as follows.

[0089] When an Auto Probe (AP) is performed as a final inspection of the display panel of the display device 1, a constant level of power is applied to the crack detection pad portion 61, and the input value and the output value can be compared.

[0090] At this time, the degree of resistance of the crack detection wiring 60 is grasped from the difference between the measured input value and the output value, and based on this, it is possible to check whether or not the crack detection wiring 60 is broken.

[0091] For example, if a crack occurs near the first optical area (OA1), part or all of the crack detection wiring 60 may be broken.

[0092] If a part of the crack detection wiring 60 is broken, the resistance will gradually increase and the output power may weaken, and if the wiring is completely broken, the output power may converge to zero. These characteristics related to electrical resistance can be used to determine whether a crack has occurred in the display panel.

[0093] The crack detection pad portion 61 can be connected to ground (GND), thereby allowing the crack detection wiring 60 connected to the crack detection pad portion 61 and other wiring connected to the crack detection wiring 60 to be connected to ground (GND) and grounded.

[0094] Furthermore, anti-static wiring 70 may be arranged on the substrate 10.

[0095] The anti-static wiring 70 can be called an ESD (Electrostatic Discharge) wiring.

[0096] The static electricity prevention wiring 70 may be formed in a form that substantially surrounds the outer periphery of the display area (AA) of the substrate 10 and extends to pass through the non-display area (NA).

[0097] In one example, the anti-static wiring 70 may be located inside the crack detection wiring 60, but is not limited to this.

[0098] The anti-static wiring 70 passing through the upper region of the substrate 10 may be formed so as to pass through the periphery of the first optical region (OA1) and the second optical region (OA2).

[0099] For example, the anti-static wiring 70 may be formed to extend adjacent to the upper areas of the first optical area (OA1) and the second optical area (OA2), but is not limited to this.

[0100] The anti-static wiring 70 passing through the lower region of the substrate 10 may be connected to an anti-static pad portion 71 .

[0101] The anti-static pad portion 71 may be disposed on the substrate 10, but is not limited to this, and may also be disposed on the flexible circuit board 50.

[0102] The static electricity prevention wiring 70 connected to the static electricity prevention pad portion 71 may be formed so as to form a closed loop as a whole.

[0103] The anti-static pad portion 71 can be connected to ground (GND), thereby allowing the anti-static wiring 70 connected to the anti-static pad portion 71 and other wiring connected to the anti-static wiring 70 to be connected to ground (GND) and grounded.

[0104] Therefore, the static electricity prevention wiring 70 can have the function of discharging static electricity generated in the display panel to the outside.

[0105] Referring to FIG. 3, the sub-pixels in the display area (AA) according to the embodiment of the present specification will be described in detail.

[0106] The substrate 10 can be made of glass or plastic such as polyimide.

[0107] A first thin film transistor, a storage capacitor and a second thin film transistor may be disposed on the substrate 10 .

[0108] On the substrate 10, a first light blocking layer (BSM1) may be disposed.

[0109] The first light-shielding layer (BSM1) can block light incident from the outside and protect the first active layer (ACT1) of the first thin film transistor.

[0110] Therefore, the first light-blocking layer (BSM1) may be disposed so as to overlap the first active layer (ACT1) of the first thin film transistor in the vertical direction.

[0111] The up-down direction in FIG. 3 can refer to the Z-axis direction.

[0112] A buffer layer (BUF) may be disposed on the first light blocking layer (BSM1).

[0113] The buffer layer (BUF) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0114] For example, the inorganic insulating layers described herein may include silicon oxide (SiOx) or silicon nitride (SiNx).

[0115] The buffer layer (BUF) may also be referred to as a lower buffer layer.

[0116] A first active layer (ACT1) may be disposed on the buffer layer (BUF).

[0117] The first active layer (ACT1) may be made of, but is not limited to, an oxide semiconductor material.

[0118] A first gate insulating layer (GI1) may be disposed on the first active layer (ACT1).

[0119] The first gate insulating layer (GI1) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0120] A first gate electrode (GAT1) may be disposed on the first gate insulating layer (GI1).

[0121] The first gate electrode (GAT1) may be disposed so as to overlap the first active layer (ACT1) in the vertical direction.

[0122] In addition, a first capacitor electrode (Cst1) may be disposed on the first gate insulating layer (GI1).

[0123] The first gate electrode (GAT1) and the first capacitor electrode (Cst1) may be formed in the same layer and made of the same material.

[0124] A first interlayer insulating layer (ILD1) may be disposed on the first gate electrode (GAT1) and the first capacitor electrode (Cst1).

[0125] The first interlayer insulating layer (ILD1) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0126] A second capacitor electrode (Cst2) may be disposed on the first interlayer insulating layer (ILD1).

[0127] The second capacitor electrode (Cst2) may be disposed so as to overlap the first capacitor electrode (Cst1) in the vertical direction, and a storage capacitor may be formed by the second capacitor electrode (Cst2) and the first capacitor electrode (Cst1).

[0128] In addition, a second light blocking layer (BSM2) may be disposed on the first interlayer insulating layer (ILD1).

[0129] The second light-shielding layer (BSM2) can block light incident from the outside and protect the second active layer (ACT2) of the second thin film transistor.

[0130] Therefore, the second light-blocking layer (BSM2) may be disposed so as to overlap the second active layer (ACT2) of the second thin film transistor in the vertical direction.

[0131] A second interlayer insulating layer (ILD2) may be disposed on the second capacitor electrode (Cst2) and the second light blocking layer (BSM2).

[0132] A second active layer (ACT2) may be disposed on the second interlayer dielectric layer (ILD2).

[0133] The second active layer (ACT2) may be made of, but is not limited to, an oxide semiconductor material.

[0134] A second gate insulating layer (GI2) may be disposed on the second active layer (ACT2).

[0135] The second gate insulating layer (GI2) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0136] A second gate electrode (GAT2) may be disposed on the second gate insulating layer (GI2).

[0137] The second gate electrode (GAT2) may be disposed so as to overlap the second active layer (ACT2) in the vertical direction.

[0138] A third interlayer insulating layer (ILD3) may be disposed on the second gate electrode (GAT2).

[0139] The third interlayer insulating layer (ILD3) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0140] The third interlayer dielectric layer (ILD3) can also be referred to as an upper buffer layer.

[0141] A pair of first source-drain electrodes (SD1) and a pair of second source-drain electrodes (SD2) may be disposed on the third interlayer insulating layer (ILD3).

[0142] The pair of first source drain electrodes (SD1) may be connected to one side and the other side of the first active layer (ACT1) via contact holes passing through the third interlayer insulating layer (ILD3), the second gate insulating layer (GI2), the second interlayer insulating layer (ILD2), the first interlayer insulating layer (ILD1), and the first gate insulating layer (GI1).

[0143] The first active layer (ACT1), the first gate electrode (GAT1), and the pair of first source / drain electrodes (SD1) thus formed may constitute a first thin film transistor.

[0144] The pair of second source / drain electrodes (SD2) may be connected to one side and the other side of the second active layer (ACT2), respectively, via contact holes penetrating the third interlayer insulating layer (ILD3) and the second gate insulating layer (GI2).

[0145] The second active layer (ACT2), the second gate electrode (GAT2), and the pair of second source / drain electrodes (SD2) thus formed may constitute a second thin film transistor.

[0146] One of the second source-drain electrodes (SD2) can be electrically connected to the second capacitor electrode (Cst2).

[0147] For example, one of the second source drain electrodes (SD2) can be electrically connected to the second capacitor electrode (Cst2) through a contact hole penetrating the third interlayer insulating layer (ILD3), the second gate insulating layer (GI2), and the second interlayer insulating layer (ILD2).

[0148] A first planarization layer (PLN1) may be disposed on the pair of first source-drain electrodes (SD1) and the pair of second source-drain electrodes (SD2).

[0149] The first planarization layer (PLN1) can function to planarize steps caused by underlying circuit elements including thin film transistors.

[0150] The first planarization layer (PLN1) may include an organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0151] A third source-drain electrode (SD3) may be disposed on the first planarization layer (PLN1).

[0152] The third source-drain electrode (SD3) can function as a connection electrode that connects the second source-drain electrode (SD2) and the anode electrode (AND).

[0153] The third source / drain electrode (SD3) may be connected to the second source / drain electrode (SD2) via a contact hole that penetrates the first planarization layer (PLN1).

[0154] A second planarization layer (PLN2) may be disposed on the third source / drain electrode (SD3).

[0155] The second planarization layer (PLN2) may include an organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0156] An anode electrode (AND) may be disposed on the second planarization layer (PLN2).

[0157] The anode electrode (AND) may be connected to the third source / drain electrode (SD3) through a contact hole that penetrates the second planarization layer (PLN2).

[0158] A bank (BNK) may be disposed on the anode electrode (AND).

[0159] The bank (BNK) may be formed so as to cover the edge of the anode electrode (AND).

[0160] The bank (BNK) serves to separate each sub-pixel (SP1, SP2, SP3) and can prevent light of different colors from being mixed and output between adjacent sub-pixels (SP1, SP2, SP3).

[0161] The bank (BNK) may include an organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0162] A light-emitting layer (EL) may be disposed on the anode electrode (AND).

[0163] The light-emitting layer (EL) may contain organic materials that emit light of different colors in each of the sub-pixels (SP1, SP2, SP3).

[0164] For example, the light-emitting layer (EL) can emit one of the following hues: red, green, blue, and white.

[0165] In addition, the light emitting layer (EL) is made of an organic material that emits white light, and color filters of different colors can be further disposed on the light emitting layer (EL) to express red, green, or blue.

[0166] The light-emitting layer (EL) may be an organic light-emitting layer having a stack structure including a hole-transporting layer, a light-emitting material layer, an electron-transporting layer, a hole-blocking layer, a hole-injecting layer, an electron-blocking layer, and an electron-injecting layer.

[0167] The light-emitting layer (EL) may be formed so as to cover the anode electrode (AND) and also to cover part of the side and upper surfaces of the bank (BNK).

[0168] Moreover, the light-emitting layer (EL) can be formed over the entire surface of the display area (AA) so as to cover the exposed surfaces of the anode electrodes (AND) and the banks (BNK).

[0169] The light-emitting layer (EL) may be formed so as to include the display area (AA) and extend to the boundary surface of the aperture area (OA).

[0170] A spacer (SPC) may be disposed between the bank (BNK) and the light-emitting layer (EL).

[0171] The spacers (SPC) may be formed to contain the same material as the banks (BNK).

[0172] The spacer (SPC) serves to prevent the light-emitting layer (EL) from receiving external impact and also to provide a separation space so that the substrate 10 does not come into direct contact with the deposition screen mask during the deposition of the light-emitting layer (EL).

[0173] A cathode electrode (CAT) may be disposed on the light-emitting layer (EL).

[0174] The cathode electrode (CAT) can be formed to cover the light-emitting layer (EL).

[0175] The cathode electrode (CAT) may be formed to extend so as to cover the plurality of pixels (P).

[0176] The region where the anode electrode (AND), the light-emitting layer (EL) and the cathode electrode (CAT) are overlapped can function as an organic electroluminescent device (OLED), which is a light-emitting element.

[0177] In FIG. 3, the anode electrode (AND) is shown positioned at the bottom and the cathode electrode (CAT) is shown positioned at the top, but this is not limited thereto, and the cathode electrode (CAT) may be positioned at the bottom and the anode electrode (AND) may be positioned at the top.

[0178] A first passivation layer (PAS1) may be disposed on the cathode electrode (CAT).

[0179] The first passivation layer (PAS1) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0180] The first passivation layer (PAS1) can serve to protect the light-emitting element from external oxygen or moisture.

[0181] A encapsulation layer (PCL) may be formed on the first passivation layer (PAS1).

[0182] The encapsulation layer (PCL) may be thick enough to cover the first passivation layer (PAS1) and have a flat surface.

[0183] The encapsulation layer (PCL) can prevent foreign matter from penetrating into the light emitting element.

[0184] The encapsulation layer (PCL) may comprise an organic insulating material.

[0185] For example, the encapsulation layer (PCL) may include an organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0186] A second passivation layer (PAS2) may be disposed on the encapsulation layer (PCL).

[0187] The second passivation layer (PAS2) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited to this.

[0188] The second passivation layer (PAS2) can serve to protect the light emitting element from external oxygen or moisture.

[0189] The first passivation layer (PAS1), the sealing layer (PCL), and the second passivation layer (PAS2) can be considered as sealing layers in a broad sense.

[0190] A touch panel unit may be further disposed on the display panel unit described above.

[0191] For example, a touch buffer layer (T-BUF) may be disposed on the second passivation layer (PAS2).

[0192] For example, the touch buffer layer (T-BUF) may be composed of a single layer or multiple layers of inorganic insulating layers, but is not limited thereto.

[0193] A touch sensor (TS) may be disposed on the touch buffer layer (T-BUF).

[0194] The touch sensor (TS) may include a touch sensor metal (TSM) and a bridge metal (BRG) located in different layers.

[0195] The touch sensor (TS) can be referred to as a touch electrode layer (TS), and the touch sensor metal (TSM) and the bridge metal (BRG) can be referred to as a second touch electrode (TSM) and a first touch electrode (BRG), respectively.

[0196] A touch interlayer insulating layer (T-ILD) may be disposed between the touch sensor metal (TSM) and the bridge metal (BRG).

[0197] For example, the touch sensor metal (TSM) may include a pair of a first touch sensor metal (TSM1) and a second touch sensor metal (TSM2) arranged adjacent to each other.

[0198] When a second touch sensor metal (TSM2) is present between a pair of first touch sensor metals (TSM1) and the pair of first touch sensor metals (TSM1) must be electrically connected to each other, the pair of first touch sensor metals (TSM1) can be electrically connected to each other via a bridge metal (BRG) in another layer.

[0199] The bridge metal (BRG) may be insulated from the second touch sensor metal (TSM2) by a touch inter-layer dielectric layer (T-ILD).

[0200] A protective layer (PAC) may be disposed on the touch sensor (TS).

[0201] The protective layer (PAC) may include an organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0202] The first region (A1) will be described in more detail below with reference to FIGS.

[0203] The second region (A2) may have substantially the same structure as the first region (A1), and a detailed description thereof will be omitted.

[0204] The first area (A1) may include an opening area (OA) therein, in which a hole is formed by cutting through the display area (AA).

[0205] An intermediate area (MA) may be formed along the peripheral periphery of the opening area (OA).

[0206] The intermediate area (MA) can be an inner bezel area where no sub-pixels (SP1, SP2, SP3) are arranged.

[0207] Therefore, the opening area (OA) and the intermediate area (MA) may be non-display areas located within the display area (AA).

[0208] The area outside the intermediate area (MA) may be a display area (AA) in which the sub-pixels (SP1, SP2, SP3) are arranged.

[0209] The intermediate area (MA) can prevent moisture penetration that may occur along the trimming line of the opening area (OA) and can prevent fine cracks that may occur during the process of forming the opening area (OA) from penetrating into the display area (AA).

[0210] The intermediate area (MA) may include a cutting margin portion (TA), a second blocking portion (SPR2), a dam portion (DM), a first blocking portion (SPR1), and a touch routing area (TRA) arranged sequentially in a direction from the opening area (OA) toward the display area (AA).

[0211] Figure 5 is a cross-sectional view of the display area (AA) shown along line A-A' in Figure 4, and any explanation that overlaps with the explanation of the display area (AA) explained with reference to Figure 3 above will be omitted.

[0212] FIG. 6 is a cross-sectional view of the first region (A1) taken along the line BB' in FIG.

[0213] The touch routing area (TRA) may have a touch sensor disposed therein, the touch sensor metal (TSM) and the bridge metal (BRG) being located in different layers.

[0214] The first blocking section (SPR1) may have one or more first blocking structures 210 arranged therein.

[0215] Adjacent first blocking structures 210 may be spaced apart from each other.

[0216] Each of the first blocking structures 210 may be formed in a concave-convex pattern.

[0217] For example, the first blocking structure 210 may be formed by removing at least a portion of an organic insulating layer, such as the first planarization layer (PLN1) and the second planarization layer (PLN2).

[0218] The first blocking structure 210 may be formed in a two-layer structure.

[0219] In one example, the first lower structure 211 located at the bottom may have a positive tapered shape in which the width decreases toward the top, and the second upper structure 222 located above the first lower structure 211 may also have a positive tapered shape in which the width decreases toward the top.

[0220] The first lower structure 211 may be formed of the same material as the third interlayer insulating layer (ILD3), and the first upper structure 212 may be formed of the same material as the second planarization layer (PLN2), but is not limited to this.

[0221] Therefore, the first blocking structure 210 may have an undercut structure at its bottom.

[0222] Depending on the shape of the first blocking structure 210 thus formed, the light emitting layer (EL) disposed on the first blocking structure 210 may be discontinuously disposed. For example, the light emitting layer (EL) may have a stack structure including, but is not limited to, a hole transport layer, an electron transport layer, a hole blocking layer, a hole injection layer, an electron blocking layer, and an electron injection layer.

[0223] That is, the light emitting layer (EL) extending between adjacent first blocking structures 210 may be discontinuously formed without being connected to each other due to the undercut structure of the first blocking structures 210.

[0224] The light-emitting layer (EL) located in the intermediate region (MA) is not continuously connected, but is arranged discontinuously, thereby effectively blocking moisture that is introduced along the light-emitting layer (EL) of the intermediate region (MA) through the opening region (OA).

[0225] The first blocking structure 210 can also be called a separator because it serves to cut off the light-emitting layer (EL).

[0226] One or more dams 250 may be disposed in the dam section (DM).

[0227] The dam 250 can act to prevent the encapsulation layer (PCL) from overflowing and flowing outside the dam 250 .

[0228] For example, the dam 250 may be formed by patterning a third interlayer insulating layer (ILD3), a second planarization layer (PLN2), and a spacer (SPC).

[0229] An aligning metal layer (AM) made of the same layer as the first gate electrode (GAT1) may be formed below the dam 250. The aligning metal layer (AM) may serve as a mark to allow the laser to accurately irradiate the opening area (OA) when cutting by irradiating a laser to form the opening area (OA). One or more second blocking structures 220 may be arranged in the second blocking portion (SPR2).

[0230] Adjacent second blocking structures 220 may be spaced apart from each other.

[0231] The second blocking structure 220 may be formed in a two-layer structure consisting of a second lower structure 221 arranged in the lower part and a second upper structure 222 arranged in the upper part.

[0232] The second blocking structure 220 may be formed to have the same shape as the first blocking structure 210 and may have an undercut structure formed thereunder.

[0233] Depending on the shape of the second blocking structure 220 thus formed, the light emitting layer (EL) disposed on the second blocking structure 220 may be disposed discontinuously.

[0234] Additionally, one or more third blocking structures 230 may be disposed in the cutting margin (TA).

[0235] Adjacent third blocking structures 230 may be spaced apart from each other.

[0236] The third blocking structure 230 may be formed in a two-layer structure consisting of a third lower structure 231 arranged in the lower part and a third upper structure 232 arranged in the upper part.

[0237] The third blocking structure 230 may be formed to have the same shape as the second blocking structure 220 and may have an undercut structure formed thereunder.

[0238] Depending on the shape of the third blocking structure 230 thus formed, the light emitting layer (EL) disposed on the third blocking structure 230 may be disposed discontinuously.

[0239] In this way, the light-emitting layer (EL) located in the intermediate region (MA) is not continuously connected but is arranged discontinuously, thereby effectively blocking moisture that is introduced along the light-emitting layer (EL) of the intermediate region (MA) through the opening region (OA).

[0240] Outside the cutting margin (TA) can be an opening area (OA).

[0241] The cutting margin (TA) may be formed to have a predetermined width in consideration of process errors that may occur when cutting by irradiating a laser to form the opening area (OA).

[0242] The cutting margin portion (TA) may be formed to have substantially the same layer structure as the second blocking portion (SPR2).

[0243] Therefore, in a broad sense, the cutting margin portion (TA) can also be said to be included in the second blocking portion (SPR2).

[0244] A first passivation layer (PAS1) may be disposed on the first blocking structure 210, the second blocking structure 220, the third blocking structure 230, and the dam 250 formed in this manner.

[0245] A first passivation layer (PAS1) may be formed to fill the separation spaces between each of the blocking structures 210, 220, and 230.

[0246] However, due to the undercut structure of the blocking structures 210, 220, and 230, in the case of the first passivation layer (PAS1), which is an inorganic insulating layer formed with a relatively thin thickness compared to an organic insulating layer, defects such as seams may occur as the connection is discontinuously broken in the space between the blocking structures 210, 220, and 230.

[0247] In this way, if the first passivation layer (PAS1) is formed discontinuously rather than continuously covering the underlying structure, the area where the seam occurs may act as a moisture permeation path in the upward direction.

[0248] With the dam 250 as the reference, a sealing layer (PCL) which is an organic insulating layer may be disposed on the first passivation layer (PAS1) of the first blocking portion (SPR1) located inside the dam 250.

[0249] With respect to the dam 250, a separate organic insulating layer may not be provided in the second blocking portion (SPR2) and cutting margin portion (TA) located outside the dam 250.

[0250] On the first passivation layer (PAS1), inorganic insulating layers such as a second passivation layer (PAS2), a touch buffer layer (T-BUF), and a touch interlayer insulating layer (T-ILD) may further be disposed.

[0251] A sealing layer (PCL) may be further disposed on the first passivation layer (PAS1) of the first blocking portion (SPR1), which can partially block the upper moisture permeation path through the seam formed by the first passivation layer (PAS1). However, in the case of the second blocking portion (SPR2) and the cutting margin portion (TA) which are formed with a laminated structure of thin inorganic insulating layers, a method may be required to block the upper moisture permeation path through the seam formed by the first passivation layer (PAS1).

[0252] This allows the display device 1 according to the embodiment of the present specification to form a capping layer (CL) in the intermediate area (MA).

[0253] The capping layer (CL) may include a first capping layer (CL1) disposed on the touch buffer layer (T-BUF) and a second capping layer (CL2) disposed on the touch inter-layer dielectric layer (T-ILD).

[0254] Therefore, the capping layer (CL) may be formed in a double structure of a first capping layer (CL1) disposed in the lower part and a second capping layer (CL2) disposed in the upper part.

[0255] The first capping layer (CL1) may be disposed in the same layer as the first touch electrode (BRG) and may be formed of the same material as the first touch electrode (BRG).

[0256] Also, the second capping layer (CL2) may be disposed in the same layer as the second touch electrode (TSM) and may be formed of the same material.

[0257] The first capping layer (CL1) and the second capping layer (CL2) may include a metallic material.

[0258] For example, the first capping layer (CL1) and the second capping layer (CL2) may be a single layer or multiple layers made of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

[0259] The first capping layer (CL1) and the second capping layer (CL2) may be arranged so as not to be electrically connected to each other through the touch inter-layer insulating layer (T-ILD), but this is not limited thereto, and in other embodiments, the first capping layer (CL1) and the second capping layer (CL2) may be electrically connected to each other through a contact hole in the touch inter-layer insulating layer (T-ILD).

[0260] The first capping layer (CL1) and the second capping layer (CL2) may be disposed so as to overlap each other in the vertical direction.

[0261] The second capping layer (CL2) may be formed to have an area larger than that of the first capping layer (CL1).

[0262] The first capping layer (CL1) and the second capping layer (CL2) may be disposed so as to surround the open area (OA), and may be formed in the shape of a closed loop.

[0263] The capping layer (CL) may be disposed in at least a portion of the intermediate region (MA).

[0264] In one embodiment, referring to FIG. 6, the capping layer (CL) may be disposed on the first blocking portion (SPR1), the dam portion (DM), and the second blocking portion (SPR2).

[0265] In this case, the capping layer (CL) may be arranged to completely cover the dam portion (DM) and the second blocking portion (SPR2), and the first blocking portion (SPR1) may be arranged to cover only a portion of the area adjacent to the dam portion (DM).

[0266] Furthermore, the second capping layer (CL2) of the capping layer (CL) disposed in the first blocking portion (SPR1) may be disposed so as to have a smaller area than the first capping layer (CL1).

[0267] For example, the first capping layer (CL1) may be formed so as to extend further in the direction toward the display area (AA) than the second capping layer (CL2).

[0268] On the first capping layer (CL1) extending further than the second capping layer (CL2), crack detection wiring 60 may be arranged so as to overlap in the vertical direction.

[0269] The crack detection wiring 60 may be disposed in the same layer as the second capping layer (CL2) and may be made of the same material.

[0270] The crack detection wiring 60 may be arranged so as to overlap the first blocking structure 210 in the vertical direction.

[0271] The crack detection wiring 60 may be arranged to surround the open area (OA).

[0272] For example, the crack detection wiring 60 may be arranged to surround the opening area (OA) in a manner that a part of the opening area (OA) is left open.

[0273] As described above, according to the embodiments of this specification, by arranging a capping layer (CL) in the intermediate region (MA) between the display region (AA) and the opening region (OA) so as to surround the opening region (OA), moisture penetration can be prevented through the upper part of the insulating layer near the opening region (OA).

[0274] In this case, the capping layer (CL) is formed so as to surround the open area (OA) in a closed loop shape, thereby more effectively blocking the moisture permeation path.

[0275] In addition, the capping layer (CL) is arranged to cover the first blocking part (SPR1) with a double layer of the first capping layer (CL1) and the second capping layer (CL2), thereby more effectively blocking the upper moisture permeation path in the first blocking part (SPR1) on which the inorganic insulating layer is laminated.

[0276] In addition, the capping layer (CL) disposed on the insulating layer contains a metal material, which can reduce the propagation of cracks through the insulating layer, thereby providing a crack-resistant structure.

[0277] In this case, the capping layer (CL) is formed so as to surround the open area (OA) in a closed loop shape, thereby more effectively blocking the path along which the crack propagates.

[0278] Referring to FIG. 6, one end portion of the capping layer (CL) of the display device 1 according to an embodiment of the present specification may be located at the boundary between the second blocking portion (SPR2) and the cutting margin portion (TA).

[0279] Therefore, the capping layer (CL) may be arranged so as not to overlap the cutting margin portion (TA) in the vertical direction, and may be arranged at a predetermined distance from the opening area (OA).

[0280] The second capping layer (CL2) may extend further in the direction toward the opening area (OA) than the first capping layer (CL1) so as to surround the side of one end portion of the first capping layer (CL1) toward the opening area (OA).

[0281] For example, one end portion of the second capping layer (CL2) may be located at the boundary between the second blocking portion (SPR2) and the cutting margin portion (TA), and one end portion of the first capping layer (CL1) may be located inside the boundary portion of the cutting margin portion (TA).

[0282] In this way, since the capping layer (CL) is not placed in the cutting margin portion (TA), when a laser cutting process is performed to form the opening area (OA), there is no need to further consider or change the process conditions of the laser cutting process in order to further cut the capping layer (CL), which is advantageous in terms of process.

[0283] Furthermore, the second capping layer (CL2) may extend further in the opening area (OA) direction than the first capping layer (CL1), so that the second capping layer (CL2) is arranged to cover the side of the touch interlayer insulating layer (T-ILD) located on one end portion of the first capping layer (CL1).

[0284] As a result, the side surfaces of the touch interlayer insulating layer (T-ILD) do not need to be exposed to the outside due to the second capping layer (CL2), so that moisture permeation paths and crack paths that may occur through the touch interlayer insulating layer (T-ILD) can be more effectively blocked.

[0285] Referring to FIG. 7, one end of the capping layer (CL) of a display device 1 according to another embodiment of the present specification may be located at the boundary between the cutting margin (TA) and the opening area (OA).

[0286] In this case, one end portion of each of the first capping layer (CL1) and the second capping layer (CL2) may be located at the boundary between the cutting margin (TA) and the opening area (OA).

[0287] When a laser cutting process is performed to form the opening area (OA), such a structure may be formed by cutting the cutting margin portion (TA) including the capping layer (CL) together, so that one end portion of the capping layer (CL) is located at the boundary between the cutting margin portion (TA) and the opening area (OA).

[0288] In this way, the capping layer (CL) can extend further to the cutting margin (TA) so that one end of the capping layer (CL) coincides with the boundary where the opening area (OA) begins. Therefore, by positioning the capping layer (CL) from the point where the moisture permeation path and crack path begin, it is possible to more effectively block moisture permeation from above, as well as provide a structure that is resistant to cracks.

[0289] On the other hand, when a fine cutting process using a laser is performed to form the open area (OA), static electricity may be generated, and therefore a structure capable of discharging this static electricity to the outside is required.

[0290] In addition, when a capping layer (CL) containing a metal material is arranged to be floating, the voltage of the capping layer (CL) may fluctuate, which may cause touch noise, and a structure that can solve this problem is also required.

[0291] As a result, according to an embodiment of the present specification, the capping layer (CL) arranged to surround the opening area (OA) can be connected to ground or supplied with a power supply having a constant voltage so that the capping layer (CL) has a constant voltage.

[0292] Referring to FIGS. 8 to 10, one embodiment of the present specification will be described. The capping layer (CL) can be electrically connected to the crack detection wiring 60. FIG.

[0293] Since the crack detection wiring 60 is connected to the ground (GND), the capping layer (CL) can be connected to the ground (GND) via the crack detection wiring 60 and grounded.

[0294] For example, the crack detection wiring 60 located in the first blocking portion (SPR1) can be electrically connected to the first capping layer (CL1) through a first contact hole (CH1) penetrating the touch interlayer insulating layer (T-ILD).

[0295] The first contact hole (CH1) may be formed in a region that overlaps vertically with the underlying sealing layer (PCL), thereby being stably formed in a planarized region via the organic insulating layer.

[0296] In addition, the first capping layer (CL1) may be electrically connected to the second capping layer (CL2) through a second contact hole (CH2) that penetrates the touch inter-layer insulating layer (T-ILD).

[0297] The second contact hole (CH2) may be formed in a region that overlaps the dam 250 located below in the vertical direction, so that the second contact hole (CH2) may be stably formed in a planarized region via the organic insulating layer.

[0298] The crack detection wiring 60 may be arranged further outward than the static electricity prevention wiring 70 .

[0299] A touch sensor metal (TSM) may be disposed around the first capping layer (CL1) so as to surround the first capping layer (CL1).

[0300] For example, the touch sensor metal (TSM) may include a first touch sensor metal (TSM1) and a second touch sensor metal (TSM2).

[0301] The first touch sensor metal (TSM1) and the second touch sensor metal (TSM2) may be arranged alternately with each other.

[0302] In this case, the adjacent first touch sensor metals (TSM1) can be electrically connected to each other by the bridge metal (BRG) disposed below.

[0303] Additionally, the touch sensor metal (TSM) may further include a touch contact (TCL).

[0304] The touch connection part (TCL) is arranged adjacent to the first capping layer (CL1) more than the first touch sensor metal (TSM1) and the second touch sensor metal (TSM2), but may also be arranged at a predetermined distance to surround the first capping layer (CL1).

[0305] The first touch sensor metal (TSM1) and the second touch sensor metal (TSM2) can be electrically connected to each other by a touch connection (TCL).

[0306] The first touch sensor metal (TSM1), the second touch sensor metal (TSM2) and the touch connection (TCL) may be formed in the same layer using the same material.

[0307] Referring to FIGS. 11 to 13, in another embodiment of the present specification, the capping layer (CL) can be electrically connected to the static electricity prevention wiring 70. FIG.

[0308] Since the static electricity prevention wiring 70 is connected to the ground (GND), the capping layer (CL) can be connected to the ground (GND) via the static electricity prevention wiring 70 and grounded.

[0309] For example, the anti-static wiring 70 extending to the first blocking portion (SPR1) can be electrically connected to the first capping layer (CL1) through a third contact hole (CH3) penetrating the touch interlayer insulating layer (T-ILD).

[0310] The third contact hole (CH3) may be formed in a region that overlaps vertically with the underlying sealing layer (PCL), thereby being stably formed in a planarized region via the organic insulating layer.

[0311] In addition, the first capping layer (CL1) may be electrically connected to the second capping layer (CL2) through a second contact hole (CH2) that penetrates the touch inter-layer insulating layer (T-ILD).

[0312] The second contact hole (CH2) may be formed in a region that overlaps the dam 250 located below in the vertical direction, so that the second contact hole (CH2) may be stably formed in a planarized region via the organic insulating layer.

[0313] As a result, according to the embodiment of the present specification, by connecting the capping layer (CL) arranged to surround the opening area (OA) to ground (GND), static electricity generated during the cutting process to form the opening area (OA) can be discharged to the outside, thereby reducing the occurrence of pixel defects.

[0314] Furthermore, according to the embodiments of the present specification, by connecting the capping layer (CL) arranged to surround the opening area (OA) to ground (GND), the voltage of the capping layer (CL) can be made constant without fluctuating, thereby reducing the occurrence of touch noise in the touch display device.

[0315] The crack detection wiring 60 may be arranged further outward than the static electricity prevention wiring 70 .

[0316] Referring to FIGS. 14 to 16, another embodiment of the present specification will be described. The capping layer (CL) can be electrically connected to the power supply connection wiring 31. FIG.

[0317] For example, the power supply connection wiring 31 may be a high-potential voltage wiring or a low-potential voltage wiring.

[0318] The power supply connection wiring 31 may be disposed below the capping layer (CL).

[0319] For example, the power supply connection wiring 31 may be formed in the same layer as the first light blocking layer (BSM1) and made of the same material as the first light blocking layer (BSM1).

[0320] The power supply connection wiring 31 may be formed so as to pass through the first blocking portion (SPR1) and the dam portion (DM) and extend to the second blocking portion (SPR2).

[0321] The power supply connection wiring 31 located in the second blocking portion (SPR2) can be electrically connected to the first capping layer (CL1) through a fourth contact hole (CH4) that penetrates the buffer layer (BUF), the first interlayer insulating layer (ILD1), the second interlayer insulating layer (ILD2), the third interlayer insulating layer (ILD3), the first planarization layer (PLN1), the first passivation layer (PAS1), and the touch buffer layer (T-BUF).

[0322] In this case, a power supply connection electrode 32 is further formed between the power supply connection wiring 31 and the first capping layer (CL1), and the power supply connection wiring 31 and the first capping layer (CL1) can be electrically connected through the fourth contact hole (CH4).

[0323] The fourth contact hole (CH4) may be disposed between adjacent second blocking structures 220.

[0324] As a result, the power supply connection electrode 32 formed in the fourth contact hole (CH4) may be disposed between the second blocking structures 220 adjacent to each other.

[0325] Therefore, the separation distance between the second blocking structures 220 through the fourth contact hole (CH4) may be greater than the separation distance between the other second blocking structures 220 in which the fourth contact hole (CH4) is not formed.

[0326] In addition, the first capping layer (CL1) may be electrically connected to the second capping layer (CL2) through a fifth contact hole (CH5) that penetrates the touch inter-layer insulating layer (T-ILD).

[0327] In this case, the fifth contact hole (CH5) may be arranged so as to overlap the fourth contact hole (CH4) in the vertical direction.

[0328] This allows the second capping layer (CL2) to be electrically connected to the power supply connecting wiring 31 via the first capping layer (CL1).

[0329] The power supply connection wiring 31, the power supply connection electrode 32, the first capping layer (CL1), and the second capping layer (CL2) formed in this manner are sequentially stacked so as to contact each other, thereby insulating the insulating layer located above.

[0330] The crack detection wiring 60 may be arranged further outward than the static electricity prevention wiring 70 .

[0331] In this way, according to the embodiments of the present specification, the capping layer (CL) can block the insulating layer using a structure that connects it to the power supply connection wiring 31 arranged below via the power supply connection electrode 32, and therefore can function as a further crack propagation prevention structure that can block cracks from propagating through the insulating layer.

[0332] In addition, according to the embodiments of the present specification, by supplying a power source having a constant voltage to the capping layer (CL) arranged to surround the opening area (OA), static electricity generated during the cutting process to form the opening area (OA) can be discharged to the outside, thereby reducing the occurrence of pixel defects.

[0333] In addition, according to the embodiments of the present specification, by supplying a power source having a constant voltage to the capping layer (CL) arranged to surround the opening area (OA), the voltage of the capping layer (CL) is constant and does not fluctuate, thereby reducing the occurrence of touch noise in the touch display device.

[0334] As described above, the display device according to the embodiment of the present specification can be explained as follows.

[0335] A display device according to an embodiment of the present specification includes a substrate including a display area, an opening area located within the display area, and an intermediate area located between the display area and the opening area, and a capping layer including a metal material, which is disposed in the intermediate area and surrounds the opening area in a closed loop, and the capping layer is connected to ground or is supplied with a power source having a constant voltage.

[0336] The display device may further include a crack detection wiring or an anti-static wiring, at least a portion of which is disposed in the intermediate region, and the capping layer may be electrically connected to the crack detection wiring or the anti-static wiring and connected to ground.

[0337] The capping layer includes a first capping layer and a second capping layer spaced apart from the first capping layer, and the second capping layer may be electrically connected to the crack detection wiring or the anti-static wiring via the first capping layer.

[0338] The semiconductor device may further include a power supply connection wiring disposed under the capping layer, the capping layer being electrically connected to the power supply connection wiring and having the same voltage as the power supply connection wiring.

[0339] The power supply connection wiring may be a high potential voltage wiring or a low potential voltage wiring.

[0340] The capping layer includes a first capping layer and a second capping layer spaced apart from the first capping layer, and the second capping layer can be electrically connected to the power supply connection wiring via the first capping layer.

[0341] In addition, a display device according to an embodiment of the present specification includes a substrate including a display area, an opening area located within the display area, and an intermediate area located between the display area and the opening area, one or more blocking portions arranged in the intermediate area, one or more insulating layers arranged to cover the one or more blocking portions, and a capping layer including a metal material arranged in the intermediate area to cover at least one or more of the blocking portions and surround the opening area, wherein the capping layer is connected to ground or is supplied with a power source having a constant voltage.

[0342] The display device may further include a dam portion arranged in the intermediate region, the blocking portion including a first blocking portion arranged between the dam portion and the display region and a second blocking portion arranged between the dam portion and the opening region, the capping layer being arranged to cover the second blocking portion and the dam portion, and the first blocking portion being arranged to cover at least a portion of the region.

[0343] The capping layer may include a first capping layer and a second capping layer spaced apart from the first capping layer, and the first capping layer and the second capping layer may have a closed loop shape.

[0344] The second capping layer may have an area greater than that of the first capping layer.

[0345] The semiconductor device may further include a crack detection wiring or an anti-static wiring disposed in the intermediate region, and the first capping layer may be electrically connected to the crack detection wiring or the anti-static wiring and connected to ground.

[0346] The first capping layer and the second capping layer are electrically connected through a contact hole, and the second capping layer can be electrically connected to the crack detection wiring or the anti-static wiring through the first capping layer.

[0347] The semiconductor device further includes a power supply connection wiring disposed under the insulating layer and supplied with the power, and a power supply connection electrode penetrating the insulating layer and having one side and the other side connected to the first capping layer and the power supply connection wiring, respectively, and the first capping layer can be electrically connected to the power supply connection wiring via the power supply connection electrode.

[0348] The second blocking section may include a plurality of blocking structures arranged in one direction, and the power supply connection electrode may be disposed between the plurality of blocking structures adjacent to each other.

[0349] The first capping layer can be electrically connected to the second capping layer in a region that overlaps in the vertical direction with a contact hole that connects the power supply connection electrode and the first capping layer.

[0350] The power supply connecting wire, the power supply connecting electrode, the first capping layer, and the second capping layer may be sequentially stacked to isolate the insulating layer.

[0351] The touch panel may further include a touch electrode layer disposed on the substrate and including a first touch electrode and a second touch electrode, wherein the first touch electrode is disposed on the same layer as the first capping layer and the second touch electrode is disposed on the same layer as the second capping layer.

[0352] The second capping layer may extend further in a direction toward the opening region than the first capping layer so as to surround a side surface of an end portion of the first capping layer that faces the opening region.

[0353] Although the embodiments of the present specification have been described in detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications are possible within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to explain, not limit, the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not limiting. [Explanation of symbols]

[0354] 1 Display device 10 Substrate 20 Data drive circuit 30 Power wiring 31 Power supply connection wiring 32 Power supply connection electrode 40 Gate driver 50 Flexible Circuit Board 51 Printed Circuit Board 60 Crack detection wiring 61 Crack detection pad 70 Anti-static wiring 71 Anti-static pad OA1 1st optical area OA2 2nd optical area

Claims

1. a substrate including a display area, an opening area located within the display area, and an intermediate area located between the display area and the opening area; a capping layer disposed in the intermediate region, surrounding the opening region in a closed loop shape, the capping layer including a metal material; Including, The capping layer is connected to ground or to a power supply having a predetermined voltage. Display device.

2. Further comprising a crack detection wiring or an anti-static wiring, at least a portion of which is disposed in the intermediate region; the capping layer is electrically connected to the crack detection wiring or the anti-static wiring and is connected to ground; The display device according to claim 1 .

3. the capping layer includes a first capping layer and a second capping layer disposed on the first capping layer at a distance; the second capping layer is electrically connected to the crack detection wiring or the static electricity prevention wiring via the first capping layer; The display device according to claim 2 .

4. The capping layer further includes a power supply connection wiring disposed below the capping layer, the capping layer is electrically connected to the power supply connection wiring and has the same voltage as the power supply connection wiring; The display device according to claim 1 .

5. The power supply connection wiring is a high-potential voltage wiring or a low-potential voltage wiring. The display device according to claim 4 .

6. the capping layer includes a first capping layer and a second capping layer disposed on the first capping layer at a distance; the second capping layer is electrically connected to the power supply connection wiring via the first capping layer; The display device according to claim 5 .

7. a substrate including a display area, an opening area located within the display area, and an intermediate area located between the display area and the opening area; one or more interrupters disposed in the intermediate region; one or more insulating layers disposed over the one or more interrupters; a capping layer including a metal material, the capping layer being disposed in the intermediate region so as to cover at least one of the blocking portions and surround the opening region; Including, The capping layer is connected to ground or to a power supply having a predetermined voltage. Display device.

8. Further comprising a dam portion disposed in the intermediate region, The blocking portion includes a first blocking portion disposed between the dam portion and the display area, and a second blocking portion disposed between the dam portion and the opening area. Including, the capping layer is disposed so as to cover the second blocking portion and the dam portion, and the first blocking portion is disposed so as to cover at least a part of the region. The display device according to claim 7 .

9. the capping layer includes a first capping layer and a second capping layer disposed on the first capping layer at a distance; The first capping layer and the second capping layer have a closed loop shape. The display device according to claim 8 .

10. The second capping layer has a larger area than the first capping layer. The display device according to claim 9 .

11. Further comprising a crack detection wiring or an anti-static wiring disposed in the intermediate region; the first capping layer is electrically connected to the crack detection wiring or the anti-static wiring and is connected to ground; The display device according to claim 9 .

12. the first capping layer and the second capping layer are electrically connected to each other through a contact hole, and the second capping layer is electrically connected to the crack detection wiring or the static electricity prevention wiring through the first capping layer. The display device according to claim 11.

13. a power supply connection electrode disposed under the insulating layer and receiving the power; and a power supply connection electrode penetrating the insulating layer and connected at one side to the first capping layer and the power supply connection electrode at the other side, respectively; the first capping layer is electrically connected to the power supply connecting wiring via the power supply connecting electrode; The display device according to claim 9 .

14. the second blocking portion includes a plurality of blocking structures arranged in one direction, the power supply connection electrode is disposed between the plurality of blocking structures adjacent to each other; The display device according to claim 13.

15. the first capping layer is electrically connected to the second capping layer in a region that overlaps in a vertical direction with a contact hole through which the power supply connection electrode and the first capping layer are connected; The display device according to claim 13.

16. the power supply connecting wiring, the power supply connecting electrode, the first capping layer, and the second capping layer are sequentially stacked to isolate the insulating layer; The display device according to claim 15.

17. a touch electrode layer disposed on the substrate, the touch electrode layer including a first touch electrode and a second touch electrode; the first touch electrode is disposed in the same layer as the first capping layer; The second touch electrode is disposed in the same layer as the second capping layer. The display device according to claim 9 .

18. the second capping layer extends further in a direction toward the opening region than the first capping layer so as to surround a side surface of an end portion of the first capping layer toward the opening region; The display device according to claim 9 .

19. a cutting margin portion disposed in the intermediate region of the substrate between the second blocking portion and the opening region; The capping layer is disposed so as not to overlap the cutting margin portion in the vertical direction and is spaced a predetermined distance from the opening region. The display device according to claim 8 .

20. a cutting margin portion disposed in the intermediate region of the substrate between the second blocking portion and the opening region; one end portion of the first capping layer and one end portion of the second capping layer are located at a boundary between the cutting margin portion and the opening region; The display device according to claim 9 .

21. Each of the one or more blocking sections is composed of a plurality of blocking structures formed in a two-layer structure including a lower structure and an upper structure disposed on the lower structure, the blocking structure defines an undercut structure below the overlying structure and adjacent to the underlying structure, the undercut structure blocking an emissive layer extending between adjacent blocking structures; The display device according to claim 7 .

22. The lower structure and the upper structure have a tapered shape in which the width decreases toward the upper side. The display device according to claim 21.

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