Information processing system, information processing apparatus, and program

Abstract

To improve the power-saving effect of a processor without missing any received packets, as compared with a case where the processor is periodically restored from a stopped state in order to execute processing related to packets.SOLUTION: A CPU sets an unprocessed flag provided for each piece of data corresponding to a packet 22 by non-periodic processing executed in response to an interrupt caused by reception of the packet 22 under control of an OS kernel when operating in a power-saving mode. The CPU clears the unprocessed flag of the data when the data composed of packets is completed by periodic processing executed in response to a periodic interrupt from a timer. The CPU permits execution of the periodic processing while at least one unprocessed flag is set, and prohibits execution of the periodic processing and stops operation when all of the unprocessed flags are cleared.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an information processing system, an information processing device, and a program. [Background technology]

[0002] Many multifunction peripherals have a function that automatically switches to a power-saving mode to reduce power consumption if the peripheral remains inactive for a predetermined period of time during normal operation. In other words, multifunction peripherals have a power-saving mode, which operates in a power-saving state, separate from the normal mode during normal operation. When a user operates the operation panel while the multifunction peripheral is operating in the power-saving mode, the multifunction peripheral automatically returns from the power-saving mode, switches the operating mode from the power-saving mode to the normal mode, and returns the multifunction peripheral to the normal state in which it can be used.

[0003] Incidentally, power saving levels vary depending on the specifications of the multifunction device, and there are various levels, such as limiting the usable functions of peripheral devices such as the printer unit and scanner unit, cutting off the power supply to peripheral devices, and even cutting off the power supply to the CPU and memory controller.

[0004] Incidentally, a multifunction peripheral may receive requests from an information processing device such as a personal computer (hereinafter referred to as "PC") via a network to check the status of the multifunction peripheral or to perform processing such as printing. Therefore, even in a power-saving state where there has been no operation on the operation panel for a predetermined period of time, it becomes necessary for the multifunction peripheral to respond to requests via the network.

[0005] To achieve this, the controller in a conventional multifunction printer performs two types of processing, which can be broadly divided into periodic processing and non-periodic processing, under the control of the operating system (hereinafter referred to as "OS"), thereby performing power-saving control that further reduces the small amount of power consumption by repeatedly starting and stopping even when in power-saving mode.

[0006] Incidentally, periodic processing is processing that is released from a stopped state by a periodic timer interrupt. Non-periodic processing is processing that is released from a stopped state by an interrupt such as packet reception. When the stopped state is released, the controller processes received packets and packets waiting to be processed in order. When the controller enters a state where there is nothing to do, generally known as an idle state, even if only for a short time, it transitions to a stopped state to reduce power consumption. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-075687 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-282398 Summary of the Invention [Problem to be solved by the invention]

[0008] As previously mentioned, periodic processing allows the processor to periodically wake up from a halted state to perform processing associated with packets received by aperiodic processing.

[0009] However, in the past, even when there were no packets to be processed because no new packets had been received, the processor was restored from the stopped state by unconditionally executing periodic processing.

[0010] The present invention aims to improve the power saving effect of a processor without missing any received packets, compared to when the processor is always periodically woken up from a stopped state to execute packet-related processing. [Means for solving the problem]

[0011] The information processing system of the present invention comprises a processor, which periodically returns from a stopped state to execute packet-related processing as periodic processing, and returns from a stopped state in response to an interrupt associated with the reception of a packet to execute packet-related processing as non-periodic processing, and stops when there are no more packets to process and does not execute the periodic processing.

[0012] The processor is also characterized in that it returns from a stopped state in response to the interrupt, sets a first flag that allows the periodic processing to be executed, and clears the first flag and stops the processing when there are no more packets to be processed in the periodic processing.

[0013] The processor is characterized in that it does not stop until all of the first flags that are set in association with data that includes one or more packets are cleared.

[0014] The processor is also characterized in that even if there are no more packets to process, it continues to execute the periodic processing without stopping until the software that processes the data generated by one or more packets has completed processing the data.

[0015] The processor is also characterized in that, when the generation of the data is completed, it sets a second flag indicating that the processing of the data by the software is incomplete, clears the second flag when the processing of the data by the software is completed, and executes the periodic processing without stopping while the second flag is set.

[0016] The processor is also characterized in that it returns from a stopped state in response to the interrupt, sets a first flag that allows execution of the periodic processing, clears the first flag when there are no more packets to process in the periodic processing, and stops only when both the first flag and the second flag are cleared.

[0017] An information processing device according to the present invention includes the information processing system described above.

[0018] The program of the present invention enables a computer to realize the following functions: periodically returning from a stopped state and executing packet-related processing as periodic processing; returning from a stopped state in response to an interrupt associated with the reception of a packet and executing packet-related processing as non-periodic processing; and stopping and not executing the periodic processing when there are no more packets to process. [Effects of the Invention]

[0019] According to the invention described in claim 1, the power saving effect of the processor can be improved without missing any received packets, compared to when the processor is always periodically restored from a stopped state to execute packet-related processing.

[0020] According to the invention as recited in claim 2, it is possible to control the restart / stop of the processor depending on the state of the first flag.

[0021] According to the invention as set forth in claim 3, the process can be stopped only after the process for the packets corresponding to all the data has been completed.

[0022] According to the invention as set forth in claim 4, periodic processing can be continuously executed without stopping the processor while data needs to be processed.

[0023] According to the invention as set forth in claim 5, periodic processing can be executed until the software completes processing of the data.

[0024] According to the invention of claim 6, even if there are no more packets to process, periodic processing can be performed without stopping the processor until processing of the data generated from the packets is completed.

[0025] According to the invention described in claim 7, the power saving effect of the processor can be improved without missing any received packets, compared to when the processor is always periodically restored from a stopped state to execute packet-related processing.

[0026] According to the invention described in claim 8, the power saving effect of the processor can be improved without missing any received packets, compared to when the processor is always periodically restored from a stopped state to execute packet-related processing. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic block diagram showing a hardware configuration of a multifunction peripheral according to an embodiment of the present invention; [Figure 2] 10A and 10B are diagrams illustrating transitions in power consumption that change with transitions in operation modes in the present embodiment. [Figure 3A] FIG. 10 is a diagram illustrating the execution state of conventional periodic processing in a state where only the controller is operable. [Figure 3B] FIG. 10 is a diagram showing the execution state of periodic processing according to the present embodiment in a state in which only the controller is operable. [Figure 4] FIG. 2 is a conceptual diagram showing execution control of periodic processing in an OS in this embodiment. [Figure 5] FIG. 10 is a conceptual diagram showing execution control of periodic processing in an OS when data processing in an application is taken into consideration in this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[0029] FIG. 1 is a schematic block diagram showing the hardware configuration of a multifunction peripheral 10 according to the present embodiment. The multifunction peripheral 10 is a form of image forming device, and is a device equipped with various functions such as a printing function, a copying function, a scanning function, and the like, and having a built-in computer. The multifunction peripheral 10 includes a control panel 11, a communication interface (IF) 12, a printing unit 13, and a controller 14. The multifunction peripheral 10 according to the present embodiment may have the same hardware configuration as conventional multifunction peripherals 10. For example, the multifunction peripheral 10 includes a scanner and storage means such as an HDD (Hard Disk Drive) to provide a scanning function (not shown), but components not used in the description of the present embodiment are omitted from FIG. 1.

[0030] The control panel 11 is a user interface that receives instructions from the user and displays information. The communication interface 12 is a communication means that performs data communication with other devices via a network 2 such as a LAN (Local Area Network) or the Internet. The printing unit 13 includes a fixing unit, heater, paper transport unit, etc., and is a printing means that performs printing.

[0031] The controller 14 is a control board that mounts a panel control circuit 141, a communication control circuit 142, a print control circuit 143, a CPU 144, a memory 145, a DMA (Direct Memory Access) controller 146, and a timer 147. Note that components of the controller 14 that are not used in the description of this embodiment are omitted from FIG.

[0032] The panel control circuit 141 controls the operation of the control panel 11. The communication control circuit 142 controls the operation of the communication interface 12. The print control circuit 143 controls the operation of the print unit 13. In this embodiment, each of the control circuits 141 to 143 controls the supply of power to the components 11 to 13 connected thereto.

[0033] The CPU 144 is a form of processor, and controls the operation of various mechanisms installed in the multifunction device 10, such as the printing unit 13, by issuing instructions to each control circuit 141-143 in accordance with an operating system (hereinafter referred to as "OS") or various libraries and applications (hereinafter simply referred to as "apps") loaded into the memory 145.

[0034] Software such as an OS and applications is loaded into memory 145 and executed by CPU 144. Memory 145 in this embodiment is formed by DRAM (Dynamic RAM). DRAM is a volatile semiconductor memory device. The DRAM in this embodiment can operate in self-refresh mode. "Self-refresh mode" is a method in which a refresh command signal is automatically generated inside the DRAM when the DRAM is not operating, and a refresh operation is performed. "Refresh" refers to the operation of periodically rewriting data while the DRAM is operating by periodically replenishing charge in memory cells. Refreshing preserves data in the DRAM without erasing it, and is also expected to have a power-saving effect. Since power is no longer supplied to the DRAM when the DRAM in this embodiment transitions to power-saving mode, it is subject to refresh control in power-saving mode.

[0035] The DMA controller 146 is a control board that controls DMA, i.e., direct data transfer between memories or between a memory and an I / O device by executing a group of programmed machine language instructions without using an accumulator or the like. The timer 147 issues an interrupt to the CPU 144. In this embodiment, the timer 147 is provided to issue an interrupt in a hardware manner, but the interrupt may also be issued in a software manner.

[0036] The power supply control in the multifunction device 10 described below is mainly realized by a kernel (hereinafter also referred to as "OS kernel"), which is the core of the OS. The OS used in this embodiment is naturally pre-installed in the multifunction device 10, but it can also be provided via communication means or stored in a computer-readable recording medium such as a USB memory.

[0037] Similar to conventional multifunction devices, the multifunction device 10 of this embodiment can operate in two modes: a normal mode in which the functions of devices such as the print unit 13 can be performed normally; and a power-saving mode or sleep mode (hereinafter referred to as "power-saving mode") in which the device automatically switches to a power-saving state to reduce power consumption if no operation is performed for a predetermined period of time while operating in the normal mode. The power-saving state can take various power-saving levels. The relationship between the operating mode and power consumption in this embodiment will now be described with reference to FIG. 2.

[0038] Fig. 2 is a diagram showing the transition of power consumption that changes with the transition of operation modes in this embodiment. In Fig. 2, the horizontal axis represents time, and the vertical axis represents power consumption. In Fig. 2, the power consumption during times t0 to t1 and t3 to t4 when the multifunction peripheral 10 is operating in normal mode is shown as being constant, but Fig. 2 simply shows that the power consumed is relatively greater than in power saving mode, and does not indicate that the actual power consumption is constant.

[0039] When the multifunction peripheral 10 is in the normal mode and does not operate for a predetermined period of time, it automatically switches to the power saving mode at time t1. In this embodiment, power saving is performed in stages in the power saving mode. That is, at time t1, the panel control circuit 141 and the print control circuit 143 in the controller 14 stop supplying power to the control panel 11 and the print unit 13, stopping the display on the control panel 11 and making the print unit 13 unavailable for immediate use. However, power to the controller 14 continues.

[0040] When this state continues for a predetermined time and reaches time t2, power to the controller 14 is also stopped. As a result, the memory 145 realized by DRAM starts a self-refresh operation. However, if power to the controller 14 is constantly stopped, processing related to packets sent via the network 2 cannot be performed, which may result in missed reception.

[0041] Therefore, the OS kernel turns on the communication control circuit 142, maintaining it in a state where it can constantly receive packets transmitted via the network 2. The CPU 144 in this embodiment executes periodic and non-periodic processing under the control of the OS kernel. In periodic processing, the CPU 144 periodically resumes from a stopped state in response to a periodic interrupt from the timer 147 and executes packet-related processing. In non-periodic processing, the CPU 144 resumes from a stopped state in response to an interrupt associated with packet reception and executes packet-related processing. When the stopped state is released, the controller 14 supplies power to the CPU 144 so that it can sequentially process received packets or received packets awaiting processing. The illustration of the increase and decrease in power consumption between times t2 and t3 indicates that power supply to the CPU 144 causes the CPU 144 to execute packet-related processing through periodic and non-periodic processing. Since power consumption can be reduced during the period between times t2 and t3 when power consumption is decreasing, further power-saving effects can be expected in power-saving mode.

[0042] Then, when an event occurs that necessitates cancellation of the power saving mode, such as the user operating the control panel 11 while the multifunction device 10 is operating in the power saving mode (occurs at time t3), the operating mode of the multifunction device 10 switches from the power saving mode to the normal mode.

[0043] In this embodiment, the power saving mode is formed into two power saving states as shown in Fig. 2, but this is just an example, and power control in the power saving mode may be different from that shown in Fig. 2. However, this embodiment is premised on power supply control being performed from time t2 to t3. The operation of the controller 14 from time t2 to t3 will be further explained using Figs. 3A and 3B. Note that when an explanation is common to Figs. 3A and 3B, it will be referred to as "Fig. 3."

[0044] In Fig. 3, the horizontal axis represents time and the vertical axis represents power consumption. Fig. 3 illustrates a portion of times t2 to t3 in Fig. 2. Fig. 3A shows that CPU 144 is performing periodic processing at times T1 and T2. That is, CPU 144 is supplied with power in response to a timer interrupt and consumes power. Fig. 3B shows that CPU 144 is performing periodic processing only at time T2. Then, at time T3 between times T1 and T2, CPU 144 is supplied with power in response to an interrupt due to packet reception and consumes power.

[0045] Incidentally, periodic processing involves processing packets waiting to be processed (hereinafter, "unprocessed packets"). Conventionally, even if there are no unprocessed packets, CPU 144 has been made to continuously execute periodic processing without stopping it. If there are no unprocessed packets, there is no need to supply power to CPU 144 to execute periodic processing. For example, if there are no unprocessed packets at time T1, power is not supplied to execute periodic processing as shown in FIG. 3A, and power is not supplied to CPU 144 as shown in FIG. 3B, thereby achieving further power savings.

[0046] Therefore, in this embodiment, the execution of periodic processing is controlled to further improve the power saving effect.

[0047] 4 is a conceptual diagram showing the execution control of periodic processing in processing performed by the OS kernel (hereinafter also referred to as "kernel processing") in this embodiment. In FIG. 4, the vertical direction of the drawing indicates the flow of time, and time flows from top to bottom of the drawing.

[0048] The OS kernel is in a wait state until an IO interrupt occurs. The DRAM is in a self-refresh state. When an IO interrupt occurs, for example, when the DMA controller 146 receives a packet 22, the OS kernel causes the CPU 144 to execute asynchronous processing in response to the IO interrupt. For convenience, FIG. 4 illustrates multiple packets 22 sent consecutively at a certain point in time (T3 in FIG. 3) as if they were received together. However, this illustrates that, as in the conventional case, packets 22 sent via the network 2 are simply received in a non-periodic process.

[0049] A feature of this embodiment is that, when a packet 22 is received, an unprocessed flag is provided for each received data consisting of that packet 22, and processing is performed to set the unprocessed flag. The "unprocessed flag" is a first flag that returns from a stopped state in response to an interrupt associated with packet reception and indicates whether execution of periodic processing is permitted or prohibited. In this embodiment, a state in which the unprocessed flag is set means that an unprocessed packet 22 exists, and therefore execution of periodic processing to process that packet 22 is permitted. On the other hand, a state in which the unprocessed flag is cleared means that an unprocessed packet 22 does not exist, and therefore there is no need to execute periodic processing to process that packet 22, and therefore execution of periodic processing is prohibited. Note that periodic processing is performed by an interrupt from the timer 147, so prohibiting execution of periodic processing and prohibiting a timer interrupt are synonymous.

[0050] When the OS kernel executed by the CPU 144 receives a packet 22 (step S110), it analyzes the received packet 22 to identify the data included in the packet 22. At this time, if the OS kernel recognizes that it has received a packet associated with new data, it creates an unprocessed flag corresponding to the data and sets it to a set state (step S120). If there is at least one set unprocessed flag, the OS kernel permits execution of periodic processing (step S130). In the example shown in FIG. 4, when the packet 22 of data A is first received, the unprocessed flag corresponding to data A is set, thereby permitting execution of periodic processing. If the received packet 22 is not a packet 22 of new data, the unprocessed flag corresponding to the data of the packet 22 has already been created and set, so no processing is required to set the unprocessed flag. The self-refresh operation in the DRAM is stopped upon reception of the packet 22.

[0051] FIG. 4 shows that packets 22 corresponding to three pieces of data A, B, and C have been received, and that the corresponding unprocessed flags have been set.

[0052] If at least one of the existing unprocessed flags is set, execution of periodic processing is permitted, and the OS kernel executes packet filtering processing on the received packets 22 in the periodic processing (step S140). "Packet filtering processing" is one of the network control functions possessed by communication devices and computers, and refers to the process of accepting or discarding data (i.e., packets) received from the outside according to certain criteria set by an administrator or the like. Therefore, in the periodic processing, received data is generated by performing packet filtering processing. In the example shown in Figure 4, data A, B, and C are generated.

[0053] Here, when one piece of data is completed (step S150), the OS kernel clears the unprocessed flag corresponding to that data (step S160). Note that the state of the unprocessed flag being cleared is equivalent to the fact that there are no packets to be processed for that data in the periodic processing. Note that the OS kernel may delete the cleared unprocessed flag. If there is even one unprocessed flag set when the unprocessed flag is cleared, the execution of the periodic processing remains permitted. In FIG. 4, the unprocessed flag corresponding to data C is cleared when data C is completed. However, when the last data C is completed, all of the unprocessed flags set corresponding to data A, B, and C are cleared (step S160A), and there are no unprocessed packets 22. In this way, the OS kernel executed by the CPU 144 prohibits the execution of the periodic processing only after all of the unprocessed flags are cleared (step S170).

[0054] The CPU 144 is in a haltable state because there is no processing to be performed in the periodic processing until an IO interrupt occurs in response to packet reception. In this embodiment, by prohibiting the execution of periodic processing, the CPU 144 does not execute the periodic processing. This allows the power supply to the CPU 144 to be stopped, thereby improving the power saving effect. Furthermore, a self-refresh operation in the DRAM is started.

[0055] In the past, periodic processing was executed as shown in FIG. 3A even when there were no packets to be processed (time T1 in FIG. 3), but in this embodiment, periodic processing is prohibited and control is exercised so that periodic processing is not executed as shown in FIG. 3B, so that CPU 144 can be stopped, thereby improving the power saving effect.

[0056] Incidentally, in order to perform externally requested processing on the received data (above data A, B, and C) generated by performing packet filtering processing, it may be necessary to separately execute higher-level application software (hereinafter simply referred to as "application" or "app") that provides network service processing. In this case, if the execution of periodic processing is prohibited, the received data cannot be processed by the application. Therefore, in this embodiment, the execution of periodic processing is controlled taking into consideration the data processing in the application. Note that the received data processed by the application is generated from packets, so the processing executed by the application corresponds to processing related to packets.

[0057] Fig. 5 is a conceptual diagram showing execution control of periodic processing in kernel processing when data processing in an application is taken into consideration in this embodiment. The vertical direction in the drawing indicates the flow of time, with time flowing from top to bottom of the drawing. The kernel processing shown in Fig. 5 is the same as the kernel processing described using Fig. 4, but for convenience, some parts are omitted in the illustration. Also, Fig. 5 focuses on processing for data A, and processing for data B and C is omitted as appropriate.

[0058] When Data A is completed, the unprocessed flag corresponding to Data A is cleared as described above (step S160). Furthermore, when the OS kernel determines that an application (hereinafter referred to as "Application A") that processes Data A needs to be executed, it allows Application A to be executed and creates and sets an incomplete flag corresponding to Application A (step S210). The "incomplete flag" is a second flag indicating an incomplete state of data processing. The incomplete flag being set indicates that processing in the application is incomplete, i.e., data processing in the application is not completed. On the other hand, the incomplete flag being cleared indicates that data processing in the application is completed. The absence of an incomplete flag indicates that processing in the application is completed or that the application is not running. Furthermore, since an application (e.g., "Application A") processes specific received data (e.g., "Data A"), the incomplete flag can be said to be set corresponding to either the application or the data.

[0059] Application A is started by the OS (step S220), acquires Data A, and performs predetermined data processing (step S230). After completing the processing of Data A, Application A sends the processing result to the OS kernel (step S240), and then enters a state of waiting for a response (step S250).

[0060] The OS kernel writes the processing result received from application A to a predetermined storage area in memory 145 used by DMA controller 146, thereby causing DMA controller 146 to perform DMA transfer to the sender of data A (step S260). After that, when it receives a notification such as a notification that reception of the processing result sent from the sender of data A has been completed (step S270), it sends the notified content to application A.

[0061] Application A, which has been waiting for a response, receives a notification from the OS kernel (step S280) and completes the data processing (step S290).

[0062] When application A completes processing of data A, the OS kernel clears the incomplete flag corresponding to application A (step S300). The OS kernel may delete the cleared incomplete flag.

[0063] In this way, the incompletion flag set corresponding to data A generated by the packet filtering process is set and cleared. The incompletion flags set corresponding to data B and data C are similarly set / cleared.

[0064] It should be noted that in FIG. 4, the execution of periodic processing is prohibited when all of the unprocessed flags are cleared (step S160A). However, as explained with reference to FIG. 5, it is not desirable to prohibit the execution of periodic processing at this point in time, considering the data processing in the application. That is, it is preferable to allow application software that processes data generated by one or more packets to continue executing the data until the processing is completed. Furthermore, if multiple applications are simultaneously executing data processing in parallel, it is preferable to have the CPU 144 continue executing the periodic processing until the execution of all applications is completed. That is, the OS kernel allows the execution of periodic processing without prohibiting it while at least one uncompleted flag is set (step S310). The OS kernel then prohibits the execution of periodic processing only after all of the unprocessed flags have been cleared, the execution of all applications has been completed, and all of the uncompleted flags have been cleared (step S320), and stops power to the CPU 144.

[0065] Incidentally, in the present embodiment, the execution control of periodic processing by CPU 144 described above is only possible when an IO interrupt occurs and packets can be received through non-periodic processing. However, in the case of DHCP (Dynamic Host Configuration Protocol), the client (in this embodiment, multifunction peripheral 10) must actively request the assignment of an IP address, and therefore controller 14 cannot be stopped until the IP address is transmitted from the server and confirmed. As described above, when no packets are received from the outside and no applications are running, CPU 144 is stopped, and it may not be possible to properly acquire an IP address.

[0066] Therefore, when using the DHCP service, the condition for prohibiting execution of periodic processing (i.e., the condition for stopping the CPU 144) is added to the condition of the connection state with the network 2, rather than the execution state of the application. For example, the connection state of the LAN cable may be monitored, and control may be exercised so that execution of the above-mentioned periodic processing is prohibited only when the LAN cable is not connected to the multifunction device 10, or only while the IP address is determined so that packets can be received even when the LAN cable is connected to the multifunction device 10.

[0067] As mentioned above, the "information processing system" in this embodiment has been described as being configured by a single multifunction peripheral 10 as an example, but it may be configured by one or more information processing devices. Furthermore, instead of the multifunction peripheral 10, which is one form of image forming device, it may also be realized by an information processing device such as a PC connectable to the network 2.

[0068] In the above embodiments, the term "processor" refers to a processor in a broad sense, and includes general-purpose processors (e.g., CPU: Central Processing Unit, etc.) and dedicated processors (e.g., GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, FPGA: Field Programmable Gate Array, programmable logic device, etc.).

[0069] Furthermore, the operations of the processors in the above embodiments may not only be performed by a single processor, but may also be performed by multiple processors located at physically separate locations working together. Furthermore, the order of the operations of the processors is not limited to the order described in the above embodiments, and may be changed as appropriate.

[0070] (Addendum) (((1))) a processor; The processor: periodically returning from a stopped state to execute packet-related processing as periodic processing, and also returning from a stopped state in response to an interrupt associated with packet reception to execute packet-related processing as non-periodic processing; When there are no more packets to process, the process stops and the periodic process is not executed. An information processing system comprising: (((2))) The processor: set a first flag that returns from a stopped state in response to the interrupt and permits execution of the periodic processing; clearing the first flag and stopping the periodic processing when there are no more packets to be processed in the periodic processing; The information processing system according to (((1))) is characterized in that: (((3))) The information processing system described in (((2))) is characterized in that the processor stops only when all of the first flags set in association with each piece of data containing one or more packets are cleared. (((4))) The information processing system described in any one of (((1))) to (((3))) is characterized in that the processor continues to execute the periodic processing without stopping until software that processes data generated by one or more packets has completed processing the data, even if there are no more packets to process. (((5))) The processor: When the generation of the data is completed, a second flag is set to indicate an incomplete state of the processing of the data by the software; clearing the second flag when the software has completed processing the data; The periodic process is executed without stopping while the second flag is set. The information processing system according to (((4))) is characterized in that: (((6))) The processor: set a first flag that returns from a stopped state in response to the interrupt and permits execution of the periodic processing; clearing the first flag when there are no more packets to be processed in the periodic processing; The operation stops only when both the first flag and the second flag are cleared. The information processing system according to (((5))) is characterized in that: (((7))) An information processing device comprising the information processing system according to any one of ((1))) to (((6))). (((8))) On the computer, a function of periodically returning from a stopped state to execute packet-related processing as periodic processing, and also returning from a stopped state in response to an interrupt associated with packet reception to execute packet-related processing as non-periodic processing; A function of stopping and not executing the periodic processing when there are no more packets to process; A program to achieve this.

[0071] According to the invention described in (((1))), it is possible to improve the power saving effect of the processor without missing any received packets, compared to when the processor is always periodically restored from a stopped state to execute packet-related processing. According to the invention described in (((2))), it is possible to control the restart / stop of the processor depending on the state of the first flag. According to the invention described in (((3))), the process can be stopped only after the process for the packets corresponding to all the data has been completed. According to the invention described in (((4))), periodic processing can be continuously executed without stopping the processor while data needs to be processed. According to the invention described in (((5))), periodic processing can be executed until the software completes processing of the data. According to the invention described in (((6))), even if there are no more packets to process, periodic processing can be performed without stopping the processor until processing of the data generated from the packets is completed. According to the invention described in (((7))), it is possible to improve the power saving effect of the processor without missing any received packets, compared to when the processor is always periodically restored from a stopped state to execute packet-related processing. According to the invention described in (((8))), it is possible to improve the power saving effect of the processor without missing any received packets, compared to when the processor is always periodically restored from a stopped state to execute packet-related processing. [Explanation of symbols]

[0072] 2 Network, 10 Multifunction device, 11 Control panel, 12 Communication interface (IF), 13 Printing unit, 14 Controller, 141 Panel control circuit, 142 Communication control circuit, 143 Printing control circuit, 144 CPU, 145 Memory, 146 DMA controller, 147 Timer.

Claims

1. a processor; The processor: periodically returning from a stopped state to execute packet-related processing as periodic processing, and also returning from a stopped state in response to an interrupt associated with packet reception to execute packet-related processing as non-periodic processing; When there are no more packets to process, the process stops and the periodic process is not executed. An information processing system comprising:

2. The processor: set a first flag that returns from a stopped state in response to the interrupt and permits execution of the periodic processing; clearing the first flag and stopping the periodic processing when there are no more packets to be processed in the periodic processing; 2. The information processing system according to claim 1, wherein:

3. 3. The information processing system according to claim 2, wherein the processor is not stopped until all of the first flags that are set in association with data that includes one or more packets are cleared.

4. The information processing system according to claim 1, characterized in that the processor continues to execute the periodic processing without stopping until software processing data generated by one or more packets has completed processing the data, even if there are no more packets to process.

5. The processor: When the generation of the data is completed, a second flag is set to indicate an incomplete state of the processing of the data by the software; clearing the second flag when the software has completed processing the data; The periodic process is executed without stopping while the second flag is set.

5. The information processing system according to claim 4.

6. The processor: set a first flag that returns from a stopped state in response to the interrupt and permits execution of the periodic processing; clearing the first flag when there are no more packets to be processed in the periodic processing; The operation stops only when both the first flag and the second flag are cleared.

6. The information processing system according to claim 5.

7. An information processing apparatus comprising the information processing system according to any one of claims 1 to 6.

8. On the computer, a function of periodically returning from a stopped state to execute packet-related processing as periodic processing, and also returning from a stopped state in response to an interrupt associated with packet reception to execute packet-related processing as non-periodic processing; A function of stopping and not executing the periodic processing when there are no more packets to process; A program to achieve this.

Images