Manufacturing method of semiconductor device and the semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device capable of miniaturizing a semiconductor element manufactured by a STI process.SOLUTION: A manufacturing method of a semiconductor device includes: an element isolation part forming step of forming a plurality of element isolation parts by using a STI process across a portion where a first well region and a second well region are connected; a protective element forming step of forming a protective element in a portion excluding a region where the plurality of element isolation parts are formed; an insulating film forming step of forming an insulating film by photolithography so as to cover two adjacent element isolation parts and at least a part of a region between the two element isolation parts in plan view of the semiconductor substrate; an insulating film etching step of etching the insulating film; a film forming step of forming a film by sputtering using the etched insulating film; and a salicide layer forming step of forming a salicide layer in the protective element by heat treatment.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having an STI structure in which multiple trenches are formed by an STI process. The semiconductor device has multiple dummy trenches formed therein, and the multiple dummy trenches separate dummy active (hereinafter, referred to as dummy AC) regions into multiple island shapes.

[0003] A salicide layer may be formed on a diffusion layer (e.g., an n-well (NWH) of a p-type MOS transistor having a gate oxide film) around the trench adjacent to the dummy AC region. The salicide layer may be interpreted as a layer formed by self-alignment of silicon and silicide through heat treatment. When a salicide layer is formed in a semiconductor device with a high power supply voltage, for example, a Schottky junction may be formed between the salicide layer formed on the protection target (protection element) on the semiconductor device and the salicide layer formed in the dummy AC region, causing leakage current to flow through the Schottky junction. Specifically, when the PN junction between the NWH and PWH (p-well) of the semiconductor device comes into contact with the salicide layer in the dummy AC region, the PN junction between this salicide layer and the semiconductor device exhibits rectification characteristics, i.e., functions as a rectifier diode, Schottky diode, etc. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-044276 Summary of the Invention [Problem to be solved by the invention]

[0005] To address this issue, conventionally, semiconductor devices are manufactured using an STI process so that the salicide layer in the dummy AC region is spaced away from the PN junction between the NWH and PWH. However, manufacturing in this manner increases the distance between the dummy AC region and the PN junction, which can cause damage to the edge of the dummy AC region and increase the area of ​​the dummy AC region, hindering miniaturization of semiconductor devices. Thus, the conventional technology leaves room for improvement in manufacturing semiconductor devices using an STI process.

[0006] In view of the above circumstances, the present disclosure has an object to provide a method for manufacturing a semiconductor device that can reduce the size of semiconductor elements manufactured by an STI process. [Means for solving the problem]

[0007] In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present disclosure includes: an isolation portion forming step of forming a plurality of isolation portions by an STI (Shallow Trench Isolation) process around a periphery of a portion where a first well region of a first conductivity type formed in the semiconductor substrate and a second well region of a second conductivity type different from the first conductivity type are connected in a planar view of the semiconductor substrate; a protection element forming step of forming a protection element in a portion of the first well region and the second well region excluding at least the region where the plurality of isolation portions are formed; an insulating film forming step of forming an insulating film by photolithography so as to cover two adjacent isolation portions and at least a part of a region between the two isolation portions in a planar view of the semiconductor substrate; an insulating film etching step of etching the insulating film; a film forming step of forming a film by sputtering using the etched insulating film; and a salicide layer forming step of forming a salicide layer by heat treatment in the region where the protection element is formed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 2]FIG. 2 is a cross-sectional view of the semiconductor device 100 according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a flowchart illustrating a method for manufacturing the semiconductor device 100 of the present disclosure. [Figure 4] FIG. 4 is a diagram for explaining the process of step S4. [Figure 5] FIG. 5 is a diagram for explaining the process of step S7. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device 100A according to a comparative example. [Figure 7] FIG. 7 is a flowchart for explaining a method for manufacturing the semiconductor device 100A according to the comparative example. [Figure 8] FIG. 8 is a diagram for explaining the process of step S41. [Figure 9] FIG. 9 is a diagram for explaining the process of step S71. [Figure 10] FIG. 10 is a diagram showing a path A of leakage current due to Schottky junction. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device 100B according to a comparative example configured to suppress the leakage current shown in FIG. [Figure 12] FIG. 12 is a graph showing values ​​of leakage current flowing through the semiconductor device 100 and the semiconductor device 100A of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0010] (Embodiment) Fig. 1 is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. Fig. 1 shows a plan view of the semiconductor device 100. Fig. 2 is a cross-sectional view of the semiconductor device 100 according to an embodiment of the present disclosure.

[0011] It may include a high-voltage N-well ACHN, an N-well NWH, a P-well PWH, a high-voltage P-well ACHP, a cobalt film Co, a protection element 3, a salicide layer 4, and a plurality of element isolation portions 1. The N-well NWH may be interpreted as a first well region of a first conductivity type. The P-well PWH may be interpreted as a second well region of a second conductivity type different from the first conductivity type. The portion including the N-well NWH and the P-well PWH may be interpreted as a semiconductor substrate.

[0012] The plurality of element isolation portions 1 may be provided around a portion 2 where the first well region (N-well NWH) and the second well region (P-well PWH) are connected in a plan view of the semiconductor substrate. The plurality of element isolation portions 1 may be interpreted as insulating portions formed using an STI (Shallow Trench Isolation) process.

[0013] The portion 2 where the first well region and the second well region are connected may be interpreted as a PN junction portion, and hereinafter, this portion 2 may also be referred to as a PN junction portion.

[0014] The protection element 3 may be interpreted as a well contact. The protection element 3 may be provided, for example, on top of an N-well NWH, and may be interpreted as a high-voltage N-well ACHN. The protection element 3 may include a wiring layer 5 and an intermediate film 6. The protection element 3 may be provided in a portion of the first well region and the second well region excluding a region in which a plurality of element isolation portions 1 are formed. The region in which a plurality of element isolation portions 1 are formed may be interpreted as a dummy AC (active) region.

[0015] In a plan view of the semiconductor substrate, the intermediate film 6 may cover two adjacent element isolation parts 1 and may also cover at least a part of the region between the two element isolation parts 1. The intermediate film 6 may further cover the salicide layer 4.

[0016] The salicide layer 4 may be included in the protection element 3 so as to cover the N-well region N+ in a plan view of the semiconductor substrate. The N-well region N+ may be disposed above the N-well NWH. Specifically, the salicide layer 4 may not be provided above two adjacent element isolation parts 1, may not be provided in the region between two adjacent element isolation parts 1, and may be provided in the region where the protection element 3 is formed. A method for providing the salicide layer 4 in this manner will be described later.

[0017] Next, a method for manufacturing the semiconductor device 100 of the present disclosure will be described with reference to Figures 3 to 5. Figure 3 is a flowchart for explaining the method for manufacturing the semiconductor device 100 of the present disclosure, and Figure 4 is a diagram for explaining the process of step S4. Figure 4 shows a cross-sectional view of the insulating film 7, element isolation portion 1, etc. formed in the insulating film etching process of step S4, and a front view of the insulating film 7, element isolation portion 1, etc. when the semiconductor substrate is viewed in plan. Figure 5 is a diagram for explaining the process of step S7.

[0018] In the element isolation portion forming process of step S1, element isolation portions 1 are formed. Specifically, in the element isolation portion forming process, in plan view of the semiconductor substrate, a plurality of element isolation portions 1 are formed by an STI process around a portion 2 where a first well region and a second well region formed in the semiconductor substrate are connected.

[0019] In the protective element forming step S2, the protective element 3 is formed in at least the portion of the first well region and the second well region excluding the region where the plurality of element isolation portions 1 are formed.

[0020] In step S3, electrodes such as a gate, a drain, and a source are formed.

[0021] In the insulating film etching process of step S4, an insulating film 7 is formed as shown in Fig. 4. The insulating film 7 may be interpreted as non-doped soda lime glass (SL mask). In the insulating film etching process, the insulating film 7 is formed by photolithography so as to cover two adjacent element isolation portions 1 and to cover at least a part of the region between the two element isolation portions 1.

[0022] Specifically, in the insulating film etching step, the insulating film 7 may cover either one of two adjacent element isolation portions 1 and also cover the periphery of the element isolation portion 1 covered by the insulating film 7. More specifically, if the distance between the edges of two adjacent element isolation portions 1 is, for example, 0.5 μm, the insulating film 7 may cover the region between the upper edge of the element isolation portion 1 and a position, for example, 0.3 μm away from the edge. In other words, the insulating film 7 may also cover a portion beyond the upper region of the element isolation portion 1.

[0023] In the insulating film etching step of step S5, the insulating film is etched into a specific shape.

[0024] In the film forming process of step S6, a metal film, for example, a cobalt film Co, is formed by sputtering.

[0025] In the salicide layer formation process of step S7, for example, the semiconductor substrate on which the cobalt film Co is formed is subjected to a heat treatment to react the Si regions of the source, drain, and gate with the metal film, thereby forming the salicide layer 4 as shown in FIG.

[0026] In step S8, an intermediate film 6 is formed on the semiconductor substrate including the salicide layer 4, and in step S9, a wiring layer is formed.

[0027] 6 is a cross-sectional view of a semiconductor device 100A according to a comparative example. The semiconductor device 100 differs from the semiconductor device 100 in that the semiconductor device 100A has salicide layers 4 also provided between a plurality of element isolation portions 1.

[0028] Next, a manufacturing method of the semiconductor device 100A of the present disclosure will be described with reference to Fig. 7 to Fig. 9. Fig. 7 is a flowchart for explaining a manufacturing method of the semiconductor device 100A according to a comparative example, Fig. 8 is a diagram for explaining the process of step S41, and Fig. 9 is a diagram for explaining the process of step S71. Of steps S1 to S9, the processes other than steps S41 and S71 are the same as the processes described above, and therefore description thereof will be omitted.

[0029] In the insulating film etching process of step S41, an insulating film 7A is formed as shown in Fig. 8. The insulating film 7A may be considered as an SL mask, similar to the insulating film 7A described above. In the insulating film etching process of step S41, the insulating film 7A does not cover the region between two adjacent element isolation portions 1, but covers the upper portions of the element isolation portions 1. Specifically, the insulating film 7A does not cover the PN junction portions, but covers the upper portions of the element isolation portions 1.

[0030] In the salicide layer formation process of step S71, for example, a heat treatment is performed on the semiconductor substrate on which the cobalt film Co is formed, thereby causing a reaction between the Si regions of the source, drain, and gate and the metal film. As a result, a salicide layer 4 is formed as shown in FIG. 9. Specifically, the salicide layer 4 is also formed in the region between two adjacent element isolation portions 1.

[0031] When the salicide layer 4 is formed in this manner, a Schottky junction can be formed between the salicide layer 4 formed on the protection element 3 on the semiconductor device 100A and the salicide layer 4 formed in the dummy AC region. FIG. 10 is a diagram showing a leakage current path A due to the Schottky junction. As shown in FIG. 10, when the PN junction between the NWH and PWH of the semiconductor device 100A contacts the salicide layer 4 in the dummy AC region, the salicide layer 4 formed on the protection element 3 and the PN junction exhibit rectification characteristics, that is, they function as a rectifier diode, a Schottky diode, or the like. This forms a leakage current path A, as shown by the dashed line.

[0032] 11 is a cross-sectional view of a semiconductor device 100B according to a comparative example configured to suppress the leakage current shown in FIG. 10. FIG. 11 shows the semiconductor device 100B manufactured by an STI process so that the salicide layer 4 in the dummy AC region is spaced apart from the PN junction between the NWH and PWH. In the semiconductor device 100B manufactured in this manner, the distance from the PN junction to the dummy AC region is increased, which may result in chipping of the edge of the dummy AC region. Furthermore, the area of ​​the dummy AC region is increased, which may hinder miniaturization of the semiconductor device 100B.

[0033] 12 is a graph showing values ​​of leakage current flowing through semiconductor device 100 and semiconductor device 100A of the present disclosure. The vertical axis of FIG. 12 represents current, and the horizontal axis represents voltage. The solid line represents the leakage current flowing through semiconductor device 100A, and the dashed line represents the leakage current flowing through semiconductor device 100. As shown in FIG. 12, it can be seen that almost no leakage current flows through semiconductor device 100.

[0034] (Actions and Effects) As described above, the manufacturing method of the semiconductor device 100 according to the present disclosure includes the steps of: forming an insulating film by photolithography to cover two adjacent element isolation portions 1 and at least a portion of the region between the two element isolation portions 1 in a plan view of the semiconductor substrate; etching the insulating film; forming a film by sputtering using the etched insulating film; and forming a salicide layer 4 by heat treatment in the region where the protection element 3 is formed. This prevents the salicide layer 4 from being formed in the region between the two adjacent element isolation portions 1, as shown in FIG. 5 . Therefore, the occurrence of the leakage current path A shown in FIG. 10 can be prevented. Since the leakage current path A can be prevented, the distance from the PN junction to the dummy AC region can be reduced, thereby preventing damage to the end of the dummy AC region and enabling the miniaturization of the semiconductor device.

[0035] In addition, the following supplementary notes are provided in relation to the above description.

[0036] (Appendix 1) an element isolation portion forming step of forming a plurality of element isolation portions by an STI (Shallow Trench Isolation) process around a portion where a first well region of a first conductivity type formed in the semiconductor substrate and a second well region of a second conductivity type different from the first conductivity type are connected in a plan view of the semiconductor substrate; a protection element forming step of forming a protection element in at least a portion of the first well region and the second well region excluding a region in which the plurality of element isolation portions are formed; an insulating film forming step of forming an insulating film by photolithography so as to cover two adjacent element isolation portions and at least a part of a region between the two element isolation portions when the semiconductor substrate is viewed from above; an insulating film etching step of etching the insulating film; a film formation step of forming a film by sputtering using the etched insulating film; a salicide layer forming step of forming a salicide layer by heat treatment in the region where the protection element is formed; A method for manufacturing a semiconductor device comprising:

[0037] (Appendix 2) 2. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film contains undoped soda lime glass.

[0038] (Appendix 3) a plurality of element isolation portions having an STI (Shallow Trench Isolation) structure provided around a portion where a first well region of a first conductivity type formed in the semiconductor substrate and a second well region of a second conductivity type different from the first conductivity type are connected in a plan view of the semiconductor substrate; a protection element provided in a portion of the first well region and the second well region excluding a region in which the plurality of element isolation portions are formed; an intermediate film that covers two adjacent element isolation portions in a plan view of the semiconductor substrate and covers at least a part of a region between the two element isolation portions; a salicide layer that is not provided in two adjacent element isolation parts or in a region between the two element isolation parts, but is provided in a region where the protection element is formed; 10. A semiconductor device comprising: [Explanation of symbols]

[0039] 1. Element isolation section 2 The area where the first and second well regions are connected 3 Protection elements 4 salicide layer 5 wiring layer 6 Interlayer 7. Insulating film 7A Insulating film 100 Semiconductor device 100A Semiconductor Device 100B Semiconductor device

Claims

1. an isolation region forming step of forming a plurality of isolation regions by using an STI (Shallow Trench Isolation) process around a portion where a first well region of a first conductivity type and a second well region of a second conductivity type different from the first conductivity type are connected to each other in a plan view of the semiconductor substrate; a protection element forming step of forming a protection element in at least a portion of the first well region and the second well region excluding a region in which the plurality of element isolation portions are formed; an insulating film forming step of forming an insulating film by photolithography so as to cover two adjacent element isolation portions and at least a part of a region between the two element isolation portions when the semiconductor substrate is viewed from above; an insulating film etching step of etching the insulating film; a film formation step of forming a film by sputtering using the etched insulating film; a salicide layer forming step of forming a salicide layer by heat treatment in the region where the protection element is formed; A method for manufacturing a semiconductor device comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said insulating film contains undoped soda lime glass.

3. a plurality of element isolation portions having an STI (Shallow Trench Isolation) structure provided around a portion where a first well region of a first conductivity type formed in the semiconductor substrate and a second well region of a second conductivity type different from the first conductivity type are connected in a plan view of the semiconductor substrate; a protection element provided in a portion of the first well region and the second well region excluding a region in which the plurality of element isolation portions are formed; an intermediate film that covers two adjacent element isolation portions in a plan view of the semiconductor substrate and covers at least a part of a region between the two element isolation portions; a salicide layer that is not provided in two adjacent element isolation portions or in a region between the two element isolation portions, but is provided in a region where the protection element is formed; 10. A semiconductor device comprising:

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