Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing the occurrence of soft errors.SOLUTION: A semiconductor device comprises a semiconductor substrate having a single crystal layer, a plurality of semiconductor devices formed on a single crystal layer, and a separation film formed on a semiconductor substrate so as to surround each of a plurality of semiconductor elements in a planar view, and to separate the plurality of semiconductor elements from one another. The separation film is composed of an antiferroelectric material. The minimum relative permittivity of the separation film is less than 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices having an element isolation film for electrically isolating a plurality of semiconductor elements formed on a semiconductor substrate from one another have been known (see, for example, Japanese Patent Laid-Open No. 2013-222838 (Patent Document 1)).

[0003] Also known is a semiconductor device that includes an SOI (Silicon On Insulator) substrate having a buried insulating film and a transistor formed in a semiconductor layer of the SOI substrate (see, for example, Japanese Patent Application Laid-Open No. 2002-313906). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-222838 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-313906 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, with the increase in operating speed of semiconductor devices, there has been a demand for reducing the capacitance of isolation films such as element isolation films and buried insulating films, and materials for constituting the isolation films with a dielectric constant lower than that of silicon oxide films have been sought.

[0006] However, when a material having a lower dielectric constant than that of a silicon oxide film is used for the isolation film, it is more difficult to suppress the occurrence of soft errors than when the isolation film is made of a silicon oxide film.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment includes a semiconductor substrate having a single-crystal layer, a plurality of semiconductor elements formed on the single-crystal layer, and an isolation film formed on the semiconductor substrate so as to surround each of the plurality of semiconductor elements in a plan view and isolating the plurality of semiconductor elements from each other. The isolation film is made of an antiferroelectric material. The minimum value of the relative dielectric constant of the isolation film is less than 2.

[0009] A semiconductor device according to another embodiment includes a semiconductor substrate having a bulk layer and a single-crystal layer, and a plurality of semiconductor elements formed in the single-crystal layer. The semiconductor substrate further includes an isolation film disposed between the bulk layer and the single-crystal layer and isolating the bulk layer from the plurality of semiconductor elements. The isolation film is made of an antiferroelectric material. The isolation film has a minimum dielectric constant of less than 2.

[0010] A method for manufacturing a semiconductor device according to one embodiment includes a first step of preparing a semiconductor substrate having a single crystal layer, a second step of forming a plurality of semiconductor elements on the single crystal layer, and a third step of forming an isolation film on the single crystal layer to isolate the plurality of semiconductor elements from each other. In the third step, the isolation film is formed at a temperature below the Curie point of the antiferroelectric so as to surround each of the plurality of semiconductor elements in a plan view.

[0011] A method for manufacturing a semiconductor device according to another embodiment includes a first step of preparing a semiconductor substrate having a bulk layer, a single-crystal layer, and an isolation film disposed between the bulk layer and the single-crystal layer to isolate the bulk layer from the single-crystal layer, and a second step of forming a plurality of semiconductor elements in the single-crystal layer. In the first step, the isolation film made of an antiferroelectric material is formed at a temperature below the Curie point of the antiferroelectric material. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to provide a semiconductor device that can suppress the occurrence of soft errors compared to when the isolation film is made of a silicon oxide film. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view showing a configuration example of a semiconductor device according to a first embodiment. [Figure 2] 2 is a partially enlarged plan view showing a configuration example of a semiconductor element included in the semiconductor device according to the first embodiment. FIG. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor element shown in FIG. [Figure 4] 1 is a graph showing the relationship between the electric field and polarization of an antiferroelectric material, obtained by simulation. [Figure 5] 10 is a graph showing the relationship between the electric field and the relative dielectric constant of an antiferroelectric material, obtained by simulation. [Figure 6] 3 is a flowchart showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 10 is a partially enlarged plan view showing a configuration example of a semiconductor element included in a semiconductor device according to a second embodiment. FIG. [Figure 8] 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 9] 11 is a partially enlarged plan view showing a configuration example of a semiconductor element included in a semiconductor device according to a third embodiment. FIG. [Figure 10] FIG. 11 is a circuit diagram showing an example of a circuit that is realized when an ESD pulse enters the semiconductor device according to the third embodiment. [Figure 11] 11 is a graph showing the change over time of a current flowing through a MOS transistor after an ESD pulse enters the semiconductor device according to the third embodiment. [Figure 12] 11 is a partially enlarged plan view showing a configuration example of a semiconductor element included in a modified example of the semiconductor device according to the third embodiment. FIG. [Figure 13] FIG. 10 is a circuit diagram showing an example of a circuit that is realized when an ESD pulse enters a modified example of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0015] (Embodiment 1) <Configuration of semiconductor device> FIG. 1 is a plan view of a semiconductor device 101 according to a first embodiment. As shown in FIG. 1, the semiconductor device 101 according to the first embodiment has a scribe region 1 and a module region 2. The scribe region 1 has the outer periphery of the semiconductor device 101 formed by scribing a semiconductor substrate. The module region 2 is formed inside the scribe region 1 in a plan view. The module region 2 has, for example, an input / output circuit IOC, an analog circuit ANA, a logic circuit LC, a memory circuit MEM, etc. The memory circuit MEM includes a plurality of memory cells.

[0016] The module region 2 includes a plurality of semiconductor elements. The plurality of semiconductor elements include at least one of transistors and diodes. The plurality of semiconductor elements include, for example, vertical insulated gate field effect transistors. The insulated gate field effect transistors are, for example, MIS (Metal Insulator Semiconductor) transistors. The MIS (Metal Insulator Semiconductor) transistors are, for example, MOS (Metal Oxide Semiconductor) transistors. The MOS transistors are, for example, included in each of a plurality of memory cells in the memory circuit MEM. Note that there are no particular limitations on the semiconductor elements included in the module region 2.

[0017] FIG. 2 is a partially enlarged plan view showing a MOS transistor included in one memory cell in the semiconductor device 101. FIG. 3 is a cross-sectional view taken along arrow III-III in FIG. 2. As shown in FIG. 2, the semiconductor device 101 is formed using a semiconductor substrate SUB. The semiconductor substrate SUB has a first surface SF1. The MOS transistor TR is formed on the first surface SF1.

[0018] In this specification, two directions along the first surface SF1 that are perpendicular to each other are referred to as the X direction and the Y direction. The direction perpendicular to the first surface SF1 is referred to as the Z direction. In the Z direction, the direction from the single crystal layer 30 toward the bulk layer 10 is referred to as the downward direction, and the direction from the bulk layer 10 toward the single crystal layer 30 is referred to as the upward direction. A viewpoint viewed from above in the Z direction is referred to as a planar view.

[0019] The semiconductor substrate SUB is, for example, an SOI (Silicon On Insulator) substrate. The SOI substrate includes a bulk layer 10, a substrate isolation film 20, and a single-crystal layer 30. The bulk layer 10, the substrate isolation film 20, and the single-crystal layer 30 are stacked in this order in the Z direction. The substrate isolation film 20 is disposed between the bulk layer 10 and the single-crystal layer 30. The bulk layer 10 is made of, for example, p-type single-crystal silicon. The substrate isolation film 20 is, for example, a buried oxide film (BOX). The substrate isolation film 20 is made of, for example, an n-type silicon oxide film. The single-crystal layer 30 is made of, for example, single-crystal silicon. The single-crystal layer 30 includes a p-type well PW, n-type impurity regions serving as a source SO and a drain DR, and a channel region between the source SO and the drain DR. The semiconductor substrate SUB of the semiconductor device 101 is not limited to an SOI substrate.

[0020] The MOS transistor TR1 is, for example, an NMOS (N-channel MOS) transistor. The MOS transistor TR1 includes a p-type well PW, a source SO and a drain DR which are n-type impurity regions, a channel region between the source SO and the drain DR, and a gate electrode GE. The p-type well PW, the source SO and the drain DR, and the channel region are formed in a single crystal layer 30. The drain DR, the source SO, and the channel region are formed above the p-type well PW. The source SO and the drain DR are spaced apart in the X direction. The gate electrode GE is formed on the channel region via a gate insulating film GI. Sidewall insulating films SW are formed on the side walls of the gate insulating film GI and the gate electrode GE. The sidewall insulating film SW includes, for example, at least one of a silicon oxide film and a silicon nitride film. Each of the source SO and the drain DR is connected to a plurality of first wiring layers M1A (described later) via a first contact CT layer C1A. Each of the source SO and the drain DR may have an LDD (Lightly Doped Drain) structure. The MOS transistor TR1 may be a PMOS (P-channel MOS) transistor.

[0021] The semiconductor device 101 further includes a contact element for fixing the potential of the p-type well PW in addition to the MOS transistor TR. The contact element is arranged alongside the MOS transistor TR in, for example, the X direction. The contact element includes, for example, a p-type impurity region HPR and a second contact CTB. The p-type impurity region HPR is formed in an upper portion of the p-type well PW. The second contact CTB is connected to the p-type impurity region HPR. The second contact CTB is arranged at an interval from the first contact CTA in, for example, the X direction.

[0022] The semiconductor device 101 further includes an isolation film ISL. The isolation film ISL is formed, for example, between MOS transistors TR adjacent to each other in the X direction or the Y direction, and between the MOS transistor TR and the contact CT element. The isolation film ISL is arranged so as to surround each of the MOS transistor TR and the contact CT element in a plan view. The MOS transistor TR1 is electrically isolated from each of the other semiconductor elements and the contact CT element by the isolation film ISL. The isolation film ISL has, for example, a shallow trench isolation (STI) structure.

[0023] The isolation film ISL is made of an antiferroelectric material. In an antiferroelectric material, in the absence of an external electric field, each of the multiple sublattices in the crystal has a dielectric polarization. However, two adjacent sublattices have dielectric polarizations in opposite directions, resulting in almost no polarization of the crystal as a whole. From a different perspective, in the absence of an external electric field, the overall electric susceptibility χ of the antiferroelectric material constituting the isolation film ISL is lower than that of a typical low-k material. The isolation film ISL is made of an antiferroelectric material whose overall electric susceptibility χ is less than 1. In other words, the minimum dielectric constant of the isolation film ISL is less than 2. Typical low-k materials include SiOCH, methyl-containing SiO2, parylene, and polyaryl ether. Their dielectric constants are between 2.6 and 2.9.

[0024] The materials that make up the element isolation film ISL are HfO2, ZrO2, Pb(In 0.5 Nb 0.5 )O3, NbNaO3, ZrPbO3, TiZrLaPbO3, TiZrPbO3, NH4H2PO4, or NH4H2AsO4.

[0025] Preferably, the antiferroelectric material constituting the isolation film ISL has an amorphous structure or a polycrystalline structure. Alternatively, the antiferroelectric material constituting the isolation film ISL may be a relaxor dielectric. In these cases, the overall electric susceptibility χ of the antiferroelectric material constituting the isolation film ISL is substantially zero. Therefore, the minimum value of the relative dielectric constant of the isolation film ISL is substantially 1.

[0026] The maximum value of the relative dielectric constant of the element isolation film ISL is greater than 2.9. Preferably, the maximum value of the relative dielectric constant of the element isolation film ISL is 4.3 or more.

[0027] Figure 4 is a graph showing the relationship between the electric field and polarization of 2-trichloromethylbenzimidazole (TCMBI), an example of an antiferroelectric, obtained by simulation. The boundary element method (BEM) was used for the simulation. The open circles in Figure 4 represent the relationship when the applied voltage is increased from negative to positive, while the filled circles represent the relationship when the applied voltage is decreased from positive to negative. As shown in Figure 4, the polarization-electric field curve of the antiferroelectric material constituting the isolation film ISL exhibits a double hysteresis loop. As shown in Figure 4, when the external electric field applied to the antiferroelectric material is smaller than a certain magnitude, the antiferroelectric material exhibits polarization similar to that of a paraelectric material. When the external electric field applied to the antiferroelectric material is larger than a certain magnitude, the polarization directions of the multiple sublattices in the antiferroelectric material align, and spontaneous polarization (spontaneous polarization) occurs, similar to that of a ferroelectric material. In this case, the relative permittivity of the antiferroelectric material is greater than 2.9, e.g., greater than 4.0. The polarization (residual polarization) of the antiferroelectric when the external electric field applied to the antiferroelectric is set to zero is 15 μC / cm 2 or less. In other words, the remanent polarization of the antiferroelectric is almost zero. The spontaneous polarization and remanent polarization of the element isolation film ISL can be determined, for example, based on a DE curve obtained by measuring the electric flux density D when an electric field E is applied to the element isolation film ISL.

[0028] Figure 5 is a graph showing the relationship between the electric field and the dielectric constant as the applied electric field is gradually increased, as determined by the above simulation, for the example of the antiferroelectric material shown in Figure 4. As shown in Figure 5, the dielectric constant of the antiferroelectric material constituting the element isolation film ISL is kept less than 2 until the strength of the electric field exceeds a specific value, at which point it becomes greater than 2.9. The specific value is, for example, 50 kV / cm or more and 70 kV / cm or less.

[0029] In the semiconductor device 101, during normal operation, the electric field applied between a pair of elements via the element isolation film ISL is set to be less than the electric field that generates spontaneous polarization in the antiferroelectric material.

[0030] In this specification, normal operation of a semiconductor device refers to normal operation that is predetermined for the semiconductor device, and operation in a state where no electric charge is generated due to cosmic rays, ESD (Electro-Static Discharge), etc.

[0031] In the semiconductor device 101, the voltage applied between two regions separated by the element isolation film ISL during normal operation is set to be less than twice the drive voltage of the MOS transistor TR1 formed in that region. When the drive voltage of the MOS transistor TR1 is 1 V, the semiconductor device 103 is set to be less than 2 V between the two regions separated by the element isolation film ISL during normal operation. When the drive voltage of the MOS transistor TR1 is 3.3 V, the semiconductor device 103 is set to be less than 6.6 V between the two regions separated by the element isolation film ISL during normal operation.

[0032] The electric field applied between the two regions separated by the element isolation film ISL during normal operation is, for example, less than 50 kV / cm.

[0033] In the semiconductor device 101, the electric field applied to the element isolation film ISL due to cosmic rays is set to be less than the electric field that causes a phase transition of the antiferroelectric material constituting the element isolation film ISL to a ferroelectric material. Preferably, the electric field applied to the element isolation film ISL due to ESD is set to be less than the electric field that causes a phase transition of the antiferroelectric material constituting the element isolation film ISL to a ferroelectric material.

[0034] In this specification, cosmic rays refer to radiation coming from outer space or particles resulting from such radiation, having energies on the order of several MeV to GeV. Cosmic rays are particle radiation or high-energy electromagnetic radiation. Examples of particle radiation include alpha rays, beta rays, neutron rays, and proton rays. Examples of electromagnetic radiation include gamma rays and X-rays. The radiation-induced particles are, for example, neutrons produced when cosmic rays collide with atomic nuclei such as oxygen or nitrogen when they enter the atmosphere.

[0035] Preferably, the element isolation film ISL does not have a plurality of pores formed therein. Preferably, the element isolation film ISL does not include a porous material. Preferably, the Young's modulus of the element isolation film ISL is higher than the Young's modulus of a low-dielectric-constant material made of a porous material. Preferably, the Young's modulus of the element isolation film ISL is 8 GPa or more.

[0036] The thickness of the element isolation film ISL is equal to or greater than 2 nm and less than 50 nm, and is the dimension of the element isolation film ISL in the Z direction.

[0037] The semiconductor device 101 further includes, for example, a plurality of wiring layers M, a plurality of interlayer insulating films ILD, and a plurality of contacts CT. The plurality of wiring layers M and the plurality of interlayer insulating films ILD are stacked in the Z direction. The plurality of wiring layers M are disposed on the upper surfaces of the plurality of interlayer insulating films ILD or in wiring grooves formed in the upper surfaces of the plurality of interlayer insulating films ILD. Each of the plurality of wiring layers M may be formed by a damascene method. A through-hole is formed in each of the plurality of interlayer insulating films ILD. Each of the plurality of contacts CT is formed in the through-hole.

[0038] The multiple interlayer insulating films ILD include a lower interlayer insulating film ILD1 located at the lowest, an upper interlayer insulating film located at the highest, and at least one middle interlayer insulating film ILD3 located between the lower interlayer insulating film ILD1 and the upper interlayer insulating film.

[0039] The lower interlayer insulating film ILD1 is formed on the first surface SF1 so as to cover the gate electrode GE and the sidewall insulating film SW. The lower interlayer insulating film ILD1 is in contact with, for example, the gate electrode GE, the sidewall insulating film SW, and the element isolation film ISL. The lower interlayer insulating film ILD1 is in contact with, for example, the source SO and the drain DR. The lower interlayer insulating film ILD1 is not in contact with the gate insulating film GI.

[0040] The plurality of wiring layers M include a lower wiring layer M1 located at the lowest position, an upper wiring layer located at the highest position, and at least one intermediate wiring layer located between the lower wiring layer M1 and the upper wiring layer.

[0041] The lower wiring layer M1 is disposed on the upper surface of the lower inter-layer insulating film ILD1 or in a groove formed on the upper surface. The lower wiring layer M1 includes a plurality of first wiring layers M1A and a second wiring layer M1B that are disposed at intervals from each other in at least one of the X direction and the Y direction. Each of the plurality of first wiring layers M1A is connected to the drain DR or the source SO of the MOS transistor TR via a first contact CT layer C1A. The second wiring layer M1B is connected to the p-type well PW via a second contact CT layer C1B. The first contact CT layer C1A and the second contact CT layer C1B are formed in a through-hole formed in the lower inter-layer insulating film ILD1.

[0042] The upper wiring layer is formed on the upper interlayer insulating film. The upper wiring layer is configured as a pad. Each of the plurality of interlayer insulating films ILD overlaps with the pad in the Z direction.

[0043] <Method of manufacturing a semiconductor device> An example of a method for manufacturing the semiconductor device 101 will now be described with reference to FIG.

[0044] First, a semiconductor substrate SUB is prepared (first step). The semiconductor substrate SUB has a first surface SF1. The semiconductor substrate SUB is prepared as, for example, an SOI substrate.

[0045] Second, an element isolation film ISL is formed in the single crystal layer 30 of the semiconductor substrate SUB (third step). The element isolation film ISL is made of an antiferroelectric material. In this step, the element isolation film ISL is formed at a temperature below the Curie point of the antiferroelectric material. Furthermore, after this step, the element isolation film ISL is not heated to a temperature equal to or higher than the Curie point of the antiferroelectric material. This prevents the antiferroelectric material constituting the element isolation film ISL from transforming into a ferroelectric material.

[0046] Third, the MOS transistor TR is formed on the first surface SF1 of the semiconductor substrate SUB (second step). In this step, the contact CT element is also formed.

[0047] Fourth, the lower interlayer insulating film ILD1 is formed on the first surface SF1 so as to cover the MOS transistor TR (fourth step).

[0048] Fifth, the contacts CT and the wiring layer M1 are formed (fifth step). The wiring layer M1 is formed by, for example, the damascene method. Thereafter, the middle interlayer insulating film, the middle wiring layer, the upper interlayer insulating film, the upper wiring layer, etc. are formed. In this manner, the semiconductor device 101 shown in FIGS. 2 and 3 is manufactured. In this step, post-metallization annealing (PMA) may be performed. In this case, the heating temperature is set to a temperature below the Curie point of the antiferroelectric material constituting the lower interlayer insulating film ILD1.

[0049] In the second to fifth steps, the layout pattern of each element is formed using photolithography. The layout pattern of each element is designed and verified based on the specifications required for the semiconductor device 101. The layout pattern of each element is designed based on the results of a circuit simulation that simulates the operation of a circuit including the MOS transistor TR, or by an automatic place and route (P&R) program. One example of the circuit simulation is SPICE (Simulation Program with Integrated Circuit Emphasis).

[0050] The third step may be performed after the step of forming the MOS transistor TR (second step).

[0051] The method for manufacturing the semiconductor device 101 may further include, after the third step, a step of adjusting the relative dielectric constant of the element isolation film ISL by, for example, irradiating the element isolation film ISL with electromagnetic waves. This step may be performed within the third step. This step may be performed as an annealing treatment of the element isolation film ISL. For example, when the element isolation film ISL is composed of an antiferroelectric material having a perovskite structure, a solvent containing the antiferroelectric material may be spin-coated on the first surface SF1, and then the solvent may be volatilized by irradiating it with electromagnetic waves under predetermined conditions, thereby obtaining an element isolation film ISL with an adjusted dielectric constant. The electromagnetic waves may be laser light.

[0052] This step may be performed as an annealing treatment using a hot plate. In this case, the element isolation film ISL is slowly cooled after heating by the hot plate is stopped, so that the crystal structure of the element isolation film ISL can be made single crystal.

[0053] Furthermore, this process may reduce the uniformity of at least one of the film quality and film thickness of the element isolation film ISL. For example, the element isolation film ISL after this process may contain at least one of a large number of aggregates and voids. Therefore, in this process, a process for improving the uniformity of the film quality and film thickness of the element isolation film ISL may be performed before the process for adjusting the relative dielectric constant. As such a process, for example, a solvent such as chlorobenzene, dimethylformamide, or 1-cyclohexyl-2-pyrrolidone may be spin-coated on a solvent containing an antiferroelectric material spin-coated on the first surface SF1.

[0054] <Effects of the semiconductor device 101> The effects of the semiconductor device 101 will be described in comparison with comparative examples. The semiconductor device according to comparative example 1 differs from the semiconductor device 101 only in that the element isolation film ISL is made of a general low-dielectric-constant material. As described above, the relative dielectric constant of general low-dielectric-constant materials is 2.6 or more and 2.9 or less. Therefore, the semiconductor device according to comparative example 1 can increase the operating speed of the semiconductor element compared to a semiconductor device including an element isolation film made of a dielectric with a relative dielectric constant greater than 2.9. However, it is difficult for the semiconductor device according to comparative example 1 to suppress the occurrence of soft errors caused by cosmic rays.

[0055] Cosmic rays that reach the earth from outer space include high-energy radiation, as well as secondary neutrons generated when the radiation collides with and destroys the nuclei of atoms such as oxygen in the atmosphere. These cosmic rays have energies ranging from several MeV to GeV, and when they enter a semiconductor device, they destroy the nuclei of the atoms that make up the semiconductor device, ultimately generating a large amount of electric charge (hereinafter referred to as anomalous charge). The large amount of anomalous charge is not captured by the element isolation film made of a low-dielectric-constant material, but reaches the impurity region that constitutes the storage node in the memory circuit. In an n-type MOS transistor, the anomalous charge reaches the drain.

[0056] Specifically, when cosmic rays disrupt the nuclei of atoms constituting the single-crystal layer 30, dipoles consisting of protons and electrons are generated. The energy of the dipole is on the order of 10 MV immediately after generation, but attenuates as the distance between the proton and electron increases. When the distance between the two increases to the order of a few atoms, the dipole becomes an electron-hole pair with energy on the order of keV. As the electron-hole pair moves through the semiconductor device, its energy weakens to the order of 10 eV, but the electrons and holes are not captured by the element isolation film made of a low-dielectric-constant material and reach the impurity region constituting the storage node in the memory circuit MEM. As a result, the semiconductor device according to Comparative Example 1 has a problem in that data stored in the storage node is easily inverted, resulting in soft errors.

[0057] In contrast, in the semiconductor device 101, since the element isolation film ISL is made of an antiferroelectric material, the relative dielectric constant of the element isolation film ISL becomes higher than the relative dielectric constant of the element isolation film ISL during normal operation only when the strength of the electric field applied to the element isolation film ISL by the anomalous charge exceeds the specific value. Therefore, a portion of the anomalous charge can be captured in the inter-wiring capacitance with the element isolation film ISL as a dielectric. As a result, the semiconductor device 101 can achieve both high integration of semiconductor elements and miniaturization of each wiring, as well as suppression of the accompanying propagation delay and soft error occurrence.

[0058] In the semiconductor device 101, the maximum value of the relative dielectric constant of the element isolation film ISL is greater than 2.9. That is, the maximum value of the relative dielectric constant of the element isolation film ISL is higher than the relative dielectric constant of a low-dielectric-constant material. In this semiconductor device 101, the occurrence of the soft error can be suppressed more effectively than in the semiconductor device according to Comparative Example 1. Preferably, the maximum value of the relative dielectric constant of the element isolation film ISL is greater than 4.3. That is, the maximum value of the relative dielectric constant of the element isolation film ISL is higher than the relative dielectric constant of a silicon oxide film. These semiconductor devices 101 are particularly suitable for technical fields where high integration of semiconductor elements and suppression of the soft error are simultaneously required, such as automobiles, aerospace systems, and medical equipment. In aerospace systems, the atmosphere cannot be expected to provide a shielding effect against cosmic rays, and therefore even a very small probability of soft error occurrence cannot be tolerated. The semiconductor device 101 is also suitable for such cases.

[0059] Furthermore, in the semiconductor device according to Comparative Example 1, if an attempt is made to reduce the capacitance value of the isolation film in order to increase the operating speed, it is necessary to widen the distance between two adjacent regions separated by the isolation film, making it difficult for the semiconductor device according to Comparative Example 1 to increase the operating speed while suppressing the occurrence of soft errors.

[0060] In contrast, in the semiconductor device 101, the isolation film ISL is made of an antiferroelectric material. Therefore, in a state where an external electric field is not applied, the overall electric susceptibility χ of the antiferroelectric material constituting the isolation film is lower than that of a general low-dielectric constant material and is less than 1. In other words, the minimum value of the relative dielectric constant of the isolation film is less than 2. Therefore, in the semiconductor device 101, the capacitance between two adjacent conductors sandwiching the isolation film (for example, the capacitance between the first wiring layer M1A and the second wiring layer M1B) is smaller than the capacitance between two adjacent conductors sandwiching the isolation film made of a general low-dielectric constant material in the semiconductor device according to Comparative Example 1. Therefore, the semiconductor device 101 can increase the operating speed while suppressing the occurrence of soft errors, compared to the semiconductor device according to Comparative Example 1.

[0061] Furthermore, in the semiconductor device according to Comparative Example 1, it is difficult to narrow the width of the isolation film in the X or Y direction in order to suppress a decrease in the operating speed of the semiconductor element due to an increase in the capacitance value of the isolation film. In other words, in the semiconductor device according to Comparative Example 1, it is difficult to reduce the chip area while suppressing a decrease in the operating speed of the semiconductor element.

[0062] In contrast, in the semiconductor device 101, the isolation film is made of an antiferroelectric material, and the minimum value of the relative dielectric constant of the antiferroelectric material is less than 2. Therefore, in the semiconductor device 101, compared to the semiconductor device according to Comparative Example 1, an increase in the capacitance value of the isolation film can be suppressed even if the width of the isolation film in the X direction or Y direction is narrowed. As a result, in the semiconductor device 101, it is possible to reduce the chip area while suppressing a decrease in the operating speed of the semiconductor element.

[0063] The size and spacing of the semiconductor elements in semiconductor device 101 may be the same as those in the semiconductor device of Comparative Example 1, in which case the operating speed can be increased compared to the semiconductor device of Comparative Example 1.

[0064] Furthermore, in the semiconductor device 101, the remanent polarization of the antiferroelectric material constituting the element isolation film ISL is 15 μC / cm 2 Because the temperature is less than 100°C, abnormal charges are less likely to remain.

[0065] In the semiconductor device 101, the thickness of the isolation film ISL is 2 nm or more and 50 nm or less. When comparing an isolation film ISL having the same thickness with an isolation film made of a general low-dielectric-constant material, the minimum value of the dielectric constant of the isolation film ISL is lower than the dielectric constant of the general low-dielectric-constant material. Therefore, in the semiconductor device 101, if the thickness of the isolation film ISL is equivalent to that of the isolation film of the semiconductor device according to Comparative Example 1, the capacitance value of the isolation film ISL during normal operation can be made smaller than that of an isolation film made of a general low-dielectric-constant material. On the other hand, in the semiconductor device 101, if the capacitance value of the isolation film ISL during normal operation is equivalent to that of the isolation film of the semiconductor device according to Comparative Example 1, the thickness of the isolation film ISL can be made thicker than that of an isolation film made of a general low-dielectric-constant material. As a result, in the semiconductor device 101, the leakage current can be reduced while the capacitance of the isolation film can be reduced compared to the semiconductor device according to Comparative Example 1, thereby enabling higher performance.

[0066] In the semiconductor device 101, the electric field applied between a pair of adjacent elements sandwiching the element isolation film ISL during normal operation is set to be less than the electric field at which spontaneous polarization occurs in the antiferroelectric, so that the relative dielectric constant of the element isolation film ISL can be maintained at less than 2 during normal operation. For example, the electric field applied between the pair of elements during normal operation may be less than 50 kV / cm. The electric field at which spontaneous polarization occurs in the antiferroelectric may be 50 kV / cm or more.

[0067] Furthermore, in the semiconductor device 101, the external electric field applied to the element isolation film ISL due to cosmic rays is set to be less than the electric field that causes a phase transition of the antiferroelectric material constituting the element isolation film ISL to a ferroelectric material. Therefore, after the application of the external electric field is stopped, the relative dielectric constant of the element isolation film ISL becomes less than 2 again, and abnormal charges are gradually released from the element isolation film ISL. As a result, in the semiconductor device 101, even if the external electric field is repeatedly applied with intervals, the occurrence of the soft error can be suppressed each time, and further, propagation delay can be suppressed during normal operation after the external electric field is removed.

[0068] An external electric field equal to or greater than the electric field that causes a phase transition of the antiferroelectric material constituting the element isolation film ISL to a ferroelectric material may be applied to the element isolation film ISL. The element isolation film ISL may also transition from an antiferroelectric material to a ferroelectric material. In this case, the above-described effects of the element isolation film ISL can be reproduced in the semiconductor device 101 by performing a process to return the element isolation film ISL from a ferroelectric material to an antiferroelectric material. Examples of a process to return the element isolation film ISL from a ferroelectric material to an antiferroelectric material include a process of alternately applying positive and negative voltages, such as an AC voltage, to the element isolation film ISL and gradually decreasing this voltage. This process disrupts the crystalline structure of the ferroelectric material, thereby reproducing the crystalline structure of the antiferroelectric material. Another example of a process is to heat the element isolation film ISL and then rapidly cool it. This process destroys the crystalline structure of the ferroelectric material, thereby reproducing the crystalline structure of the antiferroelectric material.

[0069] Furthermore, in the semiconductor device according to Comparative Example 1, when abnormal charges due to ESD enter from the pad, the element isolation film made of a low dielectric constant material cannot capture the abnormal charges.

[0070] In contrast, in the semiconductor device 101, when abnormal charges due to ESD penetrate through the pad, an external electric field of 50 kV / cm or more is applied to the isolation film ISL located between the pad and the semiconductor element. As a result, the relative dielectric constant of the isolation film ISL becomes higher than that of the low-dielectric-constant material, and some of the abnormal charges can be captured in the inter-wiring capacitance with the isolation film ISL as the dielectric. This reduces the current induced by ESD and keeps it below the current threshold that destroys the semiconductor element. As a result, the semiconductor device 101 can prevent ESD-induced damage to the semiconductor element.

[0071] In the manufacturing method of the semiconductor device 101, in the process of forming the element isolation film ISL, the temperature of the element isolation film ISL is set to be lower than the Curie point of the antiferroelectric that constitutes the element isolation film ISL, so that the antiferroelectric that constitutes the element isolation film ISL can be prevented from transitioning to a ferroelectric.

[0072] (Embodiment 2) Unless otherwise specified, the semiconductor device 102 according to the second embodiment has the same configuration, operating principle, and effects as those of the first embodiment. Therefore, the same configuration, operating principle, and effects as those of the first embodiment will not be described repeatedly.

[0073] 7, the semiconductor device 102 according to the second embodiment is different from the semiconductor device 101 in that the substrate isolation film 20 is made of an antiferroelectric material instead of the element isolation film ISL. The antiferroelectric material constituting the substrate isolation film 20 may be equivalent to the antiferroelectric material constituting the element isolation film ISL in the semiconductor device 101.

[0074] The semiconductor device 102 is configured so that the voltage applied between the bulk layer 10 and the single-crystal layer 30, which are separated by the substrate isolation film 20, during normal operation is less than twice the drive voltage of the MOS transistor TR1 formed in that region. When the drive voltage of the MOS transistor TR1 is 1 V, the semiconductor device 102 is configured so that the voltage applied between the two regions separated by the substrate isolation film 20 during normal operation is less than 2 V. When the drive voltage of the MOS transistor TR1 is 3.3 V, the semiconductor device 102 is configured so that the voltage applied between the two regions separated by the substrate isolation film 20 during normal operation is less than 6.6 V.

[0075] The electric field applied between the two regions separated by the substrate isolation film 20 during normal operation is, for example, less than 50 kV / cm.

[0076] <Method of Manufacturing the Semiconductor Device 102> The method for manufacturing the semiconductor device 102 is basically the same as the method for manufacturing the semiconductor device 101. Hereinafter, the differences between the method for manufacturing the semiconductor device 102 and the method for manufacturing the semiconductor device 101 will be mainly described with reference to FIG.

[0077] First, a semiconductor substrate SUB having a substrate isolation film 20 made of an antiferroelectric material is prepared (sixth step). The semiconductor substrate SUB has a first surface SF1. The substrate isolation film 20 is formed at a temperature below the Curie point of the antiferroelectric material. Furthermore, after this step, the substrate isolation film 20 is not heated to a temperature equal to or higher than the Curie point of the antiferroelectric material. This prevents the antiferroelectric material constituting the substrate isolation film 20 from transforming into a ferroelectric material.

[0078] Second, an isolation film ISL is formed in the single-crystal layer 30 of the semiconductor substrate SUB (seventh step).

[0079] Third, the MOS transistor TR is formed on the first surface SF1 of the semiconductor substrate SUB (third step). In this step, the contact CT element is also formed.

[0080] Fourth, the lower interlayer insulating film ILD1 is formed on the first surface SF1 so as to cover the MOS transistor TR (fourth step).

[0081] Fifth, the contacts CT and the wiring layer M1 are formed (fifth step). The wiring layer M1 is formed by, for example, the damascene method. Thereafter, the middle interlayer insulating film, the middle wiring layer, the upper interlayer insulating film, the upper wiring layer, etc. are formed. In this manner, the semiconductor device 101 shown in FIGS. 2 and 3 is manufactured. In this step, post-metallization annealing (PMA) may be performed. In this case, the heating temperature is set to a temperature below the Curie point of the antiferroelectric material constituting the lower interlayer insulating film ILD1.

[0082] The seventh step may be performed after the step of forming the MOS transistor TR (second step).

[0083] The method for manufacturing the semiconductor device 102 may further include a step of adjusting the relative dielectric constant of the substrate isolation film 20 by irradiating the substrate isolation film 20 with electromagnetic waves during or after the first step. This step may be performed in the same manner as the step of adjusting the relative dielectric constant of the element isolation film ISL in the method for manufacturing the semiconductor device 101. This step may be performed as an annealing treatment of the substrate isolation film 20. For example, when the substrate isolation film 20 is composed of an antiferroelectric material having a perovskite structure, a solvent containing the antiferroelectric material can be spin-coated on the first surface SF1, and then the solvent can be volatilized by irradiating it with electromagnetic waves under predetermined conditions, thereby obtaining a substrate isolation film 20 with an adjusted dielectric constant. The electromagnetic waves may be laser light.

[0084] This step may be performed as an annealing treatment using a hot plate. In this case, the substrate separation film 20 is slowly cooled after heating by the hot plate is stopped, so that the crystal structure of the substrate separation film 20 can be made single crystal.

[0085] Furthermore, this process may reduce the uniformity of at least one of the film quality and film thickness of the substrate separation film 20. For example, the substrate separation film 20 after this process may contain at least one of a large number of aggregates and voids. Therefore, in this process, a process for improving the uniformity of the film quality, film thickness, etc. of the substrate separation film 20 may be performed before the process for adjusting the relative dielectric constant. As such a process, for example, a solvent such as chlorobenzene, dimethylformamide, or 1-cyclohexyl-2-pyrrolidone may be spin-coated onto a solvent containing an antiferroelectric material spin-coated on the first surface SF1.

[0086] <Effects of the semiconductor device 102> The effects of the semiconductor device 102 will be described in comparison with a comparative example. The semiconductor device according to comparative example 2 differs from the semiconductor device 102 only in that the substrate isolation film is made of a typical low-dielectric-constant material. As described above, the relative dielectric constant of typical low-dielectric-constant materials is 2.6 or more and 2.9 or less. Therefore, the semiconductor device according to comparative example 2 can achieve a higher operating speed of the semiconductor element compared to a semiconductor device including a substrate isolation film made of a dielectric material with a relative dielectric constant greater than 2.9. However, in the semiconductor device according to comparative example 2, when cosmic rays are incident on the single-crystalline layer 30 immediately below the gate insulating film GI, a large number of electron-hole pairs are generated in the single-crystalline layer 30 immediately below the gate insulating film GI, resulting in electrical conduction between the source and drain. As a result, the semiconductor device according to comparative example 2 has difficulty in suppressing the occurrence of soft errors caused by cosmic rays while suppressing a decrease in the operating speed of the semiconductor element.

[0087] In contrast, in the semiconductor device 102, since the substrate isolation film 20 is made of an antiferroelectric material, the relative dielectric constant of the substrate isolation film 20 becomes higher than the relative dielectric constant of the substrate isolation film 20 during normal operation only when the strength of the electric field applied to the substrate isolation film 20 by the abnormal charge exceeds the specific value. Therefore, a portion of the abnormal charge can be captured by the substrate isolation film 20. As a result, in the semiconductor device 102, the occurrence of soft errors can be suppressed while suppressing a decrease in the operating speed of the semiconductor element.

[0088] (Embodiment 3) Unless otherwise specified, semiconductor device 103 according to embodiment 3 has the same configuration, operating principle, and effects as those of embodiment 1. Therefore, the same configuration, operating principle, and effects as those of embodiment 1 will not be described repeatedly.

[0089] 9, the semiconductor device 103 according to the third embodiment differs from the semiconductor device 101 in that at least one of the plurality of interlayer insulating films ILD is made of an antiferroelectric. The antiferroelectric constituting at least one of the plurality of interlayer insulating films ILD may be equivalent to the antiferroelectric constituting the element isolation film ISL in the semiconductor device 101. In the semiconductor device 103 shown in FIG. 9, only the lower interlayer insulating film ILD1, which is located at the bottom of the plurality of interlayer insulating films ILD, is made of an antiferroelectric.

[0090] In the semiconductor device 103, during normal operation, the electric field applied between a pair of conductors via at least one interlayer insulating film ILD made of an antiferroelectric is set to be less than the electric field at which spontaneous polarization occurs in the antiferroelectric.

[0091] In the semiconductor device 103, the electric field applied to the interlayer insulating film ILD due to cosmic rays is set to be less than the electric field that causes a phase transition from an antiferroelectric to a ferroelectric. Preferably, the electric field applied to the interlayer insulating film ILD due to ESD is set to be less than the electric field that causes a phase transition from an antiferroelectric to a ferroelectric.

[0092] The at least one interlayer insulating film ILD made of an antiferroelectric material does not have a plurality of pores formed therein. The plurality of interlayer insulating films ILD do not include a porous material. The at least one interlayer insulating film ILD made of an antiferroelectric material has a higher Young's modulus than the Young's modulus of the low-k material made of a porous material. The at least one interlayer insulating film ILD made of an antiferroelectric material has a Young's modulus of 8 GPa or more.

[0093] Preferably, at least one interlayer insulating film ILD made of an antiferroelectric material has an amorphous structure or a polycrystalline structure. The mechanical strength of an antiferroelectric material having an amorphous structure is expected to be higher than that of an antiferroelectric material having a single crystal structure. In an antiferroelectric material having a polycrystalline structure, it is preferable that each of the multiple single crystals is bonded without a binder. The mechanical strength of such an antiferroelectric material is also expected to be higher than that of an antiferroelectric material having a single crystal structure.

[0094] <Effects of the semiconductor device 103> The effects of semiconductor device 103 will be described in comparison with comparative examples. The semiconductor device according to comparative example 3 differs from semiconductor device 103 only in that the interlayer insulating film is made of a general low-dielectric-constant material. As described above, the relative dielectric constant of general low-dielectric-constant materials is 2.6 or higher. Therefore, in order to suppress propagation delay in the semiconductor device according to comparative example 3, it is necessary to increase the distance between two adjacent conductors separated by an interlayer insulating film and reduce the capacitance between the two conductors. Therefore, in the semiconductor device according to comparative example 1, it is difficult to simultaneously achieve high integration of semiconductor elements and miniaturization of each wiring while suppressing the propagation delay that accompanies these increases.

[0095] In contrast, in the semiconductor device 103, the lower interlayer insulating film ILD1 is made of an antiferroelectric material. Therefore, in a state where an external electric field is not applied, the overall electric susceptibility χ of the antiferroelectric material constituting the lower interlayer insulating film ILD1 is lower than that of a general low-dielectric constant material and is less than 1. In other words, the minimum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is less than 2. Therefore, in the semiconductor device 101, the capacitance between two adjacent conductors sandwiching the lower interlayer insulating film ILD1 (for example, the capacitance between the first wiring layer M1A and the second wiring layer M1B) is smaller than the capacitance between two adjacent conductors sandwiching the interlayer insulating film ILD made of a general low-dielectric constant material in the semiconductor device according to Comparative Example 3. Therefore, the semiconductor device 101 can achieve higher integration of semiconductor elements and finer wiring while suppressing the accompanying propagation delay, compared to the semiconductor device according to Comparative Example 3.

[0096] The size and spacing of the semiconductor elements and wiring in semiconductor device 103 may be the same as those in the semiconductor device of Comparative Example 3, in which case the operating speed can be increased compared to the semiconductor device of Comparative Example 3.

[0097] Furthermore, in the semiconductor device according to Comparative Example 3, when abnormal charges due to ESD enter from the pad, the interlayer insulating film made of a low dielectric constant material cannot capture the abnormal charges.

[0098] In contrast, in the semiconductor device 103, when an ESD pulse enters through a pad, an external electric field of 50 kV / cm or more is applied to the lower interlayer insulating film ILD1 located between the pad and the semiconductor element. As a result, the relative dielectric constant of the lower interlayer insulating film ILD1 becomes higher than the relative dielectric constant of the low-k material, and part of the abnormal charge caused by ESD can be trapped in the inter-wiring capacitance with the lower interlayer insulating film ILD1 as the dielectric.

[0099] FIG. 10 is a circuit diagram showing an example of a circuit included in semiconductor device 101 that is realized only when an ESD pulse enters through a pad. FIG. 11 is a graph showing the change over time in current flowing through a MOS transistor after an ESD pulse enters the semiconductor device. The solid line in FIG. 11 indicates the change over time in current flowing through the MOS transistor TR in semiconductor device 101, and the dashed line indicates the change over time in current flowing through the MOS transistor in the semiconductor device according to Comparative Example 1. As shown in FIG. 10, the lower interlayer insulating film ILD1 can function as a capacitor that prevents some of the abnormal charge caused by ESD from reaching the MOS transistor TR. As a result, as shown in FIG. 11, in semiconductor device 103, the current value flowing through the MOS transistor TR can be suppressed to less than the current threshold BD at which the MOS transistor TR is destroyed. As a result, in semiconductor device 103, ESD-induced destruction of semiconductor elements can be suppressed.

[0100] In the semiconductor device according to Comparative Example 3, it is possible to reduce the relative dielectric constant of the interlayer insulating film by using a low-dielectric-constant material with a plurality of pores introduced therein for the interlayer insulating film. However, when the interlayer insulating film is made of a porous low-dielectric-constant material, the mechanical strength of the interlayer insulating film is low, and there is a problem that abnormalities such as cracks are likely to occur in the interlayer insulating film when the wiring layer M is formed by a damascene method or the like. Such abnormalities may cause hard errors in the semiconductor device.

[0101] In contrast, the interlayer insulating film ILD of the semiconductor device 103 does not have multiple voids. The Young's modulus of the interlayer insulating film ILD is 8 GPa or more, which is higher than the Young's modulus of a porous low-dielectric-constant material. Therefore, in the semiconductor device 103, abnormalities such as cracks and dents are unlikely to occur in the interlayer insulating film ILD. For example, when a wire is bonded to a pad by wire bonding, load and ultrasonic waves are applied to each of the multiple interlayer insulating films ILD. When such load and ultrasonic waves are applied to an interlayer insulating film made of a porous low-dielectric-constant material, abnormalities such as cracks are likely to occur. In the semiconductor device 103, cracks are unlikely to occur even when such load and ultrasonic waves are applied to the interlayer insulating film ILD. Furthermore, when the wiring layer M is formed by the damascene method, dents are likely to occur in the interlayer insulating film when forming wiring trenches in the interlayer insulating film made of a porous low-dielectric-constant material, making it difficult to properly form the wiring trenches. In the semiconductor device 103, dents are unlikely to occur in the interlayer insulating film ILD even when the wiring layer M1 is formed by the damascene method. Therefore, in the semiconductor device 101, the occurrence of hard errors can also be suppressed.

[0102] 12, in the semiconductor device 103, only the upper interlayer insulating film ILD2 among the multiple interlayer insulating films ILD may be made of an antiferroelectric material. The lower interlayer insulating film ILD1 may be made of a paraelectric material or the above-mentioned general low-dielectric-constant material.

[0103] 13 is a circuit diagram showing an example of a circuit that is implemented only when an ESD pulse enters through a pad in the semiconductor device 103 shown in FIG. 12. As shown in FIG. 13, the upper interlayer insulating film ILD1 is disposed directly below the pad PAD and can function as a capacitor that prevents some of the abnormal charges caused by ESD from reaching the MOS transistor TR and other electronic components. Therefore, the semiconductor device 103, which includes the upper interlayer insulating film ILD2 made of an antiferroelectric, has a higher ESD protection capability due to the antiferroelectric than the semiconductor device 101, which includes only the lower interlayer insulating film ILD1 made of an antiferroelectric.

[0104] In the semiconductor device 103, each of the plurality of interlayer insulating films ILD may be made of an antiferroelectric material. The antiferroelectric materials constituting each of the plurality of interlayer insulating films ILD may be the same as or different from each other.

[0105] The semiconductor device 103 may have the same configuration as the semiconductor device 102, except that the interlayer insulating film is made of an antiferroelectric material.

[0106] As described for the semiconductor device 101, the interlayer insulating film, element isolation film, and substrate isolation film made of an antiferroelectric may also be transformed from an antiferroelectric to a ferroelectric in the semiconductor devices 102 to 104. In this case, by performing a process to return the interlayer insulating film, element isolation film, and substrate isolation film from a ferroelectric to an antiferroelectric, the above-mentioned effects achieved by the interlayer insulating film, element isolation film, and substrate isolation film made of an antiferroelectric in the semiconductor devices 101 to 104 can be reproduced. As described above, an example of a process for returning the interlayer insulating film, element isolation film, and substrate isolation film from a ferroelectric to an antiferroelectric is to apply alternating positive and negative voltages, such as AC, to the element isolation film and substrate isolation film, and gradually reduce this voltage. This process disrupts the ferroelectric crystal structure, allowing the antiferroelectric crystal structure to be reproduced. Another example of a process is to heat the element isolation film and substrate isolation film and then rapidly cool them. This process destroys the ferroelectric crystal structure, allowing the antiferroelectric crystal structure to be reproduced.

[0107] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0108] 1 scribe area, 2 module area, SUB semiconductor substrate, SF1 first surface, 10 bulk layer, 20 substrate isolation film, 30 single crystal layer, 101, 102, 103, 104 semiconductor device, IOC input / output circuit, ANA analog circuit, LC logic circuit, MEM memory circuit, CT contact, C1A first contact CT layer, C1B second contact CT layer, DR drain, SO source, GE gate electrode, GI gate insulating film, ILD interlayer insulating film, ILD1 lower interlayer insulating film, ILD2 upper interlayer insulating film, ILD3 top interlayer insulating film, ISL element isolation film, M, M1 wiring layer, M1A first wiring layer, M1B second wiring layer, M2 top wiring layer, PW p-type well, SW sidewall insulating film, TR MOS transistor.

Claims

1. a semiconductor substrate having a single crystal layer; a plurality of semiconductor elements formed on the single crystal layer; an isolation film formed on the semiconductor substrate so as to surround each of the plurality of semiconductor elements in a plan view and isolating the plurality of semiconductor elements from each other; the separation film is made of an antiferroelectric material, the minimum value of the relative dielectric constant of the isolation film is less than 2.

2. a semiconductor substrate having a bulk layer and a single-crystal layer; a plurality of semiconductor elements formed on the single crystal layer; the semiconductor substrate further includes an isolation film disposed between the bulk layer and the single-crystal layer, and isolating the bulk layer from the plurality of semiconductor elements; the separation film is made of an antiferroelectric material, the minimum value of the relative dielectric constant of the isolation film is less than 2.

3. 3. The semiconductor device according to claim 1, wherein the maximum value of the relative dielectric constant of said isolation film is greater than 2.

9.

4. 3. The semiconductor device according to claim 1, wherein the isolation film has a Young's modulus of 8 GPa or more.

5. The remanent polarization of the separator is 15 μC / cm 2 3. The semiconductor device according to claim 1, wherein:

6. 3. The semiconductor device according to claim 1, wherein the isolation film does not have a plurality of voids formed therein.

7. The material constituting the antiferroelectric is HfO 2 , ZrO 2 , Pb(In 0.5 Nb 0.5 ) O 3 , NbNaO 3 , ZrPbO 3 , TiZrLaPbO 3 , TiZrPbO 3 , N.H. 4 H 2 P.O. 4 , or NH 4 H 2 AsO 4 3. The semiconductor device according to claim 1, wherein the semiconductor device is at least one selected from the group consisting of:

8. 3. The semiconductor device according to claim 1, wherein the isolation film has a thickness of 2 nm or more and less than 50 nm.

9. the separation film is an insulating film that electrically insulates two adjacent regions with the separation film therebetween, 3. The semiconductor device according to claim 1, wherein an electric field applied between said two regions during normal operation is set to be less than an electric field that generates spontaneous polarization in said antiferroelectric material.

10. 10. The semiconductor device according to claim 9, wherein a voltage applied between said two regions via said isolation film during normal operation is less than twice the drive voltage of each of said plurality of semiconductor elements.

11. 3. The semiconductor device according to claim 1, wherein spontaneous polarization occurs in said antiferroelectric material when cosmic rays are incident thereon.

12. the cosmic rays include particle radiation and / or high-energy electromagnetic radiation; the particle radiation includes at least one selected from the group consisting of α rays, β rays, neutron rays, and proton rays; The semiconductor device according to claim 11 , wherein the high-energy electromagnetic radiation includes at least one of gamma rays and X-rays.

13. further comprising an interlayer insulating film formed on the semiconductor substrate; the interlayer insulating film is made of an antiferroelectric material, 3. The semiconductor device according to claim 1, wherein the minimum value of the relative dielectric constant of said interlayer insulating film is less than 2.

14. a pad disposed on the interlayer insulating film; 14. The semiconductor device according to claim 13, wherein spontaneous polarization occurs in the antiferroelectric material when an electric field of 50 kV / cm or more is applied to the pad.

15. After the application of the electric field is stopped, the polarization of the interlayer insulating film is 15 μC / cm 2 15. The semiconductor device according to claim 14, wherein:

16. a second interlayer insulating film formed between the semiconductor substrate and the interlayer insulating film; 14. The semiconductor device according to claim 13, wherein said second interlayer insulating film is made of a paraelectric conductor.

17. the interlayer insulating film has a second surface; the pad is formed on the second surface, 15. The semiconductor device according to claim 14, wherein said antiferroelectric material constituting at least said second surface of said interlayer insulating film has an amorphous structure or a polycrystalline structure.

18. a gate electrode formed on the single-crystal layer via a gate insulating film; a sidewall insulating film covering each side surface of the gate insulating film and the gate electrode; an interlayer insulating film formed on the single-crystal layer so as to cover the gate electrode and the sidewall insulating film; the interlayer insulating film is made of an antiferroelectric material, 3. The semiconductor device according to claim 1, wherein said interlayer insulating film is disposed at a distance from said gate insulating film.

19. 19. The semiconductor device according to claim 18, wherein said interlayer insulating film is in contact with said sidewall insulating film.

20. A first step of preparing a semiconductor substrate having a single crystal layer; a second step of forming a plurality of semiconductor elements in the single crystal layer; a third step of forming an isolation film in the single crystal layer to isolate the plurality of semiconductor elements from each other, In the third step, the isolation film made of an antiferroelectric material is formed at a temperature lower than the Curie point of the antiferroelectric material so as to surround each of the plurality of semiconductor elements in a plan view.

21. A first step of preparing a semiconductor substrate having a bulk layer, a single-crystal layer, and an isolation film disposed between the bulk layer and the single-crystal layer to isolate the bulk layer from the single-crystal layer; a second step of forming a plurality of semiconductor elements in the single crystal layer; In the first step, the isolation film made of an antiferroelectric material is formed at a temperature lower than the Curie point of the antiferroelectric material.

22. further comprising a step of designing a layout of the isolation film based on a result of a circuit simulation that simulates an operation of a circuit including the plurality of semiconductor elements; 22. The method for manufacturing a semiconductor device according to claim 20, wherein the isolation film is formed based on the layout.

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