Semiconductor device, boot program executing method, and non-transitory computer-readable medium

Abstract

To shorten a start time of a semiconductor device and suppress a device cost.SOLUTION: A semiconductor device 1 includes a CPU 11, a DMA controller 12, a first memory 13, and a second memory 14. The CPU 11 writes in an interruption program and an interruption jump command in the second memory 14 by executing an initialization program of the first memory 13. The DMA controller 12 starts DMA transfer of a boot program to the second memory 14 by over-writing the interruption jump command. The CPU 11 starts execution processing of the boot program after the lapse of a predetermined time from the start of the DMA transfer. When a command execution address reaches an address of a DMA non-transfer region, the CPU 11 executes the interruption jump command. The CPU 11 delays the execution processing of the boot program by executing the interruption program at a jump destination.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a boot program execution method, and a non-transitory computer-readable medium for storing a program. [Background technology]

[0002] In recent years, advances in autonomous driving and connected technologies have significantly increased the performance and functionality of in-vehicle systems. Accordingly, there is also a demand for shortening the startup time of in-vehicle systems. The startup process of an in-vehicle system is performed by the central processing unit (CPU) installed in the in-vehicle system executing a boot program. The boot program is stored in an auxiliary storage device and, when the in-vehicle system starts up, is transferred to a main storage device such as a random access memory (RAM) by a direct memory access (DMA) controller. Therefore, in order to shorten the startup time of an in-vehicle system, it is necessary to consider not only the time required to execute the boot program, but also the time required to transfer the boot program from the auxiliary storage device to the main storage device.

[0003] For example, Patent Document 1 discloses a technique for shortening the startup time of a device by performing a boot code (boot program) transfer process and a boot code execution process in parallel. The device disclosed in Patent Document 1 includes a CPU that executes the boot code, a NAND flash that is the source of the boot code, a RAM that is the destination of the boot code, a bus control unit that outputs a request address for reading instructions included in the boot code transferred to the RAM, and a main memory / NAND flash control unit that generates an external wait signal to put the CPU into standby mode.

[0004] The main memory / NAND flash control unit monitors the request address output from the bus control unit while transferring the boot code from the NAND flash to RAM. If the request address is larger than the transfer address used to transfer the boot code from the NAND flash to RAM, the main memory / NAND flash control unit determines that the transfer of the boot code to be executed by the CPU has not been completed and generates an external wait signal. In this case, the boot code transfer process continues, but the execution of the boot code by the CPU is suspended. On the other hand, if the request address is smaller than the transfer address, the main memory / NAND flash control unit determines that the transfer of the boot code to be executed by the CPU has been completed and does not generate an external wait signal. In this case, the boot code transfer process and the boot code execution process by the CPU are performed in parallel. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-10942 Summary of the Invention [Problem to be solved by the invention]

[0006] In this way, the device disclosed in Patent Document 1 shortens the startup time of the device by transferring the boot code from the NAND flash to the RAM and executing the boot code by the CPU in parallel. However, the device disclosed in Patent Document 1 determines whether the transfer of the boot code to be executed by the CPU has been completed by monitoring the magnitude relationship between the request address and the transfer address, so it is necessary to implement a main memory / NAND flash control unit (hardware) that monitors the magnitude relationship between the request address and the transfer address. Adding such hardware increases the cost of the device.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment includes a CPU, a first memory, a second memory, and a DMA controller. The CPU executes an initialization program stored in the first memory to write an interrupt program and multiple interrupt jump instructions to an interrupt program write area and a boot program write area in the second memory, respectively. The DMA controller starts a DMA transfer process to transfer the boot program to the second memory by overwriting the multiple interrupt jump instructions written in the second memory. The CPU starts executing instructions included in the boot program DMA-transferred to the second memory after a predetermined time has elapsed since the start of the DMA transfer process. During the execution of the instructions included in the boot program, the CPU's instruction execution address reaches an address in the boot program write area in the second memory for which the DMA transfer process has not yet been completed, causing the CPU to execute the interrupt jump instruction. After the execution of the interrupt jump instruction changes the CPU's instruction execution address to an address in the interrupt program write area in the second memory, the CPU executes the interrupt program to delay the execution of the instructions included in the boot program. [Effects of the Invention]

[0009] According to the present disclosure, the transfer and execution of the boot program can be performed in parallel without adding hardware for monitoring the magnitude relationship between the request address and the transfer address, thereby reducing the startup time of the semiconductor device while suppressing increases in device costs. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of a hardware configuration of a semiconductor device according to the first embodiment. [Figure 2]FIG. 2 is a flowchart showing an example of a processing flow of a boot program execution method. [Figure 3] FIG. 3 is a diagram illustrating an example of a memory map of the second memory according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a memory map of the second memory according to the first embodiment. [Figure 5] FIG. 5 is a diagram illustrating an example of a memory map of the second memory according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of a memory map of the second memory according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of a memory map of the second memory according to the first embodiment. [Figure 8] FIG. 8 is a block diagram showing an example of a hardware configuration of the semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of a memory map of the second memory according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, the embodiments will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are designated by the same reference numerals, and duplicate explanations will be omitted. In addition, in the drawings, configurations may be omitted or simplified for the sake of convenience.

[0012] The program may be stored on various types of non-transitory computer-readable or tangible storage media. By way of example and not limitation, non-transitory computer-readable or tangible storage media include RAM, Read Only Memory (ROM), flash memory, Solid State Drive (SSD) or other memory technology, Compact Disc (CD)-ROM, Digital Versatile Disc (DVD), Blu-ray® disc or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may also be transmitted over various types of transitory computer-readable or communication media. By way of example and not limitation, transitory computer-readable or communication media include electrical, optical, acoustic, or other forms of propagated signals.

[0013] [Embodiment 1] Fig. 1 is a block diagram showing an example of a hardware configuration of a semiconductor device 1 according to embodiment 1. As shown in Fig. 1, the semiconductor device 1 includes a CPU 11, a DMA controller 12, a first memory 13, a second memory 14, a third memory 15, and a bus 16. The CPU 11 and the DMA controller 12 are configured to be able to access the first memory 13, the second memory 14, and the third memory 15 via the bus 16. The CPU 11 and the DMA controller 12 are also configured to be able to access each other via the bus 16.

[0014] The CPU 11 executes a control program stored in the first memory 13 and a boot program stored in the second memory 14. The control program is a program for causing the semiconductor device 1 to execute a boot program execution method.

[0015] The DMA controller 12 executes a DMA transfer of data stored in the first to third memories 13 to 15 based on the DMA transfer parameters. The DMA transfer parameters are information necessary to execute a DMA transfer, such as a transfer source address and a transfer destination address, and are set by the CPU 11 before the DMA transfer is executed.

[0016] The first memory 13 is configured, for example, by a nonvolatile memory such as a ROM, and stores control programs executed by the CPU 11. The control programs include an initialization program for initializing the second memory 14, a DMA transfer processing program for causing the DMA controller 12 to execute DMA transfers, and a boot program execution processing program for executing the boot program.

[0017] The second memory 14 is configured with a volatile memory such as RAM, and has an interrupt program write area and a boot program write area. An interrupt program including an instruction for delaying the execution of the boot program is written in the interrupt program write area. The boot program is written to the boot program write area by DMA transfer.

[0018] The third memory 15 is configured by a nonvolatile memory such as a flash ROM, and stores a boot program. The boot program is a program that defines the operation of the semiconductor device 1 at startup. The boot program stored in the third memory 15 is DMA-transferred to the second memory 14 by the DMA controller 12 at startup of the semiconductor device 1. Note that, although the third memory 15 is included in the semiconductor device 1 in the configuration example shown in FIG. 1 , it may also be a memory device located outside the semiconductor device 1.

[0019] Next, a boot program execution method executed in the semiconductor device 1 according to the first embodiment will be described with reference to Figures 2 to 7. Figure 2 is a flowchart showing an example of a processing flow of the boot program execution method. The flowchart in Figure 2 includes seven processing steps consisting of steps S101 to S107. Figures 3 to 7 are diagrams for explaining the boot program transfer processing and boot program execution processing in the second memory 14.

[0020] 2, an initialization process of the second memory is executed. When power supply to the semiconductor device 1 is started and the reset signal is deactivated, the CPU 11 reads and executes the initialization program stored in the first memory 13. By executing the initialization program, the CPU 11 writes an interrupt program including an instruction for delaying execution of the boot program to an interrupt program write area of ​​the second memory 14, and also writes a plurality of interrupt jump instructions including an instruction for changing the instruction execution address of the CPU 11 to an address in the interrupt program write area to the boot program write area of ​​the second memory 14.

[0021] 3 is a diagram showing an example of a memory map of the second memory 14 before the initialization process of step S101 is executed. As shown in FIG. 3, the second memory 14 has an interrupt program write area 141 and a boot program write area 142. The sizes of the interrupt program write area 141 and the boot program write area 142 are preferably determined according to the sizes of the interrupt program and the boot program. Furthermore, the position of the interrupt program write area 141 in FIG. 3 is an example and is not limited to the position shown in FIG. 3.

[0022] 4 is a diagram showing an example of a memory map of the second memory 14 after the initialization process of step S101 has been executed. As shown in FIG. 4, an interrupt program is written to the interrupt program write area 141. Furthermore, multiple interrupt jump instructions are written to the boot program write area 142. That is, the entire area where the boot program will be written in future processing steps will be filled with interrupt jump instructions. In FIG. 4, the state where the interrupt program has been written to the interrupt program write area 141 is represented by the symbol 141a, and the state where the interrupt jump instructions have been written to the boot program write area 142 is represented by the symbol 142a. The same applies to the other drawings.

[0023] The DMA controller 12 can also be used for the write process of the interrupt program and the interrupt jump instructions in the initialization process of step S101. That is, the CPU 11 executes the initialization program to cause the DMA controller 12 to execute the DMA transfer process of the interrupt program and the multiple interrupt jump instructions to the interrupt program write area 141 and the boot program write area 142 of the second memory 14. In this case, the initialization program includes a program for setting DMA transfer parameters required for the DMA controller 12 to execute the DMA transfer process of the interrupt program and the multiple interrupt jump instructions. The interrupt program and the multiple interrupt jump instructions to be DMA transferred may be stored in either the first memory 13 or the third memory 15.

[0024] 2, DMA transfer processing of the boot program is started. The CPU 11 reads and executes the DMA transfer processing program stored in the first memory 13. By executing the DMA transfer processing program, the DMA controller 12 sets DMA transfer parameters necessary for DMA transfer of the boot program from the third memory 15 to the second memory 14, and after the setting process is completed, an instruction to start the DMA transfer is output. As a result, the DMA controller 12 starts the DMA transfer process of transferring the boot program stored in the third memory 15 to the second memory 14 by overwriting the multiple interrupt jump instructions written in the boot program write area 142.

[0025] In step S103 of FIG. 2, it is determined whether a predetermined time has elapsed since the start of the DMA transfer process of the boot program. The CPU 11 reads and executes the boot program execution process program stored in the first memory 13. This allows the CPU 11 to control the timing of starting the execution process of the boot program DMA-transferred to the second memory 14. In the present disclosure, the boot program execution process is started before the entire DMA transfer process of the boot program is completed. That is, in the present disclosure, the boot program transfer process and the boot program execution process are performed in parallel, thereby shortening the startup time of the semiconductor device 1. Note that the predetermined time in step S103, i.e., the time from the start of the DMA transfer process of the boot program to the start of the execution process of the boot program, can be determined, for example, depending on the DMA transfer processing speed of the boot program and the execution processing speed of the boot program.

[0026] If it is determined that the predetermined time has elapsed since the start of the DMA transfer process of the boot program (YES in step S103), the process proceeds to step S104. On the other hand, if it is not determined that the predetermined time has elapsed since the start of the DMA transfer process of the boot program (NO in step S103), the process returns to step S103.

[0027] 2, the boot program execution process is started. After a predetermined time has elapsed since the start of the DMA transfer process of the boot program, the CPU 11 starts the execution process of the instructions included in the boot program that has been DMA transferred to the second memory 14.

[0028] Fig. 5 is a diagram showing an example of a memory map of the second memory 14 when the execution process of the boot program has started. In Fig. 5, the state in which the boot program has been written by overwriting the interrupt jump instruction is represented by the reference numeral 142b, and the status of the execution process of the boot program is represented by the arrow with the reference numeral 143. The same applies to the other drawings.

[0029] The CPU 11 executes instructions included in the program using the address indicated by the program counter as the instruction execution address. That is, when the CPU 11 executes the boot program written in the second memory 14, an address corresponding to the boot program write area 142 in the second memory 14 is specified as the instruction execution address of the CPU 11. The address at the tip of the arrow in Figure 5 corresponds to the instruction execution address of the CPU 11 at the time shown in Figure 5. The CPU 11 fetches and executes the instruction from the boot program write area 142 that corresponds to the instruction execution address.

[0030] Furthermore, because there is a time difference between the start of the DMA transfer process of the boot program and the start of the execution process of the boot program, the range of boot program write area 142b for which the DMA transfer of the boot program has been completed is larger at the time the execution process of the boot program is started, as shown in Fig. 5. This makes it possible to prevent the instruction execution address of CPU 11 from exceeding the address of the area for which the DMA transfer has been completed in a short period of time when the execution speed of the boot program is faster than the DMA transfer speed of the boot program.

[0031] In step S105 of FIG. 2, it is determined whether the instruction execution address of the CPU 11 has reached the address of an area of ​​the boot program where DMA transfer has not yet been performed. As the CPU 11 increments the instruction execution address and sequentially executes instructions included in the DMA-transferred boot program, it is possible that the instruction execution address of the CPU 11 may reach the address of an area of ​​the boot program where DMA transfer has not yet been completed (an area where DMA transfer has not yet been performed). An interrupt jump instruction has been written to the area where DMA transfer has not yet been performed before the boot program has been overwritten. That is, when the instruction execution address of the CPU 11 reaches the address of an area where DMA transfer has not yet been performed during the execution of an instruction included in the boot program, the CPU 11 executes the interrupt jump instruction. By executing the interrupt jump instruction, the CPU 11 recognizes that the instruction execution address of the CPU 11 has reached the address of an area where DMA transfer has not yet been performed in the boot program.

[0032] There are two main cases in which the instruction execution address of the CPU 11 reaches an address in the boot program's untransferred area. The first case is when the boot program's execution speed is faster than its DMA transfer speed, causing the instruction execution address of the CPU 11 to catch up with the address in the boot program write area 142 of the second memory 14 while the boot program is being DMA transferred. The second case is when the boot program contains a branch instruction, and the branch destination of the branch instruction is located within the boot program's untransferred area. When the CPU 11 executes such a branch instruction, the instruction execution address of the CPU 11 reaches an address in the boot program's untransferred area.

[0033] 6 is a diagram showing an example of the memory map of the second memory 14 when the instruction execution address of the CPU 11 reaches the DMA untransferred area of ​​the boot program. The example in FIG. 6 corresponds to the first case described above. As shown in FIG. 6, the instruction execution address of the CPU 11 reaches the address of point A, which is included in the DMA untransferred area of ​​the boot program. The DMA untransferred area of ​​the boot program is in a state before the interrupt jump instruction is overwritten, and therefore corresponds to the boot program write area 142a where the interrupt jump instruction has been written. The CPU 11 executes the interrupt jump instruction written at point A, and changes the instruction execution address of the CPU 11 to an address in the interrupt program write area 141a where the interrupt program has been written.

[0034] If it is determined that the instruction execution address of the CPU 11 has reached the address of the DMA untransferred area of ​​the boot program, in other words, if the CPU 11 has executed an interrupt jump instruction (YES in step S105), the process proceeds to step S106. On the other hand, if it is not determined that the instruction execution address of the CPU 11 has reached the address of the DMA untransferred area of ​​the boot program, in other words, if the CPU 11 has not executed an interrupt jump instruction (NO in step S105), the process proceeds to step S107.

[0035] 2, an interrupt program including an instruction for delaying execution of the boot program is executed. After the instruction execution address of CPU 11 is changed to an address in interrupt program write area 141a where the interrupt program is written by executing the interrupt jump instruction, CPU 11 executes the interrupt program written in interrupt program write area 141a to delay execution of the instructions included in the boot program.

[0036] 7 is a diagram showing an example of a memory map of the second memory 14 when an interrupt program is executed. As shown in Fig. 7, the CPU 11 executes the interrupt program written in the interrupt program write area 141a. Because the interrupt program includes an instruction for delaying the execution of the boot program, the CPU 11 executes the interrupt program to put the execution of the boot program on hold.

[0037] The time for delaying the execution of instructions included in the boot program, i.e., the standby time for the execution of the boot program, may be determined according to the difference between the DMA transfer processing speed of the boot program and the instruction execution processing speed of the boot program. For example, if the DMA transfer processing speed of the boot program is slower than the instruction execution processing speed of the boot program and the difference between these speeds is large, the standby time for the execution of the boot program may be set long. Also, even if the DMA transfer processing speed of the boot program is slower than the instruction execution processing speed of the boot program, if the difference between these speeds is relatively small, the standby time for the execution of the boot program may be set short.

[0038] After executing the interrupt program to delay the execution of the instructions included in the boot program, the CPU 11 sets the address where the executed interrupt jump instruction was written as the instruction execution address again, and resumes the execution of the instructions included in the boot program. That is, after execution of step S106, the process returns to step S104.

[0039] As shown in Figure 7, after the execution of the interrupt program, the instruction execution address of the CPU 11 returns to point A again. While the execution of the boot program is put on hold, the DMA transfer process of the boot program by the DMA controller 12 proceeds. That is, the range of the boot program write area 142b in Figure 7 is wider than the range of the boot program write area 142b in Figure 6. As a result, point A in Figure 7 is included in the boot program write area 142b for which the DMA transfer process of the boot program has been completed. As a result, the CPU 11 can resume the execution of the instructions included in the boot program.

[0040] In step S107 of Fig. 2, it is determined whether the execution of the boot program has been completed. If it is determined that the execution of the boot program has been completed (YES in step S107), the example process flow shown in Fig. 2 ends. On the other hand, if it is not determined that the execution of the boot program has been completed (NO in step S107), the process returns to step S104, and the execution of the boot program continues.

[0041] As described above, according to the first embodiment, before executing the DMA transfer process of the boot program from the third memory 15 to the second memory 14, an interrupt jump instruction is written to the area of ​​the second memory 14 where the boot program is to be written by DMA transfer. After a predetermined time has elapsed since the start of the DMA transfer process of the boot program by the DMA controller 12, the CPU 11 starts executing the boot program. When the instruction execution address of the CPU 11 reaches an address in an area of ​​the boot program that has not yet been DMA transferred during execution of the boot program, the CPU 11 executes the interrupt jump instruction, and the instruction execution address of the CPU 11 is changed to the address of an area where an interrupt program containing an instruction for delaying execution of the boot program has been written. The CPU 11 executes the interrupt program, performs processing to delay execution of the boot program, and then resumes execution of the boot program.

[0042] In this way, the semiconductor device 1 according to the first embodiment can shorten the startup time of the semiconductor device 1 by performing the DMA transfer process of the boot program and the execution process of the boot program in parallel. Also, by writing an interrupt jump instruction and an interrupt program to the second memory 14, which is the transfer destination of the boot program, before the DMA transfer of the boot program is started, a process of detecting that the instruction execution address of the CPU 11 has reached an address in an area of ​​the boot program that has not yet been DMA transferred, and a process of putting the execution process of the boot program on hold are realized. This eliminates the need for hardware for monitoring the progress of the execution process of the boot program and the DMA transfer process, thereby suppressing increases in device costs.

[0043] [Embodiment 2] A description will be given of a second embodiment. In the first embodiment, a semiconductor device including one DMA controller has been described. In the second embodiment, a semiconductor device including multiple DMA controllers will be described.

[0044] Fig. 8 is a block diagram showing an example of a hardware configuration of the semiconductor device 2 according to the second embodiment. As shown in Fig. 8, the semiconductor device 2 according to the second embodiment includes a DMA controller 21 in addition to the configuration of the semiconductor device 1 according to the first embodiment. Also, the second memory 14 is changed to a second memory 22.

[0045] DMA controller 21 is connected to bus 16 and has a DMA transfer function similar to DMA controller 12. In semiconductor device 2 according to embodiment 2, DMA transfer is performed using DMA controller 12 (first DMA controller) and DMA controller 21 (second DMA controller).

[0046] The second memory 22 is the same as the second memory 14 in that it has an interrupt program write area and a boot program write area. However, the second memory 22 differs from the second memory 14 in that the boot program write area includes a first boot program write area and a second boot program write area. Of the DMA transfer processes related to the boot program write area, the DMA transfer process related to the first boot program write area is performed by the DMA controller 12, and the DMA transfer process related to the second boot program write area is performed by the DMA controller 21.

[0047] FIG. 9 is a diagram showing an example of a memory map of the second memory 22 before the initialization process is executed. As shown in FIG. 9, the second memory 22 has a boot program write area composed of first boot program write areas 221a and 221b and second boot program write areas 222a and 222b. The first boot program write areas 221a and 221b are arranged spaced apart from each other. The same applies to the second boot program write areas 222a and 222b. In the present disclosure, the first boot program write areas 221a and 221b are also collectively referred to as the first boot program write area 221. The second boot program write areas 222a and 222b are also collectively referred to as the second boot program write area 222.

[0048] Next, a boot program execution method executed in the semiconductor device 2 according to the second embodiment will be described with reference to Fig. 2. The difference between the first embodiment and the second embodiment is in the processing related to DMA transfer, and therefore the processing flow of the boot program execution method according to the second embodiment will be described focusing on the part related to the DMA transfer processing, and the description of the other parts will be omitted.

[0049] 2, the DMA controllers 12 and 21 can also be used to write the interrupt program and the interrupt jump instructions in the initialization process of step S101. That is, the CPU 11 executes an initialization program to cause the DMA controllers 12 and 21 to execute DMA transfer processing of the interrupt program and the multiple interrupt jump instructions to the second memory 22. In this case, the initialization program includes a program for setting DMA transfer parameters required for the DMA controllers 12 and 21 to execute DMA transfer processing of the interrupt program and the multiple interrupt jump instructions. By using two DMA controllers, the write processing of the interrupt program and the interrupt jump instructions can be executed in a shorter time than in the first embodiment, which uses one DMA controller.

[0050] When the DMA controllers 12 and 21 are used to write the interrupt program and the interrupt jump instruction, the DMA controller 12 may write a plurality of interrupt jump instructions to the first boot program write area 221a, and the DMA controller 21 may write a plurality of interrupt jump instructions to the second boot program write area 222a. Alternatively, either the DMA controller 12 or 21 may write the interrupt program to the interrupt program write area 141.

[0051] 2, the DMA transfer process of the boot program uses the DMA controllers 12 and 21. That is, the CPU 11 executes the DMA transfer process program, whereby the DMA controllers 12 and 21 perform a setting process of DMA transfer parameters required for the DMA controllers 12 and 21 to DMA transfer the boot program from the third memory 15 to the second memory 22, and after the setting process is completed, an instruction to start the DMA transfer is output.

[0052] When DMA controllers 12 and 21 are used for the DMA transfer processing of the boot program, DMA controller 12 performs the DMA transfer processing of part of the boot program, and DMA controller 21 performs the DMA transfer processing of the remaining part of the boot program. In this disclosure, the part of the boot program that is DMA transferred by DMA controller 12 is referred to as the first part of the boot program, and the part of the boot program that is DMA transferred by DMA controller 21 is referred to as the second part of the boot program. In other words, the boot program includes the first part and the second part.

[0053] 2, the DMA controller 12 starts a DMA transfer process (first DMA transfer process) for transferring a first portion of the boot program stored in the third memory 15 to the second memory 22 by overwriting the multiple interrupt jump instructions written in the first boot program write area 221. In addition, the DMA controller 21 starts a DMA transfer process (second DMA transfer process) for transferring a second portion of the boot program stored in the third memory 15 to the second memory 22 by overwriting the multiple interrupt jump instructions written in the second boot program write area 222.

[0054] It is desirable that the DMA controllers 12 and 21 give priority to executing DMA transfer processing for an area of ​​the boot program write area that is closest to the beginning of the boot program. For example, in the memory map of the second memory 22 shown in Fig. 9, if the boot program is executed from the upper left of the second memory 22 in step S104 of Fig. 2, it is desirable that the DMA controller 12 starts executing DMA transfer processing for the first boot program write area 221a, and the DMA controller 21 starts executing DMA transfer processing for the second boot program write area 222a.

[0055] 2, after a predetermined time has elapsed since the start of the DMA transfer process by DMA controller 12 and the DMA transfer process by DMA controller 21, CPU 11 starts the execution process of the instructions included in the boot program that has been DMA transferred to second memory 22. Note that in the second embodiment, since the DMA transfer process is performed by two DMA controllers, the DMA transfer processing speed in the second embodiment is greater than the DMA transfer processing speed in the first embodiment. Therefore, the time from the start of the DMA transfer processing of the boot program to the start of the execution processing of the boot program in the second embodiment may be shorter than that in the first embodiment.

[0056] 2, during the execution of an instruction included in the boot program, the instruction execution address of CPU 11 reaches an address in the boot program write area where DMA transfer processing by DMA controller 12 or DMA controller 21 has not been completed, causing CPU 11 to execute the interrupt jump instruction. By executing the interrupt jump instruction, CPU 11 recognizes that the instruction execution address of CPU 11 has reached an address in the area where DMA transfer of the boot program by DMA controllers 12 and 21 has not been completed, i.e., an address in the DMA untransferred area.

[0057] As in the first embodiment, in the second embodiment, the execution of instructions included in the boot program is delayed by executing an interrupt program in step S106. Since the DMA transfer processing speed in the second embodiment is faster than that in the first embodiment, the time for delaying the execution of instructions included in the boot program in the second embodiment, i.e., the waiting time for the execution of the boot program, may be shorter than that in the first embodiment.

[0058] As described above, in the second embodiment, similar to the first embodiment, the DMA transfer process of the boot program and the execution process of the boot program are performed in parallel, thereby shortening the startup time of the semiconductor device.

[0059] Furthermore, in the second embodiment, two DMA controllers are used to perform the DMA transfer processing of the boot program, thereby enabling a faster DMA transfer processing speed of the boot program compared to the first embodiment. Therefore, if the DMA transfer processing speed of the boot program is slower than the execution processing speed of the boot program, the difference in speed can be reduced by using two DMA controllers. This makes it less likely that the instruction execution address of the CPU 11 will catch up with the address of the boot program write area while the DMA transfer processing of the boot program is being performed. This reduces the number of times an interrupt program intended to delay the execution processing of the boot program is executed, thereby further shortening the startup time of the semiconductor device.

[0060] In the second embodiment, an example in which two DMA controllers are used to execute the DMA transfer process of the boot program has been described. However, the number of DMA controllers is not limited to two, and may be any number. For example, if the semiconductor device is equipped with three DMA controllers, all three DMA controllers may be used for the DMA transfer process of the boot program. In this case, the boot program write area of ​​the second memory may be configured to include the first to third boot program write areas. Furthermore, as long as the DMA controllers already installed in the semiconductor device are used, there is no increase in device costs.

[0061] In addition, in embodiment 2, an example was described in which each of the first boot program write area 221 and the second boot program write area 222 includes two areas spaced apart from each other, but the number of areas spaced apart from each other may be multiple and is not limited to two.

[0062] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0063] 1, 2: Semiconductor device 11:CPU 12,21:DMA controller 13: First memory 14,22: Second memory 141, 141a: Interrupt program writing area 142, 142a, 142b: Boot program write area 143: Boot program execution status 15: Third Memory 16: Bus 221a, 221b: First boot program write area 222a, 222b: Second boot program writing area

Claims

1. A CPU and a first memory for storing an initialization program; a second memory having an interrupt program write area and a boot program write area; a DMA controller; Equipped with the CPU executes the initialization program to write, into the interrupt program write area, an interrupt program including an instruction for delaying execution processing of a boot program, and writes, into the boot program write area, a plurality of interrupt jump instructions including an instruction for changing an instruction execution address of the CPU to an address in the interrupt program write area; the DMA controller starts a DMA transfer process for transferring the boot program stored in a third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the boot program write area; The CPU After a predetermined time has elapsed since the start of the DMA transfer process, an execution process of instructions included in the boot program DMA-transferred to the second memory is started; During execution of an instruction included in the boot program, an instruction execution address of the CPU reaches an address in the boot program write area for which the DMA transfer process has not been completed, thereby executing the interrupt jump instruction; After the instruction execution address of the CPU is changed to an address in the interrupt program write area by executing the interrupt jump instruction, the interrupt program written in the interrupt program write area is executed, and execution of instructions included in the boot program is delayed. Semiconductor device.

2. 2. The semiconductor device according to claim 1, the CPU delays the execution of the instructions included in the boot program, and then sets the address where the executed interrupt jump instruction was written as an instruction execution address again, and resumes the execution of the instructions included in the boot program. Semiconductor device.

3. 2. The semiconductor device according to claim 1, the time for delaying the execution of the instructions included in the boot program is determined according to the difference between the DMA transfer processing speed of the boot program and the instruction execution processing speed of the boot program. Semiconductor device.

4. 2. The semiconductor device according to claim 1, the CPU executes the initialization program to cause the DMA controller to execute a DMA transfer process of the interrupt program and the plurality of interrupt jump instructions to the second memory; Semiconductor device.

5. 2. The semiconductor device according to claim 1, further comprising the third memory; Semiconductor device.

6. 2. The semiconductor device according to claim 1, the boot program includes a first portion and a second portion; the DMA controller is a first DMA controller; the DMA transfer process is a first DMA transfer process, the boot program write area includes a first boot program write area and a second boot program write area; the semiconductor device further includes a second DMA controller; the first DMA controller starts the first DMA transfer process of transferring the first part of the boot program stored in the third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the first boot program write area; the second DMA controller starts a second DMA transfer process for transferring the second part of the boot program stored in the third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the second boot program write area; The CPU after a predetermined time has elapsed since the start of the first DMA transfer process and the second DMA transfer process, start executing instructions included in the boot program DMA-transferred to the second memory; During execution of an instruction included in the boot program, an instruction execution address of the CPU reaches an address in the boot program write area where the first DMA transfer process or the second DMA transfer process has not been completed, thereby executing the interrupt jump instruction. Semiconductor device.

7. 7. The semiconductor device according to claim 6, the CPU executes the initialization program to cause the first DMA controller and the second DMA controller to execute DMA transfer processing of the interrupt program and the plurality of interrupt jump instructions to the second memory; Semiconductor device.

8. 7. The semiconductor device according to claim 6, each of the first boot program write area and the second boot program write area includes a plurality of areas spaced apart from each other; Semiconductor device.

9. 1. A boot program execution method executed in a semiconductor device including a CPU, a first memory that stores an initialization program, a second memory that has an interrupt program write area and a boot program write area, and a DMA controller, the method comprising: an initialization step of causing the CPU to execute the initialization program; a boot program transfer step of causing the DMA controller to execute a DMA transfer process of the boot program; a boot program execution step of causing the CPU to execute the boot program; Equipped with The initialization step includes: writing an interrupt program including an instruction for delaying execution of the boot program into the interrupt program writing area; writing a plurality of interrupt jump instructions, including an instruction for changing an instruction execution address of the CPU to an address in the interrupt program writing area, into the boot program writing area; Including, the boot program transfer step includes a step of starting the DMA transfer process of transferring the boot program stored in a third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the boot program write area, The boot program execution step includes: a step of starting an execution process of instructions included in the boot program DMA-transferred to the second memory after a predetermined time has elapsed since the start of the DMA transfer process; executing the interrupt jump instruction when an instruction execution address of the CPU reaches an address in the boot program write area for which the DMA transfer process has not been completed during execution of an instruction included in the boot program; a step of executing the interrupt jump instruction to change the instruction execution address of the CPU to an address in the interrupt program write area, and then executing the interrupt program written in the interrupt program write area to delay execution of instructions included in the boot program; Including, How to run the boot program.

10. 10. The boot program execution method according to claim 9, the boot program execution step further includes, after the step of delaying the execution of instructions included in the boot program, a step of setting the address at which the executed interrupt jump instruction was written as an instruction execution address again, and resuming the execution of instructions included in the boot program. How to run the boot program.

11. 10. The boot program execution method according to claim 9, the time for delaying the execution of the instructions included in the boot program is determined according to the difference between the DMA transfer processing speed of the boot program and the instruction execution processing speed of the boot program. How to run the boot program.

12. 10. The boot program execution method according to claim 9, the initialization step further includes a step of causing the DMA controller to execute a DMA transfer process of the interrupt program and the plurality of interrupt jump instructions to the second memory by executing the initialization program. How to run the boot program.

13. 10. The boot program execution method according to claim 9, the boot program write area includes a first boot program write area and a second boot program write area; the boot program includes a first portion and a second portion; the DMA controller is a first DMA controller; the DMA transfer process is a first DMA transfer process, the semiconductor device further includes a second DMA controller; the boot program transfer step is a first boot program transfer step of causing the first DMA controller to execute the first DMA transfer process of the first part of the boot program, the first boot program transfer step includes a step of starting the first DMA transfer process for transferring the first part of the boot program stored in the third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the first boot program write area; the boot program execution method further includes a second boot program transfer step of causing the second DMA controller to execute a second DMA transfer process of the second part of the boot program; the second boot program transfer step includes a step of starting the second DMA transfer process for transferring the second part of the boot program stored in the third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the second boot program write area, The boot program execution step includes: a step of starting an execution process of instructions included in the boot program DMA-transferred to the second memory after a predetermined time has elapsed since the start of the first DMA transfer process and the second DMA transfer process; executing the interrupt jump instruction when an instruction execution address of the CPU reaches an address of the boot program write area where the first DMA transfer process or the second DMA transfer process has not been completed during execution of an instruction included in the boot program; further comprising: How to run the boot program.

14. 14. The boot program execution method according to claim 13, the initialization step further includes a step of causing the first DMA controller and the second DMA controller to execute the step of writing the interrupt program and the step of writing the plurality of interrupt jump instructions by executing the initialization program. How to run the boot program.

15. A non-transitory computer-readable medium storing a program for causing a semiconductor device including a CPU, a first memory for storing an initialization program, a second memory having an interrupt program write area and a boot program write area, and a DMA controller to execute a boot program execution method, the boot program execution method comprising: an initialization step of causing the CPU to execute the initialization program; a boot program transfer step of causing the DMA controller to execute a DMA transfer process of the boot program; a boot program execution step of causing the CPU to execute the boot program; Equipped with The initialization step includes: writing an interrupt program including an instruction for delaying execution of the boot program into the interrupt program writing area; writing a plurality of interrupt jump instructions, including an instruction for changing an instruction execution address of the CPU to an address in the interrupt program writing area, into the boot program writing area; Including, the boot program transfer step includes a step of starting the DMA transfer process of transferring the boot program stored in a third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the boot program write area, The boot program execution step includes: a step of starting an execution process of instructions included in the boot program DMA-transferred to the second memory after a predetermined time has elapsed since the start of the DMA transfer process; executing the interrupt jump instruction when an instruction execution address of the CPU reaches an address in the boot program write area for which the DMA transfer process has not been completed during execution of an instruction included in the boot program; a step of executing the interrupt jump instruction to change the instruction execution address of the CPU to an address in the interrupt program write area, and then executing the interrupt program written in the interrupt program write area to delay execution of instructions included in the boot program; Including, Non-transitory computer-readable medium.

16. 16. The non-transitory computer-readable medium of claim 15, the boot program execution step further includes, after the step of delaying the execution of instructions included in the boot program, a step of setting the address at which the executed interrupt jump instruction was written as an instruction execution address again, and resuming the execution of instructions included in the boot program. Non-transitory computer-readable medium.

17. 16. The non-transitory computer-readable medium of claim 15, the time for delaying the execution of the instructions included in the boot program is determined according to the difference between the DMA transfer processing speed of the boot program and the instruction execution processing speed of the boot program. Non-transitory computer-readable medium.

18. 16. The non-transitory computer-readable medium of claim 15, the initialization step further includes a step of causing the DMA controller to execute a DMA transfer process of the interrupt program and the plurality of interrupt jump instructions to the second memory by executing the initialization program. Non-transitory computer-readable medium.

19. 16. The non-transitory computer-readable medium of claim 15, the boot program write area includes a first boot program write area and a second boot program write area; the boot program includes a first portion and a second portion; the DMA controller is a first DMA controller; the DMA transfer process is a first DMA transfer process, the semiconductor device further includes a second DMA controller; the boot program transfer step is a first boot program transfer step of causing the first DMA controller to execute the first DMA transfer process of the first part of the boot program, the first boot program transfer step includes a step of starting the first DMA transfer process for transferring the first part of the boot program stored in the third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the first boot program write area; the boot program execution method further includes a second boot program transfer step of causing the second DMA controller to execute a second DMA transfer process of the second part of the boot program; the second boot program transfer step includes a step of starting the second DMA transfer process for transferring the second part of the boot program stored in the third memory to the second memory by overwriting the plurality of interrupt jump instructions written in the second boot program write area, The boot program execution step includes: a step of starting an execution process of instructions included in the boot program DMA-transferred to the second memory after a predetermined time has elapsed since the start of the first DMA transfer process and the second DMA transfer process; executing the interrupt jump instruction when an instruction execution address of the CPU reaches an address of the boot program write area where the first DMA transfer process or the second DMA transfer process has not been completed during execution of an instruction included in the boot program; further comprising: Non-transitory computer-readable medium.

20. 20. The non-transitory computer-readable medium of claim 19, the initialization step further includes a step of causing the first DMA controller and the second DMA controller to execute the step of writing the interrupt program and the step of writing the plurality of interrupt jump instructions by executing the initialization program. Non-transitory computer-readable medium.

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