Wiring method for semiconductor integrated circuit, wiring program and wiring device

Abstract

To select a wiring path for shielded wiring without drawing it toward existing wiring.SOLUTION: A wiring method for a semiconductor integrated circuit according to the present disclosure performs a process for placing a plurality of candidate shielded wiring at a distance from each other by opening wiring tracks for placing the shielded wiring by using a computer, a process for placing the shielded wiring on at least one of a plurality of wiring tracks provided between a plurality of candidate shielded wiring, and a process for removing candidate shielded wiring that does not contribute as shielded wiring for the placed shielded wiring.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a wiring method, a wiring program, and a wiring device for a semiconductor integrated circuit. [Background technology]

[0002] In order to prevent crosstalk between adjacent signal nets, a signal net that interferes with other signal nets or a signal net that needs to be prevented from interference from other signal nets is shielded by wiring a ground net or a power supply net on both sides of the signal net.Patent Document 1 discloses an automatic wiring method that searches for a wiring route for a signal net that needs to be shielded, and once the wiring route for the signal net has been determined, wires a shield net to shield the signal net on one or both sides of the signal net while ensuring a predetermined clearance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-259695 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, when searching for a wiring route for a signal net that needs to be shielded, if an already-wired power net or ground net exists, first, a wiring route is searched for so that the signal net is adjacent to the already-wired power net or ground net (hereinafter referred to as the already-wired power net, etc.) with a predetermined clearance secured. Then, if adjacent wiring with the already-wired power net, etc. is successful, the already-wired power net is used as a shield net for shielding the signal net.

[0005] However, in Patent Document 1, in order to use an already-wired power supply net or the like as a shield net, a wiring route is searched for so that the signal net to be shielded is attracted to the already-wired power supply net or the like, which causes a problem that an ideal wiring route cannot be selected.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A wiring method for a semiconductor integrated circuit according to the present disclosure includes a process in which a computer executes a process of arranging a plurality of shield wiring candidates spaced apart from each other by leaving open wiring tracks for arranging the shield target wiring, a process of arranging the shield target wiring on at least one of the plurality of wiring tracks provided between the plurality of shield wiring candidates, and a process of deleting shield wiring candidates that do not contribute as shield wiring for the arranged shield target wiring.

[0008] A wiring program for a semiconductor integrated circuit according to the present disclosure causes a computer to execute the following processes: a process of placing a plurality of shield wiring candidates spaced apart by leaving open wiring tracks for placing wiring to be shielded; a process of placing a wiring to be shielded on at least one of the plurality of wiring tracks provided between the plurality of shield wiring candidates; and a process of deleting shield wiring candidates that do not contribute as shield wiring to the placed wiring to be shielded.

[0009] A wiring device for a semiconductor integrated circuit according to the present disclosure includes shield wiring candidate placement means for placing a plurality of shield wiring candidates spaced apart by leaving open wiring tracks for placing shield target wiring, shield target placement means for placing a shield target wiring on at least one of the plurality of wiring tracks provided between the plurality of shield wiring candidates, and deletion means for deleting shield wiring candidates that do not contribute as shield wiring to the placed shield target wiring. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to select a wiring path for wiring to be shielded without the wiring to be shielded being attracted to an already-existing wiring. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing an example of a wiring device for a semiconductor integrated circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a shield wiring candidate. [Figure 3] FIG. 3 is a diagram showing a state in which the wiring to be shielded is routed on the wiring tracks between the shield wiring candidates in FIG. [Figure 4] FIG. 4 is a diagram illustrating the process of deleting shield wiring candidates. [Figure 5] FIG. 5 is a diagram illustrating the process of deleting shield wiring candidates. [Figure 6] FIG. 6 is a diagram illustrating the process of deleting vias between intersecting shield wiring candidates. [Figure 7] FIG. 7 is a flow chart showing an example of a wiring method for a semiconductor integrated circuit according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the drawings are simplified, and therefore the technical scope of the present disclosure should not be narrowly interpreted based on the description in the drawings. Furthermore, in each drawing, the same elements are given the same reference numerals, and redundant explanations will be omitted. Note that, for convenience of explanation, the drawings are not drawn to actual scale.

[0013] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0014] Furthermore, in the following embodiments, the components (including operational steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or approximate to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, numerical values, amounts, ranges, etc.).

[0015] The present disclosure relates to a wiring method, a wiring program, and a wiring device for automatically wiring wiring to be shielded and shield wiring on a semiconductor chip or a printed circuit board in order to manufacture a semiconductor integrated circuit equipped with shield wiring for shielding the wiring to be shielded.

[0016] Wiring to be shielded is signal wiring that interferes with other signal wiring or that needs to be prevented from interference from other signal wiring. Wiring to be shielded can be, for example, clock wiring that carries high-frequency signals, high-speed data signals (e.g., analog signals of high-speed SerDes (SERializer / DESerializer) interface circuits), or data wiring that carries highly sensitive analog signals (such as VDD sense signals for temperature or potential measurement, analog signals of ADCs, etc.). Shielding wiring is placed on both sides of signal wiring to prevent crosstalk between adjacent signal wiring.

[0017] In advanced processes, wiring pitches are becoming narrower as semiconductor elements become smaller and denser. Furthermore, voltage scaling is being adopted to reduce the reliability and power consumption of semiconductor elements. This increases the noise sensitivity of signal wiring, making fine shielded wiring essential.

[0018] Typically, wiring resources for shielding wiring are secured on both sides of each wiring to be shielded. However, it is not necessary to place shielding wiring on both sides of each wiring to be shielded, and there may be cases where it can be omitted. For example, if the wiring pitch is narrow, it is possible to share the shielding wiring between adjacent wiring to be shielded.

[0019] However, when a shielding wire is wired after a large number of wires to be shielded have been freely wired, the shielding wire cannot be shared, resulting in redundant shielding wires and causing wiring congestion. In order to reduce chip size, it is necessary to prevent wiring congestion of the shielding wires.

[0020] On the other hand, when an already-wired power supply net or ground net is used as shield wiring, as in the above-mentioned Patent Document 1, it is possible to eliminate unnecessary shield wiring, but there is a problem that the wiring position of the wiring to be shielded is attracted to the already-wired wiring. In particular, since clock wiring affects the timing and power of semiconductor integrated circuits, it is necessary to ensure the quality of clock wiring, including shield wiring.

[0021] FIG. 1 is a block diagram showing an example of a wiring device for a semiconductor integrated circuit according to an embodiment. FIG. 2 is a diagram showing an example of shield wiring candidates. FIG. 3 is a diagram showing a state in which wiring to be shielded is wired on wiring tracks between the shield wiring candidates in FIG. 2. FIG. 4 is a diagram explaining the process of deleting shield wiring candidates. FIG. 5 is a diagram explaining the process of deleting shield wiring candidates. FIG. 6 is a diagram explaining the process of deleting vias between intersecting shield wiring candidates. In the following explanation, an example will be described in which the wiring to be shielded is clock wiring and the shield wiring is a ground mesh.

[0022] The wiring device 10 performs processing to automatically determine wiring paths for multilayer wiring including clock wiring and shield wiring of a semiconductor integrated circuit. As shown in FIG. 1, the wiring device 10 includes a processing unit 11, a storage unit 12, a memory 13, and an input / output unit 14. The storage unit 12 is a storage device such as a hard disk or flash memory. The storage unit 12 stores library information, various information obtained by designing a circuit in advance, and a wiring program according to an embodiment.

[0023] The library information includes information used in circuit design, such as block graphic information for primitive blocks such as flip-flops and macroblocks such as multipliers, and terminal graphic information. Various information obtained by circuit design includes a netlist (terminal connection information, wiring width information), substrate information (wiring track spacing, number of wiring layers, etc.), wiring prohibition information, etc. The memory 13 is a volatile storage device such as a RAM, and is a storage area for temporarily storing information when the arithmetic processing unit 11 is operating.

[0024] The arithmetic processing unit 11 is a processor that controls each component of the wiring device 10. The arithmetic processing unit 11 loads a program from the storage unit 12 into the memory 13 and executes the program. In this way, the arithmetic processing unit 11 realizes the functions of the shield wiring candidate placement unit 111, the shield target placement unit 112, and the deletion unit 113, and executes the automatic wiring processing according to the embodiment. The input / output unit 14 may include a display device such as a screen, and input devices such as a keyboard and a mouse. The display device displays the detailed wiring diagram created by the arithmetic processing unit 11, etc.

[0025] Each component of the wiring device 10 may be realized by dedicated hardware. Also, some or all of the components may be realized by general-purpose or dedicated circuits, processors, etc., or a combination of these. Some or all of the components of each device may be realized by a combination of the above-mentioned circuits, etc., and programs. Furthermore, a CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array), quantum processor, etc. may be used as the processor.

[0026] The shield wiring candidate placement unit 111 executes processing to place multiple shield wiring candidates that are spaced apart by a spacing of a wiring track required for placing the wiring to be shielded. The shield wiring candidates may be ground meshes or power supply meshes. In this embodiment, the number of wiring tracks required to place one clock wiring is set to one, and a ground mesh with one wiring track spaced apart in advance is placed as the shield wiring candidate.

[0027] 2, ground mesh 20, which is a shield wiring candidate, includes at least a first shield wiring candidate 21, a second shield wiring candidate 22, and a via 23. In the example shown in Fig. 2, ground mesh 20 has a two-layer structure with a lower layer referred to as a first layer and an upper layer referred to as a second layer.

[0028] The direction in which the first shield wiring candidates 21 extend is defined as a first direction, and the direction in which the second shield wiring candidates 22 extend is defined as a second direction. The first and second directions are substantially perpendicular to each other. The multiple first shield wiring candidates 21 are arranged on the first layer and extend in the first direction. The multiple first shield wiring candidates 21 are arranged side by side in the second direction on the wiring tracks, with a spacing of a wiring track required for placing clock wiring.

[0029] The multiple second shield wiring candidates 22 are arranged on a second layer different from the first layer, and extend in a second direction perpendicular to the first direction. The multiple second shield wiring candidates 22 are arranged side by side in the first direction on the wiring tracks, with a spacing of a wiring track required for arranging the clock wiring. Vias 23 are arranged at positions where the first shield wiring candidates 21 and the second shield wiring candidates 22 intersect. The vias 23 electrically connect the first shield wiring candidates 21 and the second shield wiring candidates 22.

[0030] The second shield wiring candidates 22 arranged on the second upper layer are each connected to a GND supply source. Note that the structure of the ground mesh 20 is not limited to this, and a stacked mesh structure of three or more layers may also be used. In adjacent wiring layers, the shield wiring candidates intersect at right angles to each other. With this configuration, for example, in the case of a three-layer multilayer wiring structure, the shield wiring candidates on the first and third layers are parallel, and the shield wiring candidate on the second layer can be arranged so as to intersect at right angles to the shield wiring candidates on the first and third layers. Furthermore, the shield wiring candidate on the top layer can be connected to a GND supply source.

[0031] The shielding target placement unit 112 executes a process of placing a shielding target wire on at least one of a plurality of wiring tracks provided between a plurality of shielding wire candidates. In the example shown in Fig. 3, one clock wire 30 is placed between each of the three first shielding wire candidates 21 on the first layer.

[0032] Hereinafter, the four second shield wiring candidates 22 are distinguished from one another by being assigned the reference symbols 22a, 22b, 22c, and 22d from the left side of the drawing. In the second layer, of the four second shield wiring candidates 22, one clock wiring 30 is placed between the second shield wiring candidates 22b and 22c. In this way, the clock wiring 30 is placed using the wiring track secured within the ground mesh 20.

[0033] The deletion unit 113 executes a process of deleting shield wiring candidates that do not contribute as shield wiring to the placed wiring to be shielded. This process of deleting shield wiring candidates that do not contribute as shield wiring will be described in detail with reference to Figures 4 and 5. This deletion process includes two examples.

[0034] Example 1 The deletion unit 113 first searches whether there is a wiring to be shielded on a wiring track adjacent to the shield wiring candidate, and then deletes the shield wiring candidate for which there is no wiring to be shielded on an adjacent wiring track.

[0035] 4, in the first layer, clock wiring 30 is arranged between each of the three first shield wiring candidates 21. In addition, in the second layer, clock wiring 30 is arranged in the wiring track between the two inner second shield wiring candidates 22b and 22c.

[0036] On the other hand, other than the second shield wiring candidates 22b and 22c, the wiring tracks adjacent to the two second shield wiring candidates 22a and 22d do not have the clock wiring 30 to be shielded. In this way, the second shield wiring candidates 22a and 22d, which do not have the clock wiring 30 on any of their adjacent wiring tracks, become the wiring 40 to be deleted.

[0037] FIG. 5 is a top view of second shield wiring candidates 22 arranged on the second layer. Note that FIG. 5 is provided for the purpose of explaining which shield wiring candidates are to be deleted, and does not correspond to the configuration shown in FIG. 4. In FIG. 5, five second shield wiring candidates 22 are provided. These second shield wiring candidates 22 are distinguished and referred to as second shield wiring candidates 22e, 22f, 22g, 22h, and 22i. The positions of the dotted lines indicated by arrows in FIG. 5 are wiring tracks.

[0038] The clock wiring 30 is arranged on the wiring track between the second shield wiring candidates 22e and 22f. In this case, the deletion unit 113 determines that there is a shielding target on the wiring track adjacent to the second shield wiring candidates 22e and 22f. These second shield wiring candidates 22e and 22f become wiring to be retained.

[0039] On the other hand, the clock wiring 30 is not arranged on either of the adjacent wiring tracks on either side of the second shield wiring candidate 22g. In this case, the deletion unit 113 determines that there is no shielding target on the adjacent wiring tracks of the second shield wiring candidate 22g. This second shield wiring candidate 22g becomes the deletion-target wiring 40.

[0040] Example 2 The deletion unit 113 can delete only a portion of the shield wiring candidate. Specifically, if there is a wiring to be shielded on a wiring track adjacent to a first portion of the shield wiring candidate, and there is no wiring to be shielded on a wiring track adjacent to a second portion of the shield wiring candidate that is different from the first portion, the deletion unit 113 performs processing to delete the second portion of the shield wiring candidate.

[0041] 5, a clock wiring 30 is arranged in a portion of the wiring track between the second shield wiring candidates 22h and 22i. In this case, the deletion unit 113 determines that a shielding target exists in the portion of the second shield wiring candidates 22h and 22i where the clock wiring 30 is arranged, and determines that a shielding target does not exist in the portion of the second shield wiring candidates 22h and 22i where the clock wiring 30 is not arranged.

[0042] Therefore, the portions of the second shield wiring candidates 22h and 22i where the clock wiring 30 is located are the partial wiring to be retained. On the other hand, the portions of the second shield wiring candidates 22h and 22i where the clock wiring 30 is not located are the partial deletion target wiring 41.

[0043] The deletion unit 113 leaves the second shield wiring candidate 22 determined as the one to be retained in the first and second examples, and deletes the deletion target wiring 40 and the partial deletion target wiring 41. This deletes the shield wiring candidates that do not contribute as shield wiring to the clock wiring 30.

[0044] 6, because second shield wiring candidates 22b and 22c remain as shield wiring, there are two GND supply points to one first shield wiring candidate 21. For example, the first shield wiring candidate 21, which is the foremost in FIG. 6, is supplied with GND potential from the second shield wiring candidates 22b and 22c via two vias 23 (shown as via numbers (1) and (2) in FIG. 6). However, if two or more vias exist, current will flow, which may result in an EM (electromigration) violation.

[0045] Therefore, the deletion unit 113 deletes such redundant vias. When there are multiple second shield wiring candidate lines that will serve as shield wiring and intersect with a first shield wiring candidate that will serve as shield wiring, the deletion unit 113 leaves one via out of the multiple vias that connect the first shield wiring candidate that will serve as shield wiring and the second shield wiring that will serve as shield wiring, and deletes the remaining vias.

[0046] Next, a wiring method for a semiconductor integrated circuit according to an embodiment will be described with reference to FIG. 7. FIG. 7 is a flow chart showing an example of the wiring method for a semiconductor integrated circuit according to an embodiment. A circuit designer uses library information in the storage unit 12 to design a circuit using CAD in advance. Then, the circuit designer creates various information such as a netlist, with an internal region set inside the semiconductor chip as the wiring target region. The various information includes a netlist, substrate information, and wiring prohibition information. These various information may be collectively referred to as a netlist, etc. The created netlist, etc. is stored in the storage unit 12.

[0047] As shown in Figure 7, the wiring device 10 first uses a netlist or the like to place macroblocks (step S10) and a trunk ground net (step S11) in the internal area of ​​the semiconductor chip. Although not shown here, trunk power nets, primitive blocks, and the like may also be placed. A macroblock is partial circuit information in functional block units used when designing the layout of a semiconductor integrated circuit. The trunk ground net and trunk power net are wiring for supplying power to transistors, etc.

[0048] Here, the trunk ground net and trunk power net are power wiring with a larger current capacity than the ground mesh and power mesh. The wiring width and wiring spacing of the trunk ground net and trunk power net are larger than those of the ground mesh and power mesh. Furthermore, because current flows through the trunk ground net and trunk power net, vias larger than those of the ground mesh and power mesh are formed.

[0049] Then, the wiring device 10 performs placement and global routing of standard cells (step S12). Standard cells are standard functional blocks prepared in advance and can be stored as library information in the storage unit 12. After the placement of the standard cells, global routing is performed to check for local wiring congestion.

[0050] The wiring device 10 then arranges ground meshes that serve as shield wiring candidates over substantially the entire surface of the semiconductor chip (step S13). As described above, in the embodiment, a plurality of linear first shield wiring candidates 21 are arranged in a first direction on the first layer. The spacing between adjacent first shield wiring candidates 21 is the length of the wiring tracks required for arranging the clock wiring 30. Furthermore, on a second layer adjacent to the first layer, a plurality of linear second shield wiring candidates 22 are arranged in a second direction that is perpendicular to the first direction. The spacing between adjacent second shield wiring candidates 22 is the length of the wiring tracks required for arranging the clock wiring 30.

[0051] The layers are connected to each other by vias provided in the interlayer insulating film. Shield wiring candidates that do not contribute to the shield wiring are deleted in a later process. In this embodiment, a ground mesh is generated separately from the main ground net for power supply.

[0052] Thereafter, the wiring device 10 arranges clock wiring 30 for supplying clock signals to each component (step S14). The clock wiring 30 is arranged on at least one of a plurality of wiring tracks provided between a plurality of shield wiring candidates.

[0053] After placing the clock wiring 30, the wiring device 10 performs clock timing optimization and, with reference to a netlist or the like, places wiring other than the clock wiring 30 that requires shielding, which is part of the detailed wiring between all standard cells (step S15). Wiring that requires shielding may also be placed on at least one of the multiple wiring tracks provided between multiple shield wiring candidates. Wiring other than the clock wiring 30 that requires shielding is wiring that interferes with other wiring or wiring that needs to be prevented from interfering with other wiring.

[0054] That is, in the embodiment, an ideal wiring route can be selected for all wirings that require shielding, including the clock wiring 30, with shield wiring candidates that can serve as shield wiring arranged on both sides of the wiring. The placement location and wiring route of each component in the internal region of the semiconductor chip can be stored in the memory 13 as layout information.

[0055] Then, the wiring device 10 deletes unnecessary shield wiring candidates that do not contribute as shield wiring to the placed shield target wiring (step S16). Specifically, the wiring device 10 searches for whether there is a shield target wiring on a wiring track adjacent to the shield wiring candidate, and adds a hold setting to the shield wiring candidate that has a shield target wiring.

[0056] Furthermore, if a wiring target wiring exists in a portion of a wiring track adjacent to a shield wiring candidate, the wiring device 10 divides the pattern of the wiring target wiring and adds a retention setting to the portion that contributes to the shield wiring.The wiring device 10 then deletes the shield wiring candidate other than the portion of the shield target candidate and shield wiring candidate to which the retention setting has been added.The wiring device 10 can determine the portion of the shield wiring candidate to be deleted based on, for example, the coordinates of the clock wiring 30.

[0057] Note that deleting unnecessary shield wiring candidates may include deleting redundant vias as described above. As an example, the wiring device 10 detects the number of vias 23 that connect from a first shield wiring candidate 21 arranged in a lower layer to a second shield wiring candidate 22 maintained as a shield wiring in an upper layer. If two or more vias 23 exist, the wiring device 10 deletes the vias 23, leaving any one of the vias 23.

[0058] For example, in Fig. 6, the wiring device 10 can count the number of vias 23 connected to the second shield wiring candidate 22 held as the shield wiring in the upper layer, going from left to right through each first shield wiring candidate 21. In the example shown in Fig. 6, because there are two vias 23, the wiring device 10 can leave the via 23 on the left with via number (1) that was detected first, and delete the via 23 on the right with via number (2).

[0059] After step S16, detailed wiring including signal wiring between the remaining standard cells is performed, thereby completing the wiring of the semiconductor integrated circuit according to the embodiment (not shown in FIG. 7).

[0060] As described above, according to the embodiment, the ground mesh 20 made up of shield wiring candidates is formed to distinguish it from the backbone ground net for GND supply, which has a larger wiring spacing than the clock wiring and cannot contribute as a shield wiring. By placing the clock wiring 30 using the wiring tracks of the ground mesh 20, the degree of freedom in placing the clock wiring 30 is ensured, and it becomes possible to select an ideal wiring route.

[0061] Furthermore, since candidate shield wirings are placed adjacent to wirings that require shielding, such as the clock wiring 30, it is possible to improve the coverage rate of the shield wiring for the wirings to be shielded.

[0062] Furthermore, compared to an example in which shield wiring is placed after placing clock wiring without preparing shield wiring candidates in advance, the embodiment can eliminate the waste of overlapping unnecessary shield wiring, which is expected to lead to a smaller semiconductor integrated circuit and improved integration. Furthermore, since unnecessary shield wiring processing can be avoided, it is also possible to speed up the wiring processing.

[0063] The present invention has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the present invention is not limited to semiconductor chips and can also be applied to printed circuit boards. Furthermore, shield wiring is not necessarily required on both sides of the wiring to be shielded; if necessary, the shield wiring on one side may be omitted.

[0064] Each functional block shown in the drawings that performs various processes can be configured in hardware with a processor, memory, and other circuits. The processes described above can also be implemented by having a processor execute a program. Therefore, these functional blocks can be implemented in various forms, such as hardware only, software only, or a combination of both, and are not limited to any one of these.

[0065] The above-described program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include semiconductor memory (e.g., mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, and RAM). The program may also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable medium can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path. [Explanation of symbols]

[0066] 10 Wiring device 11. Processing unit 12 Storage section 13. Memory 14 Input / output section 111 Shield wiring candidate placement area 112 Shield target placement area 113 Deleted section 20 Ground Mesh 21 First shield wiring candidate 22 Second shield wiring candidate 23 Beer 30 Clock wiring 40 Wiring to be deleted 41 Wiring to be partially deleted

Claims

1. The computer A process of arranging a plurality of shield wiring candidates spaced apart from each other by leaving a wiring track for arranging the wiring to be shielded; a process of placing a wiring to be shielded on at least one of the plurality of wiring tracks provided between the plurality of shield wiring candidates; a process of deleting shield wiring candidates that do not contribute as shield wiring to the placed shield target wiring; To execute A wiring method for semiconductor integrated circuits.

2. The process of deleting the shield wiring candidates includes: a process of searching whether the wiring to be shielded is present on the wiring track adjacent to the shield wiring candidate; a process of deleting the shield wiring candidate that does not have the shield target wiring on the adjacent wiring track; Including, The wiring method according to claim 1 .

3. further comprising a process of deleting the second portion of the shielding wiring candidate when the wiring to be shielded exists on the wiring track adjacent to a first portion of the shielding wiring candidate and the wiring to be shielded does not exist on the wiring track adjacent to a second portion of the shielding wiring candidate that is different from the first portion. The wiring method according to claim 2 .

4. The shield wiring candidate is a plurality of first shield line candidates arranged on a first layer and extending in a first direction; a plurality of second shield wiring candidates disposed on a second layer different from the first layer and extending in a second direction perpendicular to the first direction; a plurality of vias arranged at positions where the first shield wiring candidate and the second shield wiring candidate intersect, electrically connecting the first shield wiring candidate and the second shield wiring candidate; Including, The wiring method according to claim 1 .

5. The process of removing shield wiring candidates is as follows: When there are a plurality of second shield wiring candidate lines that serve as shield wiring and intersect with a first shield wiring candidate that serves as shield wiring, The method further includes a process of leaving one via among a plurality of vias connecting a first shield wiring candidate that serves as a shield wiring and a second shield wiring candidate that serves as a shield wiring, and deleting the other vias. The wiring method according to claim 4.

6. The shield wiring candidate is a ground mesh or a power mesh. The wiring method according to claim 1 .

7. The wiring to be shielded is a clock wiring. The wiring method according to claim 1 .

8. A process of arranging a plurality of shield wiring candidates spaced apart from each other by leaving a wiring track for arranging the wiring to be shielded; a process of placing a wiring to be shielded on at least one of the plurality of wiring tracks provided between the plurality of shield wiring candidates; a process of deleting shield wiring candidates that do not contribute as shield wiring to the placed shield target wiring; to the computer, A wiring program for semiconductor integrated circuits.

9. The process of deleting the shield wiring candidates includes: a process of searching whether the wiring to be shielded is present on the wiring track adjacent to the shield wiring candidate; a process of deleting the shield wiring candidate that does not have the shield target wiring on the adjacent wiring track; Including, The wiring program according to claim 8.

10. further comprising a process of deleting the second portion of the shielding wiring candidate when the wiring to be shielded exists on the wiring track adjacent to a first portion of the shielding wiring candidate and the wiring to be shielded does not exist on the wiring track adjacent to a second portion of the shielding wiring candidate that is different from the first portion. The wiring program according to claim 9 .

11. The shield wiring candidate is a plurality of first shield line candidates arranged on a first layer and extending in a first direction; a plurality of second shield wiring candidates disposed on a second layer different from the first layer and extending in a second direction perpendicular to the first direction; a plurality of vias arranged at positions where the first shield wiring candidate and the second shield wiring candidate intersect, electrically connecting the first shield wiring candidate and the second shield wiring candidate; Including, The wiring program according to claim 8.

12. The process of removing shield wiring candidates is as follows: When there are a plurality of second shield wiring candidate lines that serve as shield wiring and intersect with a first shield wiring candidate that serves as shield wiring, The method further includes a process of leaving one via among a plurality of vias connecting a first shield wiring candidate that serves as a shield wiring and a second shield wiring candidate that serves as a shield wiring, and deleting the other vias. The wiring program according to claim 8.

13. The shield wiring candidate is a ground mesh or a power mesh. The wiring program according to claim 8.

14. a shield wiring candidate placement means for placing a plurality of shield wiring candidates spaced apart from each other by leaving a wiring track for placing wiring to be shielded; a shielding target placement means for placing a shielding target wiring on at least one of the plurality of wiring tracks provided between the plurality of shielding wiring candidates; a deletion means for deleting shield wiring candidates that do not contribute as shield wiring from the placed shield target wiring; Equipped with Wiring device for semiconductor integrated circuits.

15. The deletion means A search is performed to determine whether the wiring to be shielded is present on the wiring track adjacent to the shield wiring candidate; removing the shield wiring candidate having no wiring to be shielded on the adjacent wiring track; Including, The wiring device according to claim 14.

16. The deletion means If the wiring to be shielded exists on the wiring track adjacent to a first portion of the shield wiring candidate, and the wiring to be shielded does not exist on the wiring track adjacent to a second portion of the shield wiring candidate that is different from the first portion, the second portion of the shield wiring candidate is deleted. The wiring device according to claim 15.

17. The shield wiring candidate is a plurality of first shield line candidates arranged on a first layer and extending in a first direction; a plurality of second shield wiring candidates disposed on a second layer different from the first layer and extending in a second direction perpendicular to the first direction; a plurality of vias arranged at positions where the first shield wiring candidate and the second shield wiring candidate intersect, electrically connecting the first shield wiring candidate and the second shield wiring candidate; Including, The wiring device according to claim 14.

18. The process of removing shield wiring candidates is as follows: When there are a plurality of second shield wiring candidate lines that serve as shield wiring and intersect with a first shield wiring candidate that serves as shield wiring, The method further includes a process of leaving one via among a plurality of vias connecting a first shield wiring candidate that serves as a shield wiring and a second shield wiring candidate that serves as a shield wiring, and deleting the other vias. The wiring device according to claim 17.

19. The shield wiring candidate is a ground mesh or a power mesh. The wiring device according to claim 14.

20. The wiring to be shielded is a clock wiring. The wiring device according to claim 14.

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