Semiconductor integrated circuit and apparatus

Abstract

To provide a circuit configuration that reduces hold violation of scan data, and that is advantageous for preventing an increase in circuit scale and an increase in power consumption.SOLUTION: A plurality of logical circuits include n data holding circuits each holding data, a scan chain transferring scan data, and a clock line including a plurality of clock buffers for delaying clock signals. The clock signals in the clock line are supplied to the n data holding circuits, and clock signals are supplied to the n data holding circuits, such that the amount of delay of the clock signal is increased from the first data holding circuit toward the n-th data holding circuit that is on the most downstream side in a forward direction. The scan chain is used to transfer the scan data in a reverse direction directed from the n-th data holding circuit toward the first data holding circuit. The scan data is transferred between the logical circuits via a delay adjustment unit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit and a device using the same. [Background technology]

[0002] One method for testing semiconductor integrated circuits is to incorporate a scan chain into the semiconductor integrated circuit. An example of a semiconductor integrated circuit is an image sensor. An image sensor uses an analog-to-digital converter (ADC) to convert pixel information into a digital signal and a filter circuit to remove high-frequency noise components. As image sensors have an increasing number of pixels, the size of the logic circuits, such as filter circuits that are the subject of testing, is increasing. Patent Document 1 describes a technology for reducing hold violations. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2004-30166 Summary of the Invention [Problem to be solved by the invention]

[0004] As circuit size increases, there is a problem that the circuit size required to guarantee data hold in the scan chain used for circuit testing increases. As the circuit size increases, the circuit size and power consumption also increase. The present invention aims to provide a circuit configuration that is advantageous for suppressing increases in circuit size and power consumption in a circuit that reduces the occurrence of scan data hold violations. [Means for solving the problem]

[0005] One aspect of the present invention is a semiconductor integrated circuit in which a plurality of logic circuits are arranged, each logic circuit including n data retention circuits for retaining data, a scan chain for transferring scan data, and a clock line including a plurality of clock buffers for delaying a clock signal, wherein a clock signal is supplied to the n data retention circuits on the clock line, and in a forward direction from a first data retention circuit to an nth data retention circuit among the n data retention circuits, a clock signal with a larger delay amount is supplied from the clock line to a data retention circuit further downstream, the scan chain is arranged to transfer scan data in a reverse direction from the nth data retention circuit to the first data retention circuit, and the scan data is transferred between the logic circuits via a first delay adjustment unit. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a circuit configuration that is advantageous in suppressing an increase in circuit size and power consumption in a circuit that reduces the occurrence of hold violations in scan data. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is an example of a semiconductor integrated circuit for explaining the first embodiment. [Figure 2] 2 shows a configuration example of a filter circuit according to the first embodiment. [Figure 3] 3 shows an example of a delay adjustment unit according to the first embodiment. [Figure 4] 3 is a timing chart according to the first embodiment. [Figure 5] 10 is a modified example of the semiconductor integrated circuit according to the first embodiment. [Figure 6] 10 is a configuration example of a filter circuit according to the second embodiment. [Figure 7] 10 is a flowchart for explaining a test according to the second embodiment. [Figure 8] 1A and 1B are diagrams illustrating application of a semiconductor integrated circuit to equipment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0009] (Embodiment 1) An example of a semiconductor integrated circuit to which the present invention is applied will be described with reference to FIG. 1. FIG. 1 shows an analog-to-digital converter (ADC) 101 and a filter circuit unit 102. A semiconductor integrated circuit such as an image sensor is equipped with many ADCs 101 that convert analog data from the image sensor into digital data and many filter circuit units 102. The ADC 101 outputs a clock 103 and a clock enable 104 to the filter circuit 102. Although only one wiring is shown for the clock enable 104 here, multiple wirings may be used in practice to transmit a multi-bit signal. In the following description, it is assumed that 32 clock enable signals 104, corresponding to 32 bits, are output from the ADC 101. The ADC 101 may be, but is not limited to, a slope-type A / D conversion circuit, a successive approximation A / D conversion circuit, a delta-sigma (ΔΣ) A / D conversion circuit, or the like.

[0010] An example of scan testing a logic circuit will be described below. In this embodiment, an example will be described in which the filter circuit unit 102 is tested as the target of the scan test. The target of the scan test is not limited to filters, and other types of logic circuits may also be used. The scan test is performed based on a test clock 105. The test clock 105 is a clock used for the scan test of the filter circuit unit 102. The test clock 105 is branched and input to each of the multiple filter circuits arranged in the filter circuit unit 102. In this example, 32 filter circuits corresponding to the 32 output bits of the ADC 101 are arranged in the filter circuit unit 102. The test clock 105 is branched and supplied to each filter circuit. The filter circuits arranged according to the output bit number of the ADC 101 can be collectively referred to as one logic circuit group. In this embodiment, 32 filter circuits constitute one logic circuit group. The number of logic circuits constituting a logic circuit group is not limited to this and can be any number of logic circuits as needed. The filter circuit unit 102 in this embodiment removes noise contained in A / D converted data and includes a decimation filter, etc.

[0011] Clock buffers 110 to 113 are buffers inserted between the point where test clock 105 is supplied and each filter circuit arranged in filter circuit unit 102, and are automatically inserted by a layout tool according to constraints such as wiring length and signal transition time. Scan chain input 130 is scan data input for testing filter circuit unit 102. Scan chain output 131 is the output of the scan chain of filter circuit unit 102. Note that buffers 110 to 113 are shown in FIG. 2 as an example. Buffers can be arranged corresponding to each filter.

[0012] The test mode signal 120 is a signal for switching the filter circuit unit 102 to a test mode. When the test mode signal is at an L level ("0"), the filter circuit unit 102 operates as a normal filter, and when the test mode signal is at an H level ("1"), the filter circuit unit 102 is controlled to a scan test mode. Note that the relationship between the H level and the L level may be reversed.

[0013] 2 shows an example of the circuit configuration of the filter circuit unit 102. An AND gate 201 is a circuit that outputs the logical product of a clock 103 from the ADC and a clock enable 104. The AND gate 201 supplies the logical product to a clock input Clk of a flip-flop 202, which operates as a data holding circuit, via a clock switching circuit 207. Similarly, AND gates 221 and 241 also supply the logical product to the clock input Clk of flip-flops 222 and 242 via clock switching circuits 227 and 247.

[0014] In this embodiment, the clock enable 104 input to the clock circuit unit 102 has 32 bits ranging from [0] to

[31] . The filter circuit unit 102 has 32 logic circuits, each consisting of five flip-flops. A logic circuit group is made up of the 32 logic circuits. Note that FIG. 2 shows three of the 32 logic circuits. In this embodiment, an example is described in which one logic circuit includes five flip-flops, but the number of flip-flops is not limited to this. Alternatively, n flip-flops may be arranged that can transfer data sequentially from the first flip-flop, to which the output of the AND gate is first input, to the nth flip-flop. Each logic circuit can constitute part of a filter. Note that, below, explanations of the operation of circuits that operate similarly may be omitted.

[0015] The clock switching circuits 207, 227, and 247 are circuits that switch between the logical product of the AND gates 201, 221, and 241 and the test clock (105) depending on the value (L level ("0") or H level ("1")) of the test mode signal 120. A multiplexer may be used as the clock switching circuit.

[0016] In this embodiment, the clock switching circuits 207, 227, and 247 can select the test clock 105 when the test mode signal 120 is at H level ("1"), and can select the clock 103 output by the logical product of the AND gates 201, 221, and 241 when the test mode signal 120 is at L level ("0").

[0017] The configuration of each flip-flop will be explained using flip-flop 202 as an example. Flip-flop 202 has a clock input Clk, a data input D, a signal input SIN, an inverted output -Q, and a positive output Q. Flip-flop 202 operates differently during normal operation and during a scan test. The operation is switched by test mode signal 120. Test mode signal 120 can control the operation of flip-flop 202 via wiring (not shown).

[0018] In this embodiment, when clock switching circuits 207, 227, and 247 select the output of an AND gate, first flip-flop 202 receives the inverted data of the value it holds in synchronization with the selected clock. Second flip-flop 203 receives the inverted data of the value it holds in synchronization with the output of first flip-flop 202. Flip-flops 202 to 206, flip-flops 222 to 226, and flip-flops 242 to 246 each operate as a ripple counter that constitutes part of a filter.

[0019] When flip-flops 202 to 205 operate as ripple counters, test mode signal 120 controls the flip-flops so that their inverted outputs -Q receive data input D in synchronization with the clock to clock input Clk. The inverted output -Q of flip-flop 202 is received at data input D in synchronization with clock Clk. The inverted output -Q from flip-flop 202 is input to clock Clk of flip-flop 203 by clock switching circuit 207. The inverted output -Q of flip-flop 203 is input to clock Clk of flip-flop 204. In this way, data can be transferred sequentially from flip-flop 202 to flip-flop 206. In this way, flip-flops 202 to 205 can operate as ripple counters.

[0020] When a scan test is performed, the flip-flop is controlled to supply the test clock as a clock to the flip-flop by a test mode signal 120. During the scan test, the flip-flop is controlled to receive the positive output Q at the signal input SIN in synchronization with the test clock.

[0021] Clock buffers 208 are buffers inserted in the order of flip-flop connection, from flip-flop 202 to flip-flop 206, so as to increase the amount of delay when the clock propagates. The number and arrangement of clock buffers 208 are specified at the time of designing the semiconductor integrated circuit in order to guarantee the setup time of the flip-flops. Clock buffers 208 form clock lines that supply clocks to each of the flip-flops 202 to 206 that are arranged correspondingly.

[0022] As described above, clock buffer 228 is a buffer arranged so as to increase the amount of delay when the clock propagates from flip-flop 222 to flip-flop 226. Similarly, clock buffer 248 is a buffer arranged so as to increase the amount of delay when the clock propagates from flip-flop 242 to flip-flop 246.

[0023] Scan chains 210-214 are scan chains for transferring scan data to flip-flops 202-206. Scan chains 210-214 connect flip-flops so that scan data can be transferred in a direction opposite to the forward direction in which clock buffer 208 delays and propagates the clock. If the order in which a clock signal is supplied from a clock line to each flip-flop is defined as the forward direction, the clock signal is supplied from the clock line to flip-flops located downstream in the forward direction, with the clock signal having a greater delay. Furthermore, scan chains are arranged to transfer scan data from the flip-flop supplied with the clock having the greatest delay to the flip-flop supplied with the clock having the smallest delay. In other words, scan data is transferred in the reverse direction from the downstream flip-flop to the upstream flip-flop. While an example in which five flip-flops are arranged, from the first flip-flop 202 to the fifth flip-flop 206, is shown here, the number of flip-flops is not limited to this.

[0024] Scan data from the positive output Q of flip-flop 206 is transferred to the signal input SIN of flip-flop 205 via scan chain 210. Scan data from the positive output Q of flip-flop 205 is transferred to the signal input SIN of flip-flop 204. The scan chain is connected so that scan data is transferred in the direction opposite to the clock propagation direction. This reduces the occurrence of hold violations when flip-flops 202 to 206 receive scan data.

[0025] Similarly, scan chains 230 to 234 and scan chains 250 to 254 are scan chains for transferring scan data between flip-flops 222 to 226 and flip-flops 242 to 246. Scan chains 230 to 234 and scan chains 250 to 254 can transfer scan data in the forward direction and the reverse direction in which clock buffer 228 and clock buffer 248 propagate the clock while delaying it.

[0026] Next, the transfer of scan data between logic circuits will be described. As shown in FIG. 2, the test clock supplied to flip-flop 206 is delayed relative to the test clock supplied to flip-flop 202. The test clock supplied to flip-flop 226 may also be delayed relative to the test clock supplied to flip-flop 202. Therefore, the clock delay is not adjusted between flip-flop 202 and flip-flop 226. Since the scan data transferred from flip-flop 202 to flip-flop 226 is synchronized with test clocks with different timings, a hold violation may occur. A hold violation may also occur during data transfer between flip-flop 222 and flip-flop 246.

[0027] Buffers can be placed to adjust delay times to eliminate hold violations between logic circuits, but increasing the number of buffers can increase power consumption. In this embodiment, a lock-up latch 270 is placed in the transfer path of scan data between logic circuits. The lock-up latch 270 can delay data from the flip-flop 202 by half a cycle of the test clock 105. The lock-up latch 270 can delay the signal of the scan chain 214 by half a cycle of the test clock 105 before outputting it. By inserting the lock-up latch 270 into the scan chain 214, the occurrence of hold violations between the flip-flop 202 and the flip-flop 226 can be reduced.

[0028] Similarly, by inserting lock-up latch 280 into scan chain 234, it is possible to reduce the occurrence of hold violations between flip-flop 222 and flip-flop 246. The circuit configuration described above makes it possible to reduce the occurrence of hold violations when transferring scan data between logic circuits without inserting a buffer into the scan chain.

[0029] Next, the operation of a lock-up latch will be explained with reference to Figure 3(A). Flip-flop 301 and flip-flop 303 are flip-flops that operate in synchronization with the rising edge of clock Clk. Latch circuit 302 is placed between flip-flop 301 and flip-flop 303. Latch circuit 302 latches data in synchronization with the inverted clock of clock Clk, so data transferred from flip-flop 301 to flip-flop 303 is delayed by half a cycle of clock Clk.

[0030] 3B shows an example in which flip-flops that operate in synchronization with the falling edge of the clock Clk are used as flip-flops 311 and 312. In this case, latch circuit 312, which is placed between flip-flops 311 and 313, latches data in synchronization with the rising edge of the clock Clk. In this example, too, by using an inverted clock in clock flip-flops 311 and 313 and latch circuit 312, it is possible to delay data transferred from flip-flop 311 to flip-flop 313 by half a cycle of the clock Clk.

[0031] The lock-up latch 270 can delay the data by half a clock cycle when transferring data from the flip-flop 202 to the flip-flop 226. In this way, the occurrence of hold violations can be reduced when transferring scan data between logic circuits via scan chains.

[0032] The reduction of hold violations due to the lockup latch will be explained using the timing chart in Figure 4. Figure 4 shows the case where the test mode signal is at H level. The top rectangular wave represents the test clock 401 supplied to the flip-flop 202. Time passes as one moves to the right in Figure 4. The second trapezoidal wave from the top represents the scan data 402 that is transferred through the scan chain 214 and input to the lockup latch 270. Here, the scan data 402 begins to transition to H level in response to the rising edge of the test clock 401 at timing t410.

[0033] The third trapezoidal wave from the top represents scan data 403 output from lock-up latch 270. The fourth square wave from the top represents test clock 404 input to flip-flop 226 via clock buffer 228. The bottom waveform represents scan data 405 on scan chain 230, which is the output of flip-flop 226.

[0034] Timing t411 is to the right of timing t410, which indicates that the input clock to flip-flop 226 rises later than the input clock to flip-flop 202 due to the influence of clock propagation delay.

[0035] When the test clock 401 rises at timing t410, the scan data begins to transition to the H level on the scan chain 214. After timing t411, the scan data 402 becomes the H level.

[0036] First, we will explain the case where there is no lock-up latch 270. In this case, at timing t411, the rising edge of the test clock 404 of the flip-flop 226 and the transition of the scan data 402 signal may overlap. This may cause a hold violation, resulting in the value of the scan data 402 being erroneously received.

[0037] The case where the lockup latch 270 is present will be described. In this case, the value of the scan data 403 output from the lockup latch 270 remains at L level until the test clock 401 falls at timing t412. This reduces the possibility of a hold violation occurring in the flip-flop 226. Furthermore, since the scan data 403 begins to transition to H level from timing t412, the flip-flop 226 can receive the value of the scan data 403 at timing t413. By using the lockup latch 270 to delay the data by half a clock cycle, it is possible to reduce the occurrence of erroneous data reception, i.e., a hold violation.

[0038] As a result, when scan data is transferred from a flip-flop in a preceding logic circuit to a flip-flop in a succeeding logic circuit, the occurrence of errors can be reduced even if there is a delay difference in the clock between the preceding flip-flop and the succeeding flip-flop.

[0039] 4 shows a timing chart relating to the scan chain 214 and lock-up latch 270, but the lock-up latch 280 can also operate at the same timing. In the example of Fig. 2, only three logic circuit groups each consisting of five flip-flops are shown, but lock-up latches can also be placed between other logic circuits (not shown) in the same way and can operate in the same way.

[0040] Furthermore, a slow test clock frequency is used to shift the data obtained after the scan test. Therefore, there is little need to consider setup violations when shifting scan data. Furthermore, by inserting a lock-up latch and adding a signal propagation delay of half a clock cycle to the scan data as in this embodiment, hold violations of scan data between clocks for which the clock delay is not adjusted can be prevented, enabling the exchange of test data.

[0041] 5 shows an example of an arrangement different from that shown in FIG. 1. Here, the physical position of the test clock 105 has been changed. Furthermore, a change in the physical arrangement of the filter circuit 102 on the semiconductor integrated circuit may change the relative positions of the test clock and the filter circuit.

[0042] 5, it is assumed that the test clock 505 is supplied to the filter circuit unit 102 from a different position than in Fig. 1. As in Fig. 1, the test clock 105 can be branched into multiple parts and supplied corresponding to the multiple filters arranged in the filter circuit unit 102. Note that, as in the case of Fig. 1, the number of branches of the test clock 505 is 32.

[0043] The branched test clocks are input to the filter circuit unit 102 via clock buffers 510 to 514. In this example, clock buffers 510 to 514 are shown as being inserted into the test clock 505, but a plurality of clock buffers may be provided corresponding to the number of branches. The clock buffers are designed and inserted using a layout tool based on constraints such as wiring length and signal transition time.

[0044] 5 differs from the example in FIG. 1 in the physical layout and position where test clock 505 is input, and therefore the insertion state of clock buffers 510-514 differs from the insertion state of clock buffers 110-113. Therefore, the delay times of the 32 test clocks 505 input to filter circuit unit 120 are not the same as those in FIG. 1. However, by adopting the circuit configuration shown in FIG. 2, even in the case of FIG. 5, it is possible to reduce the occurrence of hold violations when transfer of scan data from flip-flops 202-206 without changing the internal structure of filter circuit unit 120.

[0045] Similarly, hold violations can be reduced in the transfer of scan data through the scan chains of flip-flops 222-226 and flip-flops 242-246. Even if the insertion state of clock buffers 510-514 differs from that of clock buffers 110-113, the difference in clock propagation delay between flip-flops 202-206 and flip-flops 222-226 can be absorbed by lock-up latch 270. The difference in clock propagation delay between flip-flops 222-226 and flip-flops 242-246 can also be absorbed by lock-up latch 280, reducing hold violations in the exchange of scan data. By using the implementation method of filter circuit unit 120 shown in FIG. 2, even if the clock state outside the filter changes, scan data can be exchanged without changing the inside of filter circuit unit 120.

[0046] As described above, even if the state of the test clock input to the filter circuit unit 102 changes, it is possible to guarantee hold without modifying the internal circuit configuration of the filter circuit unit 102. Furthermore, because no buffers for guaranteeing hold are inserted into the scan chain between the ripple counters, it is possible to reduce power consumption.

[0047] (Embodiment 2) An example of a configuration in which the filter circuit of the present invention is used in an image sensor with a different number of pixels will be described with reference to Fig. 6. In Fig. 6, circuits and configurations equivalent to those in the first embodiment will be given the same reference numerals and will not be described again.

[0048] In this embodiment, an example is shown in which a switching circuit for switching the configuration of the scan chain is further added to the filter circuit unit 102 used in the first embodiment, thereby making it possible to reuse the filter circuit unit 120 for image sensors with different numbers of pixels.

[0049] 6 are ADCs used for analog-to-digital conversion (AD conversion) processing provided in the upstream stage of the filter circuit unit. Dummy circuits 603 and 604 may be circuits that output fixed values ​​as input signals to the filter circuit. Dummy circuits 603 and 604 may be circuits that do not output useful data. Note that the numbers of ADCs 601 and 602 and dummy circuits 603 and 604 shown in the figure are merely examples and are not limited to the present embodiment.

[0050] The filter circuit unit 605 has multiple filter circuits provided for the ADC 601. The filter circuit unit 605 corresponds to the logic circuit group described above. Similarly, the filter circuit unit 606 is a filter circuit unit having a filter circuit provided for the ADC 602. The filter circuit unit 607 is a circuit implemented for reusing the filter unit. As shown in FIG. 6, in this example, the filter circuit unit 607 does not have a corresponding ADC due to the number of pixels of the image sensor. Therefore, the filter circuit unit 607 is connected to the dummy circuit 603. Similarly, the filter circuit unit 608 is also a circuit implemented for reusing the filter unit, but since it does not have a corresponding ADC, it is connected to the dummy circuit 604. In this example, two of the four filter circuit units 605 to 609 (filter circuit units 605 and 606) are used to process data from the ADC, and the remaining two (filter circuit units 607 and 608) are not used.

[0051] The internal configuration of the filter circuit units 605 to 608 is the same so that the filters can be reused in other image sensors. Here, the filter circuit unit 606 will be explained as an example. The lock-up latch 610 functions as a delay adjustment unit that delays the signal at the scan chain input 130-2 input from the adjacent filter circuit unit 605 by half a cycle of the test clock 105. The output data of the lock-up latch 610 is received by the flip-flop 206 of the filter circuit unit 606.

[0052] A delay of half a cycle of the test clock is applied to the scan data by the lock-up latch 610. For the scan data input from the scan chain input 130-2, the occurrence of hold violations can be reduced without disposing a buffer circuit for adjusting the delay time between the filter circuit unit 605 and the filter circuit unit 606.

[0053] The control unit 630 is a circuit that outputs control signals 631 to 634 for the scan signal switching circuit, which will be described later. The scan signal switching circuit 621 can switch between the scan chain input 130-2 input from the filter circuit unit 605 and the scan data transferred from the flip-flop 242 via the scan chain 254. When the scan signal switching circuit 621 selects the scan chain output 131-1 input from the adjacent filter circuit 605, a bypass path that bypasses the filter circuit unit 606 can be formed.

[0054] The switching of the scan signal switching circuit 621 is controlled by a control signal 632 from a control unit 630. The signal selected by the scan signal switching circuit 621 is output to the outside from the filter circuit 606 as a scan chain output 131-2, and can be input to a scan chain input 130-3 of the adjacent filter circuit 607.

[0055] In this embodiment, when the value of the control signal 632 is at L level, the scan signal switching circuit 621 can select the scan data output from the flip-flop 242. When the value of the control signal 632 is at H level, the scan signal switching circuit 621 can select the scan chain input 130-2 input from the adjacent filter circuit unit 605.

[0056] An example of the configuration of this embodiment will be described with reference to Fig. 7. Fig. 7 shows a flowchart relating to the exchange of scan data between filter units. In control signal setting step 701, the value of control signal 631 output by control unit 630 is set to L level, the value of control signal 632 is set to L level, the value of control signal 633 is set to H level, and the value of control signal 634 is set to H level.

[0057] Next, in scan test step 702, after the test mode signal 120 is set to H level, the test clock 105 is generated a predetermined number of times to set scan data. Driven by the test clock 105, test scan data is transferred via the scan chain. In this way, scan data is sent to and received from filter circuits 605 and 606 that require scan testing. Furthermore, scan data can be bypassed for filter circuits 607 and 608 that do not require scan testing.

[0058] According to this embodiment, a semiconductor integrated circuit having an appropriate number of filter circuit units is prepared, and the filter circuit units to be operated can be selected according to the number of pixels of the image sensor, and unnecessary filter circuit units can be bypassed. By preparing a semiconductor integrated circuit having general-purpose filter circuit units, it is possible to reuse filter circuit units for image sensors with different numbers of pixels.

[0059] <Application of semiconductor integrated circuits to equipment> Hereinafter, a device 1000 will be described that includes a semiconductor device 1100 including a package 1020 on which a semiconductor chip 1110 including a semiconductor integrated circuit is mounted, as shown in FIG. 8. The semiconductor chip 1110 is accommodated in the package 1020 and mounted on the device 1000. In the configuration shown in FIG. 8, the semiconductor chip 1110 includes the semiconductor integrated circuit according to the above-described embodiment. The semiconductor device 1100 can include a package 1020 that includes a base 1010 to which the semiconductor chip 1110 is fixed, and, if the semiconductor chip 1110 includes an image sensor, a light-transmitting member 1030 such as glass. The package 1020 can include bonding members such as wires and bumps that connect inner leads provided on the base 1010 to terminals such as pad electrodes provided on the semiconductor chip 1110.

[0060] The device 1000 may include at least one of an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls a semiconductor chip 1110. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0061] The processing device 1060 processes an output signal from a semiconductor integrated circuit included in the semiconductor chip 1110. The processing device 1060 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). If the semiconductor chip includes an image sensor, an image may be generated based on the event signal E, for example. The display device 1070 is an EL display device or a liquid crystal display device that displays an information image obtained by the semiconductor chip 1110. The memory device 1080 is a magnetic device or a semiconductor device that stores the information image obtained by the semiconductor chip 1110. The memory device 1080 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0062] The mechanical device 1090 has a moving part or a propulsion part such as a motor or an engine. In the device 1000, a signal output from the semiconductor chip 1110 is displayed on the display device 1070, or transmitted to the outside by a communication device (not shown) included in the device 1000. For this purpose, the device 1000 may further include a storage device 1080 and a processing device 1060 in addition to the memory circuit and arithmetic circuit included in the semiconductor chip 1110. The mechanical device 1090 may be controlled based on the signal output from the semiconductor chip 1110.

[0063] The device 1000 is also suitable for electronic devices such as information terminals with a photographing function, such as smartphones, wearable devices, and cameras, such as interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras. The mechanical device 1090 in the camera can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in the camera can move the optical device 1040 for vibration isolation.

[0064] Furthermore, the device 1000 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 1090 in the transportation equipment may be used as a moving device. The device 1000 as transportation equipment is suitable for transporting semiconductor chips 1110 or for assisting and / or automating driving by using a photographing function. The processing device 1060 for assisting and / or automating driving can perform processing for operating the mechanical device 1090 as a moving device based on information obtained by the semiconductor chip 1110. Alternatively, the device 1000 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0065] (Other embodiments) The disclosure of the present specification includes the following semiconductor integrated circuit and device using the semiconductor integrated circuit.

[0066] (Item 1) A semiconductor integrated circuit in which a plurality of logic circuits are arranged, each logic circuit including n data retention circuits for retaining data, a scan chain for transferring scan data, and a clock line including a plurality of clock buffers for delaying a clock signal; a clock signal on the clock line is supplied to the n data retention circuits; a clock signal having a larger delay amount is supplied from the clock line to a downstream data hold circuit in a forward direction from a first data hold circuit to an nth data hold circuit among the n data hold circuits; the scan chain is arranged to transfer scan data in a reverse direction from the n-th data retention circuit to the first data retention circuit; the scan data is transferred between the logic circuits via a first delay adjustment unit; A semiconductor integrated circuit characterized by: (Item 2) 2. The semiconductor integrated circuit according to item 1, wherein the first delay adjustment unit is a latch circuit, and the latch circuit delays an input to the latch circuit by half a cycle of the clock signal before outputting the delayed input. (Item 3) a predetermined number of the logic circuits form a logic circuit group; 3. The semiconductor integrated circuit according to item 1 or 2, further comprising: a switching circuit that controls transfer of scan data between the logic circuit groups; and a control unit that controls the switching circuit. (Item 4) 4. The semiconductor integrated circuit according to item 3, wherein the switching circuit controls whether the scan data is supplied to the logic circuit group or bypasses the logic circuit group. (Item 5) 5. The semiconductor integrated circuit according to item 3 or 4, further comprising a second delay adjustment unit that delays the scan data between the logic circuit groups. (Item 6) 6. The semiconductor integrated circuit according to item 5, wherein the second delay adjustment unit is a latch circuit, and the latch circuit delays an input by half a cycle of the clock signal and outputs the delayed input. (Item 7) 7. The semiconductor integrated circuit according to any one of items 3 to 6, wherein the switching circuit includes a multiplexer. (Item 8) 8. The semiconductor integrated circuit according to any one of items 1 to 7, wherein the logic circuit operates as a ripple counter. (Item 9) 9. The semiconductor integrated circuit according to item 8, wherein the ripple counter constitutes part of a filter that reduces the number of bits of data from an analog-to-digital converter. (Item 10) 10. The semiconductor integrated circuit according to item 9, wherein the analog-to-digital converter converts analog data from an image sensor into digital data. (Item 11) 11. The semiconductor integrated circuit according to item 9 or 10, wherein the analog-to-digital converter is a delta-sigma analog-to-digital converter. (Item 12) A semiconductor integrated circuit in which a logic circuit is arranged, the logic circuit including n data retention circuits for retaining data, a scan chain for transferring scan data, and a clock line including a plurality of clock buffers for delaying a clock signal, the n data holding circuits are connected to form a ripple counter that transfers data in a forward direction from a first data holding circuit to an nth data holding circuit; a clock signal on the clock line is supplied to the n data retention circuits; a clock signal having a larger delay is supplied from the clock line to a data holding circuit located downstream in the forward direction; the scan chain is arranged to transfer scan data in a reverse direction from the n-th data retention circuit to the first data retention circuit; A semiconductor integrated circuit characterized by: (Item 13) A semiconductor integrated circuit according to any one of items 1 to 12, and a processing device that processes an output signal from the semiconductor integrated circuit.

[0067] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0068] 103 clock, 104 clock enable, 105 test clock, 110 clock buffer, 111 clock buffer, 112 clock buffer, 113 clock buffer, 120 test mode signal, 130 scan chain input, 131 scan chain output, 201, 221, 241 AND gate, 208, 228, 248 clock buffer, 202, 203, 204, 205, 206 flip-flop, 222, 223, 224, 225, 226 flip-flop, 242, 243, 244, 245, 246 flip-flop, 210, 211, 212, 213, 214 scan chain, 270, 280 lock-up latch

Claims

1. A semiconductor integrated circuit in which a plurality of logic circuits are arranged, each logic circuit including n data retention circuits for retaining data, a scan chain for transferring scan data, and a clock line including a plurality of clock buffers for delaying a clock signal; a clock signal on the clock line is supplied to the n data retention circuits; a clock signal having a larger delay amount is supplied from the clock line to a downstream data hold circuit in a forward direction from a first data hold circuit to an nth data hold circuit among the n data hold circuits; the scan chain is arranged to transfer scan data in a reverse direction from the n-th data retention circuit to the first data retention circuit; the scan data is transferred between the logic circuits via a first delay adjustment unit; A semiconductor integrated circuit characterized by:

2. 2. The semiconductor integrated circuit according to claim 1, wherein the first delay adjustment section is a latch circuit, and the latch circuit delays an input to the latch circuit by a half cycle of the clock signal before outputting the delayed input.

3. a predetermined number of the logic circuits form a logic circuit group; 2. The semiconductor integrated circuit according to claim 1, further comprising: a switching circuit that controls transfer of scan data between said logic circuit groups; and a control unit that controls said switching circuit.

4. 4. The semiconductor integrated circuit according to claim 3, wherein the switching circuit controls whether the scan data is supplied to the logic circuit group or bypassed from the logic circuit group.

5. 4. The semiconductor integrated circuit according to claim 3, further comprising a second delay adjustment section for delaying the scan data between the logic circuit groups.

6. 6. The semiconductor integrated circuit according to claim 5, wherein the second delay adjustment section is a latch circuit, and the latch circuit delays an input by a half cycle of the clock signal and outputs the delayed input.

7. 4. The semiconductor integrated circuit according to claim 3, wherein the switching circuit includes a multiplexer.

8. 2. The semiconductor integrated circuit according to claim 1, wherein the logic circuit operates as a ripple counter.

9. 9. The semiconductor integrated circuit according to claim 8, wherein the ripple counter forms a part of a filter that reduces the number of bits of data from an analog-to-digital converter.

10. 10. The semiconductor integrated circuit according to claim 9, wherein the analog-to-digital converter converts analog data from an image sensor into digital data.

11. 10. The semiconductor integrated circuit according to claim 9, wherein the analog-to-digital converter is a delta-sigma analog-to-digital converter.

12. A semiconductor integrated circuit in which a logic circuit is arranged, the logic circuit including n data retention circuits for retaining data, a scan chain for transferring scan data, and a clock line including a plurality of clock buffers for delaying a clock signal, the n data holding circuits are connected to form a ripple counter that transfers data in a forward direction from a first data holding circuit to an nth data holding circuit; a clock signal on the clock line is supplied to the n data retention circuits; a clock signal having a larger delay is supplied from the clock line to a data holding circuit located downstream in the forward direction; the scan chain is arranged to transfer scan data in a reverse direction from the n-th data retention circuit to the first data retention circuit; A semiconductor integrated circuit characterized by:

13. A semiconductor integrated circuit according to any one of claims 1 to 12; and a processing device that processes an output signal from the semiconductor integrated circuit.

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