Integrated circuit for product-sum operation

Abstract

To provide a structure that achieves a product-sum operation circuit that requires a plurality of different input signals with a plurality of lateral FETs whose conductivity type of channel parts vertically stacked at the same position on the same plane are the same, in which gate electrodes and source electrodes that are stacked vertically can be electrically isolated, and a method of manufacturing the structure specifically.SOLUTION: Provided is a structure that achieves a product-sum operation circuit that requires a plurality of different input signals with a plurality of lateral FETs whose conductivity type of channel parts vertically stacked at the same position on the same plane are the same, in which gate electrodes and source electrodes that are stacked vertically can be electrically isolated, drains of the plurality of lateral FETs are electrically connected to each other vertically, gate signal electrodes and source signal electrodes of the plurality of lateral FETs are stacked vertically through insulating films between the gate electrodes and between the source electrodes, a signal is input as voltage to the source electrode, and a product-sum operation result is output as current to the drain.SELECTED DRAWING: None

Description

[Technical Field]

[0001] Integrated circuit for multiply-and-accumulate operations using gate-all-around transistors [Background technology]

[0002] In the past, LSIs have progressed in accordance with Moore's Law as planar transistors have become increasingly miniaturized, leading to steady progress in increasing capacity, reducing costs, increasing speed, and reducing power consumption.

[0003] As a result, MPUs, which are representative of logic LSIs, have achieved GHz operation using more than 1 billion planar transistors, and NAND flash memory, which uses planar transistors and has the highest capacity among memory LSIs, has been expanded to 64 Gbit (Reference 1).

[0004] However, miniaturization of this planar transistor has recently reached its limit due to short channel effects and the like.

[0005] To solve this problem, three-dimensional transistors that are resistant to short channel effects have been developed, a typical example of which is the FinFET.

[0006] FinFETs have the advantage that they can be miniaturized and are resistant to short channel effects because three sides can be used for the channel instead of one side of a planar transistor. In recent years, gate-around transistors (hereafter abbreviated as GAA) have been proposed, which can use four sides for the channel, which can control the short channel effect even more than FinFETs, and MBCFETs (Multi-Bridge Channel FETs) which are made by stacking multiple GAAs vertically and are more suitable for achieving higher speeds than GAAs.

[0007] In these structures, the source, channel, and drain of the transistor are arranged horizontally (hereafter referred to as lateral FET or GAA), so by optimizing manufacturing technology, it is relatively easy to stack multiple lateral FETs of the same conductivity type vertically in the same position on the same plane. This not only increases speed, but also reduces costs by reducing the pattern area on the plane.

[0008] However, when the conductivity type of the channel portion is the same (all N-type or all P-type), the gate electrode is common among multiple stacked lateral FETs, so a basic logic circuit that requires multiple different input signals could not be realized using multiple lateral FETs stacked vertically in the same position on the same plane.

[0009] In order to stack gate electrodes that serve as a plurality of different input signals, it is necessary to electrically isolate the different gate electrodes, but no method for doing so has been proposed in the past.

[0010] In particular, no method has been proposed that can be applied to current-driven product-sum circuits in AI integrated circuits, which are basic logic circuits suitable for multiple inputs and are configured with multiple lateral FETs stacked in multiple layers. Reference 1: M. Sako et al., “A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology,” ISSCC Dig. Tech. Papers, 2015. Summary of the Invention The problem that the invention is trying to solve

[0011] A multiply-accumulate circuit requiring multiple different input signals is realized by using multiple lateral FETs with the same conductivity type in the channel portion stacked vertically at the same position on the same plane, and no structure has been proposed that can electrically isolate the gate electrodes and source electrodes stacked vertically, nor has any specific method for manufacturing such a structure been proposed.

[0012] A product-sum operation circuit requiring a plurality of different input signals is realized by a configuration in which a plurality of horizontal FETs having the same conductivity type in the channel portion are stacked vertically at the same position on the same plane, the vertically stacked gate electrodes and source electrodes are electrically isolated from each other, the drains of the plurality of horizontal FETs are electrically connected vertically, the gate signal electrodes and source signal electrodes of the plurality of horizontal FETs are stacked vertically via insulating films between the gate electrodes and between the source electrodes, a signal is input as a voltage to the source electrode, and the product-sum operation result is output as a current to the drain.

[0013] In the sum-of-products operation, the source and drain electrodes are formed using the same material in the same process, and then replaced with different electrode materials in a different process step, and the source of the lateral FET is realized by diffusing N+ impurities from the source electrode. Also, the stacked source electrode and gate electrode are either arranged parallel in both the horizontal and vertical directions, or arranged parallel in the horizontal direction but diagonally shifted in the vertical direction instead of horizontally.

[0014] The present invention has made it possible for the first time to realize a multiply-and-accumulate circuit that requires multiple different input signals by using multiple horizontal FETs with the same conductivity type in the channel portion stacked vertically at the same position on the same plane, and to realize a structure that can electrically isolate the gate electrodes and source electrodes stacked vertically, and to specifically manufacture this structure.

[0015] As a result, without sacrificing performance (high speed, low power consumption), the planar pattern area of ​​a single FeFET-type GAA that constitutes a multiply-and-accumulate circuit can be significantly reduced (by the number of layers, 1 / 256 for 256-layer stacking, 1 / 1024 for 1024-layer stacking) compared to the conventional single-layer horizontal GAA method, and the increase in the number of manufacturing processes is also kept to a minimum compared to the conventional single-layer horizontal GAA method, resulting in a significant reduction in manufacturing costs (1 / 25-1 / 12.5 for 256-layer stacking technology, 1 / 100-1 / 50 for 1024-layer stacking technology).In other words, this invention has the characteristics to realize future high speed, low power consumption, and low cost AI LSIs. BEST MODE FOR CARRYING OUT THE INVENTION

[0016] A first embodiment of a product-sum calculation integrated circuit according to the present invention will be described below with reference to the drawings. [First embodiment] (Configuration of the first embodiment) A first embodiment of the present invention will now be described. Figure 1 shows a circuit diagram of a two-input, two-output product-sum operation circuit of the first embodiment. The horizontal FET is a ferroelectric FET (FeFET) type GAA. The FeFET type GAA is stacked in two layers vertically. (Basically, any value can be used for the number of inputs, outputs, and stacked layers.)

[0017] The input is input as a voltage to 102 (SL1) and 104 (SL2), and the weight is the resistance value of the FeFET (Ferroelectric FET) type gate array amplifier. The product-sum operation result is output as a current to BL1 (105) and BL2 (106). The resistance value is realized as the threshold voltage of the FeFET type gate array amplifier. The input SL (102, 104) runs parallel to the WL (101, 103) connected to the gate of the FeFET type gate array amplifier. The output BL (105, 106) runs perpendicular to both the WL (101, 103) and SL (102, 104). While multiple gate array amplifiers 113 are arranged horizontally on a plane in the conventional type, in the first embodiment, they can be stacked vertically (111 for 105 related and 112 for 106 related), significantly reducing the pattern area (it can be reduced to half in the pattern diagram in Figure 1).

[0018] The SL can be insulated and isolated between the upper and lower FeFET type GAA (between 107 and 109, or between 108 and 110) in the same way as the WL (N for source electrode + (Diffusion is formed by diffusion from the source electrode.) The current-driven product-sum operation circuit is characterized by the absence of series connections, which eliminates the complex process steps inherent in series connections and reduces manufacturing costs due to the fewer process steps.

[0019] FIG. 2 shows a top view 140 (for two FeFET type GAA in the direction of WL) after all process steps of the two-input, two-output product-sum operation circuit diagram of the first embodiment are completed, a cross-sectional view 141 in the AA" direction (direction of drain current flow), a cross-sectional view 142 in the BB" direction (of the gate portion in the direction of WL), a cross-sectional view 143 in the CC" direction (of the source portion in the direction of SL), and an explanatory diagram 145 of symbols used in 140-143. 120 denotes the gate portion of the FeFET type GAA, 12 Reference numeral 1 denotes the source portion of the FeFET type GAA, 134 denotes the ferroelectric gate insulating film of the FeFET type GAA, 130 denotes the gate electrode, 132 denotes the source electrode, 124 denotes the buried BL, 127 denotes the insulating film between the gate electrode and the source electrode, 136 denotes the silicon substrate, 137 denotes the interlayer insulating film, and 133 denotes a silicon epitaxial growth film for reducing resistance. In the first embodiment, in order to simplify the manufacturing process, the WL and SL run parallel not only in the horizontal direction but also in the stacking direction.

[0020] If the minimum processing dimension in manufacturing is F, the length in the AA' cross section direction is F for the source electrode part, drain electrode part, and gate part, and F for the distance between adjacent GAAs in the horizontal direction, for a total of 4F. On the other hand, in the BB' cross section direction, if the horizontal channel width of the GAA is F and the distance between adjacent GAAs in the horizontal direction is F, the horizontal length occupied by one GAA is 2F. In other words, the pattern area occupied by one GAA in plan view is 4F horizontally * 2F vertically = 8F. 2 It can be made smaller. In order to input different signals from the outside to the gate and source of one stacked FeFET type GAA, the gate electrode and source electrode are set in a stepped shape as shown in the BB' and CC' cross sections. In other words, the lower gate electrode is long and the upper one is short, and signals are input to the gate or source by vertical wiring (not shown).

[0021] 3 to 18 show a plan view of the first embodiment, cross-sectional views in three directions, and an explanation of the symbols used.

[0022] First, Ge (102), SiGe (146), Si (136), SiGe Ge, SiGe, Si, SiGe, and Ge are stacked over the entire surface of a silicon substrate (136) (Figure 3). In a later manufacturing process, the Ge portion is selectively removed, and finally, 127 (insulating film between the gate electrode and source electrode) is buried. Similarly, in a later manufacturing process, the SiGe portion is selectively removed, and after forming an insulating film between the source and gate portions, finally, gate electrode 130 and source electrode 132 are buried, respectively. On the other hand, the silicon portion 136 is not removed, and in a later process, gate insulating film 134 is formed on four sides of the gate portion, and the source portion is formed by N+ diffusion from the source electrode 132.

[0023] Next, in order to separate the adjacent FeFET type GAA in the direction in which the transistors run, an isolation is formed as shown in FIG. 4 (FIG. 4).

[0024] Next, a dummy gate source 147, which determines the sum of the gate length and source electrode length, is formed in the direction in which the word line runs. The thickness of the dummy gate source is designed to be thick. After that, a thick insulating film 137 with a large width (approximately F) is formed on the drain side of the dummy gate source in a manufacturing process that leaves the sidewall (Figure 5). In a later process, the source side of the dummy gate source 147 is removed and used as a dummy gate 148.

[0025] Next, the Ge and SiGe drain portions are removed from the side, and an insulating film 137 is formed in the removed portions. At this time, the process conditions are set so that the Si portions are not removed (FIG. 6).

[0026] Next, the insulating film 137 is buried in the element isolation portion, the dummy gate source 147 is thinned, and the insulating film 137 is left on the sidewalls of the dummy gate source 147 and the element isolation portion (FIG. 7).

[0027] In the next manufacturing process, a trench is simultaneously formed in the drain area using the oxide film on the sidewall, the dummy gate source, and the insulating film for element isolation as a mask. After that, a silicon epitaxial layer 133 is formed on the side of the silicon substrate. This is to electrically connect the Si side of the FeFET type GAA to the wiring layer formed in a later process with as low resistance as possible through ohmic contact (Figure 8).

[0028] Next, wiring 124 is buried in the trench portion opened for the drain (FIG. 9).

[0029] Next, the source side of the dummy gate source is removed (the width of the remaining dummy gate source is about half of the original width), a narrow insulating film 137 is formed on the sidewall of the gate side of the remaining dummy gate source, and then a dummy source 148 is formed on the source (FIG. 10). The narrow insulating film 137 electrically separates the gate electrode 130 and source electrode 132, which will be formed later, and the stacked structure shown in FIG. 3 will be removed in a later process based on this narrow horizontal pattern.

[0030] The sidewall insulating film on the source side of the dummy gate source 147 is peeled off, and trenches are formed at three locations (149, 150, 151) between the FeFET type GAA adjacent in the direction in which the word line runs, and the upper surface is flattened (FIG. 11).

[0031] At three locations (149, 150, 151), only the Si is removed from the side of the trench by etching (Fig. 12). The stacked SiGe and Ge are not etched. This electrically separates the gate silicon 136 of the FeFET-type GAA adjacent to the WL and SL directions.

[0032] Next, after selectively removing only Ge 102, a gate-source electrode insulating film 127 is formed in that position, and an insulating film 137 is formed at position 150 (the narrow gap between the gate electrode and source electrode) (FIG. 13). This process achieves electrical isolation between the vertically stacked gate electrode and source electrode, which is a feature of this embodiment.

[0033] Next, after removing the SiGe 146 in the gate electrode portion, a ferroelectric gate insulating film 134 is formed (FIG. 14). By realizing a ferroelectric FeFET GAA, it becomes possible to realize the weight value of the product-sum operation as the threshold voltage of the FeFET GAA.

[0034] Next, a gate electrode 130 is formed in the cavity formed after removing the SiGe 146. The impurity concentration or material of this gate electrode is different from that of the source electrode 132 to be formed later (FIG. 15).

[0035] Next, a source electrode 132 is formed in the cavity formed after removing the SiGe 146. The impurity concentration or material of this source electrode is different from that of the gate electrode 130 formed previously (FIG. 16).

[0035] Next, N+ impurities are diffused from the previously formed source electrode 132 into the contacting silicon 136 to form the source of the FeFET type GAA (FIG. 17).

[0036] Finally, insulating film 137 is buried in element isolation portions 149 and 151, and taper etching is performed so that gate electrode 130 and source electrode 132 have a stepped shape (FIG. 18). Signal input to the gate electrode and source electrode is realized by connecting vertical wiring (not shown in the patent drawings) to the stepped portions of the gate electrode and source electrode running horizontally. [Configuration of the second embodiment] (Configuration of the second embodiment)

[0037] A second embodiment of the present invention will now be described. In the first embodiment, the WL is arranged parallel to the SL not only in a plan view but also in a vertical direction, whereas in the second embodiment, the WL is parallel in a plan view but is arranged at an angle in the vertical direction. The circuit diagram is shown in Figure 19. The WLs 211 and 212 run diagonally relative to the SLs 102 and 104. This improves the reliability of the FeFET type GAA as follows, more than in the first embodiment.

[0038] That is, in the first embodiment, when programming weight data into the FeFET type GAA 107, there is a known problem that erroneous writing occurs in the FeFET type GAA 108 connected to WL1 (101), and a large programming current flows into the FeFET type GAA 109 connected to BL1 (105). The second embodiment has the feature of being able to solve this problem by wiring the WL in a diagonal direction.

[0039] FIG. 20 shows a top view 140 (for two FeFET type GAA's in the direction of WL's running) after all the process steps of the 2-input 2-output product-sum operation circuit diagram of the second embodiment are completed (for two FeFET type GAA's in the direction of WL's running), a cross section 141 in the AA' direction (direction of drain current flow), a cross section 250 in the BB' direction (of the gate portion in the direction of WL's running), and a cross section 143 in the CC' direction (of the source portion in the direction of SL's running). As shown in 250, the necessary diagonal pattern is realized by shifting the WL's 211 and 212 by one layer in the height direction in the adjacent stacked GAA's. In the conventional planar type, there was a problem that the planar pattern area increased by 3.5 times to realize this diagonal pattern, but the second embodiment has the advantage that the pattern area does not increase by introducing a method of shifting the WL's by one layer in the height direction.

[0040] Figures 21 to 24 show the process steps of the second embodiment that differ from the first embodiment, namely, the step of stacking Ge (102) and SiGe (146) diagonally and vertically offset by one layer. First, Si (136), SiGe (146), and Ge (102) are stacked on only one FeFET-type GAA in the direction of the WL (Figure 21). Next, Ge (102) is formed on the FeFET-type GAA portion adjacent to the FeFET-type GAA. At this time, the FeFET-type GAA portion is stacked, but the Ge (102) on the adjacent FeFET-type GAA portion is connected by leaving the sidewalls (Figure 22). Next, Si (136), SiGe (146), and Ge (102) are stacked on two adjacent FeFET-type GAAs (Figure 23). Finally, Si(136), SiGe(146), and Ge(102) are stacked on the adjacent FeFET type GAA portion (FIG. 24). The other process steps are almost the same as those in the first embodiment.

[0040] The present invention has made it possible for the first time to realize a multiply-and-accumulate circuit that requires multiple different input signals by using multiple horizontal FETs with the same conductivity type in the channel portion stacked vertically at the same position on the same plane, and to realize a structure that can electrically isolate the gate electrodes and source electrodes stacked vertically, and to specifically manufacture this structure.

[0041] As a result, without sacrificing performance (high speed, low power consumption), the planar pattern area of ​​a single FeFET-type GAA that constitutes a multiply-and-accumulate circuit can be significantly reduced (by the number of layers, 1 / 256 for 256-layer stacking, 1 / 1024 for 1024-layer stacking) compared to the conventional single-layer horizontal GAA method, and the increase in the number of manufacturing processes is also kept to a minimum compared to the conventional single-layer horizontal GAA method, resulting in a significant reduction in manufacturing costs (1 / 25-1 / 12.5 for 256-layer stacking technology, 1 / 100-1 / 50 for 1024-layer stacking technology).In other words, this invention has the characteristics to realize future high speed, low power consumption, and low cost AI LSIs.

[0042] Current logic LSIs and AI LSIs achieve low cost, high speed, and low power consumption performance by miniaturizing elements, as represented by the minimum processing dimensions of elements, in accordance with Moore's Law and scaling of elements. By using the manufacturing technology of this invention, it is expected that low cost, high speed, and low power consumption performance that is 2-3 generations ahead of the performance obtained by conventional miniaturization technology can be obtained (assuming that miniaturization is 0.7 times the minimum processing dimensions per generation). Other Examples Industrial Applicability

[0043] The present invention is not limited to sum-of-products circuits in which lateral FETs are connected in parallel. It can be applied to NOR circuits and more complex digital and analog circuits as long as the logic circuit is composed of multiple-input lateral FETs. Furthermore, the lateral FET is not limited to FeFET-type GAA using ferroelectrics. It can also be applied to spin transistors using magnetic spin and PRAM-type FETs using phase-change materials. Applicable products include all currently commercialized integrated circuits using the above, such as logic LSIs, AI LSIs, and FPGAs. Furthermore, the present invention can be applied not only to single integrated circuits, but also to so-called 3D LSIs in which integrated circuits of the same type or different types are stacked. [Brief explanation of the drawings]

[0044] [Figure 1] 1 is a circuit diagram in the cross section of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention; [Figure 2] 1A to 1C are a plan view, cross-sectional views in three directions, and explanations of the drawings of a first embodiment of a method for manufacturing a product-sum calculation circuit according to the present invention. [Figure 3] 1A to 1C are a top view, cross-sectional views in three directions, and an explanation of the drawings after multilayer lamination of Ge, SiGe, and Si in a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum calculation circuit according to the present invention after element isolation between adjacent GAAs is performed. [Figure 5] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention, after forming a thick dummy gate and leaving an insulating film with a large sidewall length on its sidewall. [Figure 6] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention, after forming a thick dummy gate and leaving an insulating film with a large sidewall length on its sidewall. [Figure 7] 10A and 10B are a top view and a cross-sectional view of the first embodiment of the method for manufacturing a product-sum operation circuit according to the present invention after side walls are left on the side walls of the dummy gate source. [Figure 8]1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after trench etching is performed on the drain; [Figure 9] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after a wiring is buried in a drain; [Figure 10] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after a dummy source has been formed; [Figure 11] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after the upper portion is flattened; [Figure 12] 10A and 10B are a top view and a cross-sectional view of the first embodiment of the method for manufacturing a product-sum operation circuit according to the present invention after etching silicon from the side of three trenches. [Figure 13] 1A and 1B are a top view and a cross-sectional view of the first embodiment of the method for manufacturing a product-sum operation circuit according to the present invention after removing Ge and forming an insulating film between gate and source electrodes; [Figure 14] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after a gate insulating film is formed; [Figure 15] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after forming a gate electrode; [Figure 16] 1A and 1B are a top view and a cross-sectional view of a first embodiment of a method for manufacturing a product-sum operation circuit according to the present invention after a source electrode is formed; [Figure 17] 1A and 1B are a top view and a cross-sectional view of the first embodiment of the method for manufacturing a product-sum operation circuit according to the present invention after N+ diffusion from the source electrode. [Figure 18] 1A and 1B are a top view and a cross-sectional view of the first embodiment of the method for manufacturing a product-sum operation circuit according to the present invention, after finally burying an insulating film in the element isolation portion and forming the edges of the gate and source electrodes in a stepped shape. [Figure 19] FIG. 10 is a circuit diagram of a second embodiment of the method for manufacturing a product-sum operation circuit according to the present invention. [Figure 20]10A to 10C are a plan view, cross-sectional views in three directions, and explanations of the drawings of a second embodiment of a method for manufacturing a product-sum operation circuit according to the present invention. [Figure 21] ~ [Figure 24] 10A to 10C are explanatory diagrams showing a plan view and cross-sectional views in three directions of the first step of a second embodiment of a method for manufacturing a product-sum operation circuit according to the present invention, which is different from the first embodiment. [Explanation of symbols]

[0045] Related to the first embodiment 101...WL1, 102...SL1, 103...WL2, ​​104...SL2, 105...BL1, 106...BL2, 107...FeFET type GAA11, 108...FeFET type GAA12, 109...FeFET type GAA21, 110...FeFET type GAA22, 111...Stacked type GAA1, 112...Stacked type GAA2, 113...Planar type GAA, 120...Channel portion of stacked GAA, 121...Source portion of stacked GAA, 122...Channel portion of planar GAA, 123...Source portion of planar GAA, 124...buried type BL wiring, 125...planar type BL wiring, 126...planar type SL wiring, 127...stacked type inter-gate electrode / inter-source electrode insulating film, 128...planar type N+ drain electrode, 130...stacked type gate electrode, 131...planar type gate electrode, 132...stacked type source electrode, 133...silicon epitaxial layer, 134...stacked type GAA ferroelectric type gate insulating film, 135...planar type GAA ferroelectric type gate insulating film, 136...silicon substrate, 137...interlayer insulating film, 140...Top view of the first embodiment (for two GAA's), 141...AA" cross-sectional view of the first embodiment, 142...BB" cross-sectional view of the first embodiment, 143...CC" cross-sectional view of the first embodiment, 146...Description of the views of the first embodiment, 102...SiGe film, 146...Ge film, 147...dummy gate source (to become a dummy gate in a later process), 148...dummy source, 149...trench source side between stacked GAA, 150...trench source-gate between stacked GAA, 151...trench drain side between stacked GAA,

[0046] Related to the second embodiment 200... oblique laminated type GAA1, 201... oblique laminated type GAA2, 211... oblique WL1, 212... oblique WL2, 220... GAA (cross-sectional direction), 230... oblique laminated inter-gate electrode / inter-source electrode insulating film, 250... B-B" cross-sectional view of second embodiment, 251... explanation of figure of second embodiment

Claims

1. 1. A product-sum operation integrated circuit comprising: a plurality of lateral FETs having the same conductivity type in their channel portions stacked vertically at the same position on the same plane, with gate signal electrodes of the lateral FETs stacked vertically via insulating films; a product-sum operation circuit that inputs a plurality of input signals to source electrodes of the lateral FETs, uses resistance values ​​of the lateral FETs as weights, and outputs operation results to drain electrodes connected to each other of the vertically stacked lateral FETs.

2. 2. The integrated circuit for product-sum calculation according to claim 1, wherein the lateral FET is a gate-around type using four sides as a channel, and the resistance value of the lateral FET is made variable by programming the lateral FET.

3. 3. The integrated circuit for product-sum calculation according to claim 1, wherein the lateral FET uses a ferroelectric material, a ferromagnetic material, a phase change material, or the like.

4. 4. The product-sum calculation integrated circuit according to claim 1, 2 or 3, wherein the gate electrode and source electrode of the lateral FETs adjacent to each other in the direction in which the gate electrodes run run parallel to each other in both the planar and vertical directions.

5. 4. The product-sum calculation integrated circuit according to claim 1, 2 or 3, wherein the gate electrode and source electrode of the lateral FETs adjacent to each other in the direction in which the gate electrodes run run parallel to the plane and are offset by the width of one lateral FET in the vertical direction.

6. In the integrated circuit for product-sum calculation according to claims 1 to 5, the gate electrode and source electrode are formed of the same material and in the same process, and in a later process, both are replaced with different materials.

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