High-density low voltage nvm with unidirectional plate-line and bit-line and pillar capacitor

Abstract

To provide a low-power, high-density, 1T-1C (one transistor and one capacitor) memory bit-cell.SOLUTION: The capacitor has a pillar structure, which comprises ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] This application claims priority to U.S. patent application Ser. No. 16 / 287,953, filed Feb. 27, 2019, entitled "High-Density Low Voltage Non-Volatile Memory with Unidirectional Plate-Line and Bit-Line and Pillar Capacitor," which is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] Standard memories used within processors are static random access memory (SRAM) or dynamic random access memory (DRAM) and their derivatives. These memories are volatile memories. For example, they lose the data they store when power to the memory is turned off. Today, non-volatile memories are also commonly used in computing platforms to replace magnetic hard disks. Non-volatile memories retain their stored data for long periods of time (e.g., months, years, or forever) even when power to the memory is turned off. Examples of non-volatile memories are magnetic random access memory (MRAM) and NAND or NOR flash memory. These memories suffer from high write energy, low density, and high power consumption, which may make them unsuitable for low-power, small-sized computing devices.

[0003] The background discussion provided herein is intended to provide a general context for the disclosure. Unless otherwise noted herein, the material described in this section is not intended to be prior art to the claims of this application, nor is it admitted to be prior art by inclusion in this section. [Brief explanation of the drawings]

[0004] The disclosed embodiments will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which should not be construed as limiting the disclosure to particular embodiments but are merely for purposes of illustration and understanding. [Figure 1A] FIG. 1 illustrates a three-dimensional (3D) view of a 1T-1C (one planar transistor and one capacitor) memory bit cell having a pillar capacitor with a ferroelectric material and a conductive oxide as an electrode, with one of the conductive oxide electrodes wrapped around the pillar capacitor, according to some embodiments. [Figure 1B] 1B illustrates a cross-sectional view corresponding to FIG. 1A, according to some embodiments. [Figure 1C] 1 illustrates a cross-sectional view of a 1T-1C memory bitcell in which a pillar capacitor with FE material is formed between a plate line (PL) and a bit line (BL), according to some embodiments. [Figure 1D] 1 illustrates a cross-sectional view of a 1T-1C memory bitcell in which two pillar capacitors with FE material are formed between a plate line (PL) and a bit line (BL), according to some embodiments. [Figure 2] 2 illustrates a high-density layout of the 1T-1C bitcell of FIG. 1, according to some embodiments. [Figure 3A] 3A-3B show 3D views of a pillar capacitor with a sidewall barrier seal, respectively, according to some embodiments. [Figure 3B] 3A-3B show 3D views of a pillar capacitor with a sidewall barrier seal, respectively, according to some embodiments. [Figure 4A] FIG. 1 shows a 3D view of a pillar capacitor with a wrapped conductive oxide as a first electrode on top of a ferroelectric structure and a refractive intermetallic compound inside the pillar as a second electrode, according to some embodiments. [Figure 4B]FIG. 1 shows a 3D view of a pillar capacitor with a wrapped conductive oxide as a first electrode on top of a ferroelectric structure and a stack of refractive intermetallic compounds inside the pillar as a second electrode, the stack having a metal coating, according to some embodiments. [Figure 5A] FIG. 1 shows a 3D view of a 1T-1C (one finFET and one capacitor) memory bitcell having a pillar capacitor with a ferroelectric material and a conductive oxide as an electrode, with one of the conductive oxide electrodes wrapped around the pillar capacitor, according to some embodiments. [Figure 5B] 5B illustrates a cross-sectional view corresponding to FIG. 5A, according to some embodiments. [Figure 6] 5B illustrates a high density layout of the 1T-1C bitcell of FIG. 5A according to some embodiments. [Figure 7] FIG. 1 shows a 3D view of a 1T-1C (one back-end finFET and one capacitor) memory bitcell having a pillar capacitor with a ferroelectric material and a conductive oxide as electrodes, one of the conductive oxide electrodes wrapped around the pillar capacitor, according to some embodiments. [Figure 8] 1 illustrates a flowchart for forming a 1T-1C bit cell, according to some embodiments. [Figure 9] 1 illustrates a flowchart for forming a pillar capacitor of a 1T-1C bitcell, according to some embodiments. [Figure 10] 1 illustrates a memory chip having an array of 1T-1C bit cells and logic according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0005] Some embodiments describe a 1T-1C (one transistor and one capacitor) memory bitcell in which the capacitor has a pillar structure with a ferroelectric material and a conductive oxide as an electrode. In various embodiments, a layer of conductive oxide electrode wraps around the pillar capacitor to form the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

[0006] In some embodiments, the core of the pillar capacitor includes another layer of conductive oxide such that a ferroelectric (FE) material is between the outer conductive oxide layer (or electrode) and the inner conductive oxide layer (or electrode). In some embodiments, the portion of the pillar capacitor that couples to the transistor has a barrier structure formed of a refractive intermetallic material (e.g., Ti-Al, Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co). In some embodiments, the barrier layer is a superlattice of a first material and a second material, where the first material includes Ti and Al (e.g., TiAl) and the second material includes Ta, W, and Co (e.g., layers of Ta, W, and Co together). In various embodiments, the lattice parameter of the barrier layer is matched to the lattice parameter of the conductive oxide and / or the FE material. In some embodiments, the outer conductive oxide layer is partially or completely covered with a sidewall barrier seal (e.g., Ti-Al-O or MgO). In various embodiments, the lattice parameter of the sidewall barrier seal is matched to the lattice parameter of the outer conductive oxide.

[0007] The FE material can be any suitable low-voltage FE material that allows the FE material to switch its state with a low voltage (e.g., 100 mV). In some embodiments, the FE material has an ABO3-type perovskite, where "A" and "B" are two cations of different sizes, and "O" is oxygen, an anion that bonds to both cations. Generally, the size of the A atom is larger than the size of the B atom. In some embodiments, the perovskite can be doped (e.g., with La or a lanthanide). In various embodiments, when the FE material is a perovskite, the conductive oxide is of the AA'BB'O3 type. A' is a dopant for atomic site A and can be an element from the lanthanide series. B' is a dopant for atomic site B and can be an element from the transition metal elements, particularly Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, and Zn. A' can have the same valence as site A, but with a different ferroelectric polarizability.

[0008] In some embodiments, the FE material has a hexagonal ferroelectric of the h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by buckling of the layered MnO5 polyhedra, accompanied by displacement of Y ions, which leads to a net electric polarization. In some embodiments, the hexagonal FE comprises one of YMnO3 or LuFeO3. In various embodiments, when the FE material has a hexagonal ferroelectric, the conductive oxide is of the A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where 'A' is a rare earth element and B is Mn.

[0009] In some embodiments, the FE material comprises an improper FE material. An improper ferroelectric is a ferroelectric whose primary order parameter is an ordering mechanism, such as distortion or buckling of the atomic order. Examples of improper FE materials include the LuFeO3 class of materials and superlattices of ferroelectric and paraelectric materials, such as PbTiO3 (PTO) and SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively. For example, a superlattice of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100. While various embodiments herein are described with reference to ferroelectric materials for storing charge states, the embodiments are also applicable to paraelectric materials. For example, the pillar capacitors of various embodiments may be formed using paraelectric materials instead of ferroelectric materials.

[0010] There are numerous technical advantages of various embodiments. For example, memory bitcells formed using the pillar capacitors enable very low-voltage (e.g., 100 mV) switching of the FE state in the FE pillar capacitor. FE pillar capacitors can be used with any type of transistor. For example, the FE pillar capacitors of various embodiments can be used with planar or non-planar transistors. Transistors can be formed at the front end or the back end. Memory bitcells formed using the pillar capacitors result in taller and narrower bitcells compared to traditional DRAM bitcells. Thus, more bitcells can be packed onto a die, resulting in a higher-density memory that can operate at lower voltages than traditional DRAM while providing highly sought-after nonvolatile behavior. In some embodiments, the memory bitcells are formed at the front end and the back end to further increase the density of memory per die. Other technical advantages become apparent from the various embodiments and figures.

[0011] In the following description, numerous details are set forth to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. Also, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments of the present disclosure.

[0012] It should be noted that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or may have arrows at one or more ends to indicate the primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to aid in easier understanding of the circuit or logic unit. Any signal represented may actually have one or more signals that can go in either direction and may be implemented with any suitable type of signaling, as dictated by design needs or preferences.

[0013] The term "device" may generally refer to an apparatus according to the context of the use of the term. For example, a device may refer to a stack of multiple layers or structures, a single structure or layer, a connection of various structures with active and / or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x and y directions and a height along the z direction of an xyz Cartesian coordinate system. The plane of a device may also be the plane of an apparatus that includes the device.

[0014] Throughout the specification and claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things that are connected, without any intermediate devices.

[0015] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0016] The term "adjacent" as used herein generally refers to the location of one thing next to (e.g., immediately adjacent to, or nearby with one or more things between them) or in contact with (e.g., bordering) another thing.

[0017] The terms "circuit" or "module" may refer to one or more passive and / or active components configured to cooperate with each other to provide a desired function.

[0018] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0019] The term "scaling" generally refers to the transfer of a design (diagram and layout) from one process technology to another, followed by a reduction in layout area. The term "scaling" also generally refers to the miniaturization of layouts and devices within the same technology node. The term "scaling" can also refer to the adjustment (e.g., slowing down or speeding up, i.e., scaling down or scaling up, respectively) of signal frequency relative to another parameter, such as power supply level.

[0020] The terms "substantially," "close," "approximately," "approximately," and "nearly" generally refer to within ±10% of a target value. For example, unless the express context of their use dictates otherwise, the terms "substantially equal," "approximately equal," and "approximately equal" mean that there is only a casual variation between those so described. In the art, such variation is typically no more than ±10% of a given target value.

[0021] Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object merely indicates that different instances of a similar object are being referred to and is not intended to imply that the objects so described must be in a given order in time, space, rank, or in any other manner.

[0022] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0023] The terms "left," "right," "front," "rear," "top," "bottom," "up," "under," and the like, when present in the description and claims, are used for descriptive purposes and not necessarily to describe permanent relative positions. For example, the terms "above," "below," "front," "rear," "top," "bottom," "on," "below," and "above" as used herein refer to the relative position of one component, structure, or material with respect to another referenced component, structure, or material within a device, when such physical relationship is specifically noted. These terms are used herein solely for descriptive purposes and primarily in the context of the device z-axis, which may therefore be relative to the device's orientation. Thus, a first material "over" a second material in the context of the figures provided herein may also be "below" the second material if the device is flipped over relative to the context of the figures provided. In the context of materials, a material being disposed above or below another material may mean that it is in direct contact with the other material or that it has one or more intervening layers. Furthermore, a material being disposed between two materials may mean that it is in direct contact with the other material or that it has one or more intervening layers. In contrast, a first material being "on" a second material means that it is in direct contact with the second material. A similar distinction should be made in the context of component assembly.

[0024] The term "between" can be used in the context of the z-axis, x-axis, or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or may be separated from both of the other two materials by one or more intervening materials. Thus, a material "between" two other materials may be in contact with either of the other two materials, or may be coupled to the other two materials via an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or may be separated from both of the other two devices by one or more intervening devices.

[0025] Here, multiple non-silicon semiconductor material layers can be stacked within a single fin structure. The multiple non-silicon semiconductor material layers can include one or more “P-type” layers suitable for P-type transistors (e.g., providing higher hole mobility than silicon). The multiple non-silicon semiconductor material layers can further include one or more “N-type” layers suitable for N-type transistors (e.g., providing higher electron mobility than silicon). The multiple non-silicon semiconductor material layers can further include one or more intervening layers separating the N-type layer from the P-type layer. The intervening layer can be at least partially sacrificial, for example, allowing one or more of the gate, source, or drain to completely wrap around the channel region of one or more of the N-type and P-type transistors. The multiple non-silicon semiconductor material layers can be fabricated at least in part using self-aligned techniques so that a stacked CMOS device can include both high-mobility N-type and P-type transistors in the footprint of a single FET (field-effect transistor).

[0026] As used herein, the term "back end" generally refers to the section of a die where an IC (integrated circuit) package is bonded to the IC die bumps, as opposed to the "front end." For example, higher metal layers closer to the die package (e.g., metal layers 6 and above in a 10-metal stack die) and corresponding vias are considered part of the back end of the die. Conversely, the term "front end" generally refers to the section of the die that includes the active area (e.g., where transistors are fabricated) and lower metal layers and corresponding vias closer to the active area (e.g., metal layers 5 and below in the example of a 10-metal stack die).

[0027] It is noted that elements of a drawing having the same reference number (or name) as elements of any other drawing may operate or function in a manner similar to that described, although they are not limited to such.

[0028] 1A-1B show a 3D view 100 and a corresponding cross-sectional view 120, respectively, of a 1T-1C (one planar transistor and one capacitor) memory bitcell having a pillar capacitor with a ferroelectric material and a conductive oxide as electrodes, with one of the conductive oxide electrodes wrapped around the pillar capacitor, according to some embodiments. The memory bitcell of FIGS. 1A-1B includes a planar transistor having a substrate 101, a source 102, a drain 103, a channel region 104, a gate having a gate dielectric 105, gate spacers 106a, 106b, and a gate metal 107, and a source contact 108a and a drain contact 108b.

[0029] Substrate 101 comprises a suitable semiconductor material, such as, for example, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI). In one embodiment, substrate 101 comprises other semiconductor materials, such as, for example, Si, Ge, SiGe, or suitable III-V or III-N compounds. Substrate 101 may also comprise semiconductor materials, metals, dopants, and other materials commonly found in semiconductor substrates.

[0030] In some embodiments, source and drain regions 102, 103 are formed adjacent to the transistor gate stack in the substrate 101. The source and drain regions 102, 103 are typically formed using either an etching / deposition process or an implantation / diffusion process.

[0031] In an etching / deposition process, the substrate 101 may first be etched to form recesses at the locations of the source and drain regions 102 and 103. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the source and drain regions 102 and 103. In an implantation / diffusion process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the substrate to form the source and drain regions 102 and 103. The ion-implantation process is typically followed by an annealing process to activate the dopants and further diffuse them into the substrate 101.

[0032] In some embodiments, one or more layers of a metal and / or metal alloy are used to form the source region 102 and the drain region 103. In some embodiments, the source region 102 and the drain region 103 are formed using one or more alternative semiconductor materials, such as germanium or a suitable III-V compound. In some embodiments, the source region 102 and the drain region 103 are fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy is in situ doped with a dopant, such as boron, arsenic, or phosphorus.

[0033] The semiconductor material for the channel region 104, according to some embodiments, may comprise the same material as the substrate 101. In some embodiments, the channel region 104 comprises one of Si, SiGe, Ge, and GaAs.

[0034] The gate dielectric layer 105 can include one layer or a stack of multiple layers. One or more of the layers can include a high-k dielectric material, silicon oxide, and / or silicon dioxide (SiO2). The high-k dielectric material can include elements such as zinc, niobium, scandium, low-content yttrium, hafnium, silicon, strontium, oxygen, barium, titanium, zirconium, tantalum, aluminum, and lanthanum. Examples of high-k materials that can be used for the gate dielectric layer include lead zinc niobate, hafnium oxide, lead scandium tantalum oxide, hafnium silicon oxide, yttrium oxide, aluminum oxide, lanthanum oxide, barium strontium titanium oxide, lanthanum aluminum oxide, titanium oxide, zirconium oxide, tantalum oxide, and zirconium silicon oxide. In some embodiments, if a high-k material is used, an annealing process is used on the gate dielectric layer 105 to improve its quality.

[0035] In some embodiments, a pair of spacer layers (sidewall spacers) 106 a / b are formed on both side surfaces of the gate stack, sandwiching the gate stack. The pair of spacer layers 106 a / b are formed of a material such as silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or silicon carbide. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching processes. In some embodiments, multiple spacer pairs may be used. For example, two, three, or four pairs of sidewall spacers may be formed on both side surfaces of the gate stack.

[0036] The gate metal layer 107 may comprise at least one P-type or N-type work function metal, depending on whether the transistor is a p-type or n-type transistor. The gate metal layer 107 may also comprise a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer.

[0037] For n-type transistors, metals that can be used for gate metal layer 107 include aluminum carbide, tantalum carbide, zirconium carbide, and hafnium carbide. In some embodiments, metals for gate metal layer 107 of n-type transistors include aluminum, hafnium, zirconium, titanium, tantalum, and alloys thereof. The n-type metal layer will enable the formation of an n-type gate metal layer 207 with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the metal of layer 107 includes one of TiN, TiSiN, TaN, Cu, Al, Au, W, TiSiN, or Co. In some embodiments, the metal of layer 107 includes one or more of Ti, N, Si, Ta, Cu, Al, Au, W, or Co.

[0038] For p-type transistors, metals used for the gate metal layer 107 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides. An example of a conductive oxide includes ruthenium oxide. The p-type metal layer will allow for the formation of a p-type gate metal layer 107 with a work function between about 4.9 eV and about 5.2 eV.

[0039] The drain contact 108b is coupled to a via 109b, which is coupled to a metal layer 110. The metal layer 110 is a bit line and extends along the x-axis. The source contact 108a is coupled to a refractive inter-metallic 111a through a via 109a. A conductive oxide 112c is coupled to the refractive inter-metallic 111b. Any suitable material can be used for the drain and source contacts 108a / b and the vias 109a / b. For example, one or more of Ti, N, Si, Ta, Cu, Al, Au, W, or Co can be used for the drain and source contacts 108a / b and the vias 109a / b.

[0040] The refractive intermetallic compounds 111 a / b are conductive materials that maintain the FE characteristics of the pillar capacitor. Without the refractive intermetallic compounds 111, the ferroelectric or paraelectric materials of the pillar capacitor may lose their effectiveness. In some embodiments, the refractive intermetallic compounds 111 a / b include Ti and Al (e.g., TiAl compounds). In some embodiments, the refractive intermetallic compounds 111 a / b include one or more of Ta, W, and / or Co. For example, the refractive intermetallic compounds 111 a / b include lattices of Ta, W, and Co. In some embodiments, the refractive intermetallic compounds 111 a / b include one of Ti—Al, such as TiAl, TiAl, or TiAl; Ni—Al, such as NiAl, NiAl, or NiAl; Ni—Ti; Ni—Ga; NiMnGa; FeGa; FeGa; a boride; a carbide; or a nitride. In some embodiments, the TiAl material has a composition of Ti-(45-48)Al-(1-10)M (@X trace%), where M is at least one element from V, Cr, Mn, Nb, Ta, W, and Mo, with trace amounts of 0.1-5% Si, B, and / or Mg. In some embodiments, the TiAl is a single-phase alloy γ(TiAl). In some embodiments, the TiAl is a dual-phase alloy γ(TiAl)+α2(TiAl). Single-phase γ alloys contain a third alloying element, such as Nb or Ta, which promotes strengthening and further enhances oxidation resistance. The role of the third alloying element in dual-phase alloys is to enhance ductility (V, Cr, Mn), oxidation resistance (Nb, Ta), or composite properties. Additions such as Si, B, and Mg can significantly enhance other properties. In some embodiments, the refractive intermetallic compounds 111a / b include one or more of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co.

[0041] In various embodiments, a pillar capacitor is adjacent to the refractive intermetallic compound 111 a / b. The pillar capacitor includes a first conductive oxide 112 having sections 112 a, 112 b, and 112 c, an FE or paraelectric (PE) material 113, and a second conductive oxide 114 between the FE material 113. The top section (e.g., 112 c) of the conductive oxide is coupled to a plate line or pulse line 115 through the intermetallic compound 111 b. In some embodiments, there is a barrier layer (not shown), such as a refractive intermetallic compound layer, between the conductive oxide 112 c and the PL 115.

[0042] Sections 112a and 112b are parallel to each other, and section 112c is perpendicular to sections 112a and 112b. In various embodiments, a plate line or pulse line (PL) extends parallel to BL 110 along the x-direction. Having the BL and PL parallel to each other further improves memory density by reducing the footprint of the memory bit cell compared to when the BL and PL are perpendicular to each other. Gate metal 107 is coupled to gate contact 116, which is coupled to metal line 117. Metal line 117 is used as a word line (WL) and extends perpendicular to BL 110 and PL 115. Any suitable metal can be used for BL 110, PL 115, and WL 117. For example, Al, Cu, Co, Au, or Ag can be used for BL 110, PL 115, and WL 117.

[0043] In some embodiments, the FE material 113 is a perovskite, which includes one or more of La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, and Ni. For example, metal perovskites such as (La,Sr)CoO3, SrRuO3, (La,Sr)MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, and LaNiO3 can be used for the FE material 113. The perovskite can be appropriately doped to achieve a spontaneous strain in the range of 0.3-2%. For example, in chemically substituted lead titanates, such as Zr at the Ti site and La or Nb at the Ti site, the concentrations of these substituents are adjusted to achieve a spontaneous strain in the range of 0.3-2%. In chemically substituted materials such as BiFeO3, BrCrO3, and BuCoO3, the spontaneous strain can be adjusted by substituting La or rare earth elements into the Bi site.

[0044] In various embodiments, when a metal perovskite is used for the FE material 113a / b, the conductive oxides 112 and 114 can include one or more of IrO, RuO, PdO, OsO, or ReO. In some embodiments, the perovskite is doped with La or a lanthanide. In some embodiments, a thin layer (e.g., approximately 10 nm) of a perovskite template conductor, such as SrRuO coated on IrO, RuO, PdO, or PtO, with a non-perovskite structure but higher conductivity, is used as the conductive oxide 112 and 114 to provide a seed or template for the growth of pure perovskite ferroelectrics at low temperatures.

[0045] In some embodiments, the FE material 113 comprises an AMnO3-type hexagonal ferroelectric, where A is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y). The ferroelectric phase is characterized by buckling of layered MnO5 polyhedra, accompanied by displacement of Y ions, which leads to a net electric polarization. In some embodiments, the hexagonal FE comprises one of YMnO3 or LuFeO3. In various embodiments, when the FE material comprises a hexagonal ferroelectric, the conductive oxide is of the A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where 'A' is a rare earth element and B is Mn. Examples of hexagonal metals used as the conductive oxides 112 and 114 include one or more of PtCoO2, PdCoO2, and other delafossite-structured hexagonal metal oxides, such as Al-doped ZnO.

[0046] In some embodiments, the FE material 113 comprises an improper FE material. Examples of improper FE materials include the LuFeO3 class of materials and superlattices of ferroelectric and paraelectric materials, such as PbTiO3 (PTO) and SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively. For example, a [PTO / STO]n or [LAO / STO]n superlattice, where 'n' is between 1 and 100. In some embodiments, the conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re. Other examples of conductive oxides include spinels, such as Fe3O4 and LiVO4, and cubic metal oxides, such as ITO (indium tin oxide) and Sn-doped In2O3.

[0047] Although various embodiments herein are described with reference to ferroelectric materials for storing charge states, the embodiments are also applicable to paraelectric materials. For example, the pillar capacitors of various embodiments may be formed using paraelectric materials instead of ferroelectric materials. In various embodiments, the conductive oxide and intermetallic materials in the pillar capacitor are on either side of the ferroelectric material.

[0048] 1C shows a cross-sectional view 130 of a 1T-1C memory bitcell in which a pillar capacitor having an FE material is formed between the PL and BL, according to some embodiments. By forming the pillar capacitor above the BL, the metal layer space between the BL 110 and the PL 115 can be freely and effectively used to achieve a wide range of capacitance values ​​for the pillar capacitor. This configuration for positioning the pillar capacitor allows the pitch of the 1T-1C bitcell to be substantially the pitch of the transistor MN. Therefore, high-density memory is achieved.

[0049] 1D shows a cross-sectional view 140 of a 1T-1C memory bit cell in which two pillar capacitors with FE material are formed between PL 115 and BL 110, according to some embodiments. Here, two pillar capacitors are formed with FE material 113a and 113b separated by conductive oxide section 112d. 112 is in the range of 10 nm-150 nm. The two pillar capacitors share the same barrier layer 111 a / b and the same conductive oxide section 112 c, according to various embodiments. Although two pillar capacitors are shown, three or more pillar capacitors may be formed in the space between BL 110 and PL 115. This configuration of pillar capacitors also allows the pitch of the 1T-1C bitcell to be substantially the pitch of the transistor MN. Thus, high density memory is achieved with higher capacitance.

[0050] 2 illustrates a high-density layout 200 of the 1T-1C bit cell of FIG. 1 according to some embodiments. The pitch of the bit cell layout is approximately the pitch of the transistor regions, where pitch refers to the x and y dimensions of the bit cell. This small pitch allows a large number of bit cells to be packed into an array, leading to a high-density memory array.

[0051] Although the capacitance pillars of various embodiments are shown as rectangular structures, they can have other shapes, for example, the capacitance pillars of various embodiments can have a cylindrical shape with dimensions similar to those described with reference to the rectangular capacitance pillars.

[0052] 3A-3B show 3D views of pillar capacitors 300 and 320, respectively, with sidewall barrier seals, according to some embodiments. The embodiments of FIGS. 3A-3B can be used in any of the embodiments described herein. Capacitor 300 is similar to the capacitor of FIG. 1A, except that a sidewall barrier (insulating or insulating) seal 301 is applied to output conductive oxide layer 112. In this case, sidewall barrier seal 301 is applied to two sections 112a and 112b, as sections 301a and 301b, respectively. In pillar capacitor 300, sidewall barrier seals 301a and 301b extend along the z-axis to cover the sidewalls of barrier structures 111a / b. In some embodiments, top section 112c is also sealed with sidewall barrier seal 301. In some embodiments, sidewall barrier seal 301 includes one or more of Ti, Al, O, or Mg. For example, TiAlO3, MgO, or TiO2 can be used as the sidewall barrier seal. The sidewall barrier seal 301 protects the capacitor material from the diffusion of elements into it. The sidewall barrier seal 301 is a material with low electrical conductivity and has low capacitance.

[0053] In some embodiments, the thickness t of the barrier structure (for 111a / b) 111is in the range of 0.5 nm (nanometers) to 10 nm. In some embodiments, the thickness of the conductive oxide, t 112 is in the range of 0.5 nm to 20 nm. In some embodiments, the thickness t of the FE material 113 is in the range of 0.5 nm to 100 nm. In some embodiments, the thickness of the sidewall barrier, t 301 In some embodiments, the pillar height h pillar is in the range of 50 nm to 5000 nm.

[0054] Capacitor 320 is similar to capacitor 300, except for the application of sidewall barrier seal 301. Here, the sidewall barrier is labeled as 321, but has the same material as described with reference to 301. In some embodiments, this sidewall barrier extends along all sides of output conductive oxide 112a / b / c as 321a / b / c. In this example, sidewall barrier seals 321a and 321b do not extend to barriers 111a / b. In some embodiments, a thickness t 321 is the thickness t 301 is the same as

[0055] In various embodiments, the lattice parameter of the barrier layers 111 a / b is matched to the lattice parameter of the conductive oxide and / or FE material. In some embodiments, the outer conductive oxide layer 112 is partially or completely covered with a sidewall barrier seal (e.g., Ti—Al—O or MgO). In various embodiments, the lattice parameter of the sidewall barrier seal is matched to the lattice parameter of the outer conductive oxide.

[0056] 4A shows a 3D view of a pillar capacitor 400 having a wrapped conductive oxide as a first electrode on top of a ferroelectric structure and a refractive intermetallic inside the pillar as a second electrode, according to some embodiments. In some embodiments, the central or core conductive oxide layer 114 is replaced with a stack of refractive intermetallics, such as Ti and Al. In some embodiments, the stack of refractive intermetallics includes layers 401 and 402. In some embodiments, layers 401 and 402 include TiAl. Other materials include TiAl, TiAl, NiAl, NiAl, NiAl, Ni-Ti, Ni-Ga, NiMnGa, FeGa, FeGa, borides, carbides, and nitrides. In some embodiments, the materials of layers 401 and 402 are different materials. In some embodiments, the materials of layers 401 and 402 are the same material. The refractive intermetallic stack is surrounded on three sides by FE material sections 413a, 413b, and 413c (same as material 113). The composition of the FE material is according to any of the FE materials described herein. In various embodiments, the conductive oxide 112a / b extends along the y-axis to be adjacent to the barrier structure 111a. The barrier structure 111a is also adjacent to the FE material sections 413a, 413b and one of the layers 401 or 402. In some embodiments, the sidewall barrier seal 301 of FIGS. 3A-3B can also be used for the pillar capacitor 400. In some embodiments, the stack length L stack In some embodiments, the thickness t of layer 401 ranges from 5 nm to 200 nm. 401 In some embodiments, the thickness t of layer 402 is in the range of 10 nm to 60 nm. 402 is in the range of 10 nm to 60 nm.

[0057] FIG. 4B shows a 3D view of a pillar capacitor 420 having a wrapped conductive oxide as a first electrode on top of a ferroelectric structure and a refractive intermetallic compound inside the pillar as a second electrode, the refractive intermetallic compound having a metal coating, according to some embodiments. In some embodiments, the central or core conductive oxide layer 114 is replaced with a stack of materials 421 and 422, where 421 is a metal such as Cu, Co, Ru, Ta, or W (or a combination thereof), and 422 is a via layer formed of one or more of Cu, Co, Ru, Ta, W, TaN, WN, or a combination thereof. In some embodiments, the stack of materials of layers 421 and 422 is covered by metal coatings 411a, 411b, and 411c. In some embodiments, the sidewall barrier seal 301 of FIGS. 3A-3B can also be used for the pillar capacitor 420. In some embodiments, the length L of the stack is stack In some embodiments, the thickness t of layer 421 ranges from 5 nm to 200 nm. 421 In some embodiments, the thickness t of layer 422 is in the range of 10 nm to 60 nm. 422 is in the range of 10 nm to 60 nm. The embodiment of Figures 4A-4B can be used with any of the embodiments described herein.

[0058] 5A-5B show a 3D view 500 and a corresponding cross-sectional view 520, respectively, of a 1T-1C (one finFET and one capacitor) memory bitcell having a pillar capacitor with a ferroelectric material and a conductive oxide as electrodes, with one of the conductive oxide electrodes wrapped around the pillar capacitor, according to some embodiments. The memory bitcell of FIG. 5A is similar to the memory bitcell of FIG. 1A, except for the non-planar transistor. A finFET is an example of a non-planar transistor. A finFET has a fin that includes a source region 502 and a drain region 503. A channel is located between the source region 502 and the drain region 503. A transistor MN can have multiple parallel fins coupled to the same gate stack. The fins penetrate the gate stack and form the source region 502 and the drain region 503.

[0059] Figure 6 shows a high-density layout 600 of the 1T-1C bit cell of Figure 5A, according to some embodiments. Like the pitch of the memory bit cell of Figure 2, the pitch of the bit cell layout here is approximately the pitch of the transistor regions. Here, pitch refers to the x and y dimensions of the bit cell. This small pitch allows a large number of bit cells to be packed into an array, leading to a high-density memory array.

[0060] 7 shows a 3D diagram 700 of a 1T-1C (one back-end finFET and one capacitor) memory bitcell having a pillar capacitor with a ferroelectric material and a conductive oxide as an electrode, with one of the conductive oxide electrodes wrapped around the pillar capacitor, according to some embodiments. In this embodiment, the transistor can be a back-end transistor. Although a finFET is shown, any back-end transistor that can be coupled to a capacitor pillar can be used.

[0061] FIG. 8 illustrates a flowchart 800 for forming a 1T-1C bit cell, according to some embodiments. While the blocks of flowchart 800 are shown in a particular order, this order is not critical. For example, some blocks or processes may be performed before others, and some may be performed in parallel. In block 801, a transistor MN is formed having a source, a drain, and a gate. The transistor may be planar or non-planar. In block 802, a word line 117 is coupled to the gate electrode 107 via a contact 117. In block 803, a bit line 110 is formed extending in a first direction (e.g., the x-axis). The bit line 110 is coupled to the source or drain of the transistor MN via a via 109. The bit line 110 extends perpendicular to the word line 117. In block 804, a pulse line or plate line (PL) 115 is formed extending along the first direction. The PL 115 is coupled to the source or drain of the transistor MN. At block 805, a pillar capacitor structure (eg, FIGS. 1A, 3-4) is formed adjacent to the source or drain region and coupled to PL 115.

[0062] FIG. 9 illustrates a flowchart 900 for forming a pillar capacitor for a 1T-1C bitcell, according to some embodiments. While the blocks of flowchart 900 are shown in a particular order, this order is not critical. For example, some blocks or processes may be performed before others, and some may be performed in parallel. At block 901, a first structure having a first refractive intermetallic compound (e.g., 111) is formed. The first structure is adjacent to a source or drain region of transistor MN. At block 902, a second structure having a first conductive oxide 112 is formed. The second structure has a first section 112a, a second section 112b, and a third section 112c. The first section 112a extends in a second direction (e.g., along the z-axis) that is orthogonal to the first direction (e.g., along the x-axis), and the second section 112b is parallel to the first section 112a. The third section 112c is adjacent to the first and second sections such that the third section extends in a first direction (e.g., along the x-axis), and a portion of the first section and a portion of the second section are adjacent to the first structure 111a. The section 112c is formed adjacent to the intermetallic compound 111b.

[0063] At block 903, a third structure 113 is formed having a ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric). The third structure has first, second, and third sections (113 sections along the z-axis and x-axis), where the first section is adjacent to the first section (112a) of the second structure, the second section is adjacent to the second section (112b) of the second structure, and the third section is adjacent to the third section (112c) of the second structure, and the first and second sections of the third structure are parallel to each other and extend along the second direction.

[0064] At block 904, the method includes forming a fourth structure having a second conductive oxide, the fourth structure being between the first section and the second section of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0065] At block 904, the method includes forming a fourth structure having a second conductive oxide 114. The second conductive oxide is between the first section 113 and the second section 113 of the third structure. Although flowchart 900 is shown with respect to forming the capacitive pillar structures of Figures 1A-1D, the same process can be used to form the capacitive pillar structures of Figures 3-4.

[0066] 10 illustrates a memory chip 1000 having an array of 1T-1C bit cells and logic, according to some embodiments. The chip 1000 includes a memory module 1001 having a non-volatile ferroelectric DRAM (FE-DRAM) array 1002, which includes bit cells such as those described with reference to various embodiments herein. The memory module 1001 also includes CMOS logic 1003, such as decoders, multiplexers, and drivers for driving the BL, WL, and PL. The memory module 1001 also includes an input-output (IO) interface 804 used to communicate with another device, such as an artificial intelligence (AI) processor 1005 (e.g., a dedicated AI processor, a graphics processor configured as an AI processor, etc.).

[0067] References in the specification to "one embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least some of the embodiments, but not necessarily all of the embodiments. The various appearances of "one embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiments. When the specification states that a component, feature, structure, or characteristic "may," "might," or "can" be included, this does not require the inclusion of that particular component, feature, structure, or characteristic. When the specification or claims refer to "a" or "an" element, this does not mean that there is only one of that element. When the specification or claims refer to "an additional" element, this does not preclude there being more than one of that additional element.

[0068] Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0069] While the present disclosure has been described in terms of specific embodiments thereof, numerous alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. It is intended that the embodiments of the present disclosure embrace all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0070] Additionally, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings for simplicity of illustration and description and so as not to obscure the disclosure. Furthermore, configurations may be shown in block diagram form in order to avoid obscuring the disclosure and in recognition of the fact that the details regarding the implementation of such block diagram configurations are highly dependent on the platform on which the disclosure will be implemented (i.e., such details should be within the purview of those skilled in the art). Where specific details (e.g., circuits) are described to explain example embodiments of the disclosure, it will be apparent to those skilled in the art that the disclosure may be practiced without those specific details or with variations thereof. This description is therefore to be considered illustrative and not limiting.

[0071] The following examples are provided to illustrate various embodiments. These examples can be combined with other examples. Thus, various embodiments can be combined with other embodiments without changing the scope of the invention.

[0072] Example 1: A transistor having a source, a drain, and a gate, a word line coupled to the gate, a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor, a plate line extending in the first direction, and a capacitive structure adjacent to the one of the source or the drain of the transistor and the plate line, a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction perpendicular to the first direction, the second section being parallel to the first section, and the third section intersecting the first cell such that the third section extends in the first direction. a second structure adjacent to the first section and the second section, with a portion of the first section and a portion of the second section adjacent to the first structure; a third structure comprising a perovskite, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a fourth structure comprising a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0073] Example 2: The device of Example 1, wherein the capacitive structure includes a fifth structure adjacent to a side of the first section of the second structure and a sixth layer adjacent to a side of the second section of the second structure, and the sixth structure and the seventh structure include insulating material.

[0074] Example 3: The device of Example 2, wherein the insulating material comprises one or more of an oxide of Ti, Al, or Mg.

[0075] Example 4: The device of example 2, wherein the transistor is one of a planar transistor or a non-planar transistor.

[0076] Example 5: The device of example 2, wherein the perovskite is doped with La or a lanthanide.

[0077] Example 6: The device of Example 2, wherein the refractive intermetallic compound is a conductive material comprising one or more of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co.

[0078] Example 7: The device of example 2, wherein the transistor is located at a back end of a die; or the transistor is located at a front end of a die.

[0079] Example 8: The device of Example 1, wherein the first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re.

[0080] Example 9: The device of Example 1, wherein the perovskite comprises one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.

[0081] Example 10: The device of example 1, wherein the perovskite comprises one of La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.

[0082] Example 11: The device of example 1, wherein the capacitive structure is cylindrical in shape.

[0083] Example 12: The device of example 1, wherein the perovskite is doped with Sc or Mn to control leakage through the third structure.

[0084] Example 13: A method of forming a memory bit cell, the method comprising: forming a transistor having a source, a drain, and a gate; forming a word line coupled to the gate; forming a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor; forming a plate line extending in the first direction; and forming a capacitive structure adjacent to one of the source or the drain of the transistor, the first structure having a refractive intermetallic compound adjacent to the source or the drain of the transistor; and a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, and the third section extending in the first direction. forming a second structure adjacent to the first section and the second section such that a portion of the first section and a portion of the second section are adjacent to the first structure; forming a third structure comprising a perovskite, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and forming a fourth structure comprising a second conductive oxide, the fourth structure being between the first and second sections of the third structure, and a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0085] Example 14: The method of Example 13, wherein forming the capacitive structure includes forming a fifth structure adjacent to a side of the first section of the second structure, and forming a sixth layer adjacent to a side of the second section of the second structure, wherein the sixth structure and the seventh structure have a barrier material.

[0086] Example 15: The method of Example 14, wherein the barrier material comprises one or more of an oxide of Ti, Al, or Mg, the transistor is one of a planar transistor or a non-planar transistor, the perovskite is doped with La or a lanthanide, the refractive intermetallic compound comprises one or more of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co, and the transistor is located at a back end of a die, or the transistor is located at a front end of a die.

[0087] Example 16: The method of any one of Examples 13 to 19, wherein the first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re.

[0088] Example 17: The method of Example 13, wherein the perovskite comprises one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.

[0089] Example 18: The method of example 13, wherein the perovskite comprises one of La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.

[0090] Example 19: The method of example 13, wherein the capacitive structure is cylindrical in shape.

[0091] Example 20: The method of example 13, wherein the perovskite is doped with Sc or Mn to control leakage through the third structure.

[0092] Example 21: An artificial intelligence (AI) processor and a nonvolatile memory coupled to the AI ​​processor, the nonvolatile memory including a plurality of bit cells, one of the bit cells including a transistor having a source, a drain, and a gate, a word line coupled to the gate, a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor, a plate line extending in the first direction, a capacitive structure adjacent to one of the source or the drain of the transistor, a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, and the third section being parallel to the first section. a second structure adjacent to the first section and the second section such that the third section extends in the first direction, with a portion of the first section and a portion of the second section adjacent to the first structure; a third structure having a perovskite, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a capacitive structure having a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0093] Example 22: The system of Example 21, wherein the capacitive structure has a fifth structure adjacent to a side of the first section of the second structure and a sixth layer adjacent to a side of the second section of the second structure, and the sixth structure and the seventh structure have insulating material.

[0094] Example 23: The system of Example 22, wherein the insulating material comprises one or more of an oxide of Ti, Al, or Mg, the transistor is one of a planar transistor or a non-planar transistor, the perovskite is doped with La or a lanthanide, the refractive intermetallic compound comprises one or more of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co, and the transistor is located at a back end of a die, or the transistor is located at a front end of a die.

[0095] Example 24: A transistor having a source, a drain, and a gate, a word line coupled to the gate, a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor, a plate line extending in the first direction, and a capacitive structure adjacent to one of the source or the drain of the transistor, the first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction perpendicular to the first direction, the second section being parallel to the first section, and the third section intersecting the first and second sections such that the third section extends in the first direction. a second structure adjacent to the first section and the second section, with a portion of the first section and a portion of the second section adjacent to the first structure; a third structure having a hexagonal ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0096] Example 25: The device of Example 24, wherein the capacitive structure has a fifth structure adjacent to a side of the first section of the second structure and a sixth layer adjacent to a side of the second section of the second structure, and the sixth structure and the seventh structure have an insulating barrier material.

[0097] Example 26: The device of Example 25, wherein the insulating barrier material comprises one or more of an oxide of Ti, Al, Hf, or Mg.

[0098] Example 27: The device of example 25, wherein the transistor is one of a planar transistor or a non-planar transistor.

[0099] Example 28: The device of example 25, wherein the refractive conductive intermetallic compound comprises one or more of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co.

[0100] Example 29: The device of example 25, wherein the transistor is located at a back end of a die; or the transistor is located at a front end of a die.

[0101] Example 30: The device of Example 24, wherein the first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re.

[0102] Example 31: The device of Example 24, wherein the first conductive oxide or the second conductive oxide comprises In2O3, Fe2O3, Fe3O4, PtCoO3, PdCoO2, Al-doped ZnO, or Sn-doped In2O3.

[0103] Example 32: The device of example 24, wherein the capacitive structure is cylindrical in shape.

[0104] Example 33: The device of example 24, wherein the hexagonal ferroelectric material comprises one of YMnO3 or LuFeO3.

[0105] Example 34: The device of example 24, wherein the hexagonal ferroelectric is of h-RMnO3 type, where R is a rare earth element comprising one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y).

[0106] Example 35: A method of forming a differential ferroelectric memory, the method comprising: forming a transistor having a source, a drain, and a gate; forming a word line coupled to the gate; forming a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor; forming a plate line extending in the first direction; and forming a capacitive structure adjacent to one of the source or the drain of the transistor, the first structure having a refractive intermetallic compound adjacent to the source or the drain of the transistor; and a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, the third section extending in the first direction. forming a second structure adjacent to the first section and the second section such that the first section is adjacent to the second section, with a portion of the first section and a portion of the second section adjacent to the first structure; forming a third structure having a hexagonal ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and forming a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0107] Example 36: The method of Example 35, wherein the capacitive structure has a fifth structure adjacent to a side of the first section of the second structure and a sixth layer adjacent to a side of the second section of the second structure, and the sixth structure and the seventh structure have a barrier material.

[0108] Example 37: The method of Example 36, wherein the barrier material comprises one or more of an oxide of Ti, Al, or Mg.

[0109] Example 38: The method of Example 36, wherein forming the transistor comprises forming one of a planar transistor or a non-planar transistor.

[0110] Example 39: The method of example 36, wherein the refractive intermetallic compound comprises one or more of Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co.

[0111] Example 40: The method of Example 36, wherein forming the transistor comprises locating the transistor at a back end of a die, or wherein forming the transistor comprises locating the transistor at a front end of a die.

[0112] Example 41: The method of Example 36, wherein the first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re.

[0113] Example 42: The method of Example 36, wherein the first conductive oxide or the second conductive oxide comprises In2O3, Fe2O3, Fe3O4, PtCoO3, PdCoO2, Al-doped ZnO, or Sn-doped In2O3.

[0114] Example 43: The method of example 36, wherein the capacitive structure is cylindrical in shape.

[0115] Example 44: The method of example 36, wherein the hexagonal ferroelectric material comprises one of YMnO3 or LuFeO3.

[0116] Example 45: The method of example 36, wherein the hexagonal ferroelectric is of h-RMnO3 type, wherein R is a rare earth element comprising one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y).

[0117] Example 46: An artificial intelligence (AI) processor and a nonvolatile memory coupled to the AI ​​processor, the nonvolatile memory including a plurality of bit cells, one of the bit cells including a transistor having a source, a drain, and a gate, a word line coupled to the gate, a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor, a plate line extending in the first direction, a capacitive structure adjacent to one of the source or the drain of the transistor, a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, and the third section extending in the third direction. a second structure adjacent to the first section and the second section such that the sections extend in the first direction, with a portion of the first section and a portion of the second section adjacent to the first structure; a third structure having a hexagonal ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a capacitive structure having a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0118] Example 47: The system of Example 46, wherein the hexagonal ferroelectric material comprises one of YMnO3 or LuFeO3.

[0119] Example 48: The system of example 46, wherein the hexagonal ferroelectric is of h-RMnO3 type, wherein R is a rare earth element comprising one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y).

[0120] Example 49: A transistor having a source, a drain, and a gate, a word line coupled to the gate, a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor, a plate line extending in the first direction, and a capacitive structure adjacent to one of the source or the drain of the transistor, a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction perpendicular to the first direction, the second section being parallel to the first section, and the third section intersecting the first section and the third section such that the third section extends in the first direction. a second structure adjacent to the second section, with a portion of the first section and a portion of the second section adjacent to the first structure; a third structure having an improper ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0121] Example 50: The device of Example 49, wherein the capacitive structure has a fifth structure adjacent to a side of the first section of the second structure and a sixth layer adjacent to a side of the second section of the second structure, and the sixth structure and the seventh structure have a barrier material.

[0122] Example 51: The device of Example 50, wherein the barrier material comprises one or more of an oxide of Ti, Al, or Mg.

[0123] Example 52: The device of example 50, wherein the transistor is one of a planar transistor or a non-planar transistor.

[0124] Example 53: The device of example 50, wherein the refractive intermetallic compound comprises one or more of Ti, Al, Ta, W, or Co.

[0125] Example 54: The device of example 50, wherein the transistor is located at a back end of a die; or the transistor is located at a front end of a die.

[0126] Example 55: The device of Example 49, wherein the first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re.

[0127] Example 56: The device of example 49, wherein the capacitive structure is cylindrical in shape.

[0128] Example 57: The device of example 49, wherein the improper ferroelectric comprises one of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100.

[0129] Example 58: A method of forming a ferroelectric memory, the method comprising: forming a transistor having a source, a drain, and a gate; forming a word line coupled to the gate; forming a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor; forming a plate line extending in the first direction; and forming a capacitive structure adjacent to one of the source or the drain of the transistor, the first structure having a refractive intermetallic compound adjacent to the source or the drain of the transistor; and a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, and the third section extending in the first direction. forming a second structure adjacent to the first section and the second section, with a portion of the first section and a portion of the second section adjacent to the first structure; forming a third structure having an improper ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and forming a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0130] Example 59: The method of Example 58, wherein forming the capacitive structure includes forming a fifth structure adjacent to a side of the first section of the second structure, and forming a sixth layer adjacent to a side of the second section of the second structure, wherein the sixth structure and the seventh structure have a barrier material.

[0131] Example 60: The method of example 59, wherein the barrier material comprises one or more of an oxide of Ti, Al, or Mg.

[0132] Example 61: The method of Example 59, wherein forming the transistor comprises forming one of a planar transistor or a non-planar transistor.

[0133] Example 62: The method of example 59, wherein the refractive intermetallic compound comprises one or more of Ti, Al, Ta, W, or Co.

[0134] Example 63: The method of Example 59, wherein forming the transistor comprises locating the transistor at a back end of a die, or forming the transistor comprises locating the transistor at a front end of a die.

[0135] Example 64: The method of Example 59, wherein the first conductive oxide or the second conductive oxide comprises an oxide of one or more of Ir, Ru, Pd, Ps, or Re.

[0136] Example 65: The method of example 59, wherein the capacitive structure is cylindrical in shape.

[0137] Example 66: The method of example 59, wherein the improper ferroelectric comprises one of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100.

[0138] Example 67: An artificial intelligence (AI) processor and a nonvolatile memory coupled to the AI ​​processor, the nonvolatile memory including a plurality of bit cells, one of the bit cells including a transistor having a source, a drain, and a gate, a word line coupled to the gate, a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor, a plate line extending in the first direction, a capacitive structure adjacent to one of the source or the drain of the transistor, a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, and the third section being parallel to the third section. a second structure adjacent to the first section and the second section such that sections extend in the first direction, with a portion of the first section and a portion of the second section adjacent to the first structure; a third structure having an improper ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, with a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0139] Example 68: The system of Example 67, wherein the improper ferroelectric comprises one of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100.

[0140] Example 69: A first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor; and a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction perpendicular to the first direction, the second section being parallel to the first section, the third section adjacent to the first section and the second section such that the third section extends in the first direction, and a portion of the first section and A capacitive structure comprising: a second structure, a portion of the second section adjacent to the first structure; and a third structure having a ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction.

[0141] Example 70: The capacitive structure of Example 69, having a fourth structure having a second conductive oxide, the fourth structure being between the first section and the second section of the third structure, and a portion of the fourth structure being adjacent to a portion of the third section of the third structure.

[0142] Example 71: The capacitor structure of Example 69, having a fourth structure, the fourth structure being a stack of a layer of a first material and a layer of a second material, the first material including one of Cu, Co, Ru, Ta, or W, and the second material including one of Cu, Co, Ru, Ta, W, TaN, or WN, and a layer surrounding three sections of the stack, the layer including Ti and Al, the fourth structure being between the first section and the second section of the third structure.

[0143] Example 72: The capacitance structure of Example 69, wherein the refractive structure is a first refractive structure, and the capacitance structure has a fifth structure having a second refractive intermetallic compound, the fifth structure being adjacent to the plate line and adjacent to the fourth structure.

[0144] Example 73: The capacitive structure of Example 69, comprising a sixth structure adjacent to a side of the first section of the second structure and a seventh layer adjacent to a side of the second section of the second structure, wherein the sixth structure and the seventh structure comprise a barrier material.

[0145] Example 74: The capacitor structure of Example 73, wherein the ferroelectric material is one of a perovskite, a hexagonal ferroelectric, or an improper ferroelectric.

[0146] Example 75: The ferroelectric material comprises one of the following: the perovskite comprises one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3, the hexagonal ferroelectric comprises one of YMnO3 or LuFeO3, or the hexagonal ferroelectric is of the h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium (E 75. The capacitor structure of Example 74, wherein the improper ferroelectric material is selected from the group consisting of [PTO / STO]n, [LAO ...

[0147] Example 76: The capacitive structure of Example 74, wherein the barrier material comprises one or more of an oxide of Ti, Al, or Mg.

[0148] Example 77: The capacitive structure of Example 74, wherein the first or second refractive material comprises one or more of Ti, Al, Ta, W, or Co.

[0149] Example 78: The capacitor structure of Example 74, wherein the first and second conductive oxides comprise an oxide of one of: Ir, Ru, Pd, Ps, or Re when the ferroelectric material is a perovskite; PtCo, PdCo, ​​a hexagonal metal with a delafossite structure when the ferroelectric material is a hexagonal ferroelectric; Fe, LiV; or InTi.

[0150] Example 79: The capacitor structure of example 74, wherein the ferroelectric material is doped with Sc or Mn to control leakage through the ferroelectric material.

[0151] Example 80: A method of forming a capacitor structure, comprising forming a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor; and a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, the third section adjacent to the first section and the second section such that the third section extends in the first direction, and the first section being electrically conductive. forming a second structure, a portion of the first section and a portion of the second section adjacent to the first structure; and forming a third structure having a ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, and the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction.

[0152] Example 81: The method of Example 80, comprising forming a fourth structure having a second conductive oxide, the fourth structure being between the first section and the second section of the third structure, and a portion of the fourth structure being adjacent to a portion of the third section of the third structure.

[0153] Example 82: The method of Example 81, comprising forming a fourth structure, the fourth structure being a stack of a layer of a first material and a layer of a second material, the first material including one of Cu, Co, Ru, Ta, or W, and the second material including one of Cu, Co, Ru, Ta, W, TaN, or WN; and forming a layer around three sections of the stack, the layer having Ti and Al, the fourth structure being between the first section and the second section of the third structure.

[0154] Example 83: The method of Example 81, wherein the refractive structure is a first refractive structure, and the method further includes forming a fifth structure having a second refractive intermetallic compound, the fifth structure being adjacent to the plate line and adjacent to the fourth structure.

[0155] Example 84: The method of Example 81, comprising forming a sixth structure adjacent to a side of the first section of the second structure, and forming a seventh layer adjacent to a side of the second section of the second structure, wherein the sixth structure and the seventh structure comprise a barrier material.

[0156] Example 85: The method of Example 84, wherein the ferroelectric material is one of a perovskite, a hexagonal ferroelectric, or an improper ferroelectric.

[0157] Example 86: The ferroelectric material comprises one of the following: the perovskite comprises one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3, the hexagonal ferroelectric comprises one of YMnO3 or LuFeO3, or the hexagonal ferroelectric is of h-RMnO3 type, where R is a rare earth element, i.e., cerium (Ce), dysprosium (Dy), erbium ( 86. The method of example 85, wherein the improper ferroelectric material is selected from the group consisting of [PTO / STO]n, [LAO ...

[0158] Example 87: The method of Example 86, wherein the barrier material comprises one or more of an oxide of Ti, Al, or Mg.

[0159] Example 88: The method of Example 86, wherein the first or second refractive material comprises one or more of Ti, Al, Ta, W, or Co.

[0160] Example 89: The method of Example 86, wherein the first and second conductive oxides comprise an oxide of one of: Ir, Ru, Pd, Ps, or Re when the ferroelectric material is a perovskite; PtCo, PdCo, ​​a hexagonal metal with a delafossite structure when the ferroelectric material is a hexagonal ferroelectric; Fe, LiV; or InTi.

[0161] Example 90: The method of example 86, wherein the ferroelectric material is doped with Sc or Mn to control leakage through the ferroelectric material.

[0162] Example 91: A memory having a capacitive structure, and an artificial intelligence (AI) processor coupled to the memory, wherein the capacitive structure is a first structure having a refractive intermetallic compound, the first structure adjacent to the source or the drain of the transistor, and a second structure having a first conductive oxide, the second structure having first, second, and third sections, the first section extending in a second direction orthogonal to the first direction, the second section being parallel to the first section, the third section adjacent to the first section and the second section such that the third section extends in the first direction, and a portion of the first section and a portion of the second section adjacent to the first structure. a third structure having a ferroelectric material, the third structure having first, second, and third sections, the first section adjacent to the first section of the second structure, the second section adjacent to the second section of the second structure, the third section adjacent to the third section of the second structure, the first and second sections of the third structure being parallel to each other and extending along the second direction; and a fourth structure having a second conductive oxide, the fourth structure being between the first and second sections of the third structure, and a portion of the fourth structure adjacent to a portion of the third section of the third structure.

[0163] Example 92: The system of Example 91, wherein the ferroelectric material is one of a perovskite, a hexagonal ferroelectric, or an improper ferroelectric.

[0164] Example 93: The ferroelectric material comprises one of the following: the perovskite comprises one of LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3, the hexagonal ferroelectric comprises one of YMnO3 or LuFeO3, or the hexagonal ferroelectric is of the h-RMnO3 type, where R is a rare earth element. the elements cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); 93. The system of Example 92, wherein the improper ferroelectric comprises one of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100.

[0165] An Abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A device for storing data, a transistor having a source, a drain, and a gate; a word line coupled to the gate; a bit line extending in a first direction, the bit line coupled to one of the source or the drain of the transistor; a plate line extending in the first direction; a capacitive structure coupled to one of the source or the drain of the transistor through one or more vias and coupled to the plate line; a ferroelectric material having an inverted U-shape and including a Mn or Sc dopant for controlling leakage through the ferroelectric material; a first conductive oxide in the inverted-U-shaped gap region, the first conductive oxide contacting an inner wall of the ferroelectric material, the first conductive oxide completely filling the gap region, and a portion of the first conductive oxide coupled to one of the source or the drain of the transistor; a second conductive oxide in contact with an outer wall of the ferroelectric material, a portion of the second conductive oxide being coupled to the plate line; an insulating material in contact with the outer wall of the second conductive oxide, the insulating material including an oxide of Al; and a refractive intermetallic material in contact with the first conductive oxide and a bottom surface of the inverted U-shape of the ferroelectric material; a capacitance structure having A device having:

2. 10. The device of claim 1, wherein the ferroelectric material is doped to achieve a spontaneous strain in the ferroelectric material in the range of 0.3% to 2%.

3. the refractive intermetallic material is a first refractive intermetallic material, and the capacitive structure comprises: a second refractive intermetallic material in contact with the sidewalls of the second conductive oxide; 10. The apparatus of claim 1, comprising:

4. The apparatus of claim 1 , wherein the insulating material further comprises Ti.

5. The device of claim 1 , wherein the transistor is one of a planar transistor or a non-planar transistor.

6. The device of claim 1 , wherein the transistor is located at a back end of a die, or the transistor is located at a front end of a die, or the capacitive structure is cylindrical in shape.

7. a perovskite material having an inverted U-shape, the perovskite material including a Mn or Sc dopant to modify the spontaneous strain of the perovskite material; a first conductive oxide in the inverted U-shaped gap region, the first conductive oxide contacting an inner wall of the perovskite material, the first conductive oxide completely filling the gap region; and a second conductive oxide in contact with an outer wall of the perovskite material; and an insulating material in contact with the outer wall of the second conductive oxide; a refractive intermetallic material in contact with the first conductive oxide and a bottom surface of the inverted U-shape of the perovskite material; A capacitance structure having

8. 8. The capacitive structure of claim 7, wherein the perovskite material includes a dopant to modify the spontaneous strain in the perovskite material to a range of 0.3% to 2%.

9. 8. The capacitor structure of claim 7, wherein the Mn or Sc dopant controls leakage through the perovskite material.

10. 8. The capacitor structure of claim 7, wherein the perovskite material comprises one of La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.

11. The perovskite material is LaCoO ３ , SrCoO ３ , SrRuO ３ , LaMnO ３ , SrMnO ３ , YBa ２ Cu ３ O ７ , Bi ２ Sr ２ CaCu ２ O ８ , or LaNiO ３ 8. The capacitor structure of claim 7, comprising one of:

12. 1. A method of forming a capacitive structure, comprising: forming a perovskite material having an inverted U-shape, the perovskite material including a Mn or Sc dopant to modify the spontaneous strain of the perovskite material; forming a first conductive oxide in the inverted U-shaped gap region, the first conductive oxide contacting an inner wall of the perovskite material, the first conductive oxide completely filling the gap region; forming a second conductive oxide in contact with an outer wall of the perovskite material; forming an insulating material in contact with an outer wall of the second conductive oxide; forming a refractive intermetallic material in contact with the first conductive oxide and a bottom surface of the inverted U-shape of the perovskite material; A method having the following.

13. 13. The method of claim 12, wherein the perovskite material includes a dopant to modify the spontaneous strain in the perovskite material to be in the range of 0.3% to 2%.

14. 13. The method of claim 12, wherein the Mn or Sc dopant controls leakage through the perovskite material.

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