Fault protection for switch driver units

Abstract

The system includes multiple driver modules coupled by an abnormal condition bus, e.g., a single-wire bus. Each driver module includes an error flag interface block coupled between a one-terminal error flag input / output (EF I / O) and a control block. Each driver module may be coupled to a motor. When a driver module detects a local abnormal condition, its error flag interface block is configured to lower a voltage at the one-terminal EF I / O to communicate the change to other driver modules. The error flag interface block is further configured to monitor a voltage change at the one-terminal EF I / O. An external abnormal condition is detected when the one-terminal EF I / O is at a low voltage. The error flag interface block is further configured to send a signal to disable an output of the driver module.

Description

[Technical field]

[0001]

[0001] This application claims priority under Article 8 of the Patent Cooperation Treaty (PCT) to currently pending U.S. patent application Ser. No. 17 / 845,117, filed Jun. 21, 2022, which claims the benefit of U.S. Provisional Patent Application Ser. No. 63 / 311,273, filed Feb. 17, 2022. U.S. Patent Application Ser. No. 17 / 845,117 and U.S. Provisional Patent Application Ser. No. 63 / 311,273 are incorporated by reference in their entireties.

[0002]

[0002] This application claims priority under Article 8 of the PCT to currently pending European Patent Application No. EP22166294.3, filed April 1, 2022, which is incorporated by reference in its entirety. [Background technology]

[0003]

[0003] The present invention relates generally to a system of multiple electronic switching modules using a single-wire bus between the switching modules for fault condition management. More particularly, the present invention relates to a half-bridge inverter module that may be used in such a system for a multi-phase brushless DC (BLDC) or synchronous permanent magnet motor drive.

[0004]

[0004] Home and industrial appliances, such as ventilation fans, cooling systems, coolers, dishwashers, washers / dryers, and many other large household items / goods, use electric motors to transfer energy from a power source to a mechanical load. Electrical energy for driving the electric motor is provided through a drive system that extracts electrical energy from a power source (e.g., from an AC low-frequency power source). The electrical energy received from the power source is first processed through a power converter and then converted to a desired form of electrical energy (typically a DC voltage) that is supplied to the motor through a system of drivers that typically includes two or more DC-AC inverters. The inverters are operated by a system controller to achieve a desired mechanical output. The desired mechanical output of the motor can be a mechanical operating parameter, such as the speed, torque, or position of the motor shaft of the motor.

[0005]

[0005] Motors and motor-related circuits, such as motor drives, represent a large portion of the utility network load. The functionality, efficiency, size, and price of motor drives are challenging and competitive factors considered by suppliers of these products. A motor drive system provides input electrical signals, such as voltage, current, frequency, and phase, to the motor for a desired mechanical output. A motor drive system typically includes multiple driver modules. The driver module in one example may include an inverter that receives a DC input and generates an AC output of the desired voltage, current, frequency, and phase. A system controller is typically a digital processor (sometimes called a microcontrol unit or MCU) that receives low-power signals from the driver module or from special external sensors to generate the desired mechanical output. The system controller may compare the detected value with a desired value and adjust the operation of the driver to maintain the target output of the motor. The system controller may further receive information from the driver module via a digital communication bus that provides status information about the driver or other information useful for managing the system.

[0006]

[0006] An important consideration for any system that controls a motor is the safety of the user in the event of an abnormal condition. Such systems must generally undergo rigorous testing by regulatory agencies before they are approved for sale. Systems that rely on an MCU system controller to manage abnormal conditions must typically repeat safety certification testing whenever there is any change to the MCU's program, even if the change is unrelated to handling of the abnormal condition. It is desirable for the system to have the ability to safely respond to abnormal conditions independent of the system controller.

[0007]

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various drawings unless otherwise specified. [Brief description of the drawings]

[0008] [Figure 1]

[0008] Figure 1 illustrates an embodiment of a system 10. For a plurality of driver modules 12n, each driver module is coupled to ground and includes an error flag (EF) output. [Diagram 2]

[0009] FIG. 2 illustrates another embodiment of the system 10 that includes an external error flag reset. [Diagram 3]

[0010] FIG. 3 is a functional block diagram for a driver module, such as half-bridge inverter 12n, configured according to FIG. [Figure 4]

[0011] FIG. 4 is a functional block diagram for a half-bridge inverter 12n configured according to FIG. [Diagram 5]

[0012] FIG. 5 is a block diagram for control block 22 constructed according to FIG. [Figure 6]

[0013] FIG. 6 is an error flag timing diagram showing delay periods t1D ​​and t2D (typically 10 μs) which act as a deglitch function. [Figure 7]

[0014] FIG. 7 is a logic diagram corresponding to the error flag interface block 24 included in each half-bridge inverter 12n. [Figure 8]

[0015] FIG. 8 is an embodiment of a circuit implementation of the error flag interface block 25 shown in FIG. [Figure 9]

[0016] FIG. 9 is a circuit diagram corresponding to the external EF reset block 20 shown in FIG. [Figure 10]

[0017] FIG. 10 is a circuit diagram corresponding to the external EF block 26 shown in FIG. [Figure 11]

[0018] FIG. 11 is a schematic diagram of an inverter that includes three phase legs. [Figure 12]

[0019] FIG. 12 is a schematic diagram of an exemplary gate driver unit. [Figure 13]

[0020] FIG. 13 is a schematic diagram of an embodiment of a gate driver unit. [Figure 14]

[0021] FIG. 14 is a schematic diagram of an inverter including three phase legs. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0022] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the figures are drawn for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements in order to facilitate a better understanding of the various embodiments of the present invention. Moreover, common but well-understood elements that are useful or necessary in commercially available embodiments are often not drawn in order to avoid cluttering the figures of these various embodiments of the present invention.

[0010]

[0023] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the specific details may not necessarily be used to practice the present invention. In other instances, well-known materials or methods have not been described in detail to avoid obscuring the understanding of the present invention.

[0011]

[0024] Reference herein to "one embodiment," "an embodiment," "an example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the invention. Thus, the use of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Particular features, structures, or characteristics may be included in an integrated circuit, electronic circuit, combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is understood that the figures provided herewith are for illustrative purposes to persons skilled in the art, and that the drawings are not necessarily drawn to scale.

[0012]

[0025] In the context of this application, when a transistor is in an "off state" or "off", the transistor does not substantially pass current. Conversely, when a transistor is in an "on state" or "on", the transistor can substantially pass current. By way of example, in one embodiment, the high voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field effect transistor (FET) in which a high voltage is supported between a first terminal, the drain, and a second terminal, the source. The high voltage metal-oxide-semiconductor field effect transistor (MOSFET) may comprise a power switch driven by an integrated controller circuit to regulate the energy provided to the load. In another embodiment, the high voltage transistor comprises a normally-on GaN device in series with a normally-off low voltage metal-oxide-semiconductor (MOS) FET. For purposes of this disclosure, "ground" or "ground potential" refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured.

[0013]

[0026] Half-bridge inverter modules are typically coupled to drive a motor, such as a single-phase motor or a three-phase motor, in response to a system controller. The power switching block of each half-bridge inverter module may include a high-side switch coupled to a low-side switch, with a midpoint terminal between the high-side and low-side switches coupled to a respective terminal of the motor.

[0014]

[0027] The system includes multiple driver modules connected by an abnormal condition bus, such as a single-wire bus. Each driver module includes a control block and an error flag interface block. The control block may include a number of conventional known electronic circuits that perform specific tasks essential to the desired operation of the driver module. For example, the control block may include a reference circuit for generating and maintaining a reference voltage and a reference current, a detection circuit for detecting the voltage at the terminals and the current at the transistor switches, a comparator circuit for detecting when a parameter is higher or lower than a limit, a thermal circuit for identifying the temperature of a component in the module, a logic circuit for determining whether a local abnormality has occurred in the module, a digital communication circuit for communicating with a system microcontroller, an error detection circuit for receiving an error signal in response to a signal transmitted from an external module, a test circuit for identifying the proper operation of a subcircuit in the module, a driver circuit for operating an output transistor, and a shutoff circuit for preventing the output of the module from switching. The error flag interface block includes a one-terminal error flag input / output (EF I / O) connected to the single-wire bus. The driver module may include an inverter output HB connected to the motor.

[0015]

[0028] The error detection circuitry in the control block is configured to detect a local abnormal condition, and the logic circuitry in the control block is configured to generate an ERROR_LOCAL signal when the driver module detects a local abnormal condition. A local abnormal condition, as distinguished from an external abnormal condition, is one that is detected by the driver module. When the error flag interface block receives the ERROR_LOCAL signal, the one-terminal error flag I / O is configured to change the state of the single-wire bus from a first logic state (indicating no error) to a second logic state (indicating an error).

[0016]

[0029] The error flag interface block is further configured to receive an external error flag signal from the single-wire bus. The external flag signal indicates an external abnormal condition, e.g., one detected external to the driver module. When the external flag signal is in the second logic state, the external abnormal condition has been detected. When the external flag signal is in the first logic state, the external abnormal condition has been cleared, indicating that the receiving driver module may be reset.

[0017]

[0030] For each driver module, when the one-terminal error flag I / O receives an external error flag signal in a second logic state, the error flag interface block locally sends an ERROR signal to the control block to trigger a shutoff circuit in the control block that causes the driver module to stop switching its inverter output HB. When the state of the external error flag signal changes from the second logic state to the first logic state, the error flag interface block locally sends a switch signal to trigger a logic circuit in the control block of the driver module to resume normal operation. Alternatively, when a user-specified condition is met, the error flag interface block may locally send a switch signal to trigger the motor to begin normal operation.

[0018]

[0031] The local abnormal condition is selected from the group including overcurrent, overvoltage, and overtemperature.

[0019]

[0032] A driver module can be a half-bridge inverter integrated circuit in a three-phase motor drive configuration, a half-bridge inverter integrated circuit in an H-bridge configuration for a single-phase motor drive, or an assembly of multiple components including smart devices (e.g., drivers and power switches) in one package. A system can include multiple motors using multiple driver modules.

[0020]

[0033] FIG. 1 illustrates an embodiment of a system 10. n For each half-bridge inverter, each half-bridge inverter is coupled to ground and includes a one-terminal error flag input / output flag EF I / O. Each one-terminal EF I / O is electrically coupled to an abnormal condition bus, such as a single-wire bus 14. A pull-up resistor R UP 16 is the system voltage V CC and a single-wire bus 14. A system MCU 18 controls the multiple half-bridge inverters 12. n , and are electrically coupled to each of the

[0021]

[0034] In operation, for each half-bridge inverter, half-bridge inverter 12 n The state of the single terminal EF I / O enables simple inter-module communication if one of the half-bridge inverters detects a local fault condition. This local fault condition is typically detected by the half-bridge inverter 12. n This requests that the FET stop switching its output.

[0022]

[0035] The system 10 uses an open-drain architecture with controlled pull-down capability using a current sink, and CC A pull-up resistor R coupled to UP A pull-up resistor R UP Through the voltage V CC When more current is removed from the single-wire bus than the current the power supply can provide, the voltage on the single-wire bus drops.

[0023]

[0036] In one embodiment, when the half-bridge inverter detects a local fault condition, such as over-temperature, over-voltage, or over-current, it prevents switching by pulling the one terminal EF I / O to a logic low state level VEFL, thereby lowering the voltage on the single-wire bus 14 and setting the state of all of the one terminal EF I / O in the system to VEFL. In response, the half-bridge inverter stops switching. In one embodiment, the half-bridge inverter sets an internal fault latch to maintain the prevented switching until the one terminal EF I / O is reset. The internal fault latch can be set by fault conditions including low-side (LS) MOSFET over-temperature protection latching shutdown, line over-voltage, and LS MOSFET sustained over-current protection latching shutdown.

[0024]

[0037] Local abnormal conditions may be user defined. By way of example, these conditions may include a selection between hysteresis or latched shutdown protection modes for overcurrent and overtemperature conditions.

[0025]

[0038] In one embodiment, resetting the one terminal EF I / O occurs when the local fault condition is cleared or falls below a predetermined threshold. As a result, the affected half-bridge inverter changes the state at each one terminal EF I / O in the system to VEHL by releasing the one terminal EF I / O (stopping pulling current from the single-wire bus) so as to raise the voltage at the single-wire bus 14. In response, the half-bridge inverter resumes normal operation and resets its internal fault latch.

[0026]

[0039] In another embodiment, resetting one terminal EF I / O occurs when the half-bridge inverters receive an external signal to reset. To reset one terminal EF I / O, an external source may pull one terminal EF I / O to the logic high state level VEFH. A rising edge at one terminal EF I / O raising the voltage above the logic high state level VEFH resets an internal fault latch (not shown) for each half-bridge inverter connected to the single-wire bus 14.

[0027]

[0040] FIG. 2 shows another embodiment of the system 11. n For each half-bridge inverter, each half-bridge inverter is coupled to ground and has one terminal EF I / O. Each terminal EF I / O is electrically coupled to the single-wire bus 14. A pull-up resistor R UP 16 is System V CC and a single-wire bus 14. A system MCU 18 controls the multiple half-bridge inverters 12. n , and to an external EF reset circuit 20 that is coupled to the single-wire bus 14. The system 10 may be reset externally through the external EF reset circuit 20 or via the system MCU 18.

[0028]

[0041] By applying a reset signal, the external EF reset circuit 20 provides a maximum one-terminal EF I / O pull-down current I EF (MAX) Larger current I RES and drives one terminal EF I / O of each of the half-bridge inverters high, which in turn resets their respective internal latches.

[0029]

[0042] In another embodiment, the system MCU 18 sends a latch reset command at some point after the affected half-bridge inverters pull their respective EF I / O terminals to a logic low. For each half-bridge inverter, EF I / O terminals are made logic high, which in turn resets its respective internal latch.

[0030]

[0043] FIG. 3 illustrates a half-bridge inverter 12 configured according to FIG. n FIG. 1 is a block diagram of a half-bridge inverter 12. n includes an error flag interface block 24 having one terminal EF I / O connected to the circuitry in the control block 22. The circuitry in the control block 22 is further connected to a drive circuit which provides an inverter output signal HB. The drive circuit drives two switches 28, 30 which share a common node at the output of the half-bridge inverter. The switches are electrically connected between a high voltage supply +HV and a low voltage supply -HV. A current monitoring circuit in the control block 22 provides a respective current sense signal ISENSE H and ISENSE L 2. The current in a switch coupled between the high voltage supply +HV and the low voltage supply -HV is measured from the control block 24. The inverter output HB for the half-bridge driver is at the midpoint between the two switches 28, 30. When the logic circuit 22 in the control block sends an ENABLE signal to the error flag interface block 24, the error flag interface block may be enabled.

[0031]

[0044] The half-bridge inverter may be part of a three-phase motor drive in an H-bridge configuration or part of a single-phase motor drive. Many half-bridge inverters driving many different motors in a system may share a single wire bus.

[0032]

[0045] When a local abnormal condition is detected or when the EF detection function is tested by asserting the TEST_EF signal, logic circuitry in control block 22 sends an ERROR_LOCAL signal to error flag interface block 24. Error flag interface block 24 pulls one terminal EF I / O to a logic low VEFL.

[0033]

[0046] For an external abnormal condition, when error flag interface block 24 detects that one terminal EF I / O is at logic low VEFL, an ERROR signal is sent to logic circuitry in control block 22 to disable switching of the drive circuitry. In one embodiment, assertion of the ERROR signal may configure the logic circuitry in control block 22 to ignore signals from the system MCU.

[0034]

[0047] FIG. 4 illustrates a half-bridge inverter 12 configured according to FIG. n The external EF reset block 20 and the external EF block 26 are functional block diagrams for the half-bridge inverter 12. n The EF I / O terminal is electrically coupled to the EF I / O terminal.

[0035]

[0048] During operation, the external EF reset block 20 provides a maximum one-terminal EF I / O pull-down current I EF (MAX) Larger current I RES When injecting Vin, one terminal EF I / O of each of the half-bridge inverters will thereby go high, thereby resetting their respective internal latches.

[0036]

[0049] In operation, when the external EF block 26 pulls the voltage on the single-wire bus down to logic level low VEFL, one terminal EF I / O of each of the half-bridge inverters goes low, thereby disabling their respective drive circuits.

[0037]

[0050] Figure 5 is an exemplary block diagram for control block 22 configured according to Figure 3. In the example of Figure 5, communication logic circuit 70 is connected to system MCU 18 (shown in Figure 2) and provides outputs ENABLE and TEST_EF to logic circuit 72. Drive logic circuit 74 is connected between logic circuit 72 and driver circuits 84, 86. High drive circuit 84 provides a High_Drive signal, while low drive circuit 86 provides a Low_Drive signal.

[0038]

[0051] Fault detector logic circuitry is connected between the logic circuitry 72 and sensors 80, 82. The voltage sensor 80 may provide an output indicative of an over-voltage or under-voltage fault condition for a voltage that may be internal or external to the module depending on how the module is configured in the motor drive system. The temperature sensor 82 provides an output indicative of an over-temperature fault condition. The current monitor circuitry 78 communicates with the fault detector logic circuitry 76 and a current sense signal ISENSE H and ISENSE L The current monitor circuit 78 is connected between the output +HV I FAULT and -HV I FAULT Provides +HV I FAULT indicates an overcurrent fault condition associated with the current drawn from the high voltage source +HV. -HV I FAULT indicates an overcurrent fault condition associated with the current delivered to the low voltage source -HV.

[0039]

[0052] The anomaly detector logic circuit 76 provides an output LOCAL_ERROR, which indicates a local anomaly condition, to the logic circuit 72. The logic circuit 72 provides outputs ENABLE, ERROR_LOCAL, and TEST_EF to the error flag interface 24 (shown in FIG. 3).

[0040]

[0053] The error flag interface block provides an input ERROR signal to logic circuit 72. An asserted ERROR signal indicates an external abnormal condition. Logic circuit 72 also provides an output STOP signal to drive logic circuit 74 which provides signals to drive circuits 84, 86 to stop switching of the inverter output.

[0041]

[0054] FIG. 6 illustrates a delay period t (e.g., 10 μs) that may provide a deglitching function for responding to an external error. 1D and t 2D 1 is an error flag timing diagram showing an error flag timing diagram for an error flag terminal for monitoring purposes or to reset a latch, as in the embodiment of FIG. 2. The deglitch function can avoid false alarms that might otherwise be caused by noise on the single-wire bus. As shown in the embodiment of FIG. 1, no intervention of the System MCU 18 is required for the error flag function. However, the System MCU 18 can be optionally connected to the error flag terminal for monitoring purposes or to reset the latch, as in the embodiment of FIG.

[0042]

[0055] Initially, the one terminal EF I / O is in the logic high state VEFH. In response to detecting that the one terminal EF I / O has changed to the logic low state VEFL (indicating an external error), the error flag interface block asserts an ERROR signal which disables its respective drive circuit. When the one terminal EF I / O has changed to the logic high state VEFH, the affected half-bridge inverter deasserts the ERROR signal, allowing its respective drive circuit to resume operation.

[0043]

[0056] FIG. 7 shows each half-bridge inverter 12 n 1 is a logic diagram corresponding to the error flag interface block 24 included in

[0044]

[0057] The TEST_EF and ERROR_LOCAL signals are inputs to an OR gate 46. The output of OR gate 46 and the ENABLE signal are inputs to an AND gate 48. The drain of transistor 50 is connected to one terminal EF I / O 47. The output of AND gate 48 is connected to the gate of transistor 50. The source of transistor 50 is connected to ground.

[0045]

[0058] An optional ESD clamp circuit 44 connected between one terminal EF I / O 47 and ground delivers an EF_SENSE signal indicative of the voltage state at one terminal EF I / O 47. The ESD clamp circuit 44 limits the magnitude of the EF_SENSE signal to protect the logic circuitry from damage due to excessive voltages that may appear on the single-wire bus. A first delay inverter 52 and a second delay inverter 54 are electrically cascaded. A capacitance 56 is connected to the midpoint between the first delay inverter 52 and the second delay inverter 54 and to ground. The EF_SENSE signal is the input to the first delay inverter 52. The output of the second delay inverter 54 is the delayed EF_SENSE signal.

[0046]

[0059] The ENABLE signal is received by an inverter 40. The delayed EF_SENSE signal and the inverted ENABLE signal are inputs to a NOR gate 42. The output of NOR gate 42 is an ERROR signal that indicates an external abnormal condition.

[0047]

[0060] FIG. 8 is an embodiment of a circuit implementation of the error flag interface block 25 shown in FIG.

[0048]

[0061] The nFET MN1 has a bias current I BIAS nFET MN26 has a drain and gate connected to the source of nFET MN1, and a source connected to ground.

[0049]

[0062] The pFET MP11 is driven by a bias voltage V BIAS The gate and drain of pFET MP11 are electrically connected. nFET MN12 has a drain connected to the gate and drain of pFET MP11, a gate connected to the gate of nFET MN26, and a source connected to ground. nFET MN2 has a drain connected to the gate of nFET MN12, a gate connected to the output of inverter 51, and a source connected to ground.

[0050]

[0063] The pFET MP1 is driven by the bias voltage V BIAS , a gate for receiving the ENABLE signal, and a drain connected to the gate and drain of pFET MP11.

[0051]

[0064] The pFET MP21 is driven by a bias voltage V BIAS and a drain connected to the gate and drain of pFET MP11. pFET MP0 has a source connected to the drain of pFET MP21, a gate and a drain for receiving the EF_SENSE signal. nFET MN4 has a drain connected to the drain of pFET MP0, a gate and a source for receiving the EF_SENSE signal. nFET MN3 has a drain connected to the source of nFET MN4, a gate connected to the gate of nFET MN2, and a source connected to ground.

[0052]

[0065] The OR gate 46 receives the ERROR_LOCAL signal and the TEST_EF signal. The AND gate 48 receives the output of the OR gate 46 and the ENABLE signal.

[0053]

[0066] The drain of nFET MN4 is the input to inverter 58. Capacitor 56 connects between the input of inverter 58 and ground. The output of inverter 58 is the delayed EF_SENSE signal. The delayed EF_SENSE signal and the inverted ENABLE signal are inputs to NOR gate 42. The output of NOR gate 42 is the ERROR signal, which indicates an external abnormal condition.

[0054]

[0067] An optional ESD clamp circuit 44, connected between one terminal EF I / O, ground, and the gate of MP0, delivers an EF_SENSE signal that indicates the voltage state at one terminal EF I / O. The ESD clamp circuit 44 limits the magnitude of the EF_SENSE signal to protect logic circuits from damage due to excessive voltages that may appear on the single-wire bus.

[0055]

[0068] nFET MN0 includes a drain connected to one terminal EF I / O, a gate connected to the output of AND gate 48, and a source. nFET MN6 includes a drain connected to the source of nFET MN0, a gate connected to the source of nFET MN1, and a source connected to ground.

[0056]

[0069] In operation, one terminal EF I / O is an open drain connected directly to the single-wire bus 14. When a local error is detected by the error detection circuitry in the control block 22, the ERROR_LOCAL signal goes high, thereby switching on transistor nFET MN0 and causing a current I BIAS Current I proportional to EF With this, one terminal EF I / O is pulled to the logic low state level VEFL.

[0057]

[0070] The EF_SENSE signal is high during normal operation and low when the signal indicates an external abnormal condition, such as an external device EF control or control from the system MCU 18, is detected. When the EF_SENSE signal is low, the ERROR signal is asserted causing the inverter to stop switching its output. When the EF_SENSE signal is high, the ERROR signal is deasserted causing the inverter to resume switching its output.

[0058]

[0071] 9 is a circuit diagram corresponding to the external EF reset block 20 shown in FIG. BIAS The anode of diode 62 receives the output of switch 60. A resistor 64 is connected between the cathode 62 of the diode and the single-wire bus 14. In operation, closing switch 60 causes a current I RES Inject current I RES is the single terminal EF I / O pull-down current capability I EF(MAX) Higher, it raises the voltage on the single wire bus 14 and resets the latch.

[0059]

[0072] 10 is a circuit diagram corresponding to the external EF block 26 shown in FIG. 4. A resistor 66 is electrically connected to the single-wire bus 14. A switch 68 is connected between the resistor 66 and ground. Closing the switch 68 diverts a current I from the single-wire bus 14. EXT Pull the CLKIN pin to assert the external error flag signal.

[0060]

[0073] The above description of examples shown for the present invention, including those matters described in the Abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it will be understood that specific and exemplary voltages, currents, frequencies, power range values, times, and the like are presented for purposes of illustration, and that other values ​​may be used in other embodiments and examples consistent with the teachings of the invention.

[0061]

[0074] For illustrative purposes, the embodiments describe a driver module connected to an abnormal condition bus, but any circuit with a one terminal EF I / O may be used with the abnormal condition bus. Driver Module. Although the exemplary embodiments describe a driver module therein that is a half-bridge inverter integrated circuit in a three-phase motor drive configuration, the driver module may also be a half-bridge inverter integrated circuit in an H-bridge configuration for a single-phase motor drive, or a smart device (e.g., driver and power switch) in one package. A system may include multiple motors using multiple driver modules.

[0062]

[0075] In some situations, the switching of multiple switches - and the operation of the driver units that drive the switches - are coordinated to achieve a particular purpose. One example of such a context is in an inverter. An inverter converts a battery or other DC input into an AC signal. The AC signal may be suitable for driving, for example, an electric motor in an electric vehicle. Many different types of inverters exist and different circuit topologies and control schemes may be used. A typical inverter includes three phase legs. Each phase leg includes a pair of power switches coupled in a half-bridge configuration between a high-voltage rail and a low-voltage rail, with an intermediate output node (also called a phase output, switch node, or LX node) between them. The switching of the switches in the different phase legs is coordinated to generate a desired waveform at the output node.

[0063]

[0076] 11 is a schematic diagram of an inverter 1100 including three phase legs 1105, 1110, 1115 coupled between a high voltage rail 1120 and a low voltage rail 1125. Each phase leg 1105, 1110, 1115 includes a respective high side power switch 1130, a low side power switch 1135, an output node 1140, a high side driver unit 1145, and a low side driver unit 1150. Each high side driver unit 1145 drives a respective high side power switch 1130. Each low side driver unit 1145 drives a respective low side power switch 1135.

[0064]

[0077] Although the power switches 1130, 1135 are shown as insulated gate bipolar transistors (IGBTs) and their terminals are described using corresponding terms (such as gate, emitter, and collector), the power switches 1130, 1135 - and indeed all of the power switches described herein - may be implemented as metal-oxide field effect transistors (MOSFETs) or bipolar junction transistors (BJTs). Furthermore, the power switches may be implemented using gallium nitride (GaN), silicon (Si), or silicon carbide (SiC) semiconductors. Furthermore, while the gate driver units 1145, 1150 are depicted as triangular blocks, the driver units 1145, 1150 generally include both some level of communication and control circuitry - in addition to drive circuitry that biases the respective control terminals of the power switches 1130, 1135. In some implementations, the driver units 1145, 1150 may further include fault detection circuitry for detecting an abnormal condition of the power switches 1130, 1135 (eg, a short circuit or an overcurrent fault).

[0065]

[0078] The switching of the switches 1130, 1135 in the phase legs 1105, 1110, 1115 is coordinated by the system controller 1150 according to a drive scheme. Due to this coordination, the gate driver units 1145, 1150 form a network that achieves the desired drive of the load 1155. The specific details of the drive scheme depend on the desired drive and the load 155. In the embodiment shown, the load 1155 is shown as a three-phase induction motor. However, the load 1155 may be any of a number of different loads and a variety of different drive schemes may be used.

[0066]

[0079] The system controller 1150 communicates with the gate driver units 1145, 1150 using a gate driver bus 1160. Although only one line is depicted in the schematic representation of the inverter 1100, this single line generally represents a bus including multiple wires or other communication channels, as represented by the diagonal lines across the bus 1160. For example, the system controller 1150 and the gate driver units 1145, 1150 may coordinate the switching of the switches 1130, 1135 using separate communication channels on the bus 1160 for each pair of gate driver units 1145, 1150, a pair of communication channels for each pair of gate driver units 1145, 1150, or a pair of communication channels for each individual gate driver unit 1145, 1150 (i.e., four gate driver path sections per each phase leg 1105, 1110, 1115). As another example, the system controller 1150 and the gate driver units 1145, 1150 may communicate using one or more communication channels - for example, conveying status and / or fault detection information - in either or both directions, from the system controller 1150 to the gate driver units 1145, 1150 and from the gate driver units 1145, 1150 to the system controller 1150. Thus, communication between the system controller 1150 and the gate driver units 1145, 1150 is not limited to switching coordination.

[0067]

[0080] FIG. 12 is a schematic diagram of an example gate driver unit 1200. The gate driver unit 1200 may be configured to drive power switches, such as the high-side power switch 1130 and the low-side power switch 1135, in an inverter, such as the inverter 1100 (FIG. 11). However, in addition to the functions assigned to the gate driver units 1145, 1150, the gate driver unit 1200 may further communicate with other gate driver units, such as to communicate fault protection information. At least some part of this communication is not mediated by a system controller, such as the system controller 1150. Rather, one gate driver unit 1200 may communicate information to another gate driver unit 1200, thus speeding up communication and shortening the time required for one gate driver unit 1200 to respond to a condition in another gate driver unit.

[0068]

[0081] More specifically, the illustrated embodiment of the gate driver unit 1200 includes terminals 1202, 1204, 1206, 1208, 1210, 1212, a sense input 1215, and a drive signal output 1220. The sense input 1215 is configured to receive one or more signals including information characteristic of the operation of the power switches 1130, 1135 driven by the gate driver unit 1200. The received information may be sufficient for the gate driver unit 1200 to identify an abnormal condition in the driven power switches 1130, 1135. The information may represent, for example, a current flow through the driven power switches, a voltage at one or more terminals of the driven power switches, and / or a temperature characteristic of the power switches. In one example, the sense input 1215 may be realized using multiple physical terminals, each assigned to receive a different signal. In another example, one terminal may be used for the sense input 1215 to sense multiple characteristics of the power switches 1130, 1135, such as current flow or voltage at one terminal of the power switches 1130, 1135. Additionally, multiplexing and other channel splitting schemes may also be used to receive different signals on one terminal.

[0069]

[0082] The drive signal output 1220 outputs a drive signal coupled to the gate terminal of the power switch 1130, 1135 being driven. The particular characteristics of the drive signal depend on the nature of the power switch 1130, 1135 being driven. Furthermore, the drive signal is generally tailored to achieve a particular switching profile including, for example, switching speed, level of dv / dt immunity, etc. In some implementations, a gate resistor and / or other component is coupled between the drive signal output 1220 and the gate terminal of the power switch 1130, 1135 being driven.

[0070]

[0083] The terminals 1202, 1204, 1206, 1208, 1210, 1212 are all configured to be coupled to wires in the bus 1260 for exchanging information and / or commands with the system controller 1150. As described below, at least one of the terminals 1202, 1204, 1206, 1208, 1210, 1212 may be further coupled to a bus 1265 that establishes at least one communication channel that allows different gate driver units to exchange information and / or commands with each other, i.e., without mediation by the system controller 1150. Although the bus 1265 is shown as a single-wire bus, the bus 1265 may also be implemented using multiple wires and / or communication channels.

[0071]

[0084] The specific details regarding the information and / or commands communicated through the terminals 1202, 1204, 1206, 1208, 1210, 1212 may vary in different embodiments of different gate driver units. However, in the illustrated gate driver unit 1200, the terminal 1202 may be an input terminal configured to receive commands specifying when a power switch driven by the gate driver unit 1200 is driven on and off. The timing commands may be received from a system controller, such as the system controller 1150. The commands received by the terminal 1202 may convey the timing information in a variety of different ways. For example, a pulse train including a logic high section and a logic low section may convey when the power switch is driven on and off. For example, the logic high section may convey when the power switch is driven on and the logic low section may convey when the power switch is driven off.

[0072]

[0085] Although the terminal 1202 is shown as one terminal connected to one line of the bus 1260, the terminal 1202 may further be realized as a pair of terminals connected to different lines. For example, one terminal of the pair may be configured to receive a command that specifies when a power switch is driven on by the gate driver unit 1200. The other may be configured to receive a command that specifies when the same driven power switch is driven off by the gate driver unit 1200. As another example, one terminal of the pair may be configured to receive a command that specifies when a power switch driven by the gate driver unit 1200 is driven on and off. The other of the pair may be configured to receive a command that specifies when different gate driver units drive different power switches on and off. For example, if the gate driver unit 1200 is coupled to drive a high-side switch, a different gate driver unit may be coupled to drive a low-side switch in the same inverter phase leg. An on / off timing command for both gate driver units in a phase leg may be used by a gate driver unit, such as gate driver unit 1200, to ensure that unintentional short circuits across the phase legs are avoided.

[0073]

[0086] Returning to the illustrated gate driver unit 1200, terminal 1204 may be an input terminal configured to receive a command to enable (effectively "switch on") or disable (effectively "switch off") the gate driver unit 1200. The command may be received from a system controller, such as system controller 1150. In one example, when terminal 1204 is set low, the gate driver unit 1200 ignores signals received at terminal 1202 to switch on and off the power switch. When terminal 1204 is set high, the gate driver unit 1200 responds to signals received at terminal 1202.

[0074]

[0087] Terminal 1208 may be an input terminal that may be configured to receive information characteristic of a position of the gate driver unit 1200 in the network of gate driver units. For example, the position information may be embodied in a signal received from a system controller, such as system controller 1150. As another example, the position information may be inferred from the nature of a component coupled to terminal 1208. For example, to hard-code the position of the gate driver unit 1200 in the network of gate driver units, a pull-down or pull-up resistor may be connected between terminal 1208 and a return (e.g., GND) or a voltage source (e.g., V CC ) In this case, terminal 1208 is not coupled to a system controller.

[0075]

[0088] The position information received at the terminal 1208 is sufficient to specify the role of the gate driver unit 1200 in the network of gate driver units such that the gate driver unit 1200 can respond appropriately if an abnormal condition occurs in the network. Referring again to the inverter 1100 (FIG. 11) as an example, the operation of the six driver units 1145, 1150 forms a network, and the switching of the power switches 1130, 1135 must be coordinated to perform a task, namely, driving a three-phase induction motor 1155. In this context, the position information may specify whether the gate driver unit 1200 is arranged as a high-side gate driver unit 1145 or a low-side gate driver unit 1150. In other contexts where the operation of the gate driver units is coordinated to perform other tasks using other coordination schemes, different position information may be received.

[0076]

[0089] In either case, the received position information may contribute to the fault protection functions provided by the gate driver unit 1200, as will be described in more detail below.

[0077]

[0090] The terminal 1210 may be a bidirectional input / output terminal configured to transmit and receive status information characteristic of the operational status of the device or system in which the gate driver unit 1200 is active, and of the operational status of the gate driver unit 1200 or the power switches 1130, 1135 driven thereby. The exchange of status information is generally mediated by a system controller, such as the system controller 1150. For example, assuming that the gate driver unit 1200 transmits status information through the terminal 1210, the system controller 1150 may receive the status information and relay the received status information to other gate driver units using the same channel in the bus 1260.

[0078]

[0091] As described below, the status information communicated through terminal 1210 may be used by the gate driver units to interpret the fault protection command. In some implementations, the status information may characterize the fault at a relatively high level of abstraction. For example, rather than specifying the exact nature of the fault, a gate driver unit detecting the fault may transmit status information indicating a classification of the fault. The classification may contribute to interpreting the fault protection command to identify an appropriate response. In some implementations, position information received through terminal 1208 may further contribute to interpreting the fault protection command to identify an appropriate response. In such cases, even if the other gate driver units are not provided with extensive details related to the nature of any particular fault, they may still respond appropriately based on the processing performed by the transmitting gate driver unit to classify the fault.

[0079]

[0092] In any case, the particular status information communicated through the terminal 1210 depends on the operational context of the gate driver unit 1200. For example, in one embodiment in which the gate driver unit 1200 operates within an inverter, the status information may characterize whether or not an anomaly has been detected within the inverter.

[0080]

[0093] In other embodiments, the status information may provide further details related to the nature of the anomaly. For example, in the context of an inverter, the status information may include: - there is an under-voltage lockout condition on the primary side of the power converter that supplies the power used by the gate driver unit 200 to drive the power switches 130, 135; - there is an under-voltage lockout condition on the secondary side of the power converter that supplies the power used by the gate driver unit 200 to drive the power switches 130, 135; - A phase short circuit is present in the inverter, - a short circuit exists across the switches 130, 135; - overheat detection of the gate driver unit 200; - a monitoring timeout in the gate driver unit 200; - detection of a communication failure in the gate driver unit 200; - a failure of a power switch driven by the gate driver unit 200 or elsewhere in the network of power switches being switched on, or - Anomalies indicated by external devices, As such, anomalies can be identified.

[0081]

[0094] Other anomalies and / or information may be identified by the status information.

[0082]

[0095] The terminal 1212 may be a bidirectional input / output terminal configured to transmit and receive fault protection commands. In the embodiment shown, the terminal 1212 is coupled to both a channel in the bus 1260 and at least one channel in the bus 1265 that may communicate information to a corresponding terminal in another gate driver unit. The channels in the bus 1260 and the bus 1265 may be physically realized in a variety of different ways. For example, the buses 1260, 1265 may be formed using multiple insulated wires housed in one insulating sheath. As another example, the buses 1260, 1265 may be formed using independent insulated wires that are separate from each other or tied together, for example, using a cable tie. As another example, the buses 1260, 1265 may be formed by multiplexing or otherwise splitting the wires into multiple communication channels. In either case, the gate driver units may communicate with each other through the bus 1265 without mediation by the system controller 1150.

[0083]

[0096] The fault protection commands on the buses 1260, 1265 may originate from individual gate driver units in the network, including the gate driver unit 1200. In some implementations, the fault protection commands may also originate from the system controller 1150. However, when the gate driver units can communicate with each other without mediation by the system controller 1150, the network of gate driver units may respond relatively more quickly to fault conditions. Fault protection functions present in the individual gate driver units may be utilized to monitor the operation of the power switches that the gate driver units drive. Indeed, more serious failures may be avoided if the system controller 1150 itself experiences a fault.

[0084]

[0097] As mentioned above, the appropriate interpretation of the fault protection command received through terminal 1212 may be based on other information and / or commands received by the gate driver unit 1200. For example, the fault protection command received through terminal 1212 may be represented at a relatively high level of abstraction, for example using logic high / logic low states.

[0085]

[0098] In the following example, the commands represented by logic high / logic low states correspond to the location of the fault in the inverter, e.g., whether the fault occurs on the high side or the low side. In such cases, the appropriate response of the gate driver unit is determined based on other relevant information. For example, the appropriate response of the gate driver unit to these conditions may depend on the location of the gate driver in the inverter, as indicated by the location information received at terminal 1208. As yet another example, the appropriate response of the gate driver unit to a fault protection command received through terminal 1212 may depend on whether a fault exists or not, or even on the specific characteristics of the fault, as indicated by the status information communicated through terminal 1210.

[0086]

[0099] 13 is a schematic diagram of an embodiment of a gate driver unit 1300. The gate driver unit 1300 is one possible implementation of the gate driver unit 1200 (FIG. 12), and common features are labeled using the same reference numerals.

[0087]

[0100] The gate driver unit 1300 includes a drive interface 1305, a drive control circuit 1310, a detection circuit 1315, and an abnormality protection controller 1320. The drive interface 1305 is a communication interface that converts timing commands received at the terminal 1202 into commands suitable for the drive control circuit 1310. In general, the drive interface 1305 is galvanically isolated from the drive control circuit 1310. The circuit coupled to the primary side of the galvanic isolation is the terminal V CCand GND. Circuitry coupled to the secondary side of the galvanic isolation receives operating power from terminals VISO and COM. The dashed line between the drive interface 1305 and the drive control circuit 1310 indicates the galvanic isolation and that information may be communicated across the galvanic isolation. For example, the drive interface 1305 may send timing commands to the drive control circuit 1310 using, for example, optical components, communication transformers, magnetically coupled indicators, capacitively coupled components, etc. The details of the conversion performed by the drive interface 1305 may depend, for example, on the nature of the drive control circuit 1310, the signals received at terminals 1202, and whether and how the drive interface 1305 is galvanically isolated from the drive control circuit 1310.

[0088]

[0101] The conversion performed by the drive interface 1305 is further based on input from the fault protection controller 1320. As described in more detail below, the fault protection controller 1320 can recognize and classify a short circuit fault in a power switch driven by the gate driver unit 1300, or can be notified about a short circuit fault in another power switch driven by a different gate driver unit. The fault protection controller 1320 is configured to instruct the drive interface 1305 (or the drive control circuit 1310 in some implementations) to adjust the drive of the power switches 1130, 1135 based on such faults. For example, the fault protection controller 1320 can be configured to instruct the drive interface 1305 or the drive control circuit 1310 to maintain the power switches 1130, 1135 in an open or closed state regardless of the timing command received at the terminal 1202.

[0089]

[0102] The drive control circuit 1310 is responsible for generating drive signals for the power switches 1130, 1135 driven by the gate driver unit 1300. The drive control circuit 1310 generates the drive signals according to commands received from the drive interface 1305 and any adjustments received from the fault protection controller 1320. For example, in the embodiment shown, the drive control circuit 1310 biases the pull-up transistor 1325 and the pull-down transistor 1330 to couple and decouple appropriate voltages to the control terminals of the driven power switches 1130, 1135. In some embodiments, the drive signals for the driven power switches 1130, 1135 can be shaped, for example, to achieve a particular on-switching profile, to avoid damage to the driven power switches 1130, 1135, to respond to operating conditions, or to achieve other purposes. For example, the drive signals for the driven power switches 1130, 1135 can be controlled based on measurements or feedback signals received from the detection circuit 1315.

[0090]

[0103] The detection circuit 1315 is coupled to the actuated power switches 1130, 1135 and is configured to detect one or more parameters characteristic of a state of the actuated switches. At least some of the detected parameters are suitable for identifying one or more abnormal conditions in the switching of the switches. The measurements or other information about the parameters are communicated to the fault protection control 1320. Generally, the detection circuit 1315 is galvanically isolated from the fault protection control 1320, and the dashed lines between the detection circuit 1315 and the fault protection control 1320 indicate that information may be communicated across the galvanic isolation. In some implementations, the detection circuit 1315 communicates information about the detected parameters of the actuated switches 1130, 1134 to the drive interface 1305 using the same galvanically isolated communication channel used to send timing commands from the drive interface 1305 to the drive control circuit 1310. The drive interface 1305 may then transmit the detected parameters to the fault protection control 1320.

[0091]

[0104] With respect to the detected parameters, the detection circuit 1315 may be configured to detect a main current through the power switches 1130, 1135, one or more voltages at the nodes of the power switches 1130, 1135, or both a current and a voltage. In some implementations, the detection circuit 1315 may further detect a temperature of the power switches 1130, 1135. For example, a short circuit or a failure to switch on may be identified from a magnitude and / or a waveform of a main current through a driven power switch. As another example, a short circuit or a failure to switch on may be identified from a voltage drop across a main terminal of a driven power switch. As mentioned above, in some implementations, the detection circuit 1315 may provide a measurement or a feedback signal to the drive control circuit 1310.

[0092]

[0105] The fault protection controller 1320 is a circuit configured to realize a fault protection function in the gate driver unit 1300. The fault protection function is a set of operations performed by the gate driver unit 1300 to recognize and respond to an fault condition. The fault condition may be present in the gate driver unit 1300 or in another gate driver unit in the network of gate driver units. The fault condition may be present in a power switch driven by the gate driver unit 1300 or in another power switch driven by another gate driver unit in the network of gate driver units. In some examples, the fault condition may be present in both the gate driver unit and the power switch.

[0093]

[0106] The fault protection function typically enables each gate driver unit to monitor the operation of the power switch it drives to recognize and characterize a short circuit. For example, the gate driver unit 1300 may compare the voltage across and / or the current flowing between the main terminals of the power switches 1130, 1135 to each other and / or to threshold levels or waveforms to recognize a short circuit condition or whether the power switches 1130, 1135 will not switch on. As another example, the gate driver unit 1300 may monitor the temperature of the power switches it drives.

[0094]

[0107] Furthermore, the fault protection function ensures that each gate driver unit: - transmitting information related to an anomaly in the actuation of each actuated power switch; and - responding appropriately to information received from other gate driver units relating to anomalies in the driving of the power switches they drive; Information may be exchanged between the gate driver units without intermediation by, for example, system controller 1150 (FIG. 11). Rather, information and / or commands may be exchanged between the gate driver units themselves.

[0095]

[0108] Fault protection control 1320 is coupled to terminal 1204 for receiving enable / disable commands, terminal 1206 for receiving reset commands, terminal 1208 for receiving position information, terminal 1210 for sending and receiving status information, and terminal 1212 for sending and receiving fault protection commands. As mentioned above, terminal 212 is coupled to both buses 260, 265, and fault protection commands can be exchanged on bus 1265 between gate driver units - including gate driver unit 1300 - without intervention by system controller 1150.

[0096]

[0109] The fault protection function implemented by the fault protection circuit control unit 1320 may depend on the operating context of the gate driver unit 1300. An exemplary operating context is in an inverter, such as the inverter 1100 (FIG. 11). In such a context, the fault protection function may cause the gate driver unit 1300 to respond in different manners when a low-side short circuit or a high-side short circuit occurs. Examples of types of faults and responses implemented by the fault protection circuit function in an inverter are shown in Table 1. In Table 1, "UVLO" represents an under-voltage lockout condition on the primary or secondary side of the power converter that provides power to drive the power switch. In the context of the gate driver unit 1300 (FIG. 13), an under-voltage lockout condition occurs on the secondary side when the voltage across the terminals labeled "VISO" and "COM" drops below a threshold. "V CC An under-voltage lockout condition occurs on the primary side when the voltage across the terminals labeled "GND" and "GND" falls below a threshold value. [Table 1]

[0097]

[0110] Commands and / or information related to the type and location of the fault exchanged between the gate driver units on the bus 1265 may be encoded using a variety of different schemes. An encoding scheme using binary states (e.g., logic high / logic low) may be relatively robust in operational contexts where relatively large voltages are switched, including, for example, inverters.

[0098]

[0111] In some implementations, commands to enable and disable the gate driver unit may be encoded as logic high / logic low states. Position information specifying whether the gate driver unit is located on the high side or low side may be encoded as logic high / logic low states. Status information specifying that a fault has or has not been detected anywhere within the device in which the gate driver unit is operating may be encoded as logic high / logic low states. Fault protection circuit commands specifying whether the fault detected is on the high side of the inverter or on the low side of the inverter may be encoded as logic high / logic low states.

[0099]

[0112] Tables 2 and 3 represent exemplary implementations of the fault protection circuit function using a binary encoding scheme. Binary information (yes / no, low / high, fault / no fault) may be encoded using logic high / logic low states in any desired manner. Table 2 describes an implementation of the fault protection circuit function in the high side gate driver unit, while Table 3 describes a corresponding implementation in the low side gate driver unit.

[0100] [Table 2] [Table 3]

[0101]

[0113] As shown, in the exemplary embodiment of Tables 2 and 3, the type and location of the detected fault (e.g., UVLO, phase short, switching failure, collector-emitter short) is abstracted and classified into two categories: whether the fault is on the high side or the low side of the inverter. The fault protection circuit command encodes this classification as a logic high or logic low. The appropriate response of the gate drive unit to the command depends on the location of the gate drive unit in the inverter.

[0102]

[0114] FIG. 14 is a schematic diagram of an inverter 1400 including three phase legs 1405, 1410, 1415 coupled between a high voltage rail 1420 and a low voltage rail 1425. Each phase leg 1405, 1410, 1415 includes a respective high side power switch 1130, low side power switch 1135, output node 1140, high side gate driver unit 1445, and low side gate driver unit 1450. Each of these gate driver units 1445, 1450 is implemented as a gate driver unit 1200, 1300 (FIGS. 12, 13). The high side gate driver unit 1445 and the low side gate driver unit 1450 can communicate fault protection information to each other without mediation by the system controller 1150. This speeds up communication and shortens the time required for one gate driver unit 1445, 1450 to respond to a condition in another gate driver unit.

[0103]

[0115] Each gate driver unit 1445, 1450 includes a terminal 1212 configured to send and receive fault protection commands over a bus 1265 (indicated by a dashed line). The bus 1265 is shown separate from the bus 1260 to emphasize that communication over the bus 1265 is not mediated by the system controller 1150. Rather, a fault protection command sent over the bus 1265 by one gate driver unit 1200 may be received, interpreted, and actioned upon by the other gate driver unit 1200. As described below, the fault protection command may be communicated over the bus 1265 to the system controller 1150, thereby allowing the system controller 1150 to still evaluate the fault protection commands sent by the gate drivers 1445, 1450.

[0104]

[0116] In the illustrated embodiment, the bus 1265 is shown as one wire that is physically separate from the other wires in the bus 1260. Furthermore, the system controller 1150 is shown coupled to the bus 1265 separately from its coupling to the bus 1260. This is not necessarily the case. As mentioned above, the buses 1260, 1265 can be physically implemented in a variety of different ways and using partitioning schemes if necessary. For example, the wires of the bus 1265 can be housed separately from the wires of the bus 1260 or in the same sheath as the wires of the bus 1260. Regardless of the physical implementation, information can be communicated between the gate driver units 1200 without mediation by the system controller 1150.

[0105]

[0117] Moreover, generally, system controller 1150 may further communicate over bus 1265. For example, system controller 1150 may further include a bi-directional input / output terminal configured to transmit and receive fault protection commands. In such an embodiment, system controller 1150 may communicate fault protection commands received from an external device, such as from another system controller. In some cases, primary and secondary UVLO commands may be provided on bus 1265 by system controller 1150.

[0106]

[0118] The above description of examples shown for the present invention, including those matters described in the Abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it will be understood that specific and exemplary voltages, currents, frequencies, power range values, times, and the like are presented for purposes of illustration, and that other values ​​may be used in other embodiments and examples in accordance with the teachings of the present invention.

[0107]

[0119] While the present invention is defined in the claims, it should be understood that the invention can alternatively be defined by the following examples.

Claims

1. A driver module, the driver module comprising: an error flag interface block having a one-terminal error flag input / output (EF I / O); a control block coupled to the error flag interface block, the control block configured to detect abnormal conditions local to the driver module; Equipped with the control block is configured to enable the error flag interface block to respond to a signal indicating an abnormal condition; the control block is configured and coupled to prevent switching of the output of the driver module in response to detecting an abnormal condition external to the driver module, the abnormal condition external to the driver module being indicated by an error flag state at the one terminal EF I / O received by the error flag interface block; the control block is configured and coupled to control the error flag interface block to set an error flag state at the one-terminal EF I / O in response to detecting an abnormal condition local to the driver module; the error flag interface block is configured to respond to a reset condition at the one-terminal error flag input / output by sending a switch signal to trigger logic circuitry in the control block to enable the output of the driver module to switch; Driver module.

2. the fault condition local to the driver module is selected from the group consisting of overcurrent, overvoltage, and overtemperature; The driver module of claim 1 .

3. The driver module is a half-bridge inverter. The driver module of claim 1 .

4. The driver module is a three-phase motor drive inverter. The driver module of claim 1 .

5. the driver module is a driver and a power switch in one package; The driver module of claim 1 .

6. an abnormal condition bus; at least one driver module coupled to the abnormal condition bus; Equipped with the at least one driver module: an error flag interface block comprising a one-terminal error flag input / output (EF I / O), said one-terminal EF I / O coupled to said error status bus; a control block coupled to the error flag interface block, the control block configured to detect abnormal conditions local to the driver module; Further provided with the control block is configured to enable the error flag interface block to respond to an abnormal condition; the control block is configured and coupled to prevent operation of the driver module in response to detecting an abnormal condition external to the driver module, the abnormal condition external to the driver module being indicated by an error flag status at the one terminal EF I / O received by the error flag interface block; the control block is configured and coupled to control the error flag interface block to set an error flag state at the one-terminal EF I / O in response to detecting an abnormal condition local to the driver module; the error flag interface block is configured to respond to a reset condition at the one-terminal error flag input / output by sending a switch signal to trigger logic circuitry in the control block to enable the output of the driver module to switch; system.

7. the abnormal condition bus is a single-wire bus; The system of claim 6.

8. the fault condition local to the driver module is selected from the group consisting of overcurrent, overvoltage, and overtemperature; The system of claim 6.

9. the system further comprising a system controller coupled to the abnormal condition bus; the system controller configured and coupled to set the reset state and to receive the error flag state; The system of claim 6.

10. The driver module is a half-bridge inverter. The system of claim 6.

11. The driver module is a three-phase motor drive inverter. The system of claim 6.

12. the driver module is a driver and a power switch in one package; The system of claim 6.

13. 1. A method for fault condition management by a driver module having a single terminal error flag input / output coupled to a fault condition bus, the method comprising: responding to an abnormal condition occurring external to the driver module, the abnormal condition being indicated by an external error flag signal at the one-terminal error flag input / output, the external error flag signal being received by an error flag interface block of the driver module, responding including preventing switching of an output of the driver module by a control block in response to the abnormal condition occurring external to the driver module; asserting, by the error flag interface block, an error flag state at the one-terminal error flag input / output in response to an abnormal condition being detected local to the driver module; responding by the error flag interface block to a reset state of the one-terminal error flag input / output by sending a switch signal to trigger logic circuitry in the control block to enable the control block to switch the output of the driver module; A method comprising:

14. The method of claim 13, further comprising detecting an abnormal condition local to the driver module; the abnormal condition detected locally to the driver module is selected from the group consisting of overcurrent, overvoltage, and overtemperature; The method of claim 13.

15. receiving the error flag status by a system controller coupled to the abnormal status bus; setting a reset state at the one-terminal error flag input / output of the driver module by the system controller; The method of claim 13 further comprising:

16. Responding to a local elimination of the abnormal condition; and deasserting the error flag state of the one-terminal error flag input / output by a half-bridge inverter, wherein deasserting the error flag state corresponds to the reset state; The method of claim 13 further comprising:

17. Multiple switches and a plurality of driver units, each driver unit coupled to drive a respective one of the plurality of switches; a system controller coupled to each of the driver units by a bus, the system controller configured to coordinate the actuation of each of the switches by the driver units, and configured to communicate a position of each of the driver units to each of the driver units over the bus, the communicated position specifying a role of the gate driver unit in a gate driver unit network; and at least one communication channel coupled to each of the driver units, the driver units configured to communicate with each other through the communication channel without mediation by the system controller, and each driver unit configured to interpret abnormal commands received through the communication channel based on the communicated position; A device comprising:

18. each of the driver units configured to obtain a characteristic of an anomaly in the actuation of the switch of the respective driver unit and to output the characteristic of the anomaly through the communication channel; 18. The device of claim 17.

19. each of the driver units is configured to respond to a corresponding characteristic of an anomaly in the actuation of another of the plurality of switches; the corresponding characteristics are received over the communication channel; 20. The device of claim 18.

20. the system controller is configured to communicate the status of the device to each of the driver units over the bus; 18. The device of claim 17.

21. each said driver unit is configured to interpret an abnormal command received over said communication channel based on the communicated status of said device; 21. The device of claim 20.

22. the system controller is further coupled to the communication channel; 18. The device of claim 17.

23. the communication channel is implemented in at least one wire of a second bus; 18. The device of claim 17.

24. the device comprises an inverter; 18. The device of claim 17.

25. A driver unit suitable for driving a transistor, said driver unit comprising: a communications interface configured to receive timing information from a system controller indicating when the transistors driven by the driver units are switched, the system controller configured to coordinate the timing of driving the transistors by the driver units in a driver unit network, the driver units including a first terminal and a second terminal both coupled to the system controller, the first terminal configured to receive the timing information and the second terminal configured to receive position information characteristic of a position of the driver unit in the network of driver units, the position information specifying a role of the gate driver unit in the gate driver unit network; a detection circuit configured to detect one or more characteristics of a state of the transistor driven by the driver unit; a fault protection control circuit coupled to the detection circuit, the fault protection control circuit configured to classify a fault in the driving of the driven transistor based on the one or more characteristics of the state of the driven transistor, the fault protection control circuit coupled to output the classification of the fault from the driver unit, the fault protection control circuit further configured to interpret corresponding classifications of faults in the driving of other of the transistors by other of the driver units based on the position of the driver unit in the network of driver units, and to respond to the corresponding classification; A driver unit comprising:

26. the fault protection control circuit is coupled to output the classification of the fault from the driver unit via a terminal and to receive the corresponding classification via the same terminal; 26. A driver unit according to claim 25.

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