Semiconductor device and method of manufacturing the same

Abstract

To improve the flatness of metal wiring.SOLUTION: A semiconductor device according to an embodiment includes a wiring layer containing a first metal as a main component, wherein the wiring layer includes a core layer containing the first metal as a main component, and a liner layer provided on at least one surface of the core layer, and the liner layer is a metal nitride layer containing the first metal as a main component and a second metal at least partially alloyed with the first metal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Metal wiring such as a molybdenum layer is sometimes used in semiconductor devices. When forming the metal wiring, a liner layer such as a metal nitride layer may be formed as a precursor before forming a layer that will become the core of the metal wiring. However, if the melting point of the liner layer is low, the liner layer may aggregate when the core layer is formed, which may deteriorate the flatness of the metal wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0301088 [Patent Document 2] US Patent Application Publication No. 2024 / 0098998 [Patent Document 3] US Patent Application Publication No. 2012 / 0306081 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the flatness of metal wiring. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a wiring layer mainly composed of a first metal, the wiring layer having a core layer mainly composed of the first metal and a liner layer provided on at least one surface of the core layer, the liner layer being a metal nitride layer mainly composed of the first metal and containing a second metal at least partially alloyed with the first metal. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram showing a schematic configuration example of a semiconductor device according to an embodiment; [Figure 2] 1 is a cross-sectional view taken along the Y direction showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 3] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 10A to 10C are enlarged cross-sectional views illustrating in order a part of the procedure of the word line replacement process according to the embodiment. [Figure 9] 10A to 10C are enlarged cross-sectional views illustrating in order a part of the procedure of the word line replacement process according to the embodiment. [Figure 10] 10A to 10C are cross-sectional views illustrating in order some steps of a method for forming a wiring layer according to another embodiment. [Figure 11] 10A to 10C are cross-sectional views illustrating in order some steps of a method for forming a wiring layer according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] [Embodiment] The configuration of the embodiment will be described in detail below with reference to the drawings. In the following embodiment, a semiconductor memory device such as a three-dimensional nonvolatile memory will be described as an example of a semiconductor device using metal wiring such as a molybdenum layer.

[0009] (Configuration example of semiconductor device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor device 1 according to an embodiment. More specifically, Fig. 1A is a cross-sectional view of the semiconductor device 1 taken along the X direction, and Fig. 1B is a schematic plan view illustrating the layout of the semiconductor device 1.

[0010] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0011] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0012] As shown in FIG. 1(a), the semiconductor device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0013] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from outside to the semiconductor device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL.

[0014] 1(a) and 1(b), a memory region MR is arranged in the center in the X direction of the plurality of word lines WL, etc., and staircase regions SR are arranged at both ends in the X direction of the plurality of word lines WL, etc. These memory region MR and staircase region SR are divided into a plurality of regions by a plurality of plate-like portions LI that extend in the X direction and penetrate the plurality of word lines WL, etc.

[0015] The area arranged between adjacent plate-like portions LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as the erase unit for this data.

[0016] Furthermore, between plate-like portions LI adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the select gate lines SGD. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0017] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction thereof. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR. Therefore, the semiconductor device 1 of the embodiment is also a semiconductor memory device.

[0018] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0019] In this specification, the direction in which the terrace surfaces of the word lines WL and select gate lines SGD and SGS face is defined as the upper side of the semiconductor device 1.

[0020] The above-mentioned isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0021] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0022] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0023] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0024] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0025] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0026] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components including the word lines WL.

[0027] The semiconductor substrate SB above the insulating layer 50 covering the above-described configuration is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0028] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0029] Next, a detailed configuration example of the semiconductor device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view taken along the Y direction showing an example of the configuration of the semiconductor device 1 according to the embodiment.

[0030] More specifically, Figure 2(a) is a cross-sectional view of the memory region MR of the semiconductor device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0031] Fig. 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL, Fig. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS, and Fig. 2(d) is an enlarged cross-sectional view of a plate-like portion LI at the height of the word line WL and the select gate lines SGD and SGS.

[0032] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Of these, at least the intermediate source line BSL may be, for example, a conductive polysilicon layer into which impurities are diffused.

[0033] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA within the insulating layer 50 outside the laminated body LM.

[0034] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0035] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0036] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, molybdenum (Mo) layers. The insulating layer OL is, for example, a silicon oxide layer.

[0037] Here, the word lines WL and select gate lines SGD, SGS are, more specifically, metal layers of molybdenum alone. "Molybdenum alone" means that the only metal intentionally included in the constituent materials of the word lines WL, etc., is molybdenum. "Molybdenum alone" also means that the proportion of molybdenum in the word lines WL, etc. is the highest, and that there are no other components, such as impurities, that may be mixed in during the manufacturing process that have a proportion higher than that of molybdenum.

[0038] As shown in Figures 2(b) to 2(d), each of the multiple word lines WL and select gate lines SGD, SGS is covered on both sides in the stacking direction of the laminate LM with a metal nitride layer 25 and a metal oxide layer 55, in that order.

[0039] The metal nitride layer 25 is a composite metal nitride layer containing, for example, molybdenum as a main component and other metals. The fact that molybdenum is the main component in the metal nitride layer 25 means, for example, that the proportion of molybdenum in the constituent materials of the metal nitride layer 25 is the highest, and the proportions of other metals are lower than the proportion of molybdenum. In this case, the proportion of other metals relative to molybdenum in the metal nitride layer 25 is preferably, for example, 0.5 atomic % or more and 3 atomic % or less. It also means that there are no other components, such as impurities, that may be mixed in during the manufacturing process that have a proportion higher than that of molybdenum.

[0040] The other metal may be a metal that has the property of being alloyed with molybdenum, such as titanium (Ti), aluminum (Al), nickel (Ni), niobium (Nb), or cobalt (Co).

[0041] Therefore, the other metals listed above are at least partially or entirely alloyed with molybdenum in the metal nitride layer 25, and the metal nitride layer 25 can also be said to be a molybdenum alloy layer. Furthermore, due to the alloying of the other metals with molybdenum, the melting point of the metal nitride layer 25 becomes higher than that of a metal layer that does not contain other metals that alloy with molybdenum, such as the word line WL, or a metal nitride layer.

[0042] As will be described later, the metal nitride layer 25 is a layer that serves as a precursor when forming the word lines WL and the select gate lines SGD, SGS, such as a molybdenum layer.

[0043] The metal oxide layer 55 is, for example, an aluminum oxide (Al2O3) layer, and functions as a block insulating layer in the memory cells MC, which will be described later.

[0044] 2(a), the upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53 each constitute a part of the insulating layer 50 in FIG.

[0045] As described above, the laminate LM is divided in the Y direction by a plurality of plate-like portions LI. That is, the plate-like portions LI are aligned in the Y direction and extend in the stacking direction and the X direction of the laminate LM.

[0046] In this way, the plate-shaped portion LI extends continuously within the stack LM from one end to the other end in the X direction of the stack LM. The plate-shaped portion LI also penetrates the stack LM and the upper source line DSLb to reach the intermediate source line BSL.

[0047] The plate-like portion LI has, for example, a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or alternatively, the plate-like portion LI has, for example, a bowing shape in which the width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0048] Each of the plate-shaped portions LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0049] The insulating layer 54 covers the side walls of the plate-shaped portion LI that face each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54. However, instead of the conductive layer 24, a plate-shaped member filled with an insulating layer may penetrate the laminate LM and extend in the X direction, thereby dividing the laminate LM in the Y direction.

[0050] FIG. 2(d) shows the details of the layer structure of the word lines WL, select gate lines SGD, SGS, etc., the metal nitride layer 25, and the metal oxide layer 55 in the vicinity of the plate-shaped portion LI.

[0051] 2(d), of the metal nitride layer 25 and the metal oxide layer 55 covering both surfaces Pw of the word lines WL, etc. in the stacking direction, the metal oxide layer 55 extends from both surfaces Pw of the word lines WL, etc. on the side surface of the plate-shaped portion LI to the end surface Eo of the insulating layer OL facing the side surface of the plate-shaped portion LI. In other words, at the end surface Eo of the insulating layer OL, the metal oxide layer 55 is interposed between the insulating layer OL and the insulating layer 54 of the plate-shaped portion LI.

[0052] Between the plate-like portions LI adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the upper layer portion of the stacked body LMb. These isolation layers SHE are insulating layers 56, such as silicon oxide layers, which penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0053] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped portions LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0054] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0055] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0056] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0057] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0058] More specifically, the channel layer CN is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. That is, the memory layer ME is disposed on the side surface of the pillar PL except for the depth of the intermediate source line BSL. The memory layer ME is also disposed on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0059] As described above, the channel layer CN further penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME to reach the depth of the lower source line DSLa and is in contact with the intermediate source line BSL at its side, thereby electrically connecting the channel layer CN to the source lines SL including the intermediate source line BSL.

[0060] The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is further connected to the bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0061] 2(a), plugs CH are connected only to three of the six pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 2(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a) via plugs CH not shown in Fig. 2(a).

[0062] As shown in FIGS. 2(b) and 2(c), the memory layer ME has a stacked structure including a block insulating layer BK, a tunnel insulating layer TN, and a charge storage layer CT.

[0063] The block insulating layer BK, the tunnel insulating layer TN, and the core layer CR of the memory layer ME are, for example, silicon oxide layers, etc. The charge storage layer CT is, for example, a silicon nitride layer, etc. The channel layer CN and the cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0064] As shown in Figure 2(b), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL in portions facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0065] In addition, select gates STD are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGD0 and SGD1 above the word lines WL, and select gates STS are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGS0 and SGS1 below the word lines WL.

[0066] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0067] 2(b) and 2(c) show the details of the layer structure of the word lines WL, the metal nitride layer 25, and the metal oxide layer 55 in the vicinity of the pillars PL.

[0068] That is, the metal nitride layer 25 and the metal oxide layer 55 covering both surfaces Pw of the word lines WL etc. in the stacking direction both extend from both surfaces Pw of the word lines WL etc. to the end surfaces Ew of the word lines WL etc. facing the side surfaces of the pillar PL. That is, on the end surfaces Ew of the word lines WL etc., the metal nitride layer 25 and the metal oxide layer 55 are interposed, in this order from the word line WL etc. side, between the word lines WL etc. and the block insulating layer BK of the pillar PL.

[0069] In the semiconductor device 1 of the embodiment, the word lines WL and the select gate lines SGD, SGS are an example of a core layer included in the wiring layer, and the metal nitride layer 25 is an example of a liner layer included in the wiring layer. Also, the configuration including the word lines WL, the select gate lines SGD, SGS, and the metal nitride layer 25 is an example of a wiring layer.

[0070] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described with reference to Figures 3 to 9. Of Figures 3 to 9, Figures 3 to 7 are views illustrating in order some of the steps of the method for manufacturing the semiconductor device 1 according to the embodiment. Figures 3 to 7 show a cross section along the Y direction of a region that will later become the memory region MR.

[0071] As shown in FIG. 3(a), a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are formed in this order on a support substrate SS.

[0072] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate. The insulating layer 60 (see FIG. 2, etc.) may be formed on the upper surface of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0073] A stacked body LMsa is formed on the upper source line DSLb, in which multiple insulating layers NL and multiple insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become the word lines WL or the select gate lines SGS.

[0074] After that, although not shown, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsa multiple times.

[0075] That is, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away one by one. Then, by processing using oxygen plasma or the like, the edges of the mask pattern are recessed to expose the top surface of the laminate LMsa anew, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the laminate LMsa is formed with a stepped shape at both ends in the X direction.

[0076] As shown in Figure 3(b), multiple memory holes MHa are formed in the stack LMsa, extending in the stacking direction. The multiple memory holes MHa penetrate the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, and reach the lower source line DSLa. These memory holes MHa will later become the lower structure of the pillar PL.

[0077] 3(c), these memory holes MHa are filled with a sacrificial layer 27 such as an amorphous silicon layer or a CVD-carbon layer, thereby forming pillars PLc in which the sacrificial layer 27 is filled in the multiple memory holes MHa.

[0078] As shown in Fig. 3(d), a laminate LMsb is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, covering the laminate LMsa. The insulating layers NL of the laminate LMsb function as sacrificial layers that will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0079] After this, although not shown, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the processing performed on the laminate LMsa described above.

[0080] At this time, the uppermost step of the staircase portion already formed in the laminate LMsa and the lowermost step of the staircase portion formed in the laminate LMsb are brought close to each other to form a staircase shape that is continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. As a result, the laminates LMsa and LMsb are formed with staircase regions SR having a staircase shape extending from the laminate LMsa to the laminate LMsb, at both ends in the X direction.

[0081] As shown in Fig. 4(a), multiple memory holes MHb are formed through the stack LMsb and connected to the multiple pillars PLc already formed in the stack LMsa. The memory holes MHb will later become the upper structure of the pillars PL.

[0082] 4(b), the sacrificial layer 27 is removed from the pillar PLc at the bottom of the memory hole MHb, thereby opening a memory hole MHa at the bottom of each of the memory holes MHb, and forming a plurality of memory holes MH that penetrate the stacks LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN and reach the lower source line DSLa.

[0083] In addition, if the sacrificial layer 27 filled in the pillars PLc is a CVD-carbon layer or the like, when the mask pattern or the like used in forming the memory holes MHb in Figure 4(a) above is removed by ashing using oxygen plasma or the like, the sacrificial layer 27 can be removed all at once from these pillars PLc.

[0084] As shown in Figure 4(c), the memory layer ME, channel layer CN, and core layer CR are formed in this order in the memory hole MH. As a result, the memory layer ME and channel layer CN are formed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the core layer CR is filled in the center of the memory hole MH. The memory layer ME, channel layer CN, and core layer CR are also formed in this order on the top surface of the stacked body LMsb.

[0085] As shown in Fig. 4(d), the core layer CR, the channel layer CN, and the memory layer ME on the upper surface of the laminate LMsb are sequentially removed by CMP (Chemical Mechanical Polishing) etc. Also, a recess DN is formed at the upper end of the core layer CR and the channel layer CN.

[0086] 5(a), a cap layer CP is formed in the recess DN at the upper end of the memory hole MH. The cap layer CP is also formed on the upper surface of the stacked body LMsb.

[0087] As shown in FIG. 5(b), the cap layer CP on the top surface of the stacked body LMsb is removed by CMP or the like, and a cap layer CP is formed to be disposed at the upper end of the memory hole MH.

[0088] As shown in Figure 5(c), an insulating layer OL is deposited on the top layer of the laminate LMsb, which has been thinned by CMP or other methods. This forms a pillar PL in which the cap layer CP is buried in the top insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and only a portion of the side of the channel layer CN is exposed from the memory layer ME.

[0089] 6(a), a slit ST is formed that penetrates the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. Insulating layers 54s are formed on side walls of the slit ST that face each other in the Y direction. The slit ST also extends in the X direction within the stacked bodies LMsa, LMsb.

[0090] As shown in FIG. 6(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0091] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs. At this time, since the sidewalls of the slits ST are protected by the insulating layer 54s, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well.

[0092] As shown in Fig. 6(c), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figs. 2(b) and (c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0093] 6(d), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0094] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0095] As shown in FIG. 7(a), the insulating layer 54s on the sidewall of the slit ST is temporarily removed.

[0096] 7(b), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0097] The laminates LMga and LMgb, which include multiple gap layers GP, have a fragile structure. The multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layers OL remaining in the laminates LMga and LMgb from bending and prevents the laminates LMga and LMgb from being distorted or broken.

[0098] 7(c), a source gas of a conductive material such as molybdenum is injected into the laminates LMga, LMgb through the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0099] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0100] Thereafter, an insulating layer 54 is formed on the sidewall of the slit ST, and the conductive layer 24 is filled in the insulating layer 54 to form the plate-like portion LI. However, the plate-like member may be formed by filling the insulating layer 54 or the like in the slit ST without forming the conductive layer 24.

[0101] Thereafter, a trench is formed through one or more conductive layers, including the top conductive layer of the laminated body LMb, and an insulating layer 56 is filled into the trench to form a separation layer SHE that divides these conductive layers into the pattern of the select gate line SGD.

[0102] Furthermore, a plurality of contacts CC are formed from the upper side of the staircase region SR, reaching the word lines WL and select gate lines SGD, SGS that constitute each step of the staircase structure of the staircase region SR.

[0103] An insulating layer 52 is formed on the upper surface of the laminate LM, and plugs CH connected to the pillars PL and plugs connected to the contacts CC are formed through the insulating layer 52. An insulating layer 53 is further formed on the insulating layer 52, and bit lines BL connected to the plugs CH and upper layer wiring connected to the contacts CC via the plugs are formed. Electrode pads and the like for electrical conduction with the peripheral circuit CBA are also formed on the upper surface of the insulating layer 53.

[0104] The plugs CH and the bit lines BL may be formed collectively by using, for example, a dual damascene method.

[0105] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0106] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0107] In this manner, the semiconductor device 1 of the embodiment is manufactured.

[0108] Next, details of the replacement process of the word lines WL will be described with reference to Figures 8 and 9. Figures 8 and 9 are enlarged cross-sectional views illustrating in order a part of the procedure of the replacement process of the word lines WL according to the embodiment.

[0109] More specifically, Figures 8(Aa) to 8(Ad) and 9(Aa) to 9(Ac) show a cross section of a memory hole MH at the height position of any insulating layer NL, gap layer GP, or word line WL, and Figures 8(Ba) to 8(Bd) and 9(Ba) to 9(Bc) show a cross section of a slit ST at the height position of any insulating layer NL, gap layer GP, or word line WL.

[0110] 8(Aa) and 8(Ba), the pillars PL and slits ST are already formed in the stacks LMsa and LMsb including the insulating layer NL before replacement. The end faces En and Eo of the insulating layers NL and OL face the side surfaces of the pillars PL and the inside of the slits ST, respectively.

[0111] 8(Ab) and 8(Bb), when a remover for the insulating layer NL, such as hot phosphoric acid, is introduced into the stacks LMsa and LMsb through the slits ST, the insulating layer NL is removed, and gap layers GP are formed between the insulating layers OL. This results in the stacks LMga and LMgb. The inside of the slits ST is connected to the newly formed gap layers GP on the side, and some of the side surfaces Ep of the pillars PL face the gap layers GP.

[0112] Thereafter, as will be described below, a metal oxide layer 55, a metal nitride layer 25, and a word line WL are formed in the gap layer GP in this order by, for example, atomic layer deposition (ALD) or the like.

[0113] As shown in FIGS. 8(Ac) and 8(Bc), the source gas of the metal oxide layer 55 is supplied into the gap layer GP to form the metal oxide layer 55.

[0114] At this time, when the metal oxide layer 55 is an aluminum oxide layer or the like, a source gas such as aluminum chloride (AlCl3) gas, which is a source of aluminum, and an oxygen-containing gas such as oxygen gas are supplied into the gap layer GP. These source gases may be supplied in parallel so that there is at least a period when they are supplied simultaneously, or they may be supplied simultaneously throughout by starting and stopping their supply at the same time. Alternatively, these source gases may be supplied alternately one by one repeatedly.

[0115] In this case, the aluminum source gas is supplied for a period of time required for an aluminum layer having a thickness of one to several atoms to be formed, and then the oxygen-containing gas is supplied for a period of time required for the aluminum layer having a thickness of one to several atoms to be oxidized. By repeating this supply cycle of the aluminum source gas and the oxygen-containing gas until an aluminum oxide layer having a desired thickness is obtained, metal oxide layers 55 are formed on the upper and lower surfaces Po of the insulating layer OL exposed above and below the gap layer GP.

[0116] In the vicinity of the pillar PL, the metal oxide layer 55 is formed on the top and bottom surfaces Po of the insulating layer OL, and is also formed on the side surfaces Ep of the pillar PL exposed in the gap layer GP from the top and bottom surfaces of the insulating layer OL. Meanwhile, in the vicinity of the slit ST, the metal oxide layer 55 is also formed on the end surfaces Eo of the insulating layer OL facing into the slit ST from the top and bottom surfaces Po of the insulating layer OL.

[0117] As shown in FIGS. 8(Ad) and 8(Bd), a source gas for the metal nitride layer 25 is supplied into the gap layer GP on which the metal oxide layer 55 has been formed, thereby forming the metal nitride layer 25.

[0118] At this time, if the metal nitride layer 25 is a composite metal nitride layer containing molybdenum as its main component, a raw material gas such as molybdenum dioxide dichloride (MoO2Cl2) gas, which is a raw material for molybdenum, a raw material gas for other metals such as titanium, aluminum, nickel, niobium, or cobalt, and a nitrogen-containing gas such as ammonia gas are supplied into the gap layer GP.

[0119] In this case, it is preferable to adjust the ratio of the supply amount of the source gas of the other metal to the source gas of molybdenum so that the ratio of the other metal to molybdenum in the metal nitride layer 25 is 0.5 atomic % or more and 3 atomic % or less. Here, the supply amount ratio of these source gases is calculated from the supply amount of each of these source gases per unit time and the total supply time.

[0120] When the other metal is titanium, aluminum, nickel, niobium, or cobalt, the source gas may be, for example, a metal chloride gas such as titanium chloride (TiCl4) gas, aluminum chloride (AlCl3) gas, nickel chloride (NiCl2) gas, or niobium chloride (NbCl5) gas. In addition to a nitrogen-containing gas such as ammonia gas, a reducing gas such as hydrogen (H2) gas may be supplied to promote the nitriding reaction of each metal by the nitrogen-containing gas.

[0121] When supplying these source gases, two or more gases or all gases may be supplied in parallel so that there is at least a period in which they are supplied simultaneously, or two or more gases or all gases may be supplied simultaneously by starting and stopping the supply at the same time, or these source gases may be supplied alternately one by one repeatedly.

[0122] In this case, the molybdenum source gas and the other metal source gas can be supplied for a period sufficient to form a metal layer having a thickness of one to several atoms. The nitrogen-containing gas is supplied for a period sufficient to nitride the metal layer having a thickness of one to several atoms. As mentioned above, a reducing gas may be supplied together with the nitrogen-containing gas.

[0123] In this case, the order in which the source gas of molybdenum, the source gas of the other metal, and the nitrogen-containing gas are supplied is not particularly limited. For example, the source gas of one metal may be supplied first, the source gas of the other metal may be supplied, and then the nitrogen-containing gas may be supplied, or the source gas of one metal may be supplied, the nitrogen-containing gas may be supplied, the source gas of the other metal may be supplied, and then the nitrogen-containing gas may be supplied. By repeating the above supply cycle until a composite metal nitride layer of the desired thickness is obtained, a metal nitride layer 25 is formed via a metal oxide layer 55 on the upper and lower surfaces Po of the insulating layer OL exposed above and below the gap layer GP.

[0124] Furthermore, in the vicinity of the pillar PL, the metal nitride layer 25, like the metal oxide layer 55, is formed on the upper and lower surfaces Po of the insulating layer OL via the metal oxide layer 55, and is also formed from the upper and lower surfaces Po of the insulating layer OL to the side surfaces Ep of the pillar PL exposed in the gap layer GP via the metal oxide layer 55. Meanwhile, in the vicinity of the slit ST, the metal nitride layer 25, like the metal oxide layer 55, is also formed from the upper and lower surfaces Po of the insulating layer OL to the end surfaces Eo of the insulating layer OL facing into the slit ST via the metal oxide layer 55.

[0125] As described above, by forming the metal nitride layer 25 by adding other metals in addition to the main component molybdenum, the melting point of the metal nitride layer 25 can be made higher than, for example, a metal nitride layer containing molybdenum as the main component without any other metals.

[0126] As shown in FIGS. 9A and 9B, the word lines WL are formed by supplying a source gas of the metal that constitutes the word lines WL into the gap layer GP on which the metal oxide layer 55 and the metal nitride layer 25 are formed.

[0127] At this time, if the word line WL is a molybdenum layer containing molybdenum as a main component, a source gas such as molybdenum dioxide dichloride (MoO2Cl2) gas, which is a source of molybdenum, is supplied into the gap layer GP. As a result, a molybdenum layer is formed on the upper and lower surfaces Po of the insulating layer OL via the metal oxide layer 55 on the metal nitride layer 25 already formed, with a thickness of one to several atoms.

[0128] Furthermore, by forming the molybdenum layer using the metal nitride layer 25 as an underlayer, the metal nitride layer 25 acts as a precursor, facilitating the formation of nuclei for the molybdenum layer. As a result, the deposition rate of the molybdenum layer can be increased. Furthermore, by using a precursor such as the metal nitride layer 25, the morphology of the molybdenum layer can be improved, reducing unevenness and suppressing the generation of voids and the like in the molybdenum layer.

[0129] Furthermore, it is preferable to form the molybdenum layer at a high temperature equal to or higher than a predetermined temperature. This allows the deposition rate of the molybdenum layer to be further increased. However, in this case, the metal nitride layer 25 underlying the molybdenum layer must be heat-resistant. As described above, when forming the metal nitride layer 25, other metals are added to the molybdenum to increase the melting point of the metal nitride layer 25, thereby providing the metal nitride layer 25 with sufficient heat resistance.

[0130] As described above, by continuing to supply the molybdenum source gas for a predetermined period of time, the voids remaining in the gap layer GP are filled with a molybdenum layer, forming multiple word lines WL, thereby forming stacks LMa and LMb, and the word lines WL have end faces Ew that face the side surfaces of the pillars PL.

[0131] When the word lines WL are formed, the select gate lines SGD and SGS are also formed in the same manner. However, as described above, at this point, the select gate line SGD is in a state before being separated by the separation layer SHE.

[0132] After the formation of the word lines WL and the select gate lines SGD and SGS, the slits ST are partially or entirely filled with a molybdenum layer.

[0133] 9(Ab) and 9(Bb), the molybdenum layer filling the slit ST is removed. As a result, the word line WL has an end face Ew facing the inside of the slit ST. Also, the metal nitride layer 25 formed on the end face Eo of the insulating layer OL facing the inside of the slit ST is exposed again.

[0134] Furthermore, the metal nitride layer 25 formed on the end surface Eo of the insulating layer OL and exposed in the slit ST is removed. This prevents the word lines WL of different layers to be formed subsequently from becoming electrically connected to each other via the metal nitride layer 25 on the end surface Eo of the insulating layer OL. At this time, the metal oxide layer 55 on the end surface Eo of the insulating layer OL may or may not be removed together with the metal nitride layer 25. This is because the metal oxide layer 55 has almost no conductivity, and there is no concern that the word lines WL of different layers will become electrically connected to each other via the metal oxide layer 55.

[0135] 9(Ac) and 9(Bc), an insulating layer 54 is formed on the sidewall of the slit ST, and a conductive layer 24 is formed in the remaining gap in the slit ST, thereby forming a plate-like portion LI.

[0136] In the replacement process of the word lines WL, etc., the metal oxide layer 55, the metal nitride layer 25, and the word lines WL are formed by the ALD method, etc. However, the metal oxide layer 55, the metal nitride layer 25, and the word lines WL may be formed by other methods such as the chemical vapor deposition (CVD) method.

[0137] (Overview) In semiconductor devices, the use of a molybdenum layer, which has excellent microfabrication properties, for metal wiring, etc., can further increase the integration density of the semiconductor device. When a molybdenum layer is used for metal wiring, etc., a liner layer, such as a molybdenum nitride layer, which serves as a precursor, may be formed prior to the molybdenum layer. This is because if a film is formed using molybdenum alone without using a precursor, the formation of the molybdenum layer hardly progresses.

[0138] However, if high-temperature conditions are used during the deposition of the molybdenum layer, the liner layer, such as a molybdenum nitride layer, may melt and move within the layer, causing aggregation, which may result in a deterioration in the flatness of the entire metal wiring.On the other hand, if the molybdenum layer is deposited under low-temperature conditions, the deposition rate of the molybdenum layer decreases, resulting in a decrease in productivity.

[0139] The semiconductor device 1 of the embodiment includes the word line WL containing molybdenum as a main component and the metal nitride layer 25. The metal nitride layer 25 contains molybdenum as a main component and also contains another metal at least partially alloyed with the molybdenum.

[0140] This prevents the melting point of the metal nitride layer 25 from increasing and causing aggregation of the metal nitride layer 25, even when high temperature conditions are used in forming the word lines WL. This makes it possible to improve the flatness of the word lines WL and the metal nitride layer 25 while increasing productivity.

[0141] According to the semiconductor device 1 of the embodiment, the other metal in the metal nitride layer 25 is at least one of titanium, aluminum, nickel, niobium, and cobalt. It is known that when these metals are added to molybdenum, they partially or completely alloy with molybdenum and increase the melting point of the alloyed molybdenum. This increases the melting point of the metal nitride layer 25.

[0142] [Other embodiments] In the above-described embodiment, the semiconductor device 1 includes a stack LM having a two-tier structure in which two stacks LMa and LMb are stacked one above the other. However, the configuration of the stack is not limited to two tiers, and may be one tier, or three or more tiers.

[0143] In the above-described embodiment, the pillars PL and the like are connected to the source lines SL at the side surfaces of the channel layers CN, but this is not limiting. For example, the pillars may be configured so that the memory layer at the bottom of the pillars is removed and the lower end of the channel layer is connected to the source lines.

[0144] In the above-described embodiment, the peripheral circuits CBA and CUA are arranged above or below the stacked body LM. However, the peripheral circuits may be arranged on the same layer as the stacked body. In this case, the stacked body can be formed at a different position from the peripheral circuits on the semiconductor substrate on which the peripheral circuits are formed.

[0145] In the above-described embodiment, the semiconductor device 1 is a semiconductor memory device such as a three-dimensional nonvolatile memory. However, the wiring layer including the core layer and liner layer described above can also be applied to other semiconductor devices such as a DRAM (Dynamic Random Access Memory) or a logic semiconductor. When applied to a semiconductor device other than a three-dimensional nonvolatile memory, the wiring layer may be formed by a method other than a replacement process. Other examples of methods for forming the wiring layers WRx and WRy are shown in the following Figures 10 and 11.

[0146] 10 and 11 are cross-sectional views illustrating, in order, some steps of a method for forming wiring layers WRx and WRy according to another embodiment. In the example of Fig. 10, the wiring layer WRx is formed by a damascene method, and in the example of Fig. 11, the wiring layer WRy is formed using lithography and etching techniques.

[0147] As shown in Fig. 10(a), an insulating layer 50x such as a silicon oxide layer is formed on an underlayer 60x made of an arbitrary material, and as shown in Fig. 10(b), a plurality of grooves GR are formed in the insulating layer 50x.

[0148] As shown in Fig. 10(c), a liner layer 25x, which is a nitride layer containing molybdenum as a main component and other metals, similar to the metal nitride layer 25 described above, is formed on the top surface of the insulating layer 50x and on the side and bottom surfaces of the grooves GR. As shown in Fig. 10(d), a core layer 26x, which is mainly composed of molybdenum, similar to the word lines WL described above, is filled into the grooves GR of the insulating layer 50x on which the liner layer 25x has been formed. At this time, the core layer 26x is also formed on the top surface of the insulating layer 50x via the liner layer 25x.

[0149] 10(e), the core layer 26x and the liner layer 25x formed on the upper surface of the insulating layer 50x are sequentially removed by CMP, etc. As a result, a wiring layer WRx is formed, which includes the core layer 26x and the liner layer 25x covering the side and bottom surfaces of the core layer 26x.

[0150] This method of forming the wiring layer WRx etc. using the groove GRx formed in the insulating layer 50x as a template is also called the damascene method. On the other hand, in the method shown in Fig. 11 described below, a wiring layer WRy having a desired shape is obtained by performing an etching process using a resist pattern 70 as a mask.

[0151] As shown in FIG. 11(a), an insulating layer 50y such as a silicon oxide layer is formed on an underlying layer 60y made of an arbitrary material.

[0152] As shown in Fig. 11(b), a liner layer 25y, which is a nitride layer containing molybdenum as a main component and other metals, similar to the above-described metal nitride layer 25, is formed on the upper surface of the insulating layer 50y. As shown in Fig. 11(c), a core layer 26y, which is mainly composed of molybdenum, similar to the above-described word line WL, is formed on the liner layer 25y. In addition, a resist pattern 70, such as a photoresist layer, is formed on the upper surface of the core layer 26y.

[0153] 11(d), using the resist pattern 70 as a mask, the core layer 26y and the liner layer 25y are sequentially processed by etching, etc. As a result, a wiring layer WRy including the core layer 26y and the liner layer 25y covering the bottom surface of the core layer 26y is formed.

[0154] 11(e), after removing the resist pattern 70, an insulating layer 40y such as a silicon oxide layer is formed to cover the wiring layer WRy. As shown in FIG. 11(f), the insulating layer 40y is polished by CMP or the like to expose the upper surface of the wiring layer WRy at the upper surface of the insulating layer 40y.

[0155] As described above, the wiring layers WRx and WRy can be formed by various methods other than the above-mentioned replacement process. However, in the example of Figures 10 and 11, the fine wiring layer WRx can be formed more easily by using the damascene method shown in Figure 10, which has excellent microfabrication capabilities.

[0156] In the examples of FIGS. 10 and 11, the wiring layer may be formed by the ALD method or the like, as in the above-described embodiment, or may be formed by the CVD method or the like.

[0157] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0158] 1...semiconductor device, 25...metal nitride layer, 25x, 25y...liner layer, 26x, 26y...core layer, 55...metal oxide layer, BK...block insulating layer, CC...contact, CN...channel layer, CT...charge storage layer, LI...plate-shaped portion, LM...stacked body, MC...memory cell, MR...memory region, NL, OL...insulating layer, PL...pillar, SR...staircase region, SGD, SGS...select gate line, ST...slit, TN...tunnel insulating layer, WL...word line.

Claims

1. a wiring layer containing a first metal as a main component; The wiring layer is a core layer containing the first metal as a main component; a liner layer provided on at least one surface of the core layer, The liner layer comprises: a metal nitride layer containing the first metal as a main component and a second metal at least partially alloyed with the first metal; Semiconductor device.

2. The liner layer comprises: a melting point higher than that in the absence of the second metal; The semiconductor device according to claim 1 .

3. the first metal is Mo; the second metal is at least one of Ti, Al, Ni, Nb, or Co; The semiconductor device according to claim 1 .

4. a stacked body in which a plurality of word lines are stacked and spaced apart from each other; a pillar having a semiconductor layer extending within the stack in a stacking direction of the stack, each of the plurality of word lines is the wiring layer; The semiconductor device according to claim 1 .

5. The liner layer comprises: a metal oxide layer provided on both surfaces of the core layer in the stacking direction and covered with the metal oxide layer; The semiconductor device according to claim 4 .

6. a laminate in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated one by one; a pillar having a semiconductor layer extending within the stack in a stacking direction of the stack, The plurality of wiring layers include: a core layer containing a first metal as a main component; and liner layers provided on both sides of the core layer in the stacking direction, The liner layer comprises: a nitride layer containing the first metal as a main component and a second metal at least partially alloyed with the first metal; Semiconductor device.

7. The liner layer comprises: the insulating film is provided on both surfaces of the core layer in the stacking direction and on an end surface of the core layer facing the side surface of the pillar; The semiconductor device according to claim 6.

8. a plate-like portion extending in the stacking direction and a first direction intersecting the stacking direction within the stacked body and dividing the stacked body in a second direction intersecting the stacking direction and the first direction; a metal oxide layer provided on each of both surfaces of the plurality of wiring layers in the stacking direction, The metal oxide layer is the insulating layer is provided on each of both surfaces of the plurality of wiring layers in the stacking direction, and on each of end surfaces of the plurality of insulating layers facing the side surface of the plate-like portion. The semiconductor device according to claim 6.

9. The liner layer comprises: a melting point higher than that in the absence of the second metal; The semiconductor device according to claim 6.

10. the first metal is Mo; the second metal is at least one of Ti, Al, Ni, Nb, or Co; The semiconductor device according to claim 6.

11. a core layer containing a first metal as a main component; a liner layer provided on at least one surface of the core layer, The formation of the wiring layer is a first gas that is a material for the first metal, a second gas that is a material for the second metal, and a nitrogen-containing gas are supplied to a surface on which the wiring layer is to be formed, to form the liner layer that is a metal nitride layer that contains the first metal as a main component and the second metal that is at least partially alloyed with the first metal; supplying the first gas onto the liner layer to form the core layer; A method for manufacturing a semiconductor device.

12. the liner layer is formed using atomic layer deposition or chemical vapor deposition; At least two of the first gas, the second gas, and the nitrogen-containing gas are supplied in parallel. The method for manufacturing a semiconductor device according to claim 11 .

13. the liner layer is formed using atomic layer deposition or chemical vapor deposition; supply start and supply stop of at least two or more of the first gas, the second gas, and the nitrogen-containing gas are performed at the same timing; The method for manufacturing a semiconductor device according to claim 11 .

14. the first gas is a source gas of Mo, The second gas is a source gas of at least one of Ti, Al, Ni, Nb, and Co. The method for manufacturing a semiconductor device according to claim 11 .

15. forming a first stacked body in which a plurality of insulating layers are stacked and spaced apart from each other; The wiring layer is formed in the gaps between the insulating layers, The method for manufacturing a semiconductor device according to claim 11 .

16. The liner layer comprises: supplying the first gas, the second gas, and the nitrogen-containing gas into gaps between the insulating layers to form a film on each of both surfaces in a stacking direction of the insulating layers exposed in the gaps between the insulating layers; The core layer is forming the insulating layer by supplying the first gas onto the liner layers formed on both surfaces of the insulating layers; The method for manufacturing a semiconductor device according to claim 15.

17. Before forming the wiring layer, further comprising forming a metal oxide layer on both surfaces of the plurality of insulating layers. The method for manufacturing a semiconductor device according to claim 16.

18. The formation of the first laminate includes: forming a second laminate in which the plurality of insulating layers and the plurality of sacrificial layers are alternately laminated one by one; removing the plurality of sacrificial layers from the second stack; The method for manufacturing a semiconductor device according to claim 16.

19. The formation of the first laminate includes: forming a pillar having a semiconductor layer penetrating the second stacked body in a stacking direction of the plurality of sacrificial layers; The method for manufacturing a semiconductor device according to claim 18.

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