STL / TTL modulator and STL / TTL demodulator

Abstract

To avoid overflow and underflow of a modulator input buffer for a terrestrial digital broadcast and a next-generation terrestrial broadcast and to reproduce and provide a modulator clock for slave synchronization of each broadcast program signal.SOLUTION: A STL / TTL modulator (100) in a system for multiplexing a plurality of broadcast program signals with counter values added thereto by STL / TTL and transmitting the multiplexed signals includes counter sections (14, 17) for counting clocks synchronized with a modulation clock of the STL / TTL and a plurality of counter value adding sections (151-15N, 181-18M) for adding the counter values supplied from the counter sections (14, 17) to the packets to generate broadcast program signals with counter values at timing when the packets of the plurality of broadcast program signals arrive.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to an STL / TTL modulator and an STL / TTL demodulator. [Background technology]

[0002] The line that wirelessly transmits terrestrial broadcasting program signals from a broadcasting station's studio or transmitting station to the transmitting station is called STL (Studio to Transmitter Link) / TTL (Transmitter to Transmitter Link). The STL / TTL transmission method (see, for example, Non-Patent Document 1) of current terrestrial digital television broadcasting (hereinafter abbreviated as "terrestrial digital broadcasting") is capable of transmitting only one broadcasting program signal (called "broadcast TS (Transport Stream)").

[0003] As shown in Figure 1, the current terrestrial digital STL / TTL modulator 700 modulates the broadcast TS as a transmission signal with an STL / TTL modulation clock (e.g., 6.693 MHz) synchronized with the terrestrial digital modulator clock (e.g., 8.127 MHz), which is then demodulated by the STL / TTL demodulator 800 at the transmitting station and outputs the terrestrial digital modulator clock and broadcast TS. By modulating with this terrestrial digital modulator clock and broadcast TS, the terrestrial digital modulator at the transmitting station can realize an SFN (Single Frequency Network) through slave synchronization of the modulator clock.

[0004] In next-generation terrestrial broadcasting (advanced terrestrial broadcasting system) compatible with 4K8K, it is expected that 4K8K broadcast program signals will be transmitted via IP (Internet Protocol) (hereinafter, this signal will be referred to as an "advanced program transmission signal"). Since it is possible to increase transmission capacity by upgrading the STL / TTL transmission system, from the perspective of securing channels and sharing facilities during the transition period from current terrestrial digital broadcasting to next-generation terrestrial broadcasting, multiplexing and transmitting multiple broadcast program signals (broadcast TS and advanced program transmission signal, broadcast TS and broadcast TS, etc.) via STL / TTL is being considered (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2022-178649 [Non-patent literature]

[0006] [Non-Patent Document 1] Murakami, et al., "Outline of Terrestrial Digital Broadcasting STL / TTL (TS Transmission Method) Specifications," 2003, Institute of Image Information and Television Engineers Annual Conference, 4-7 Summary of the Invention [Problem to be solved by the invention]

[0007] As shown in Figure 2, when multiple broadcast program signals are multiplexed and transmitted using STL / TTL, the advanced STL / TTL modulation clock (e.g., 20.078 MHz) can only synchronize with the modulator clock of one of the broadcast program signals, which poses a problem in that the modulator clock of each broadcast program signal cannot be reproduced and provided on the demodulation side for slave synchronization.

[0008] Furthermore, if a broadcast program signal other than one reproduced on the demodulation side is output at an interval based on the modulator clock of that broadcast program signal, there is a problem that an overflow or underflow occurs in the input buffer of the modulator, and modulation may not be performed normally. In particular, in terrestrial digital broadcasting, the three signals of broadcast TS, F_sync (a terrestrial digital frame synchronization signal), and modulator clock are synchronized, and timing constraints are strict.

[0009] Conventional STL / TTL does not multiplex broadcast program signals and therefore does not have the above problem, and the technology disclosed in Patent Document 1 also does not address the above problem.

[0010] The present invention was made in consideration of these circumstances and aims to prevent overflow and underflow of modulator input buffers for terrestrial digital broadcasting and next-generation terrestrial broadcasting, and to regenerate and provide modulator clocks for slave synchronization of each broadcast program signal. [Means for solving the problem]

[0011] The gist of the present invention for solving the above problems is as follows.

[0012] (1) An STL / TTL modulator in a system that multiplexes and transmits multiple counter value-added broadcast program signals using STL / TTL, comprising: a counter unit that counts a clock synchronized with an STL / TTL modulation clock; and multiple counter value adding units that, when multiple broadcast program signal packets arrive, add the counter values ​​supplied from the counter units to the packets to generate the counter value-added broadcast program signals.

[0013] (2) An STL / TTL modulator as described in (1), comprising an FEC block construction unit that generates an FEC block by multiplexing a plurality of the counter value-added broadcast program signals, and an OFDM modulation processing unit that performs modulation processing on the FEC block to generate an OFDM signal.

[0014] (3) An STL / TTL modulator as described in (1) or (2), wherein the clock frequency of the counter unit is 27 MHz when the broadcast program signal is a broadcast TS, and 125 MHz when the broadcast program signal is an IP.

[0015] (4) An STL / TTL demodulator in a system that multiplexes and transmits multiple counter value-added broadcast program signals using STL / TTL, the STL / TTL demodulator comprising: a counter unit that counts a clock synchronized with the reproduced STL / TTL modulation clock; and multiple counter value synchronization units that output a packet for each broadcast program signal at the timing when the counter value of the packet of the counter value-added broadcast program signal and the counter value supplied from the counter unit match.

[0016] (5) An STL / TTL demodulator as described in (4) that is provided with a modulator clock recovery unit that configures a PLL based on the output interval of packets of the broadcast program signal or the interval of frames consisting of multiple packets of the broadcast program signal, and recovers and outputs the modulator clock of the broadcast program signal.

[0017] (6) An STL / TTL demodulator as described in (4) or (5), comprising an OFDM demodulation processing unit that performs demodulation processing on an OFDM signal to reproduce an FEC block, and an FEC block separation unit that performs error correction decoding processing on the FEC block, separates the multiplexed broadcast program signal with counter value, and outputs each to the counter value synchronization unit.

[0018] (7) An STL / TTL demodulator described in any one of (4) to (6), wherein the clock frequency of the counter unit is 27 MHz when the broadcast program signal is a broadcast TS, and 125 MHz when the broadcast program signal is an IP. [Effects of the Invention]

[0019] This makes it possible to send packets from the STL / TTL demodulator at the same time intervals as when they arrived at the STL / TTL modulator, preventing overflows and underflows of the modulator input buffer for terrestrial digital broadcasting and next-generation terrestrial broadcasting.It also makes it possible to recover and provide the modulator clock for slave synchronization of each broadcast program signal. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a conventional STL / TTL system. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of a conventional advanced STL / TTL system. [Figure 3A] 1 is a diagram illustrating an example of the configuration of an advanced STL / TTL transmitting device according to the present invention. [Figure 3B] 1 is a diagram showing an example of the configuration of an advanced STL / TTL receiving device according to the present invention; [Figure 4A] 1 is a diagram illustrating an example of the configuration of an advanced STL / TTL transmission device according to a first embodiment of the present invention. [Figure 4B] 1 is a diagram illustrating an example of the configuration of an advanced STL / TTL receiving device according to a first embodiment of the present invention. [Figure 5] 2 is a diagram illustrating an example of the configuration of a counter unit and a counter value adding unit in the advanced STL / TTL transmission device according to the first embodiment of the present invention. FIG. [Figure 6] 1 is a diagram illustrating an example of the configuration of a counter unit and a counter value synchronization unit in an advanced STL / TTL receiving device according to a first embodiment of the present invention. [Figure 7] 1 is a diagram illustrating an example of the configuration of a modulator clock recovery unit in an advanced STL / TTL receiver according to a first embodiment of the present invention. [Figure 8] 1 is a diagram illustrating an example of the configuration of a modulator clock recovery unit in an advanced STL / TTL receiver according to a first embodiment of the present invention. [Figure 9A] FIG. 10 is a diagram illustrating an example of the configuration of an advanced STL / TTL transmission device according to a second embodiment of the present invention. [Figure 9B]FIG. 10 is a diagram illustrating an example of the configuration of an advanced STL / TTL receiving device according to a second embodiment of the present invention. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a counter unit and a counter value adding unit in an advanced STL / TTL transmission device according to a second embodiment of the present invention. [Figure 11] FIG. 10 is a diagram illustrating an example of the configuration of a counter unit and a counter value synchronization unit in an advanced STL / TTL receiving device according to a second embodiment of the present invention. [Figure 12] FIG. 10 is a diagram illustrating an example of the configuration of a modulator clock recovery unit in an advanced STL / TTL receiver according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] First, by generalizing the present invention, an advanced STL / TTL system in which N advanced program transmission signals and M broadcast TSs are multiplexed and transmitted using advanced STL / TTL will be outlined with reference to Fig. 3. Fig. 3A is a diagram showing an example of the configuration of an advanced STL / TTL transmitter, and Fig. 3B is a diagram showing an example of the configuration of an advanced STL / TTL receiver.

[0022] The advanced STL / TTL modulator 100 shown in FIG. 3A includes counter units 14 and 17 that count clocks synchronized with an advanced STL / TTL modulation clock (hereinafter referred to as an "advanced STL / TTL modulation clock"), and counter value adding units 151 to 15 that add counter values ​​at the timing when a packet of a broadcast program signal arrives to the beginning of the packet, etc. N and 181-18 M The counter value output by the counter unit 14 is added to the counter value adding units 151 to 155. N The counter value output by the counter unit 17 is input to the counter value adding units 181 to 188. M is entered into

[0023] The advanced STL / TTL demodulator 200 shown in FIG. 3B includes counter units 25 and 29 that count clocks synchronized with the reproduced advanced STL / TTL modulated clock (hereinafter referred to as the "advanced STL / TTL reproduced modulated clock"), and counter value synchronizers 261 to 26 that output packets of the received broadcast program signal at the timing when the counter value of the packet of the received broadcast program signal and the counter value of the demodulator match. N and 301-30 M The counter value output by the counter unit 25 is synchronized with the counter value synchronizers 261 to 266. N The counter value output from the counter unit 29 is input to the counter value synchronization units 301 to 303. M is entered into

[0024] The advanced STL / TTL demodulator 200 also includes modulator clock regenerators 271 to 277 that configure a PLL based on the output interval of packets of a broadcast program signal or the interval of a frame consisting of a plurality of packets of a broadcast program signal, and regenerate and output a modulator clock of the broadcast program signal. N and 311-31 M may also be provided.

[0025] This configuration enables packets to be sent from the advanced STL / TTL demodulator 200 at the same time intervals as when they arrived at the advanced STL / TTL modulator 100, suppressing jitter and preventing overflow or underflow of the modulator input buffer for terrestrial digital broadcasting and next-generation terrestrial broadcasting. It also enables the recovery and provision of a slave synchronization modulator clock for each broadcast program signal.

[0026] When the broadcast program signal is a broadcast TS, the clock frequency of counter units 17 and 29 may be 27 MHz. When the broadcast program signal is a broadcast TS (DVB-ASI format), data is input and output to and from the broadcast TS input and output interfaces at a clock of 27 MHz. Therefore, if the clock frequency of counter units 17 and 29 is 27 MHz, matching can be achieved and jitter can be suppressed.

[0027] Furthermore, when the broadcast program signal is an advanced program transmission signal, the clock frequency of counter units 14 and 25 may be 125 MHz. When the broadcast program signal is an advanced program transmission signal (IP format), data is input and output to and from the IP input and output interfaces at a clock of 125 MHz. Therefore, if the clock frequency of counter units 14 and 25 is 125 MHz, matching can be achieved and jitter can be suppressed.

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following embodiments, an advanced STL / TTL demodulator is provided with a modulator clock recovery unit.

[0029] (First embodiment) An advanced STL / TTL system for multiplexing and transmitting a broadcast TS and a broadcast TS according to a first embodiment will be described with reference to Fig. 4. Fig. 4A is a diagram showing an example of the configuration of an advanced STL / TTL transmitter, and Fig. 4B is a diagram showing an example of the configuration of an advanced STL / TTL receiver. The advanced STL / TTL transmitter 4000 shown in Fig. 4A includes an advanced STL / TTL modulator 100, a transmitting converter 300, and a transmitting antenna 500. The advanced STL / TTL receiver 5000 shown in Fig. 4B includes a receiving antenna 600, a receiving converter 400, and an advanced STL / TTL demodulator 200.

[0030] The advanced STL / TTL modulator 100 receives broadcast TS#1, broadcast TS#2, and a modulator clock. Here, #1 and #2 represent system numbers. The modulator clock is assumed to be a system that also considers the use of a slave synchronization modulator clock according to conventional technology. The advanced STL / TTL modulator 100 includes an FEC (Forward Error Correction) block configuration unit 11, an OFDM (Orthogonal Frequency Division Multiplexing) modulation processing unit 12, a PLL unit 13, a counter unit 17, and counter value adding units 181 and 182.

[0031] The PLL unit 13 generates an advanced STL / TTL modulation clock from the input modulator clock by utilizing the relationship of the division ratio of the clock frequency, and supplies it to the OFDM modulation processing unit 12 and counter unit 17 .

[0032] The counter unit 17 generates a 27 MHz clock synchronized with the advanced STL / TTL modulated clock, operates the counter, and outputs the counter value.

[0033] When a packet of broadcast TS#1 arrives, counter value adding unit 181 adds the 27 MHz counter value supplied from counter unit 17 to the beginning of the packet or the like to generate counter-value-added broadcast TS#1, and outputs it to FEC block configuration unit 11. Also, when a packet of broadcast TS#2 arrives, counter value adding unit 182 adds the 27 MHz counter value supplied from counter unit 17 to the beginning of the packet or the like to generate counter-value-added broadcast TS#2, and outputs it to FEC block configuration unit 11.

[0034] The FEC block construction unit 11 multiplexes the counter value-attached broadcast TS#1 and the counter value-attached broadcast TS#2 into the main signal area of ​​the FEC block, adds parity of the error correction code, generates an FEC block, and outputs it to the OFDM modulation processing unit 12.

[0035] The OFDM modulation processing unit 12 performs OFDM modulation processing on the FEC block to generate an OFDM signal. Specifically, the OFDM modulation processing unit 12 interleaves the FEC block, performs symbol mapping, assigns signals to orthogonal subcarriers in the frequency domain, and configures an OFDM transmission frame together with pilot carriers, auxiliary signal carriers, etc. Next, the OFDM modulation processing unit 12 converts the signals into time-domain signals using IFFT (Inverse Fast Fourier Transform), adds guard intervals to generate OFDM symbols, performs orthogonal modulation, and outputs an IF (Intermediate Frequency) OFDM signal to the transmission converter 300.

[0036] The transmission converter 300 converts the IF OFDM signal into a predetermined RF (Radio Frequency) signal and amplifies it to a predetermined transmission output.

[0037] The transmitting antenna 500 radiates an RF OFDM signal into space.

[0038] The receive antenna 600 receives the radiated RF OFDM signal.

[0039] The receiving converter 400 amplifies and converts the desired RF OFDM signal to IF.

[0040] The advanced STL / TTL demodulator 200 has an OFDM demodulation processing unit 21, an FEC block separation unit 22, frame synchronization units 231 and 232, a PLL unit 24, a counter unit 29, counter value synchronization units 301 and 302, and modulator clock recovery units 311 and 312.

[0041] The OFDM demodulation processor 21 demodulates the received OFDM signal to reproduce the FEC block. Specifically, the OFDM demodulation processor 21 performs quadrature demodulation on the IF OFDM signal, reproduces an advanced STL / TTL modulation clock using a clock recovery circuit, performs symbol synchronization and guard interval removal, and converts the signal into a frequency domain signal using FFT (Fast Fourier Transform). Next, the OFDM demodulation processor 21 synchronizes the OFDM transmission frame, estimates propagation path information using pilot carriers, performs propagation path equalization, and performs demapping (bit likelihood detection) and deinterleaving to reproduce the FEC block.

[0042] The FEC block separation unit 22 performs error correction decoding processing on the reproduced FEC block, separates the counter value-attached broadcast TS#1 and counter value-attached broadcast TS#2 that were multiplexed in the main signal area, and outputs the counter value-attached broadcast TS#1 to the counter value synchronization unit 301 and the counter value-attached broadcast TS#2 to the counter value synchronization unit 302.

[0043] The PLL unit 24 regenerates a modulator clock from the advanced STL / TTL regenerated modulation clock by utilizing the relationship of the division ratio of the clock frequency, and outputs the clock to the outside of the advanced STL / TTL receiver 5000 .

[0044] The counter unit 29 generates a 27 MHz clock synchronized with the advanced STL / TTL regenerated modulation clock, operates the counter, and outputs the counter value to the counter value synchronizers 301 and 302 .

[0045] Counter value synchronization unit 301 outputs the packet of broadcast TS#1 to frame synchronization unit 231 at the timing when the counter value of the packet of counter value-included broadcast TS#1 matches the counter value supplied from counter unit 29, and outputs a pulse at the timing when the counter values ​​match to modulator clock recovery unit 311. Furthermore, counter value synchronization unit 302 outputs the packet of broadcast TS#2 to frame synchronization unit 232 at the timing when the counter value of the packet of counter value-included broadcast TS#2 matches the counter value supplied from counter unit 29, and outputs a pulse at the timing when the counter values ​​match to modulator clock recovery unit 312.

[0046] The frame synchronization unit 231 generates F_sync based on the timing of the frame head packet of the broadcast TS#1, adjusts the timing with the terrestrial digital modulator clock #1, and outputs the broadcast TS#1 and F_sync#1 to the outside of the advanced STL / TTL receiving device 5000. The frame synchronization unit 232 generates an F_sync signal based on the timing of the frame head packet of the broadcast TS#2, adjusts the timing with the terrestrial digital modulator clock #2, and outputs the broadcast TS#2 and F_sync#2 to the outside of the advanced STL / TTL receiving device 5000.

[0047] The modulator clock recovery unit 311 configures a PLL based on the output interval of broadcast TS#1 packets or the interval between frames made up of multiple broadcast TS#1 packets, recovers terrestrial digital modulator clock #1, and outputs it to the outside of the advanced STL / TTL receiving device 5000 and to the frame synchronization unit 231. The modulator clock recovery unit 312 configures a PLL based on the output interval of broadcast TS#2 packets or the interval between frames made up of multiple broadcast TS#2 packets, recovers terrestrial digital modulator clock #2, and outputs it to the outside of the advanced STL / TTL receiving device 5000 and to the frame synchronization unit 232.

[0048] <Counter Unit 17 and Counter Value Addition Unit 18> 5, the counter unit 17 and the counter value adding unit 18 (181, 182, ... 18 M 5 is a diagram showing an example of the configuration of the counter unit 17 and the counter value adding unit 18.

[0049] The counter unit 17 includes a PLL unit 171 and a 27 MHz counter unit 172 .

[0050] The PLL unit 171 generates a 27 MHz clock CKW synchronized with the advanced STL / TTL modulated clock and outputs it to the 27 MHz counter unit 172 .

[0051] The 27 MHz counter unit 172 counts the 27 MHz clock CKW from a predetermined reset timing, and outputs the counter value C[31:0] to the counter value adding unit 18. The counter reset timing can be an integer multiple of the advanced STL / TTL transmission frame, which is equal to or less than the maximum counter value expressed by a finite number of bits (32 bits in this example), can be easily reproduced on the receiving side, or the like.

[0052] Counter value adding unit 18 (181, 182, ... 18 M ) includes FIFO buffer units 181 and 183, a FIFO buffer control unit 182, and a combining unit 184.

[0053] When the FIFO buffer control unit 182 receives a data output ready signal RDY from the DVB-ASI receiving IC, which is the broadcast TS input I / F (Interface) unit 40, it writes the broadcast TS packet output from the D[7:0] terminal into the FIFO buffer unit 181 and writes the counter value C[31:0] into the FIFO buffer unit 183.

[0054] The combining unit 184 reads the paired counter value and broadcast TS from the FIFO buffer unit 183 and the FIFO buffer unit 181, respectively, adds the counter value to the beginning of the packet of the broadcast TS, and outputs the broadcast TS with the counter value to the FEC block configuration unit 11. The broadcast TS with the counter value has a counter value C, a header H, information D, ISDB-T information I, and a dummy P, as shown in Fig. 5, for example.

[0055] <Counter Unit 29 and Counter Value Synchronization Unit 30> 6, the counter unit 29 and the counter value synchronization unit 30 (301, 302, ... 30 M 6 is a diagram showing an example of the configuration of the counter unit 29 and the counter value synchronization unit 30.

[0056] The counter unit 29 includes a PLL unit 291 and a 27 MHz counter unit 292 .

[0057] The PLL unit 291 generates a 27 MHz clock CKW synchronized with the advanced STL / TTL regenerated modulation clock, and outputs it to the 27 MHz counter unit 292 .

[0058] The 27 MHz counter unit 292 counts the 27 MHz clock CKW from a predetermined reset timing, and outputs the counter value C'[31:0] to the counter value synchronization unit 30. The reset timing of the counter may be a timing obtained by offsetting a predetermined processing delay from the reset timing of the 27 MHz counter unit 172 on the modulator side.

[0059] Counter value synchronization unit 30 (301, 302, ... 30M ) includes a separator 301, FIFO buffer units 302 and 303, a comparator 304, and a FIFO buffer controller 305.

[0060] The separator 301 separates the counter value C[31:0] and the broadcast TS from the counter value-added broadcast TS, and writes them into the FIFO buffer unit 303 and the FIFO buffer unit 302, respectively.

[0061] The comparison unit 304 reads the counter value C[31:0] from the FIFO buffer unit 303, compares it with the counter value C'[31:0] output by the 27MHz counter unit 292, and notifies the FIFO buffer control unit 305 and the modulator clock recovery unit 31 of the matching timing as the packet period of the broadcast TS.

[0062] The FIFO buffer control unit 305 reads the broadcast TS from the FIFO buffer unit 302 at the timing when it receives a notification from the comparison unit 304 that the counter values ​​match, and transfers the broadcast TS to the frame synchronization unit 23 .

[0063] Frame synchronization unit 23 (231, 232, ... 23 M ) generates F_Sync based on the timing of the frame head packet of the broadcast TS, adjusts the timing with the terrestrial digital modulator clock, and outputs the broadcast TS and F_Sync. The broadcast TS is input to the DVB-ASI transmission IC, which is the broadcast TS output I / F unit 50, where it is converted into DVB-ASI format and output from the advanced STL / TTL demodulator 200.

[0064] <Modulator clock recovery unit 31> 7 and 8, the modulator clock recovery unit 31 (311, 312, ... 31 M ) will be described in detail. Fig. 7 is a diagram showing an example of the configuration of the modulator clock recovery unit 31 when recovering the terrestrial digital modulator clock from the packet period of the broadcast TS. Fig. 8 is an example of the configuration of the modulator clock recovery unit 31 when recovering the terrestrial digital modulator clock from the frame period of the broadcast TS.

[0065] Current terrestrial digital broadcasting is operated in mode 3 with an IFFT / FFT size of 8,192 points and a guard interval ratio of 1 / 8. With these parameters, one OFDM symbol of terrestrial digital broadcasting is 9,216 clocks, one frame (204 OFDM symbols) is 1,880,064 clocks, and since 4,608 packets of broadcast TS are transmitted at equal intervals per frame, the packet period of the broadcast TS is 408 clocks. The modulator clock recovery unit 31 shown in Figure 7 configures a PLL using this relationship and generates a terrestrial digital broadcasting modulator clock from the packet period of the broadcast TS.

[0066] The modulator clock recovery unit 31 (311, 312, ... 31) shown in FIG. M ) includes a phase comparison unit 311, a loop filter unit 312, a VCXO (Voltage Controlled Crystal Oscillator) unit 313, and a frequency division unit 314.

[0067] Specifically, the phase comparator 311 compares the phase of the signal with the packet period of the broadcast TS with the phase of the signal obtained by dividing the 8.127 MHz clock output by the VCXO unit 313 by 408 in the frequency divider 314, and outputs the difference to the loop filter unit 312.

[0068] The loop filter unit 312 smoothes the differential output and outputs it as a control voltage for the VCXO unit 313. In a steady state, the control voltage is a constant value, and the output of the VCXO unit 313 becomes a terrestrial digital modulator clock synchronized with the packet period of the broadcast TS.

[0069] The modulator clock recovery unit 31 (311, 312, ... 31) shown in FIG. M ) includes a phase comparison unit 311, a loop filter unit 312, a VCXO unit 313, and frequency division units 314 and 315.

[0070] As mentioned above, in current terrestrial digital broadcasting, the frame period of a broadcast TS consisting of 4,608 packets is 1,880,064 clocks. The modulator clock recovery unit 31 shown in Figure 8 configures a PLL using this relationship and generates a terrestrial digital broadcasting modulator clock from the frame period of the broadcast TS.

[0071] Specifically, the phase comparator 311 compares the phase of the signal obtained by dividing the packet period of the broadcast TS by 4,608 using the frequency divider 315 with the phase of the signal obtained by dividing the 8.127 MHz clock output by the VCXO unit 313 by 1,880,064 using the frequency divider 314, and outputs the difference to the loop filter unit 312.

[0072] The loop filter unit 312 smoothes the differential output and outputs it as a control voltage for the VCXO unit 313. In a steady state, the control voltage is a constant value, and the output of the VCXO unit 313 becomes a terrestrial digital modulator clock synchronized with the frame period of the broadcast TS.

[0073] (Second embodiment) An advanced STL / TTL system according to a second embodiment, which multiplexes and transmits an advanced program transmission signal and a broadcast TS, will be described with reference to Fig. 9. Fig. 9A is a diagram showing an example of the configuration of an advanced STL / TTL transmitter, and Fig. 9B is a diagram showing an example of the configuration of an advanced STL / TTL receiver. The advanced STL / TTL transmitter 4000 shown in Fig. 9A includes an advanced STL / TTL modulator 100, a transmitting converter 300, and a transmitting antenna 500. The advanced STL / TTL receiver 5000 shown in Fig. 9B includes a receiving antenna 600, a receiving converter 400, and an advanced STL / TTL demodulator 200.

[0074] The advanced program transmission signal #1, broadcast TS #1, and a modulator clock are input to the advanced STL / TTL modulator 100. The modulator clock is assumed to be a modulator clock of a system that also considers the use of a slave synchronization modulator clock according to conventional technology.

[0075] The advanced STL / TTL modulator 100 includes an FEC block configuration unit 11, an OFDM modulation processing unit 12, a PLL unit 13, counter units 14 and 17, and counter value adding units 151 and 181.

[0076] The PLL unit 13 generates an advanced STL / TTL modulation clock from the input modulator clock by utilizing the relationship of the division ratio of the clock frequency, and supplies it to the OFDM modulation processing unit 12 and counter units 14 and 17 .

[0077] Counter unit 14 generates a 125 MHz clock synchronized with the advanced STL / TTL modulated clock, operates the counter, and outputs the counter value to counter value adding unit 151. Counter unit 17 generates a 27 MHz clock synchronized with the advanced STL / TTL modulated clock, operates the counter, and outputs the counter value to counter value adding unit 181.

[0078] Counter value adding unit 151 adds the 125 MHz counter value supplied from counter unit 14 at the timing when the packet of the advanced program transmission signal arrives to the beginning of the packet, etc., and outputs the advanced program transmission signal with the counter value to FEC block configuration unit 11. Also, counter value adding unit 181 adds the 27 MHz counter value supplied from counter unit 17 at the timing when the packet of the broadcast TS arrives to the beginning of the packet, etc., and outputs the broadcast TS with the counter value to FEC block configuration unit 11.

[0079] The FEC block configuration unit 11 multiplexes the counter value-added advanced program transmission signal and the counter value-added broadcast TS into the main signal area of ​​the FEC block, adds parity of the error correction code, and outputs the multiplexed signal to the OFDM modulation processing unit 12 .

[0080] The processing of the OFDM modulation processing unit 12 is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0081] The transmission converter 300 converts the IF OFDM signal to a predetermined RF signal and amplifies it to a predetermined transmission output.

[0082] The transmitting antenna 500 radiates an RF OFDM signal into space.

[0083] The receive antenna 600 receives the radiated RF OFDM signal.

[0084] The receiving converter 400 amplifies and converts the desired RF OFDM signal to IF.

[0085] The advanced STL / TTL demodulator 200 has an OFDM demodulation processing unit 21, an FEC block separation unit 22, a frame synchronization unit 231, a PLL unit 24, counter units 25 and 29, counter value synchronization units 261 and 301, and modulator clock recovery units 271 and 311.

[0086] The processing of the OFDM demodulation processing unit 21 is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0087] The FEC block separator 22 performs error correction decoding processing on the reproduced FEC block, and separates and outputs the advanced program transmission signal with counter value and the broadcast TS with counter value that were multiplexed in the main signal area.

[0088] The PLL unit 24 regenerates and outputs a modulator clock from the advanced STL / TTL regenerated modulation clock by utilizing the relationship of the division ratio of the clock frequency.

[0089] Counter unit 25 generates a 125 MHz clock synchronized with the advanced STL / TTL regenerative modulation clock, operates a counter, and outputs a counter value. Counter unit 29 generates a 27 MHz clock synchronized with the advanced STL / TTL regenerative modulation clock, and operates a counter, and outputs a counter value.

[0090] Counter value synchronization unit 261 outputs a packet of the advanced program transmission signal at a timing when the counter value of the packet of the counter value-attached advanced program transmission signal matches the counter value supplied from counter unit 25. Furthermore, counter value synchronization unit 301 outputs a packet of the broadcast TS at a timing when the counter value of the packet of the counter value-attached broadcast TS matches the counter value supplied from counter unit 29.

[0091] The frame synchronization unit 231 generates an F_Sync signal based on the timing of the frame head packet of the broadcast TS, adjusts the timing with the terrestrial digital modulator clock, and outputs the broadcast TS and F_Sync.

[0092] The modulator clock regeneration unit 271 configures a PLL based on the interval between frames made up of multiple advanced program transmission signal packets, and regenerates and outputs a modulator clock for the advanced terrestrial broadcasting standard.

[0093] The modulator clock recovery unit 311 configures a PLL based on the output interval of packets of a broadcast TS and the interval between frames made up of a plurality of packets of a broadcast TS, and recovers and outputs a terrestrial digital modulator clock.

[0094] <Counter Unit 14 and Counter Value Addition Unit 15> 10, the counter unit 14 and the counter value adding unit 15 (151, 152, ... 15 N 10 is a diagram showing an example of the configuration of the counter unit 14 and the counter value adding unit 15.

[0095] The counter unit 14 includes a PLL unit 141 and a 125 MHz counter unit 142 .

[0096] The PLL unit 141 generates a 125 MHz clock GTXCLK synchronized with the advanced STL / TTL modulated clock and outputs it to the 125 MHz counter unit 142 .

[0097] The 125 MHz counter unit 142 counts the 125 MHz clock GTXCLK from a predetermined reset timing, and outputs the counter value C[39:0] to the counter value adding unit 15. The counter reset timing can be an integer multiple of the advanced STL / TTL transmission frame, which is equal to or less than the maximum counter value expressed by a finite number of bits (40 bits in this embodiment) and can be easily reproduced on the receiving side.

[0098] Counter value adding unit 15 (151, 152, ... 15N ) includes FIFO buffer units 151 and 153, a FIFO buffer control unit 152, and a combining unit 154.

[0099] When the FIFO buffer control unit 152 receives a received data valid signal RXDV from the Ethernet physical layer IC, which is the IP input I / F unit 60 of the advanced program transmission signal, it writes the advanced program transmission signal packet output from the RXD[7:0] terminal to the FIFO buffer unit 151 and writes the counter value C[39:0] to the FIFO buffer unit 153.

[0100] The combining unit 154 reads the paired counter value and advanced program transmission signal from the FIFO buffer unit 153 and the FIFO buffer unit 151, respectively, adds the counter value to the beginning of the packet of the advanced program transmission signal, and outputs the advanced program transmission signal with the counter value to the FEC block configuration unit 11. The advanced program transmission signal with the counter value has a counter value C, a header H, and information D, as shown in Fig. 10, for example.

[0101] The counter unit 17 and the counter value adding unit 18 are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0102] <Counter Unit 25 and Counter Value Synchronization Unit 26> 11, the counter unit 25 and the counter value synchronization unit 26 (261, 262, ... 26 N 11 is a diagram showing an example of the configuration of the counter unit 25 and the counter value synchronization unit 26.

[0103] The counter unit 25 includes a PLL unit 251 and a 125 MHz counter unit 252 .

[0104] The PLL unit 251 generates a 125 MHz clock synchronized with the advanced STL / TTL regenerated modulation clock.

[0105] The 125 MHz counter unit 252 counts the 125 MHz clock from a predetermined reset timing and outputs a counter value C'[39:0]. The reset timing of the counter can be, for example, the reset timing of the 125 MHz counter unit 142 on the modulator side offset by a predetermined processing delay.

[0106] The counter value synchronization unit 26 includes a separation unit 261 , FIFO buffer units 262 and 263 , a comparison unit 264 , and a FIFO buffer control unit 265 .

[0107] The separator 261 separates the counter value C[39:0] and the advanced program transmission signal from the counter value-added advanced program transmission signal, and writes them into the FIFO buffer unit 263 and the FIFO buffer unit 262, respectively.

[0108] The comparison unit 264 reads the counter value C[39:0] from the FIFO buffer unit 263, compares it with the counter value C'[39:0] output by the 125 MHz counter unit 252, and notifies the FIFO buffer control unit 265 and the modulator clock recovery unit 27 of the matching timing as the packet period of the advanced program transmission signal.

[0109] The FIFO buffer control unit 265 reads the advanced program transmission signal from the FIFO buffer unit 262 upon receiving notification from the comparison unit 264 that the counter values ​​match, and transfers it to the IP output I / F unit 70. The advanced program transmission signal is converted into an Ethernet frame format by the Ethernet physical layer IC, which is the IP output I / F unit 70, and is output from the advanced STL / TTL demodulator 200.

[0110] The counter unit 29 and the counter value synchronization unit 30 are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0111] <Modulator clock recovery unit 27> 12, the modulator clock recovery units 27 (271, 272, ... 27 N12 is a diagram showing an example of the configuration of modulator clock recovery section 27 when recovering an advanced modulator clock from the frame period of an advanced program transmission signal.

[0112] The modulator clock recovery units 27 (271, 272, ... 27) shown in FIG. N ) includes a phase comparison unit 271, a loop filter unit 272, a VCXO unit 273, and frequency division units 274 and 275.

[0113] The advanced terrestrial broadcasting standard adopts a frame-synchronized signal format that takes future expansion into consideration. A frame consists of a frame synchronization signal section, a TMCC section, and multiple subframe sections. The frame length is the sum of the lengths of each section and can take various values. As an example, consider the following: one subframe, one layer, no partial reception, mode 4 IFFT / FFT size of 16,384 points, guard interval ratio 800 / 16,384, 108 OFDM symbols per subframe, and one layer modulation method with 256QAM error correction coding rate 12 / 16. In this case, the frame length is 1,889,216 clocks, and 1,093 packets of the advanced program transmission signal are transmitted at equal intervals per frame. The modulator clock recovery unit 27 in Figure 12 configures a PLL using this relationship and generates the advanced modulator clock from the frame period of the advanced program transmission signal.

[0114] Specifically, the phase comparison unit 271 compares the phase of the signal obtained by dividing the packet period of the advanced program transmission signal by 1,093 using the frequency division unit 274 with the phase of the clock obtained by dividing the 6.321 MHz signal output by the VCXO unit 273 by 1,889,216 using the frequency division unit 275, and outputs the difference to the loop filter unit 272.

[0115] Loop filter unit 272 smoothes the differential output and outputs it as a control voltage for VCXO unit 273. In a steady state, the control voltage is a constant value, and the output of VCXO unit 273 becomes an advanced modulator clock synchronized with the frame period of the advanced program transmission signal.

[0116] Even when the transmission parameters are different, the frame period is an integer multiple of the advanced modulator clock, and the number of packets of the advanced program transmission signal per frame is an integer. Therefore, even when the transmission parameters are different, the present invention can be applied by changing the division ratios of the frequency dividers 274 and 275 to values ​​that correspond to the transmission parameters.

[0117] As described above, the advanced STL / TTL demodulator 200 is able to reproduce an advanced STL / TTL modulation clock of the same frequency as that of the advanced STL / TTL modulator 100 by using the clock recovery circuit included in the OFDM demodulation processing unit 21. The clocks of the counter units 14 and 17 included in the advanced STL / TTL modulator 100 and the clocks of the counter units 25 and 29 included in the advanced STL / TTL demodulator 200 are synchronized with the advanced STL / TTL modulation clock and the advanced STL / TTL reproduction modulation clock, respectively, and can therefore be considered to be common. The counter value synchronization units 26 and 30 output packets of the broadcast program signal at a timing when the counter value of the packet of the received broadcast program signal matches the counter value of the counter units 25 and 29 of the advanced STL / TTL demodulator 200. Therefore, according to the present invention, even for broadcast program signals in which the STL / TTL modulation clock is not synchronized, packets can be sent from the advanced STL / TTL demodulator 200 at the same time intervals as when they arrived at the advanced STL / TTL modulator 100, thereby suppressing the occurrence of jitter and preventing overflow and underflow of the modulator input buffer for terrestrial digital broadcasting and next-generation terrestrial broadcasting.

[0118] Furthermore, the modulator clock recovery units 27 and 31 configure a PLL based on the packet output interval of the broadcast program signal or the interval between frames consisting of multiple packets, and recover the modulator clock of the broadcast program signal. Since the packet period of the broadcast program signal and the frame period consisting of a specified number of packets can be expressed as an integer multiple of the modulator clock period of the broadcast program signal, the modulator clock recovery units 27 and 31 recover the modulator clock using a PLL from the packet period or frame period of the broadcast program signal sent from the advanced STL / TTL demodulator 200 at the same time interval as when it arrived at the advanced STL / TTL modulator 100. Therefore, according to the present invention, it is possible to recover and provide a modulator clock for slave synchronization of each broadcast program signal in STL / TTL multiplex transmission.

[0119] (program) A computer capable of executing program instructions can be used to function as the above-described advanced STL / TTL modulator 100 or the advanced STL / TTL demodulator 200. Here, the computer may be a general-purpose computer, a special-purpose computer, a workstation, a PC (Personal Computer), an electronic notepad, etc. The program instructions may be program code, code segments, etc., for performing the necessary tasks.

[0120] The computer includes a processor, a storage unit, an input unit, an output unit, and a communication unit. The processor may be a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), an SoC (System on a Chip), or the like, and may be configured with multiple processors of the same or different types. The processor reads and executes programs from the storage unit to control the above components and perform various arithmetic processing. Note that at least a portion of these processing contents may be implemented by hardware. The input unit is an input interface that accepts user input operations and acquires information based on the user operations, such as a pointing device, keyboard, or microphone. The output unit is an output interface that outputs information, such as a display or speaker. The communication unit is a communication interface for communicating with external devices.

[0121] The program may be recorded on a computer-readable recording medium. Using such a recording medium, the program can be installed on a computer. Here, the recording medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, and may be, for example, a CD-ROM, a DVD-ROM, or a USB (Universal Serial Bus) memory. Furthermore, the program may be downloaded from an external device via a network.

[0122] (Variation) Although the above-described embodiments have been described as typical examples, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the above-described embodiments, and modifications such as those described below are possible without departing from the scope of the claims.

[0123] The embodiment of the present invention has been described using an example in which two broadcast program signals are multiplexed, but the number of multiplexes is not limited to two, and the present invention can be applied in a similar way even when the number of multiplexes is increased.

[0124] Even if the frequencies of the modulator clock input to the advanced STL / TTL modulator 100 and the modulator clock output by the advanced STL / TTL demodulator 200 are different from those in the above-described embodiment, the concept is the same except for the division ratio, and the present invention can be applied.

[0125] If the constraints on the reproducibility of transmission delay time due to power OFF / ON or resetting of the device are not strict, the counter value adding units 15 and 18 may add the difference in counter values ​​instead of the counter value, and the counter value synchronizing units 26 and 30 may compare the difference in counter values ​​and output packets at the matching timing.

[0126] The reset timing of the 27 MHz counter unit 292 and the 125 MHz counter unit 252 of the advanced STL / TTL demodulator 200 may be set to the same as the reset timing of the 27 MHz counter unit 172 and the 125 MHz counter unit 142 of the advanced STL / TTL modulator 100, and the comparators 304 and 264 of the counter value synchronizers 30 and 26 may output packets of the broadcast program signal not when the counter values ​​match, but when the difference between the counter values ​​equals a predetermined processing delay. Taking advantage of the existence of a starting transmission frame that starts storing packets from the beginning in the FEC block at the beginning of the transmission frame, the processing delay may be automatically set based on the difference between the timing when the starting transmission frame arrives at the receiving end and the timing when the first packet stored in that transmission frame is output from the FEC block separator 22.

[0127] The functional blocks for realizing the present invention may be provided outside the advanced STL / TTL modulator 100 and the advanced STL / TTL demodulator 200. [Explanation of symbols]

[0128] 11 FEC block configuration section 12 OFDM modulation processing section 13,24,141,171,251,291 PLL section 14, 17, 25, 29 Counter section 15,18 Counter value addition section 21 OFDM demodulation processing unit 22 FEC block separator 23 Frame Synchronization Unit 26,30 Counter value synchronization section 27,31 Modulator clock recovery section 40 Broadcast TS input I / F section 50 Broadcast TS output I / F section 60 IP input I / F section 70 IP output I / F section 72 Single carrier modulation processing unit 81 Single carrier demodulation processing unit 100 Advanced STL / TTL Modulator 142,252 125MHz counter section 151,153,181,183,262,263,302,303 FIFO buffer section 152,182,265,305 FIFO buffer control unit 154,184 Joint 172,292 27MHz counter section 200 Advanced STL / TTL Demodulator 261,301 Separation section 264,304 Comparison section 271,311 Phase comparator 272,312 Loop filter section 273,313 VCXO section 274,275,314,315 Frequency divider 300 Transmitting Converter 400 receiving converter 500 transmit antennas 600 receiving antenna 700 STL / TTL Modulator 800 STL / TTL Demodulator 4000 Advanced STL / TTL transmitter 5000 Advanced STL / TTL Receiver

Claims

1. 1. An STL / TTL modulator in a system for multiplexing and transmitting a plurality of counter-value-added broadcast program signals by STL / TTL, comprising: a counter unit that counts clocks synchronized with the STL / TTL modulation clock; a plurality of counter value adding units that, when a plurality of packets of the broadcast program signal arrive, add counter values ​​supplied from the counter units to the packets to generate the broadcast program signal with the counter values; An STL / TTL modulator comprising:

2. an FEC block constructing unit that generates an FEC block by multiplexing a plurality of the counter value-added broadcast program signals; an OFDM modulation processing unit that performs modulation processing on the FEC block to generate an OFDM signal; 2. The STL / TTL modulator of claim 1, comprising:

3. The clock frequency of the counter unit is If the broadcast program signal is a broadcast TS, the frequency is 27 MHz, If the broadcast program signal is IP, it is 125 MHz.

3. The STL / TTL modulator according to claim 1 or 2.

4. 1. An STL / TTL demodulator in a system in which a plurality of counter value-added broadcast program signals are multiplexed and transmitted by STL / TTL, a counter unit that counts clocks synchronized with the reproduced STL / TTL modulated clock; a plurality of counter value synchronization units that output a packet for each broadcast program signal at a timing when the counter value of the packet of the counter value-attached broadcast program signal and the counter value supplied from the counter unit match; An STL / TTL demodulator comprising:

5. 5. The STL / TTL demodulator of claim 4, further comprising a modulator clock regeneration unit that configures a PLL based on the output interval of packets of the broadcast program signal or the interval of frames consisting of multiple packets of the broadcast program signal, and regenerates and outputs a modulator clock of the broadcast program signal.

6. an OFDM demodulation processing unit that performs demodulation processing on the OFDM signal to reproduce the FEC block; an FEC block separator that performs error correction decoding processing on the FEC block, separates the multiplexed broadcast program signals with counter values, and outputs the separated signals to the counter value synchronizer; 5. The STL / TTL demodulator of claim 4, comprising:

7. The clock frequency of the counter unit is If the broadcast program signal is a broadcast TS, the frequency is 27 MHz, If the broadcast program signal is IP, it is 125 MHz.

7. An STL / TTL demodulator according to any one of claims 4 to 6.

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