Methods for inspecting semiconductor devices

Abstract

This improves the reliability of semiconductor devices equipped with MOSFETs having a double-gate structure including a gate electrode and a field plate electrode within a trench. [Solution] An inspection is performed on a semiconductor device comprising a source region SR formed on the upper side of a semiconductor substrate SB1, a drain region formed on the lower side of the semiconductor substrate SB1, a trench TR formed on the upper surface, and a gate electrode GE and a field plate electrode FG formed within the trench TR. In this inspection, the source electrode and drain electrode are fixed at ground potential, an offset voltage is applied to the field plate electrode FG, and a screening voltage is applied to the gate electrode GE. This allows for the inspection of the insulation between the source region SR and the gate electrode GE, and the insulation between the gate electrode GE and the field plate electrode FG.

Description

Technical Field

[0001] The present invention relates to a method for inspecting a semiconductor device, and more particularly to a technique effective for applying to a method for inspecting a vertical MOSFET having a trench gate.

Background Art

[0002] As a trench gate power MOSFET for low and medium voltages, a trench double gate type power MOSFET having a field plate electrode below a gate electrode (intrinsic gate electrode) in a trench is known. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2010-258153) describes a vertical MOSFET in which a gate electrode and a source wiring layer insulated from each other through a gate insulating film are embedded in a trench.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One of the tests performed on semiconductor devices equipped with MOSFETs is the Time Dependent Dielectric Breakdown (TDDB) test. In this test, a high voltage is applied to the gate electrode, focusing on areas of the gate insulating film that are particularly thin, to check for the presence or absence of gate insulating film breakdown. In contrast, in trench-type double-gate power MOSFETs, multiple types of insulating films with different thicknesses are in contact with the gate electrode or field plate electrode. Therefore, even if the test is performed focusing on one area of ​​the gate insulating film that is particularly thin, defects in other insulating films of different thicknesses may be overlooked. Thus, in semiconductor devices equipped with trench-type double-gate power MOSFETs, there is a challenge in ensuring the reliability of the multiple types of insulating films formed in the trench, thereby improving the reliability of the semiconductor device.

[0005] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0006] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0007] One embodiment of a semiconductor device inspection method involves inspecting a semiconductor device comprising a source region formed on the upper side of a semiconductor substrate having an upper and lower surface, a drain region formed on the lower side of the semiconductor substrate, a trench formed from the upper surface toward the lower surface, and a gate electrode and a field plate electrode formed within the trench. In this inspection, the source electrode and the drain electrode are fixed at ground potential, a first offset voltage is applied to the field plate electrode, and a first screening voltage is applied to the gate electrode. This inspects the insulation between the source region and the gate electrode, and the insulation between the gate electrode and the field plate electrode. [Effects of the Invention]

[0008] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a planar layout showing a semiconductor device that is an embodiment of the design. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a cross-sectional view showing a semiconductor device that is an embodiment of the device. [Figure 4] This is an equivalent circuit diagram showing a semiconductor device that is an embodiment of the present invention. [Figure 5] This is a cross-sectional view showing a semiconductor device that is an embodiment of the device. [Figure 6] This is an equivalent circuit diagram showing a semiconductor device that is an embodiment of the present invention. [Figure 7] This is a cross-sectional view showing a semiconductor device that is an embodiment of the device. [Figure 8] This is a cross-sectional view showing a semiconductor device that is an embodiment of the device. [Figure 9] This is an equivalent circuit diagram showing a semiconductor device that is an embodiment of the present invention. [Modes for carrying out the invention]

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, the number is not limited to the number mentioned and may be greater than or less than the number mentioned.

[0011] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it shall include those that substantially approximate or resemble their shape, etc., unless specifically stated or considered to be not in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0012] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0013] In the following explanation, each plan view (plan layout) is hatched on the contact plugs to make the diagrams easier to understand.

[0014] Here, we will explain the semiconductor device of this application using a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, MOS type field-effect transistor) as an example. A power MOSFET is a semiconductor device capable of handling power of several watts or more. The semiconductor device of this application has a trench-gate power MOSFET, which is a type of power MOSFET. A trench-gate power MOSFET has a gate electrode made of a polycrystalline silicon film or the like in a trench (a relatively long and narrow groove) formed in the upper surface (first main surface) of a semiconductor substrate, and a channel is formed in the thickness direction of the semiconductor substrate. In this case, the upper surface side of the semiconductor substrate usually becomes the source, and the lower surface (back surface, second main surface) side becomes the drain.

[0015] In addition, the semiconductor device of the present application includes a double-gate power MOSFET in the trench among trench gate power MOSFETs. The double-gate power MOSFET in the trench is a device having a field plate electrode below a gate electrode (intrinsic gate electrode) in the trench. When the field plate electrode is connected to the source potential, it disperses a steep potential gradient concentrated near the drain-side end of the gate electrode and keeps the electric field constant. By keeping the electric field near the field plate electrode constant, the breakdown voltage of the device can be ensured.

[0016] Hereinafter, an oxide film breakdown test performed on a semiconductor device including a double-gate power MOSFET in the trench will be described. The first inspection and the second inspection performed here are inspections performed when the insulating films in contact with the gate electrode and the field plate electrode respectively have different thicknesses. The first inspection and the second inspection are inspections performed on separate semiconductor devices (semiconductor devices). In the first inspection and the second inspection, screening voltages and offset voltages are applied to each electrode so that the electric fields applied to each of the plurality of insulating films in contact with the gate electrode and the field plate electrode are equal to each other, and the plurality of insulating films are inspected simultaneously. Hereinafter, the oxide film breakdown test (screening inspection) will be simply referred to as an inspection.

[0017] (Embodiment) <Structure of Semiconductor Device> Hereinafter, the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 4. Here, the X direction and the Y direction are directions along the upper surface of the semiconductor substrate, respectively, and are directions perpendicular to each other in plan view. Further, the Z direction perpendicular to each of the X direction and the Y direction is the height direction (thickness direction, vertical direction, longitudinal direction) perpendicular to the upper surface of the semiconductor substrate. The plan view referred to in the present application means viewing the semiconductor device in the Z direction.

[0018] The semiconductor device of this embodiment has a semiconductor chip equipped with a semiconductor substrate. As shown in Figure 1, the semiconductor chip has a plurality of MOSFETs 1Q arranged in the X direction and connected in parallel to each other. In Figure 1, the structure beneath the wiring formed on the upper surface of the semiconductor substrate is shown through a transparent view, and the semiconductor substrate and insulating films such as the interlayer insulating film and passivation film on the semiconductor substrate are not shown. The outline of the semiconductor chip is not shown in Figure 1. Figure 2 shows a cross-sectional view along line AA in Figure 1. Figure 3 shows an enlarged cross-sectional view of the structure near the trench shown in Figure 2. Figure 4 shows an equivalent circuit diagram of the semiconductor device of this embodiment. In Figure 3, the interlayer insulating film on the semiconductor substrate is not shown.

[0019] As shown in Figure 2, the semiconductor substrate SB1 constituting the semiconductor device of this embodiment has a substrate SB made of, for example, single-crystal Si (silicon), and a drift layer DF which is a semiconductor layer formed on the substrate SB by an epitaxial growth method or the like. The semiconductor substrate SB1 has a first main surface and a second main surface opposite to the first main surface. Hereinafter, the first main surface will be referred to as the top surface and the second main surface as the bottom surface.

[0020] The substrate SB is n + It constitutes an n-type drain region DR. That is, the semiconductor substrate SB1 is an n-type laminated substrate consisting of a substrate SB and a drift layer (semiconductor layer) DF, and the semiconductor substrate SB1 has a drain region DR formed from the bottom surface to a predetermined depth. In other words, the drain region DR is formed in the substrate SB between the bottom surface of the semiconductor substrate SB1 and the drift layer DF. Although not shown in the figure, the bottom surface of the substrate SB is covered by a drain electrode DE containing, for example, Au (gold), and the drain region DR is electrically connected to the drain electrode DE. The drift layer DF is n - It is a semiconductor layer of a certain type.

[0021] As shown in Figure 1, multiple trenches TR extending in the Y direction are formed on the upper surface of the semiconductor substrate SB1, arranged in the X direction. MOSFETs 1Q are formed near the trenches TR.

[0022] As shown in Figures 2 and 3, a gate electrode (trench gate electrode) GE and a field plate electrode (trench gate electrode) FG, located on the lower side of the semiconductor substrate SB1 than the gate electrode GE, are formed inside the trench TR. An insulating film IF1, which is a gate insulating film, is formed between the semiconductor substrate SB1 and the gate electrode GE. An insulating film IF3, which is a gate insulating film, is formed between the semiconductor substrate SB1 and the field plate electrode FG. As a result, the gate electrode GE and the field plate electrode FG are electrically insulated from the semiconductor substrate SB1. In other words, the gate electrode GE and the field plate electrode FG are electrically insulated from the source region SR and the drain region DR, respectively. An insulating film IF2 is formed between the gate electrode GE and the field plate electrode FG. As a result, the gate electrode GE and the field plate electrode FG are electrically insulated from each other.

[0023] In this context, a structure in which two electrodes are formed within a trench is called a double-gate structure (double-gate type). The width of the field plate electrode FG in the short direction (X direction) is smaller than the width of the gate electrode GE on the field plate electrode FG in the short direction (X direction). Therefore, in the X direction, the thickness of the insulating film IF3 between the field plate electrode FG and the semiconductor substrate SB1 is greater than the thickness of the insulating film IF1 between the gate electrode GE and the semiconductor substrate SB1. However, in Figure 1, the width of the field plate electrode FG is shown to be wider than it actually is in order to make its shape easier to understand.

[0024] The gate electrode GE and the field plate electrode FG are each made of, for example, a polycrystalline silicon film. The insulating films IF1, IF2, and IF3 are each made of, for example, a silicon oxide film.

[0025] Within the semiconductor substrate SB1, a body layer PB, which is a p-type semiconductor layer, is formed in contact with the side surface of the trench TR, extending to a predetermined depth from the top surface of the semiconductor substrate SB1 (the top surface of the drift layer DF). In other words, the body layer PB is formed between the top surface of the semiconductor substrate SB1 and the drift layer DF. The depth of the body layer PB is shallower than, for example, the depth of either the trench TR or the gate electrode GE. In other words, the trench TR penetrates the body layer PB.

[0026] Furthermore, within the semiconductor substrate SB1, there is a certain depth extending from the upper surface of the semiconductor substrate SB1 (the upper surface of the drift layer DF, the upper surface of the body layer PB), + Semiconductor region of type (n + A source region SR (diffusion layer) is formed in contact with the side surface of the trench TR. The source region SR is in contact with the upper surface of the semiconductor substrate SB1. The depth of the source region SR is shallower than the depth of either the body layer PB or the gate electrode GE. In other words, the source region SR is formed between the upper surface of the semiconductor substrate SB1 and the body layer PB. The lower surface of the source region SR is in contact with the body layer PB, and the lower surface of the body layer PB is in contact with the drift layer DF. The trench TR penetrates the source region SR and the body layer PB to reach the drift layer DF. In other words, the trench TR penetrates the source region SR and the body layer PB and is formed to reach a predetermined depth from the upper surface to the lower surface of the semiconductor substrate SB1.

[0027] The source region SR, drain region DR, body layer PB, and gate electrode GE constitute an n-type MOSFET 1Q, which is a vertical MOSFET.

[0028] As shown in Figures 1 to 3, on the semiconductor substrate SB1, gate electrode GE, insulating film IF1, and field plate electrode FG, metal films (conductive films, source wiring) and gate wiring GW, which constitute source pads (source electrodes) SP1 and SP2 respectively, are formed via an interlayer insulating film IL. The interlayer insulating film IL is mainly composed of silicon oxide film, for example. The metal films and gate wiring GW that constitute source pads SP1 and SP2 respectively are made of Al (aluminum), for example. These metal films and gate wiring GW are located at the same height and spaced apart from each other. The gate electrode GE and the source region SR are electrically insulated from each other via the interlayer insulating film IL.

[0029] Multiple openings (through holes, contact holes) are formed in the interlayer insulating film IL. Contact plugs (conductive connection parts) are formed within these openings, which are integrated with the metal film or gate wiring GW that constitute the source pads SP1 and SP2, respectively. In the following, source pads SP1 and SP2 refer strictly to the portion of the upper surface of the metal film (source wiring) that is exposed from an insulating film such as a passivation film (not shown), but in the following, the metal film itself will be referred to as source pad SP1 or SP2.

[0030] The trench TR, gate electrode GE, field plate electrode FG, and contact plug C2 extend in the Y direction. However, in the central part of the semiconductor chip in the Y direction, the gate electrode GE within the trench TR is separated into two, and the contact plug C3 is connected to the field plate electrode FG between these two adjacent gate electrode GEs in the Y direction.

[0031] A portion of the gate wiring GW is formed adjacent to the end of the source pad SP1 in the Y direction and extends in the X direction. Another portion of the gate wiring GW is adjacent to the source pads SP1 and SP2 in the X direction. The gate wiring GW is electrically connected to the gate electrode GE in the trench TR via a contact plug C1. A portion of the upper surface of the gate wiring GW constitutes the gate pad GP, and the gate potential is supplied to the gate electrode GE via the gate pad GP, the gate wiring GW, and the contact plug C1. The contact plug C1 is formed directly above the end of the gate electrode GE in the Y direction.

[0032] The source pad SP2 is electrically connected to the field plate electrode FG in the trench TR via a contact plug C3. The contact plug C3 is formed directly above the center of the field plate electrode FG in the Y direction. Near the area where the contact plug C3 is formed (the power supply area), the gate electrode GE is not formed in the trench TR. In other words, in the area where the contact plug C3 is connected to the upper surface of the field plate electrode FG, the upper surface of the field plate electrode FG is exposed from the gate electrode GE. That is, the field plate electrode FG is embedded in the trench TR near the area where the contact plug C3 is formed, extending from near the lower end to near the upper end of the trench TR. Source potential is supplied to the field plate electrode FG via the source pad SP2 and the contact plug C3. Although not shown in the diagram, source pads SP1 and SP2 are electrically connected via a bonding wire.

[0033] The source pad SP1 is electrically connected to the source region SR and the body layer PB via a contact plug C2. The contact plug C2 extends along the direction of extension of the trench TR (Y direction). However, in the central part of the semiconductor chip in the Y direction, the contact plug C2 is separated into two parts. The contact plug C2 reaches an intermediate depth in the body layer PB, which is deeper than the source region SR, and is in contact with the source region SR. To reduce the connection resistance between the contact plug C2 and the body layer PB, a p-type semiconductor region with a higher density than the body layer PB may be formed in the semiconductor substrate SB1 between the contact plug C2 and the body layer PB. The source potential is supplied to the source region SR and the body layer PB via the source pad SP1 and the contact plug C2.

[0034] As shown in Figure 3, the width of the trench TR in the short direction (X direction) gradually decreases from the top side to the bottom side of the semiconductor substrate SB1. Also, the corners that form the boundary between the bottom and side surfaces of the trench TR are rounded. In the process of forming the internal structure of the trench TR, first, an insulating film IF3 with a relatively large thickness that does not completely fill the inside of the trench TR is formed. Next, a field plate electrode FG is formed in the space between the insulating films IF3 that cover each of the sides of the trench TR in the short direction. Here, etching back is performed to recede the upper surface of the field plate electrode FG below the upper end of the trench TR. Subsequently, etching back is performed to recede the upper surface of the insulating film IF3 below the upper surface of the field plate electrode FG.

[0035] Next, insulating films IF1 and IF2 are formed simultaneously, for example, by thermal oxidation. Additionally, oxide film growth is performed using CVD (Chemical Vapor Deposition) as needed. Here, insulating film IF1 covers the sides of the trench TR, and insulating film IF2 covers the field plate electrode FG exposed from insulating film IF3. By utilizing the characteristics of film formation by thermal oxidation (the oxidation rate differs depending on the surface orientation and impurity concentration, etc.), the thickness of insulating film IF1 covering the sides of the trench TR can be made smaller than the thickness of insulating film IF2. Next, the gate electrode GE is embedded in the trench TR, thereby forming the gate electrode GE, field plate electrode FG, insulating films IF1, IF2, and IF3.

[0036] Here, the field plate electrode FG has a protrusion that projects above the upper surface of the insulating film IF3 toward the gate electrode GE at the center of the trench TR in the short direction in a plan view. A portion of the gate electrode GE sandwiches this protrusion in the short direction of the trench TR. That is, the gate electrode GE has a recess that covers the vicinity of the upper end of the field plate electrode FG extending in the Z direction, and the upper end of the field plate electrode FG is fitted into this recess.

[0037] The insulating film IF1 insulates the source region SR, drain region DR, and body layer PB from the gate electrode GE. The minimum thickness of the insulating film IF1 between the semiconductor substrate SB1 and the gate electrode GE is T1. For a semiconductor device with a rated voltage (withstand voltage) of 40V, the value of thickness T1 is, for example, 30nm or more and 50nm or less. A semiconductor device with a rated voltage of 40V is a semiconductor device that can safely maintain the off state as long as the voltage difference between the source and drain is up to 40V. For a semiconductor device with a rated voltage of 80V, the value of thickness T1 is 70nm or more and 90nm or less. The minimum thickness T2 of insulating film IF2 and the minimum thickness of insulating film IF3 are both 250nm or less.

[0038] The position where the thickness of the insulating film IF2 is minimum is, for example, the location shown at T2 in Figure 3, in the short-side direction of the trench, where a portion of the gate electrode GE sandwiches the field plate electrode FG (protrusion). In other words, the thickness of the insulating film IF2 is minimum between the side surface of the field plate electrode FG and the gate electrode GE facing that side surface. Therefore, in the first and second inspections described later, the insulating properties between the gate electrode GE and the field plate electrode FG are checked, for example, by inspecting the insulating properties of the insulating film IF2 between the side surface of the protrusion in the X direction and the gate electrode GE facing that side surface. The position where the thickness of the insulating film IF3 is minimum is, for example, the location shown at T3 in Figure 3, between the lower end of the field plate electrode FG or the corner of the lower surface of the field plate electrode FG and the lower end of the trench TR or the corner of the lower surface of the trench TR. Therefore, in the second inspection described later, the insulating properties between the drain region DR (semiconductor substrate SB1) and the field plate electrode FG are checked by inspecting the insulating properties of the insulating film IF3 at that location.

[0039] Figure 3 shows a structure in which the upper end (convex portion) of the field plate electrode FG fits into the recess at the bottom of the gate electrode GE. However, the shapes of the field plate electrode FG and the gate electrode GE are not limited to the structure shown in Figure 3, and may be structures such as those described later using Figure 8.

[0040] Figure 4 is an equivalent circuit diagram showing a semiconductor device according to this embodiment. The nodes shown in Figure 4, gate G, source S, drain D, and field plate F, respectively, represent the gate electrode GE, source electrode (source pad SP1, source region SR), drain electrode DE (drain region DR), and field plate electrode FG. MOSFET1Q has an internal diode D1, the anode of which is connected to source S, and the cathode of which is connected to drain D. The resistance and capacitance connected in series between gate G and field plate F represent insulating film IF2. The resistance and capacitance connected in series between drain D and field plate F represent insulating film IF3. Here, the field plate F and source S are electrically connected by a bonding wire BW. However, the first and second tests described below are performed before the field plate F and source S are electrically connected by the bonding wire BW.

[0041] <First Examination> Next, the first inspection, which is a screening inspection performed on the semiconductor chip described above, will be explained using Figures 5 and 6. The first inspection is performed when the difference between the thickness T1 of insulating film IF1 and the thickness T2 of insulating film IF2, as shown in Figure 3, is small, and the thickness T3 of insulating film IF3 is sufficiently thicker than the thicknesses T1 and T2, or when such a case is expected. For example, the thickness T3 of insulating film IF3 is 1.5 times or more the thickness T2 of insulating film IF2. Figure 5 is a cross-sectional view showing a semiconductor device according to this embodiment. Figure 6 is an equivalent circuit diagram showing a semiconductor device according to this embodiment. In the first inspection, the insulation between the source region and the gate electrode, and the insulation between the gate electrode and the field plate electrode are inspected simultaneously. The following method is used for this.

[0042] Here, the source S and drain D are connected to ground potential. In other words, the source electrode and drain electrode are fixed at ground potential. An offset voltage Vofa is applied to the field plate F (field plate electrode FG). A screening voltage Vsa is applied to the gate G (gate electrode GE). This tests the insulation properties of the insulating film IF1 between the source region SR and the gate electrode GE, and the insulation properties of the insulating film IF2 between the gate electrode GE and the field plate electrode FG.

[0043] In the first inspection, the target to which the screening voltage Vsa will be applied is determined. That is, the electrode in contact with the area requiring particular inspection (the area of ​​interest) among several insulating films with different thicknesses is selected. Here, the insulating film IF1 is chosen, and it is decided to apply the screening voltage Vsa to the gate electrode GE in contact with insulating film IF1. The value of the screening voltage Vsa is determined so that the electric field E applied to the insulating film of interest falls within a predetermined range. This predetermined range of the electric field E is, for example, 0.6 V / nm or more and 0.8 V / nm or less.

[0044] The screening voltage Vsa is the product of the electric field E applied to the insulating film IF1 and the minimum thickness T1 of the insulating film IF1. In other words, when considering the insulating film IF1 between the source region SR, which is fixed at ground potential (e.g., 0V), and the gate electrode GE, the screening voltage Vsa applied to the gate electrode GE can be calculated as Vsa = T1 × E. For example, when the minimum thickness of the insulating film IF1 is 50nm, the screening voltage Vsa is 30V or more and 40V or less. Also, when the minimum thickness of the insulating film IF1 is 80nm, the screening voltage Vsa is 48V or more and 64V or less.

[0045] Next, the target to which the offset voltage Vofa will be applied is determined. That is, among several insulating films with different film thicknesses, the insulating film to be focused on after insulating film IF1 in the first inspection is determined, and the electrode to which the offset voltage Vofa will be applied, which is in contact with that insulating film, is determined. Here, the insulating film IF2 is focused on, and it is decided to apply the offset voltage Vofa to the field plate electrode FG in contact with insulating film IF2. The value of the offset voltage Vofa is determined so that the electric field E applied to the insulating film of interest falls within the same predetermined range as the electric field applied to insulating film IF1. This predetermined range of electric field E is, for example, 0.6 V / nm or more and 0.8 V / nm or less.

[0046] The value of the offset voltage Vofa is determined by the ratio of the minimum thickness T1 of the insulating film IF1 to the minimum thickness T2 of the insulating film IF2. Here, the value of the offset voltage Vofa is determined such that it satisfies the following equation 1. (Vsa-Vofa) / T2=Vsa / T1 (Formula 1) In Equation 1, (Vsa - Vofa) represents the potential difference between the two regions sandwiching the insulating film IF2, i.e., the gate electrode GE and the field plate electrode FG. In Equation 1, Vsa represents the potential difference between the two regions sandwiching the insulating film IF1, i.e., the source region SR fixed at ground potential and the gate electrode GE. For example, when T1 = 50 nm, T2 = 100 nm, and Vsa = 35 V, an offset voltage Vofa = -35 V is applied to the field plate electrode FG.

[0047] In the first test, the same electric field is applied to both insulating films IF1 and IF2 by applying a screening voltage Vsa and an offset voltage Vofa such that equation 1 is satisfied. In other words, by adjusting the offset voltage considering the ratio of the thicknesses of the two insulating films IF1 and IF2, an equivalent electric field can be applied to the two insulating films IF1 and IF2, which have different thicknesses. This allows for simultaneous insulation testing of both insulating films IF1 and IF2.

[0048] The value of the screening voltage Vsa and the ratio of thickness T1 to thickness T2 determine whether the offset voltage Vofa is positive or negative. This prevents dielectric breakdown between the object to which the offset voltage Vofa is applied (in this case, the field plate electrode FG) and the semiconductor substrate SB1. In other words, it is important to keep the difference between thickness T1 and thickness T2 small enough to satisfy Equation 1 and prevent dielectric breakdown between the object to which the offset voltage Vofa is applied and the semiconductor substrate SB1.

[0049] <Second examination> Next, the second inspection, which is a screening inspection performed on the semiconductor chip described above, will be explained using Figures 7, 8, and 9. The second inspection is performed when the difference between the thickness T2 of the insulating film IF2 and the thickness T3 of the insulating film IF3 shown in Figure 3 is small, and the thickness T1 of the insulating film IF1 is sufficiently thinner than the thicknesses T2 and T3, or when such a case is anticipated. Screening of the thin insulating film IF1 alone may be performed before or after the second inspection. Figures 7 and 8 are cross-sectional views showing the semiconductor device of this embodiment. Figure 9 is an equivalent circuit diagram showing the semiconductor device of this embodiment.

[0050] The second inspection may be performed on either the semiconductor device shown in Figure 7 or Figure 8. In the structure shown in Figure 7, similar to the structure shown in Figure 3, the convex portion of the upper end of the field plate electrode FG protrudes above the upper surface of the insulating film IF3, and the side surface of this convex portion faces a part of the gate electrode GE. However, compared to Figure 3, the thickness T2 of the insulating film IF2 in Figure 7 is larger, and the difference between the thickness T2 of the insulating film IF2 and the thickness T3 of the insulating film IF3 is smaller.

[0051] The structure shown in Figure 8 differs from the structure shown in Figure 3 in that the field plate electrode FG does not have a portion that protrudes above the upper surface of the insulating film IF3. Here, the bottom of the gate electrode GE has a gently curved surface and does not have a recess into which the upper end of the field plate electrode FG fits. In other words, the upper end of the field plate electrode FG is located below the lowest surface of the gate electrode GE, via the insulating film IF2. In this case, the minimum thickness T2 of the insulating film IF2 is equal to, for example, the distance between the gate electrode GE and the field plate electrode FG in the Z direction. Compared to Figure 3, the thickness T2 of the insulating film IF2 in Figure 8 is larger, and the difference between the thickness T2 of the insulating film IF2 and the thickness T3 of the insulating film IF3 is smaller.

[0052] In the second test, the insulation between the drain region and the field plate electrode, and the insulation between the gate electrode and the field plate electrode are tested simultaneously. The following method is used for this test.

[0053] Here, the source S and drain D are connected to ground potential. In other words, the source electrode and drain electrode are fixed at ground potential. A screening voltage Vsb is applied to the field plate F (field plate electrode FG). An offset voltage Vofb is applied to the gate G (gate electrode GE). This tests the insulation properties of the insulating film IF3 between the drain region DR and the field plate electrode FG, and the insulation properties of the insulating film IF2 between the gate electrode GE and the field plate electrode FG.

[0054] In the second inspection, first, the target to which the screening voltage Vsb will be applied is determined. That is, the electrode in contact with the area requiring particular inspection (the area of ​​interest) among multiple insulating films with different thicknesses is determined. Here, the insulating film IF3 is the focus, and it is decided to apply the screening voltage Vsb to the field plate electrode FG in contact with insulating film IF3. The value of the screening voltage Vsb is determined so that the electric field E applied to the insulating film of interest falls within a predetermined range. This predetermined range of the electric field E is, for example, 0.6 V / nm or more and 0.8 V / nm or less.

[0055] The screening voltage Vsb is the product of the electric field E applied to the insulating film IF3 and the minimum thickness T3 of the insulating film IF3. In other words, when considering the insulating film IF3 between the drain region DR, which is fixed at ground potential (e.g., 0V), and the field plate electrode FG, the screening voltage Vsb applied to the field plate electrode FG can be calculated as Vsb = T3 × E. For example, when the minimum thickness of the insulating film IF3 is 100 nm, the screening voltage Vsb is 60V or more and 80V or less.

[0056] Next, we determine the target to which the offset voltage Vofb will be applied. That is, among several insulating films with different film thicknesses, we determine the insulating film to focus on after insulating film IF3 in the second inspection, and then determine the electrode to which the offset voltage Vofb will be applied that is in contact with that insulating film. Here, we focus on insulating film IF2 and decide to apply the offset voltage Vofb to the gate electrode GE that is in contact with insulating film IF2. The value of the offset voltage Vofb is determined so that the electric field E applied to the insulating film of interest falls within the same predetermined range as the electric field applied to insulating film IF3. This predetermined range of electric field E is, for example, 0.6 V / nm or more and 0.8 V / nm or less.

[0057] The value of the offset voltage Vofb is determined by the ratio of the minimum thickness T3 of the insulating film IF3 to the minimum thickness T2 of the insulating film IF2. Here, the value of the offset voltage Vofb is determined such that it satisfies the following equation 2. (Vsb-Vofb) / T2=Vsb / T3 (Formula 2) In Equation 2, (Vsb - Vofb) represents the potential difference between the two regions sandwiching the insulating film IF2, i.e., the gate electrode GE and the field plate electrode FG. In Equation 2, Vsb represents the potential difference between the two regions sandwiching the insulating film IF3, i.e., the drain region DR fixed at ground potential and the field plate electrode FG. For example, when T3 = 100 nm, T2 = 75 nm, and Vsb = 70 V, an offset voltage Vofb = 17.5 V is applied to the gate electrode GE. Also, for a semiconductor device with a rated voltage of 40 V, the offset voltage Vofb is, for example, between -20 V and 20 V.

[0058] In the second test, the same electric field is applied to both insulating films IF2 and IF3 by applying a screening voltage Vsb and an offset voltage Vofb such that equation 2 is satisfied. This allows for simultaneous insulation testing of both insulating films IF2 and IF3.

[0059] The value of the screening voltage Vsb and the ratio of thickness T3 to thickness T2 determine whether the offset voltage Vofb is positive or negative. This prevents dielectric breakdown between the object to which the offset voltage Vofb is applied (in this case, the gate electrode GE) and the semiconductor substrate SB1. In other words, it is important to keep the difference between thickness T2 and thickness T3 small enough to satisfy equation 2 and prevent dielectric breakdown between the object to which the offset voltage Vofb is applied and the semiconductor substrate SB1.

[0060] <Effects of this embodiment> In the manufacturing process of semiconductor devices, defects can occur in the insulating film (oxide film) during the film deposition process due to dust, scratches, or dirt. The insulating film in areas with defects (defective deposition) may be locally thinner than the non-defective areas. Products containing semiconductor devices with such defects in the insulating film are likely to fail relatively quickly. Therefore, a method has been adopted to eliminate semiconductor devices (products) that will reach the end of their lifespan prematurely due to defects through pre-inspection. In this inspection, a strong voltage is applied to the electrodes of the semiconductor device. As a result, semiconductor devices with a short lifespan (TDDB lifespan) will experience dielectric breakdown on the spot, allowing for the detection of the abnormality. Therefore, the shipment of defective products can be prevented.

[0061] In the inspection, it is conceivable to focus on insulating films that are particularly prone to deposition defects and apply a high electric field only to those insulating films. Insulating films that are particularly prone to deposition defects are, for example, insulating films formed between the gate electrode and the semiconductor substrate, which are thinner than other insulating films. However, in trench double-gate power MOSFETs, multiple insulating films in contact with the trench gate electrode, including the gate electrode and the field plate electrode, each have different thicknesses. In this case, defects such as reduced thickness of the insulating film may occur not only in the thinnest insulating film but also in the other insulating films due to the generation of foreign matter during the manufacturing process.

[0062] One method for inspecting a trench-type double-gate power MOSFET shown in Figure 4, focusing only on the thinnest insulating film, is as follows: In this method, the source S, drain D, and field plate F are fixed to ground potential, and a screening voltage of approximately 35V is applied to the gate G. In this case, a high electric field is applied between the gate electrode GE and the semiconductor substrate SB1 (source region SR) to the thinnest insulating film IF1 shown in Figure 3. As a result, if the thickness of insulating film IF1 is reduced due to a defect, dielectric breakdown occurs, allowing for the detection of a semiconductor device defect. However, in this case, the presence or absence of defects in the other insulating films IF2 and IF3 cannot be inspected. For example, if the thickness of insulating film IF1, which is designed to be deposited at 50nm, is reduced to 30nm due to a defect, this defect can be detected by the above inspection. However, even if the thickness of insulating film IF2, which is designed to be deposited at 100nm, is reduced to 60nm due to a defect, this defect cannot be detected by the above inspection.

[0063] Another method for inspecting a trench-type double-gate power MOSFET by focusing only on the thinnest insulating film is as follows: In this method, the gate G, source S, and drain are fixed at ground potential, and a screening voltage of, for example, 70V is applied to the field plate F. In this case, a high electric field is applied between the gate electrode GE and the field plate electrode FG to insulating film IF2, which is thinner than insulating film IF3. As a result, if the thickness of insulating film IF2 is reduced due to the occurrence of a defect, dielectric breakdown occurs, and a defect in the semiconductor device can be detected. However, in this case, it is not possible to inspect for defects in the other insulating films IF1 and IF3.

[0064] As described above, even if the insulating film in contact with the trench gate electrode has the second or third largest thickness in the design, the occurrence of defects in this film can shorten the lifespan of the semiconductor device. Therefore, in semiconductor devices where the insulating film insulating the electrodes has multiple thicknesses, it is important to ensure higher reliability by inspecting not only one insulating film but also insulating films of other thicknesses. However, performing separate inspections for each insulating film with different thicknesses complicates the process and increases the manufacturing cost of the semiconductor device.

[0065] Therefore, in this embodiment, two of the three insulating films are selected, and these two insulating films are inspected simultaneously in a single inspection. This is done by applying the same electric field to each of the two insulating films during the inspection, thereby allowing the insulating properties of the two insulating films to be tested. Even if the thicknesses of the two insulating films being inspected differ, as explained using Equation 1 or Equation 2, the same electric field can be applied to each of the two insulating films by adjusting the offset voltage considering the ratio of the thicknesses of the two insulating films.

[0066] As described above, in this embodiment, in a semiconductor device where the insulating film that insulates the electrodes has multiple different thicknesses, it is possible to simultaneously inspect two or more insulating films in a single inspection. Therefore, the reliability of multiple types of insulating films can be ensured, thereby improving the reliability of the semiconductor device. In addition, it is possible to prevent an increase in the number of inspections and reduce the manufacturing cost of the semiconductor device.

[0067] In this embodiment, the first and second inspections were described. For example, if insulating film IF3 is sufficiently thicker than insulating films IF1 and IF2, the first inspection can be performed to simultaneously inspect the two insulating films IF1 and IF2, which have smaller film thicknesses, among the multiple types of insulating films formed in the trench. Also, for example, if insulating film IF1 is sufficiently thinner than insulating films IF2 and IF3, the second inspection can be performed to simultaneously inspect the two insulating films IF2 and IF3, which have larger film thicknesses, among the multiple types of insulating films formed in the trench. Therefore, since multiple locations can be inspected in a single inspection, the reliability of the semiconductor device can be improved.

[0068] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0069] For example, the polarity of the components of the MOSFET described in the above embodiment may be reversed. In other words, the MOSFET may be a p-type MOSFET. [Explanation of Symbols]

[0070] 1Q MOSFET C1, C2, C3 contact plugs D Drain D1 Built-in diode DE drain electrode DF Drift Layer DR drain area F Field Plate FG Field Plate Electrode G Gate GE Terminal GP Gate Pad GW gate wiring IF1, IF2, IF3 insulating film IL interlayer film PB body layer S Sauce SB board SB1 Semiconductor Substrate SP1, SP2 Sourcepad SR Source Area TR Trench

Claims

1. A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, A source region formed on the first main surface side of the semiconductor substrate, A drain region formed on the second main surface side of the semiconductor substrate, A trench is formed that penetrates the source region and extends from the first main surface toward the second main surface to a predetermined depth, A gate electrode formed within the trench and electrically insulated from the source region and the drain region, Within the trench, a field plate electrode is formed on the second main surface side with respect to the gate electrode and is electrically insulated from the source region, the drain region, and the gate electrode. A source electrode electrically connected to the source region, A drain electrode electrically connected to the drain region, Equipped with, In the first examination, The source electrode and the drain electrode are fixed at ground potential. A first offset voltage is applied to the field plate electrode. When a first screening voltage is applied to the aforementioned terminal electrode, A method for inspecting a semiconductor device, wherein the insulating properties between the source region and the gate electrode, and the insulating properties between the gate electrode and the field plate electrode are inspected.

2. A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, A source region formed on the first main surface side of the semiconductor substrate, A drain region formed on the second main surface side of the semiconductor substrate, A trench is formed that penetrates the source region and extends from the first main surface toward the second main surface to a predetermined depth, A gate electrode formed within the trench and electrically insulated from the source region and the drain region, Within the trench, a field plate electrode is formed on the second main surface side with respect to the gate electrode and is electrically insulated from the source region, the drain region, and the gate electrode. A source electrode electrically connected to the source region, A drain electrode electrically connected to the drain region, Equipped with, In the second examination, The source electrode and the drain electrode are fixed at ground potential. A second offset voltage is applied to the terminal electrode. The field plate electrode is subjected to a second screening voltage, A method for inspecting a semiconductor device, wherein the insulating properties between the drain region and the field plate electrode, and the insulating properties between the gate electrode and the field plate electrode are inspected.

3. In the method for inspecting a semiconductor device according to claim 1, A first insulating film formed between the source region and the gate electrode, A second insulating film formed between the gate electrode and the field plate electrode, Furthermore, A method for inspecting a semiconductor device, wherein, in the first inspection, the electric field applied to the first insulating film and the second insulating film is 0.6 V / nm or more and 0.8 V / nm or less.

4. In the method for inspecting a semiconductor device according to claim 2, A second insulating film formed between the gate electrode and the field plate electrode, A third insulating film formed between the drain region and the field plate electrode, Furthermore, A method for inspecting a semiconductor device, wherein, in the second inspection, the electric field applied to the second insulating film and the third insulating film is 0.6 V / nm or more and 0.8 V / nm or less.

5. In the method for inspecting a semiconductor device according to claim 3, A method for inspecting a semiconductor device, wherein the value of the first screening voltage is the product of the electric field applied to the first insulating film and the minimum thickness of the first insulating film.

6. In the method for inspecting a semiconductor device according to claim 4, A method for inspecting a semiconductor device, wherein the value of the second screening voltage is the product of the electric field applied to the third insulating film and the minimum thickness of the third insulating film.

7. In the method for inspecting a semiconductor device according to claim 1, A first insulating film formed between the source region and the gate electrode, A second insulating film formed between the gate electrode and the field plate electrode, Furthermore, A method for inspecting a semiconductor device, wherein the equation (Vsa - Vofa) / T2 = Vsa / T1 is satisfied, where Vsa is the first screening voltage, Vofa is the first offset voltage, T1 is the minimum thickness of the first insulating film, and T2 is the minimum thickness of the second insulating film.

8. In the method for inspecting a semiconductor device according to claim 2, A second insulating film formed between the gate electrode and the field plate electrode, A third insulating film formed between the drain region and the field plate electrode, Furthermore, A method for inspecting a semiconductor device, wherein the second screening voltage is Vsb, the second offset voltage is Vofb, the minimum thickness of the third insulating film is T3, and the minimum thickness of the second insulating film is T2, and the equation (Vsb - Vofb) / T2 = Vsb / T3 is satisfied.

9. In the method for inspecting a semiconductor device according to claim 1, A method for inspecting a semiconductor device, wherein the insulating properties between the source region and the gate electrode, and the insulating properties between the gate electrode and the field plate electrode are inspected simultaneously.

10. In the method for inspecting a semiconductor device according to claim 2, A method for inspecting a semiconductor device, wherein the insulation between the drain region and the field plate electrode, and the insulation between the gate electrode and the field plate electrode are inspected simultaneously.

11. In the method for inspecting a semiconductor device according to claim 1, The first insulating film is further formed between the source region and the gate electrode, A method for inspecting a semiconductor device, wherein when the minimum film thickness of the first insulating film is 50 nm, the first screening voltage is 30 V or more and 40 V or less.

12. In the method for inspecting a semiconductor device according to claim 1, The first insulating film is further formed between the source region and the gate electrode, A method for inspecting a semiconductor device, wherein when the minimum film thickness of the first insulating film is 80 nm, the first screening voltage is 48 V or more and 64 V or less.

13. In the method for inspecting a semiconductor device according to claim 2, The third insulating film is further formed between the drain region and the field plate electrode, A method for inspecting a semiconductor device, wherein when the minimum film thickness of the third insulating film is 100 nm, the second screening voltage is 60 V or more and 80 V or less.

14. In the method for inspecting a semiconductor device according to claim 1, The facility further comprises a second insulating film formed between the gate electrode and the field plate electrode, The trench extends along the first main surface, The field plate electrode has a protrusion toward the gate electrode at the center of the trench in the short direction in a plan view, A portion of the gate electrode sandwiches the protrusion in the shorter direction of the trench. A method for inspecting a semiconductor device, wherein the first inspection involves inspecting the insulating properties between the gate electrode and the field plate electrode, specifically the insulating properties of the second insulating film between the side surface of the protrusion in the short direction and the gate electrode facing the side surface of the protrusion.

15. In the method for inspecting a semiconductor device according to claim 2, The facility further comprises a second insulating film formed between the gate electrode and the field plate electrode, The trench extends along the first main surface, The field plate electrode has a protrusion toward the gate electrode at the center of the trench in the short direction in a plan view, A portion of the gate electrode sandwiches the protrusion in the shorter direction of the trench. A method for inspecting a semiconductor device, wherein the second inspection involves inspecting the insulating properties between the gate electrode and the field plate electrode, specifically the insulating properties of the second insulating film between the side surface of the protrusion in the short direction and the gate electrode facing the side surface of the protrusion.

16. In the method for inspecting a semiconductor device according to claim 1, A first insulating film formed between the source region and the gate electrode, A second insulating film formed between the gate electrode and the field plate electrode, A third insulating film formed between the drain region and the field plate electrode, Furthermore, The thickness of the first insulating film is 30 nm or more and 50 nm or less, or 70 nm or more and 90 nm or less. A method for inspecting a semiconductor device, wherein the thickness of the third insulating film is 1.5 times or more the thickness of the second insulating film.

17. In the method for inspecting a semiconductor device according to claim 1 or claim 2, A first insulating film formed between the source region and the gate electrode, A second insulating film formed between the gate electrode and the field plate electrode, A third insulating film formed between the drain region and the field plate electrode, Furthermore, Each of the first insulating film, the second insulating film, and the third insulating film is a silicon oxide film. A method for inspecting a semiconductor device, wherein each of the gate electrode and the field plate electrode is made of a polycrystalline silicon film.

18. In the method for inspecting a semiconductor device according to claim 1 or claim 2, A method for inspecting a semiconductor device, wherein the gate electrode, the source region, and the drain region constitute a MOS-type field-effect transistor.

19. In the method for inspecting a semiconductor device according to claim 1 or claim 2, The interlayer insulating film is further formed on the first main surface, the gate electrode, and the source region, A method for inspecting a semiconductor device, wherein the gate electrode and the source electrode are electrically insulated from each other by the interlayer insulating film.

20. In the method for inspecting a semiconductor device according to claim 2, A method for inspecting a semiconductor device, wherein the second offset voltage is -20V or greater and 20V or less.

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