A test circuit, a calibration method of a detection chip and a test device

Abstract

This disclosure provides a test circuit, a calibration method for a detection chip, and a test device. The test circuit includes a main control chip, an internal calibration circuit, and a detection chip. The detection chip is connected to the internal calibration circuit via an external signal channel. The main control chip controls a relay array to activate the calibration channel based on a received control signal. The test electrical signal generated by the detection chip is input into the calibration channel, and the value of the received test electrical signal is acquired by a correction ADC in the calibration channel. The detection chip is calibrated based on the acquired electrical signal value and the corresponding set value. The test electrical signal generated by the detection chip is output to the internal calibration circuit via the external signal channel. This disclosure utilizes the above circuit to acquire the electrical signal output by the detection chip within the ATE equipment and calibrate the detection chip based on these signals, thereby achieving the goal of integrating the detection chip calibration function into the ATE equipment and improving the integration level of the ATE equipment.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing, and in particular to a test circuit, a calibration method for testing chips, and a test device. Background Technology

[0002] In a chip testing system, the test chip is responsible for providing precise voltage and current signals to the device under test. The accuracy of its output DC signal directly determines the test quality, so calibrating the test chip is an essential step.

[0003] Currently, conventional calibration methods primarily rely on external instruments, which presents several drawbacks. Firstly, manual calibration, involving connecting a DC signal to a resistor and source meter via cables, requires manual calculation of calibration parameters, resulting in extremely low efficiency and unsuitability for multi-channel, large-scale mass production environments. Secondly, calibration board-based solutions utilize external dedicated calibration boards to extract signals and work with the source meter. This not only increases the complexity of hardware connections and operations but also reduces the overall integration of the automated test equipment (ATE), contradicting the trend towards equipment miniaturization. Finally, directly connecting the source meter to a relay board for calibration is severely limited by the communication and measurement speed of the source meter itself, leading to excessively long calibration times during mass production and significantly reducing production capacity.

[0004] In summary, existing technologies generally suffer from problems such as heavy reliance on external source meters, cumbersome hardware physical connections, and low calibration efficiency. Therefore, there is an urgent need for a calibration method that requires no external source meters or calibration boards, has high integration, and offers fast calibration speed, which has become a pressing technical challenge in the current chip testing field. Summary of the Invention

[0005] This disclosure provides a test circuit, a calibration method for a detection chip, and a test device to solve the problems of low integration and reliance on external devices in existing detection chip calibration methods.

[0006] In view of the above problems, in a first aspect, this disclosure provides a test circuit, including: a main control chip, an internal calibration circuit, and a detection chip; the detection chip is connected to the internal calibration circuit through an external signal channel; the internal calibration circuit includes multiple sets of resistors with preset resistance values, a relay array, and a correction ADC; The main control chip is used to control the relay array according to the received control signal to turn on the calibration channel in the internal calibration circuit; input the test electrical signal generated by the detection chip into the calibration channel, and collect the value of the received test electrical signal through the correction ADC in the calibration channel; and calibrate the detection chip according to the collected electrical signal value and the corresponding set value. The detection chip is used to generate a test electrical signal and output it to the internal calibration circuit through the external signal channel.

[0007] In conjunction with the first aspect, in one possible implementation, the internal calibration circuit is further provided with a test signal interface for connection to an external signal channel; The relays in the relay array are respectively set at the connection nodes between the resistor, the test signal interface and the correction ADC. They are used to switch the conduction relationship according to the first control command of the main control chip when calibrating the voltage-related function of the detection chip, so that the first end of the first target resistor is connected to the test signal interface and the correction ADC respectively, and a calibration channel is established between the test signal interface, the first target resistor and the correction ADC. or This is used to switch the conduction relationship according to the second control command of the main control chip when calibrating the current-related function of the detection chip, so that the test signal interface and the correction ADC are respectively connected to the first end of different second target resistors, and a calibration channel is established between the test signal interface, the second target resistor and the correction ADC.

[0008] In conjunction with the first aspect, in one possible implementation, the test circuit further includes: an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel, so that the main control chip can obtain the actual value of the generated test electrical signal to the internal measurement channel through the internal measurement channel.

[0009] In conjunction with the first aspect, in one possible implementation, the external signal channels are multiple; the circuit further includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are connected to the signal input terminals of the main control chip and the corresponding detection chip, respectively, and are used to control the corresponding detection chip to generate test electrical signals according to the third control instruction of the main control chip, and transmit them through the corresponding external signal channel. The signal channel controllers in the signal channel controller array are connected to the signal output terminals of the corresponding detection chips and the corresponding external signal channels, respectively, and are used to control the conduction relationship between the signal output terminals of the corresponding detection chips and the external signal channels according to the fourth control instruction of the main control chip.

[0010] In conjunction with the first aspect, in one possible implementation, the internal calibration circuit includes a preset number of resistor groups, the resistance value of the resistors contained in each group is set according to the value range of the test electrical signal; the conduction relationship within each resistor group is switched by a relay array to establish a calibration channel within the group; each resistor group is provided with a test signal interface for connection to an external signal channel. For each resistor group, the first end of the resistor in the group is connected to the first common connection point and the second common connection point of the group, the first common connection point of the group is connected to the test signal interface corresponding to the group, and the second common connection point of the group is connected to the correction ADC corresponding to the group. The second end of the resistor is connected to the ground point; The first common connection point and the second common connection point of each resistor group are switched by a relay array to determine the resistor group connected to the test signal interface.

[0011] Secondly, this disclosure also provides a calibration method for a detection chip, wherein the detection chip is disposed in a test circuit, and the test circuit further includes: a main control chip and an internal calibration circuit; the output terminal of the detection chip is connected to the internal calibration circuit through an external signal channel; the internal calibration circuit includes multiple sets of resistors with preset resistance values, a relay array, and a correction ADC; The method includes: The relay array is switched to switch the conduction state according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit. The target detection chip is controlled to output a test electrical signal to the target calibration channel, and the output electrical signal value is sampled. The calibration value of the target detection chip is determined by a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value.

[0012] In conjunction with the second aspect, in one possible implementation, the test electrical signal is a first voltage signal; the test circuit further includes: an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel; The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: The target detection chip is controlled to output different first voltage signals to the target calibration channel multiple times, and the sampled value of the first voltage signal output by the correction ADC is obtained respectively. Before determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: The actual values ​​of the different voltage signals output by the target detection chip are obtained through the internal measurement channel; The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the first sampled value of the first voltage signal and the first set electrical signal value corresponding to the first voltage signal, a plurality of first calibration points are determined in the first coordinate system; wherein, the horizontal coordinate of the first calibration point is the first sampled value, and the vertical coordinate of the first calibration point is the first set electrical signal value; The first calibration equation is obtained by fitting the first calibration point; wherein the first calibration equation is a linear equation in two variables with the first sampled value as the independent variable and the first set electrical signal value as the dependent variable. The correction coefficient in the first calibration equation is determined as the voltage output correction value of the detection chip; Based on the first sampled value and the first actual value of the first voltage signal, a plurality of second calibration points are determined in the second coordinate system; wherein, the vertical coordinate of the second calibration point is the first sampled value, and the horizontal coordinate of the second calibration point is the first actual value; The second calibration equation is obtained by fitting the second calibration point; wherein the second calibration equation is a linear equation in two variables with the first actual value as the independent variable and the first sampled value as the dependent variable. The correction coefficient in the second calibration equation is determined as the voltage acquisition correction value of the detection chip.

[0013] In conjunction with the second aspect, in one possible implementation, the test electrical signal is a first current signal; the test circuit further includes: an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel; The step of switching the conduction state of the relay array according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit includes: The relay array is switched on and off multiple times according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit. Each target calibration channel is matched with a different set first current signal. The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: For each established target calibration channel, the target detection chip is controlled to output a corresponding first current signal to the target calibration channel, and the sampled value of the first current signal for correcting the ADC sampling is obtained; Before determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: The actual values ​​of the different first current signals output by the target detection chip for each established target calibration channel are obtained through the internal measurement channel; The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: For each established target calibration channel, based on the second sampled value of the first current signal acquired multiple times and the second set electrical signal value corresponding to the first current signal, multiple third calibration points are determined in the third coordinate system; wherein, the horizontal coordinate of the third calibration point is the second sampled value, and the vertical coordinate of the third calibration point is the second set electrical signal value; The third calibration equation is obtained by fitting the third calibration point; wherein the third calibration equation is a linear equation in two variables with the second sampled value as the independent variable and the second set electrical signal value as the dependent variable. The correction coefficient in the third calibration equation is determined as the current output correction value of the detection chip; For each established target calibration channel, multiple fourth calibration points are determined in the fourth coordinate system based on the second sampled value of the first current signal and the second actual value of the first current signal; wherein, the vertical coordinate of the fourth calibration point is the second sampled value, and the horizontal coordinate of the second calibration point is the second actual value; The fourth calibration equation is obtained by fitting the fourth calibration point; wherein the fourth calibration equation is a linear equation in two variables with the second actual value as the independent variable and the second sampled value as the dependent variable. The correction coefficient in the fourth calibration equation is determined as the current acquisition correction value of the detection chip.

[0014] In conjunction with the second aspect, in one possible implementation, the test electrical signal is a clamping signal; The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: Different clamping voltage values ​​are set for the target detection chip; the clamping voltage values ​​include: a high clamping voltage value and a low clamping voltage value; The target detection chip is controlled to output a corresponding clamping signal to the target calibration channel according to the different clamping voltage values, and the sampled value of the second voltage signal output by the correction ADC is obtained respectively. The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the third set electrical signal value of the high clamping voltage value and the third sampled value of the second voltage signal corresponding to the high clamping voltage value, a plurality of fifth calibration points are determined in the fifth coordinate system; wherein, the horizontal coordinate of the fifth calibration point is the third sampled value, and the vertical coordinate of the fifth calibration point is the third set electrical signal value; The fifth calibration equation is obtained by fitting the fifth calibration point; wherein the fifth calibration equation is a linear equation in two variables with the third sampled value as the independent variable and the third set electrical signal value as the dependent variable. The correction coefficient in the fifth calibration equation is determined as the high clamping correction value of the detection chip; Based on the fourth set electrical signal value of the low clamping voltage value and the fourth sample value of the second voltage signal corresponding to the low clamping voltage value, a plurality of sixth calibration points are determined in the sixth coordinate system; wherein, the horizontal coordinate of the sixth calibration point is the fourth sample value, and the vertical coordinate of the sixth calibration point is the fourth set electrical signal value; The sixth calibration equation is obtained by fitting the sixth calibration point; wherein the sixth calibration equation is a linear equation in two variables with the fourth sampled value as the independent variable and the fourth set electrical signal value as the dependent variable. The correction coefficient in the sixth calibration equation is determined as the low clamping correction value for the detection chip.

[0015] In conjunction with the second aspect, in one possible implementation, the test electrical signal is a high clamping current signal; The relay array is switched on and off according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit; including: The relay array is switched on and off multiple times according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit. Each target calibration channel is matched with a different set high clamping current value. The step of controlling the target detection chip to output a test electrical signal to the target calibration channel and obtaining the electrical signal value of the ADC sampling correction includes: For each established target calibration channel, the target detection chip is controlled to output a corresponding high clamping current signal to the target calibration channel according to the different high clamping current values, and the sampled value of the second current signal output by the correction ADC is obtained respectively. The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the fifth set electrical signal value of the high clamping current value and the fifth sampled value of the second current signal corresponding to the high clamping current value, a plurality of seventh calibration points are determined in the seventh coordinate system; wherein, the horizontal coordinate of the seventh calibration point is the fifth sampled value, and the vertical coordinate of the seventh calibration point is the fifth set electrical signal value; The seventh calibration equation is obtained by fitting the seventh calibration point; wherein the seventh calibration equation is a linear equation in two variables with the fifth sample value as the independent variable and the fifth set electrical signal value as the dependent variable. The correction coefficient in the seventh calibration equation is determined as the high clamping current correction value for the detection chip.

[0016] In conjunction with the second aspect, in one possible implementation, the test electrical signal is a low-clamping current signal; The test circuit further includes: an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel; The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: Different low clamping current values ​​are set for the target detection chip; The target detection chip is controlled to output a corresponding low clamping current signal to the target calibration channel according to the different low clamping current values; Before determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: The actual value of the third current signal output by the target detection chip for different low clamping current values ​​is obtained through the internal measurement channel; The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the sixth set electrical signal value of the low clamping current value and the sixth sample value of the third current signal corresponding to the low clamping current value, multiple eighth calibration points are determined in the eighth coordinate system; wherein, the horizontal coordinate of the eighth calibration point is the sixth sample value, and the vertical coordinate of the eighth calibration point is the sixth set electrical signal value; The eighth calibration equation is obtained by fitting the eighth calibration point; wherein the eighth calibration equation is a linear equation in two variables with the sixth sample value as the independent variable and the sixth set electrical signal value as the dependent variable. The correction factor in the eighth calibration equation is determined as the low clamping current correction value for the detection chip.

[0017] In conjunction with the second aspect, in one possible implementation, the external signal channels are multiple; the circuit further includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are respectively connected to the signal input terminals of the main control chip and the corresponding detection chip; the signal channel controllers in the signal channel controller array are respectively connected to the signal output terminal of the corresponding detection chip and the corresponding external signal channel. Before switching the conduction state of the relay array according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit, the method further includes: The target detection chip is determined based on the received control signal, and the target detection chip is controlled by the signal controller; and / or Based on the received control signal, the conduction relationship of the target detection chip corresponding to the external signal channel is controlled.

[0018] In conjunction with the second aspect, in one possible implementation, after determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: A verification equation is established based on the correction value, the calibrated object is verified, and the percentage of error corresponding to the correction value is determined based on the verification result. The error percentage is compared with a first threshold. If the error percentage is less than the first threshold, the calibration object is determined to have passed calibration.

[0019] Thirdly, embodiments of this disclosure provide a testing device, including: a testing circuit as described in any of the first aspects, and / or a calibration method for a detection chip as described in any of the second aspects.

[0020] The beneficial effects of the embodiments disclosed herein include: This disclosure provides a test circuit, a calibration method for a detection chip, and a test device. The test circuit includes a main control chip, an internal calibration circuit, and a detection chip. The detection chip is connected to the internal calibration circuit via an external signal channel. The internal calibration circuit includes multiple sets of resistors with preset resistance values, a relay array, and a correction ADC. The main control chip controls the relay array to activate the calibration channel in the internal calibration circuit based on a received control signal. It inputs the test electrical signal generated by the detection chip into the calibration channel and acquires the value of the received test electrical signal through the correction ADC in the calibration channel. It then calibrates the detection chip based on the acquired electrical signal value and the corresponding set value. The detection chip generates a test electrical signal and outputs it to the internal calibration circuit through the external signal channel. In this disclosure, the above circuit allows for the acquisition of electrical signals output by the detection chip within the ATE (Automatic Test Equipment) device, and the calibration of the detection chip based on these signals. This achieves the goal of integrating the detection chip calibration function into the ATE device, improving the integration level of the ATE device. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the test circuit provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the internal calibration circuit provided in an embodiment of the present disclosure; Figure 3This is a schematic diagram of the resistor wiring structure provided in an embodiment of the present disclosure; Figure 4 A schematic flowchart illustrating the calibration method for the detection chip provided in this embodiment of the disclosure; Figure 5 A schematic diagram of the source voltage and measurement voltage calibration process provided in the embodiments of this disclosure; Figure 6 A schematic diagram of the source current and measurement current calibration process provided in this embodiment of the disclosure; Figure 7 This is a schematic diagram of the clamping function calibration process provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of the clamping function calibration process provided in an embodiment of this disclosure. Detailed Implementation

[0022] This disclosure provides a test circuit, a calibration method for a detection chip, and a test device. Preferred embodiments of this disclosure are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit this disclosure. Furthermore, the embodiments and features described in this application can be combined with each other unless otherwise specified.

[0023] This disclosure provides a test circuit, such as... Figure 1 As shown, it includes: a main control chip 1, an internal calibration circuit 2, and a detection chip 3; the detection chip 3 is connected to the internal calibration circuit 2 through an external signal channel; the internal calibration circuit 2 includes multiple sets of resistors 21 with preset resistance values, a relay array 22, and a correction ADC 23; The main control chip 1 is used to control the relay array 22 to turn on the calibration channel in the internal calibration circuit 2 according to the received control signal; input the test electrical signal generated by the detection chip 3 into the calibration channel, and collect the value of the received test electrical signal through the correction ADC 23 in the calibration channel; and calibrate the detection chip 3 according to the collected electrical signal value and the corresponding set value. The detection chip 3 is used to generate a test electrical signal and output it to the internal calibration circuit 2 through the external signal channel.

[0024] In this embodiment of the disclosure, the test circuit can be a circuit for testing a chip. The circuit is equipped with a detection chip 3, which outputs an electrical signal to the chip under test. Based on the response of the chip under test, the performance of the chip under test is detected, thereby realizing the testing of the chip under test. As a preferred embodiment, the detection chip can be implemented as a PE (Pin Electronics) chip.

[0025] To calibrate the detection chip 3 in this circuit, the test circuit of this disclosure also integrates an internal calibration circuit and a main control chip, among other components, for calibrating the detection chip 3. This allows the ATE equipment to calibrate the detection chip 3 without requiring an additional calibration device.

[0026] The test circuit may include an internal calibration circuit 2 and a main control chip 1. The main control chip 1 can communicate with a lower-level computer and receive control signals from the lower-level computer. It should be noted that the lower-level computer referred to in this disclosure is in contrast to the upper-level computer used for overall control of the ATE equipment. The lower-level computer in this disclosure can be a computer device capable of controlling devices such as the main control chip and acquiring the data it collects (e.g., the value of the collected test electrical signal). This lower-level computer can also execute corresponding calibration algorithms based on this data. The upper-level computer in this disclosure can communicate with the lower-level computer and can send corresponding control signals through the lower-level computer to control the main control chip.

[0027] Specifically, such as Figure 1 As shown, the main control chip 1 can be connected to the data transfer unit board (DTU) via a signal backplane. Signal connectors are located at both ends of the signal backplane; one connector connects to the main control chip 1, and the other connects to the DTU board. The DTU board can communicate with the lower-level machine via an optical module or other network protocols. It can convert control signals from the lower-level machine and send them to the main control chip 1, and it can also send data acquired by the main control chip 1 to the lower-level machine.

[0028] The main control chip 1 can be implemented as a programmable system-on-a-chip. Embedded software can be pre-installed within the main control chip 1. Based on the instructions of the control signals, the main control chip 1 can output corresponding signals through expansion interfaces such as the integrated circuit bus (I2C), serial peripheral interface (SPI), or local bus. Specifically, the main control chip 1 can include a processing system (PS) section and a programmable logic (PL) section.

[0029] The internal calibration circuit 2 may include multiple sets of resistors 21 with different preset resistance values, so as to... Figure 2 For example, Figure 2The device includes three sets of resistors 21. Each set of resistors 21 contains resistors with different resistance values, which correspond to different electrical signal values ​​output by the detection chip 3, thereby calibrating the detection chip 3. The number of sets of resistors 21 can be set according to the number of output channels of the detection chip 3 to be calibrated. Each set of resistors 21 can correspond to multiple output terminals of the detection chip 3. It can be seen that... Figure 2 R1 to R5, R6 to R10, and R11 to R15 are three identical sets of resistors. Taking R1 to R5 as an example, the five resistors can have different preset resistance values, such as 83Ω, 2.5MΩ, 500kΩ, 50kΩ, and 5kΩ. This is for illustrative purposes only and is not a limitation.

[0030] Specifically, the ATE equipment can be equipped with multiple detection chips 3. Each detection chip 3 can integrate multiple output signal channels for outputting electrical signals. In the actual chip testing process, each output signal channel can correspond to a pin of the chip under test, so that the electrical signal can be input to the chip under test through the pin, thereby testing the chip under test.

[0031] like Figure 1 The test circuit shown can include 144 detection chips, each of which can include two output signal channels (i.e., detection chips #0 to #287 in the diagram, totaling 288 signal output channels). The number of detection chips in the test circuit and the number of output signal channels for each detection chip can be set according to the actual situation of the target chip under test. If the chip under test has a large number of pins, more detection chips can be set accordingly. This is for illustration only and is not a limitation.

[0032] The correction ADC can acquire the value of the electrical signal in the internal calibration circuit 2 and is connected to the main control chip 1. It can upload the acquired value to the main control chip 1, and the main control chip 1 can transmit it to the lower-level machine for calibration calculation and data recording. The correction ADC can be implemented as an analog-to-digital converter (ADC).

[0033] Multiple relays can be installed on the connection lines between each resistor 21, the correction ADC 23, and the test signal interface. These relays form a relay array 22, which may also include an input / output (I / O) expansion chip. This expansion chip is connected to the I2C interface of each relay and the main control chip 1. Under the control of the main control chip 1, the expansion chip switches the conduction state of different relays, thereby forming different signal paths as calibration channels for the output signal of the measurement and detection chip 3.

[0034] The circuit described above can acquire the electrical signals output by the detection chip 3 within the ATE equipment and calibrate the detection chip 3 based on these electrical signals, thereby achieving the goal of integrating the calibration function of the detection chip 3 into the ATE equipment and improving the integration level of the ATE equipment.

[0035] In yet another embodiment provided in this disclosure, such as Figure 1 As shown, the internal calibration circuit 2 is also provided with a test signal interface 24 for connecting to an external signal channel; The relays in the relay array are respectively set at the connection nodes between resistor 21, test signal interface 24 and correction ADC 23. They are used to switch the conduction relationship according to the first control command of main control chip 1 when calibrating the voltage related function of detection chip 3, so that the first end of the first target resistor is connected to the test signal interface and correction ADC respectively, and a calibration channel is established between the test signal interface, the first target resistor and correction ADC. or This is used to switch the conduction relationship according to the second control command of the main control chip 1 when calibrating the current-related function of the detection chip 3, so that the test signal interface 24 and the correction ADC 23 are respectively connected to the first end of different second target resistors, and a calibration channel is established between the test signal interface, the second target resistor and the correction ADC.

[0036] In this embodiment of the disclosure, each component in the internal calibration circuit 2 can be a pre-calibrated component. By calibrating these components, the accuracy of the calibration of the detection chip 3 can be improved, thereby improving the accuracy of subsequent testing of the chip under test.

[0037] The test signal interface 24 is the interface for inputting the test electrical signal output from the detection chip 3 into the internal calibration circuit 2. The test signal interface 24 can establish a connection with the signal output terminal of the detection chip 3 through an external signal channel outside the internal calibration circuit 2. The signal output terminal of the detection chip can be the interface of the output signal channel of each detection chip.

[0038] Depending on the actual situation, each external signal channel can be connected to multiple signal output terminals and connected to a corresponding test signal interface 24. The external signal channel can be implemented as a load board, on which multiple signal lines can be configured. Figure 1 Taking the load board as an example, it can include 6 signal lines. Each signal line can be connected to a test signal interface 24 in the internal calibration circuit, thereby realizing the purpose of transmitting the test electrical signal output by the detection chip 3 to the internal calibration circuit.

[0039] It should be noted that the detection chip 3 not only has signal output function, but also measurement function. That is, the actual value of its own test electrical signal can be output through the measurement port of the detection chip 3. This value can be output to the main control chip 1 through the internal measurement channel 4, and the main control chip 1 uses this value to calibrate the detection chip 3.

[0040] Furthermore, the calibration of the relevant functions of the detection chip is carried out by taking the output signal channel of the detection chip as the basic unit, that is, calibrating the output function of each output signal channel separately.

[0041] The voltage-dependent function refers to the calibration of the source voltage, measurement voltage, and clamping functions of the detection chip. Calibration of the voltage-dependent function requires the output signal channel to output a corresponding test electrical signal, which is then output to the calibration ADC via the calibration channel for calibration based on the acquired electrical signal value. In this process, the voltage-dependent function of the output signal channel needs to select a calibration channel. The resistor in this calibration channel can be the resistor with the largest resistance value in the internal calibration circuit as the first target resistor. According to the first control command, the relays between the first target resistor and the test signal interface, as well as the relays between the first target resistor and the calibration ADC, can be activated to obtain the calibration channel. The first terminal of this resistor can be connected to both the test signal interface for the input test electrical signal and the interface for acquiring the test electrical signal, while the second terminal of the resistor is grounded. In one possible implementation, a 2.5MΩ resistor can be selected. Here, the first target resistor can act as a pull-down resistor in the calibration channel.

[0042] The current-related function refers to the calibration of the source current, measurement current, and clamping current functions of the detection chip. During this calibration process, the current-related function of the output signal channel requires selecting different calibration channels based on the current range. Specifically, the resistance value in different calibration channels corresponds to the current range of the output signal channel. Depending on the current range to be calibrated, a second control command can activate the calibration channel containing the second target resistor corresponding to that current range. After completing the calibration for that current range, the calibration channel can be deactivated to activate another calibration channel containing a second target resistor, thus calibrating different current ranges. In one possible implementation, an 83.167Ω resistor can be selected for calibration at a 60mA current range; a 2.5MΩ resistor can be selected for calibration at a 2μA current range; a 500kΩ resistor can be selected for calibration at a 10μA current range; a 50kΩ resistor can be selected for calibration at a 100μA current range; and a 5kΩ resistor can be selected for calibration at a 1mA current range. The first terminals of these resistors can be connected to the test signal interface for inputting the test signal, and to the correction ADC for acquiring the test signal, respectively, while the second terminals are grounded. This second target resistor serves as both a pull-down resistor and a sampling resistor in the calibration channel.

[0043] In another embodiment provided in this disclosure, the test circuit further includes: an internal measurement channel 4; the detection chip 3 is connected to the main control chip 1 through the internal measurement channel 4, so that the main control chip 1 can obtain the actual value of the generated test electrical signal to the internal measurement channel 4 through the internal measurement channel 4.

[0044] In this embodiment, the internal measurement channel 4 may specifically include a selector, a buffer, and voltage / current acquisition components. The selector can control the selection of measurement ports of different detection chips 3. The actual value of the test signal fed back by the selected detection chip 3 is transmitted through the buffer. The buffer provides circuit isolation, preventing load effects between the internal measurement channel 4 and the measurement port of the selected detection chip 3. This ensures that the signal with high fidelity is sent to the voltage / current acquisition component for processing before being transmitted to the main control chip 1, thus completing the numerical acquisition of the actual value of the test electrical signal. The voltage / current acquisition component can be implemented as an ADC (Analog-to-Digital Converter).

[0045] In yet another embodiment provided in this disclosure, such as Figure 1 As shown, there are multiple external signal channels; the circuit also includes: a signal controller array 5 and a signal channel controller array 6; The signal controller 51 in the signal controller array 5 is connected to the signal input terminals of the main control chip 1 and the corresponding detection chip 3 respectively, and is used to control the corresponding detection chip 3 to generate test electrical signals according to the third control command of the main control chip 1, and transmit them through the corresponding external signal channel. The signal channel controller 61 in the signal channel controller array 6 is connected to the signal output terminal of the corresponding detection chip 3 and the corresponding external signal channel, respectively, and is used to control the conduction relationship between the signal output terminal of the corresponding detection chip 3 and the external signal channel according to the fourth control instruction of the main control chip 1.

[0046] In this embodiment of the disclosure, since multiple detection chips 3 can be set in a test circuit, the number of control channels of the main control chip 1 cannot correspond one-to-one with the number of detection chips 3. Therefore, a signal controller array 5 can be set to expand the control channels of the main control chip 1 to control more detection chips 3. Specifically, the signal controller can be implemented as a field-programmable gate array (FPGA). Figure 1 As shown, each FPGA can expand the main control chip with 24 control channels, meaning one FPGA can control 24 detection chips and 48 output signal channels. In practical applications, the number of FPGAs can be flexibly configured according to the control capabilities of the main control chip, the control capabilities of the FPGA, and the number of detection chips; this is for illustrative purposes only and is not a limitation.

[0047] The main control chip 1 can send a third control command carrying specific address information or following specific timing information, which allows it to locate and independently drive a specific detection chip 3 to generate test electrical signals via the signal controller 51 in the signal controller array 5. This enables the main control chip 1 to control a large number of detection chips 3 even with a limited number of interfaces.

[0048] The signal channel controller array 6 can be located at the signal output terminal of the detection chip 3. By responding to the fourth control command issued by the main control chip 1, it selectively connects or disconnects the loop between the signal output terminal of the detection chip 3 and the external signal channel, thereby controlling the signal output terminal of the detection chip 3. This ensures that only the test electrical signal generated by the target detection chip 3 is transmitted to the designated external signal channel, thus isolating non-target test electrical signals from entering the internal calibration circuit 2. This prevents signal interference and guarantees the accuracy of the calibration process.

[0049] Specifically, the signal channel controller can be implemented as an optocoupler relay, and each optocoupler relay can be connected to the signal output terminal of a detection chip 3 to control the conduction relationship between the signal output terminal and the external signal channel. Figure 1For example, each external signal channel can be connected to 48 optocoupler relays, meaning 48 output signal channels can be aggregated into a single external signal channel. During each calibration process, only the optocoupler relay of the target detection chip among the 48 optocoupler relays connected to this external signal channel is activated. The main control chip can control the on / off state of the signal channel controllers in the signal channel controller matrix through the signal channel controller driver. Specifically, if the signal channel controller is an optocoupler relay, the driver can be implemented as an optocoupler relay driver.

[0050] The number of external signal channels can be determined based on the number of resistor groups in the internal calibration circuit. The number of resistor groups determines the number of detection chips that can be calibrated simultaneously. Figure 1 For example, the internal calibration circuit may include three sets of resistors with preset resistance values. Each set of resistors is connected to a correction ADC and connected to the output signal channels of 96 detection chips through two test signal interfaces. That is, this test circuit can calibrate three output signal channels simultaneously. This is for illustrative purposes only and is not a limitation.

[0051] In another embodiment provided in this disclosure, the internal calibration circuit 2 includes a preset number of resistor groups, the resistance value of the resistors contained in each group is set according to the value range of the test electrical signal; the conduction relationship of each resistor group is switched by a relay array 22 to establish a calibration channel in the group; each resistor group is provided with a test signal interface 24 connected to an external signal channel; For each resistor group, the first end of the resistor in the group is connected to the first common connection point and the second common connection point of the group, the first common connection point of the group is connected to the test signal interface 24 corresponding to the group, and the second common connection point of the group is connected to the correction ADC 23 corresponding to the group. The second end of the resistor is connected to the ground point; The first common connection point and the second common connection point of each resistor group are switched through the relay array 22 to determine the resistor group connected to the test signal interface 24.

[0052] In this embodiment, during the calibration process of the detection chip 3, multiple different signals need to be output from the detection chip 3 to the internal calibration circuit 2, and the detection chip 3 is calibrated based on the values ​​collected by the internal calibration circuit 2. To accommodate the different signal output levels of the detection chip 3, the internal calibration circuit 2 includes multiple resistors of different values, which can be divided into multiple groups. Each group of resistors corresponds to the complete signal output range of the detection chip 3. In one possible implementation, for the 60mA output level of the detection chip 3, an 83.167Ω resistor can be set in each group to adapt to this current level, ensuring that the voltage across the resistor is controlled within the range and preventing voltage over-limit. For the 10uA output level of the detection chip 3, a 500KΩ resistor can be set in each group to adapt to this current level, ensuring that the voltage across the resistor is a larger, easily acquired value, facilitating calibration.

[0053] Depending on the number of output terminals, multiple such resistor groups can be set in the internal calibration circuit 2. Each group can be responsible for receiving test electrical signals output from multiple detection chips 3. In practical applications, multiple resistors can be calibrated simultaneously to reduce calibration time and improve calibration efficiency.

[0054] Each group of resistors in the internal calibration circuit 2 can be connected to at least one test signal interface 24. That is, the group of resistors can measure the test electrical signal at the output terminal of the PE chip connected to the test signal interface 24, thereby calibrating these channels.

[0055] like Figure 3 As shown, one end of each resistor in each group is connected to two common connection points (i.e., the first common connection point and the second common connection point). The first common connection point is connected to at least one test signal interface 24, and the second common connection point is connected to the correction ADC 23. A relay is installed on the connection line between each resistor and these two common connection points. The on / off state of the connection line can be controlled by controlling the conduction of the relays. Furthermore, relays are also installed between the common connection point and the correction ADC 23 side, and between the common connection point and the test signal interface 24.

[0056] This disclosure also provides a calibration method for a detection chip 3, wherein the detection chip 3 is disposed in a test circuit, and the test circuit further includes: a main control chip 1 and an internal calibration circuit 2; the output terminal of the detection chip 3 is connected to the internal calibration circuit 2 through an external signal channel; the internal calibration circuit 2 includes multiple sets of resistors with preset resistance values, a relay array 22, and a correction ADC; The method, such as Figure 4 As shown, it can be implemented as follows: S101. Switch the conduction state of the relay array 22 according to the received control signal to establish a target calibration channel between the output terminal of the target detection chip 3 and the corresponding correction ADC in the internal calibration circuit 2. S102. Control the target detection chip 3 to output a test electrical signal to the target calibration channel, and sample the output electrical signal value; S103. Based on the sampled electrical signal value and the corresponding set electrical signal value, determine the correction value of the target detection chip 3 through a preset calibration algorithm.

[0057] In this embodiment, the calibration is mainly performed on the parameter measurement unit (PMU) function of the detection chip 3. The PMU function may specifically include the source voltage / measured voltage (FV / MV, Force Voltage / Measure Voltage), source current / measured current (FI / MI, Force Current / Measure Current), clamp voltage, and clamp current functions of the detection chip 3.

[0058] During source voltage (FV) and source current (FI) function calibration, the main control chip 1 can send a set control command to the detection chip 3 to control the target detection chip 3 to output a test electrical signal with a specific voltage or current value. The signal channel controller 61 can select the circuit between the output terminal of the detection chip 3 and the external signal channel, and transmit the signal to the target calibration channel corresponding to the test electrical signal in the internal calibration circuit 2 through the external signal channel. The main control chip 1 can sample the value of the test electrical signal through the internal calibration circuit 2, and calculate the error of the FV and FI functions respectively by combining the set value of the test electrical signal, thereby determining the correction value of the target detection chip 3 in the FV and FI functions.

[0059] When calibrating the voltage (MV) and current (MI) measurement functions, the main control chip 1 can sample the value of the electrical signal output by the output terminal of the detection chip 3 through the internal measurement channel 4, compare it with the value of the test electrical signal sampled by the internal calibration circuit 2, calculate the error of the MV and MI functions respectively, and then determine the correction value of the target detection chip 3 in the MV and MI functions.

[0060] During clamping and clamping current calibration, the main control chip 1 can configure the clamping or clamping current value of the detection chip 3 and control the test circuit to generate a driving condition exceeding that clamping or clamping current value. The internal calibration circuit 2 samples the actual output test signal value of the main control chip 1 to determine whether the output of the detection chip 3 is accurately limited to the set clamping or clamping current value, thereby determining the error of the clamping or clamping current function and the correction value for the target detection chip 3 in the clamping and clamping current functions.

[0061] In another embodiment provided in this disclosure, the test electrical signal is a first voltage signal; the test circuit further includes: an internal measurement channel 4; the detection chip 3 is connected to the main control chip 1 through the internal measurement channel 4. In step S102 above, "controlling the target detection chip 3 to output a test electrical signal to the target calibration channel and sampling the output electrical signal value" can be implemented as follows: The target detection chip 3 is controlled to output different first voltage signals to the target calibration channel multiple times, and the sampled value of the first voltage signal output by the correction ADC is obtained respectively. Before step S103 above, "determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm," the method further includes: The actual values ​​of the different voltage signals output by the target detection chip 3 are obtained through the internal measurement channel 4; In step S103 above, "determining the correction value of the target detection chip 3 based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm" can be implemented as follows: S103A1. Based on the first sampled value of the first voltage signal and the first set electrical signal value corresponding to the first voltage signal, determine a plurality of first calibration points in the first coordinate system; Wherein, the horizontal coordinate of the first calibration point is the first sampled value, and the vertical coordinate of the first calibration point is the first set electrical signal value; S103A2. A first calibration equation is obtained by fitting the first calibration point; wherein, the first calibration equation is a linear equation in two variables with the first sampled value as the independent variable and the first set electrical signal value as the dependent variable. S103A3, The correction coefficient in the first calibration equation is determined as the voltage output correction value of the detection chip 3; S103A4. Based on the first sampled value of the first voltage signal and the first actual value of the first voltage signal, determine a plurality of second calibration points in the second coordinate system; Wherein, the vertical coordinate of the second calibration point is the first sampled value, and the horizontal coordinate of the second calibration point is the first actual value; S103A5. A second calibration equation is obtained by fitting the second calibration point; wherein, the second calibration equation is a linear equation in two variables with the first actual value as the independent variable and the first sampled value as the dependent variable. S103A6. The correction coefficient in the second calibration equation is determined as the voltage acquisition correction value of the detection chip 3.

[0062] In this embodiment, the process is for calibrating the FV and MV functions of the detection chip 3. In this process, the lower-level machine can send a corresponding calibration command as a control signal to the main control chip 1 for each detection chip 3. The main control chip 1 controls the I / O expansion chip in the internal calibration circuit 2 according to the control signal. The I / O expansion chip further controls the relay to switch on and off, obtaining a target calibration channel for that detection chip 3. Furthermore, the main control chip 1 can control the signal channel controller 61 in the signal channel controller array 6, making the output of the detection chip 3 connected to an external signal channel. Further, the signal controller 51 in the signal controller array 5, corresponding to the detection chip 3, controls the output of the detection chip 3 to output a first voltage signal.

[0063] The first voltage signal is output to the internal calibration circuit 2 and sampled by the correction ADC in the internal calibration circuit 2. The correction ADC transmits the value of the sampled electrical signal as the first sample value of the first voltage signal to the main control chip 1. The main control chip 1 combines the first preset electrical signal value set for the first voltage signal with the first sample value, and calibrates the FV function of the detection chip 3 through a preset calibration algorithm.

[0064] Simultaneously, the main control chip 1 acquires the actual value of the first voltage signal output from the measurement port of the detection chip 3 through the internal measurement channel 4. This first actual value is then combined with the first sampled value, and a preset calibration algorithm is used to calibrate the MV function of the detection chip 3.

[0065] It should be noted that the correction ADC in the internal calibration circuit 2 has already been calibrated. During the calibration of the FV function, the first sampled value can be considered as the actual voltage signal value output by the output terminal of the detection chip 3. By determining the deviation between this value and the set value, the deviation between the actual voltage output capability of the detection chip 3 and the set value of the voltage output can be obtained, thereby calibrating the FV function. During the calibration of the MV function, the first actual value can be the electrical signal value measured by the detection chip 3 in response to the first voltage signal. By comparing this value with the first sampled value, the deviation between the measurement capability of the detection chip 3 and the actual output can be determined, thereby calibrating the MV function.

[0066] In one possible implementation, the internal calibration circuit 2 can be equipped with multiple correction ADCs and multiple sets of resistors. During the calibration process, multiple non-interfering target calibration channels can be turned on simultaneously to calibrate multiple detection chips 3 at the same time, thereby improving calibration efficiency.

[0067] After acquiring multiple first sampled values, first actual values, and corresponding first set electrical signal values, multiple first calibration points can be obtained in a first coordinate system, with the first sampled values ​​as the abscissa and the first set electrical signal values ​​as the ordinate. By performing fitting operations on these first calibration points using a lower-level computer, a linear equation in two variables can be obtained, which is the first calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the first calibration equation, thereby obtaining the voltage output correction value of the detection chip 3.

[0068] Simultaneously, multiple second calibration points can be calculated in a second coordinate system using the first actual value as the x-axis and the first sampled value as the y-axis. By fitting these second calibration points using a lower-level computer, a linear equation in two variables can be obtained, which is the second calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the second calibration equation, thereby obtaining the voltage acquisition correction value of the detection chip 3.

[0069] In one possible implementation, the above calibration process can be carried out as follows: Figure 5 The flowchart shown here is for reference only. Figure 5 Taking this as an example, the process of FV and MV calibration described above will be explained.

[0070] In combination with the above Figure 1 The test circuit shown can be used to calibrate the FV and MV functions of the detection chip. The lower-level computer can first send a control signal to the main control chip, and the main control chip can then initialize the calibration process.

[0071] The main control chip can first traverse all the output signal channels of the detection chips through the signal controller array, shutting down the output of these signal channels to prevent the detection chips from being in an output state and causing circuit damage if they directly output after power-on. After shutting down all signal channels, the initialization of the FV and MV calibration process is completed. Then, the judgment program can be entered to determine whether all output signal channels of the detection chips that need calibration have been calibrated. If all are calibrated, the FV and MV calibration process can be terminated. If there are any uncalibrated output signal channels of the detection chips, the subsequent calibration program will be executed.

[0072] Furthermore, the test circuit can be switched to a specific calibration mode depending on the calibration content to be performed. Figure 1Regarding the test circuit, since the external signal channel has 6 signal lines, while the internal calibration circuit only has 3 sets of resistors and 3 correction ADCs, only 3 detection chips can be calibrated at the same time. To avoid interference between nearby chips and data lines, [the following can be done]: Figure 1 The 288 output signal channels of the 144 detection chips are divided into 6 groups, namely groups 0-47, 48-95, 96-143, 144-191, 192-239, and 240-287, which are respectively groups 1, 2, 3, 4, 5, and 6. Detection chips in groups 1, 3, and 5 are calibrated simultaneously, as are those in groups 2, 4, and 6. Calibration of groups 1, 3, and 5 can be performed using one on-board voltage calibration mode, while calibration of groups 2, 4, and 6 can be performed using another. This can be achieved through the formula... The on-board voltage calibration mode corresponding to a given output signal channel can be determined based on the channel number. This refers to the output signal channel number. Within the range of these channel numbers, two possible modes, Mode 29 and Mode 30, can be calculated. The lower-level computer, using the instructions contained in the control signals, can control the main control chip to enter the corresponding on-board calibration mode and activate the corresponding circuit structure via these two values ​​(29 and 30). Mode 29 and Mode 30 can each represent an on-board voltage calibration mode, i.e., a calibration mode that performs calibration by acquiring voltage.

[0073] The calibration mode here refers to controlling a switching device (e.g., a relay) in the test circuit to establish a target calibration channel between the calibration ADC and the signal output terminal of the target detection chip, thereby allowing the calibration ADC to receive and acquire the electrical signal value at that output terminal. The different numbered modes are pre-set control logics for the switching devices that establish different calibration channels. These control logics are pre-stored in a storage space connected to the main control chip. The main control chip can read the corresponding control logic based on the number and control the switching devices in the test circuit to establish the calibration channel. The mode numbers can be set according to actual conditions and are not limited here.

[0074] Furthermore, the type of electrical signal that needs to be measured by the measurement port corresponding to the output signal channel of the detection chip to be calibrated can be set. For the current FV and MV calibration, the electrical signal that the detection chip needs to measure and output is set to the actual value of the first voltage signal.

[0075] After the measurement values ​​are set, the correction values ​​for the FV and MV functions of the output signal channel can be reset in the storage space of the main control chip. The reset process is to reset the correction coefficients (i.e. the slope and intercept of the two linear equations) to 1 and 0 respectively.

[0076] After the reset is complete, the output voltage of the target output signal channel of the target detection chip can be set to 0V first through the signal controller. Then, the optocoupler relay of the output signal channel can be turned on through the relay driver.

[0077] Based on the set voltage points, the target detection chip outputs the corresponding first voltage signal through the target output signal channel. The main control chip samples these signals through a correction ADC and an internal measurement channel, obtaining the first sampled value from the correction ADC and the first actual value from the internal measurement channel, until sampling at the set voltage points is complete. For each voltage point, multiple pairs of values ​​are obtained from the first sampled value and the first actual value. For example, sampling can be performed at nine different voltage points for each detection chip's target output signal channel, resulting in nine pairs of values.

[0078] After sampling is complete, the output of the signal channel can be restored to 0V, and the optocoupler relay corresponding to the output signal channel can be turned off. Multiple pairs of sampled first values ​​and first actual values ​​are uploaded to the lower-level computer, which calculates the correction value and sends it to the non-volatile storage space connected to the main control chip for storage. Then, the system switches to the next output signal channel of the target detection chip until the voltage acquisition correction value and voltage output correction value of all output signal channels of all detection chips in the test circuit are obtained. After each output signal channel is matched and recorded, the calibration of the FV and MV functions is completed.

[0079] After determining the correction value, the calibration effect of that value can be verified. Let's assume the accuracy specification of the FV function is... After applying the correction value to the detection chip, the FV function of the detection chip is controlled to output a voltage value of 2V, and the voltage collected by the correction ADC is 2.000041V.

[0080] The maximum accuracy error of the FV function of this chip is then: The error is The calculated error percentage is: If the error percentage does not exceed the preset threshold of 100%, then the voltage output correction value of the output signal channel is verified.

[0081] Similarly, assuming the accuracy metric for the MV function is If the voltage value collected through the internal measurement channel at the same time is 2.000096V, then the error is... The calculated error percentage is: If the error percentage does not exceed the preset threshold of 100%, then the voltage acquisition correction value of the output signal channel is verified.

[0082] In another embodiment provided in this disclosure, the test electrical signal is a first current signal; the test circuit further includes: an internal measurement channel 4; the detection chip 3 is connected to the main control chip 1 through the internal measurement channel 4. In step S101 above, "switching the conduction state of the relay array 22 according to the received control signal to establish a target calibration channel between the output of the target detection chip 3 and the corresponding correction ADC in the internal calibration circuit 2" can be implemented as follows: The relay array 22 is switched on and off multiple times according to the received control signal, so as to establish a target calibration channel between the output terminal of the target detection chip 3 and the corresponding correction ADC in the internal calibration circuit 2. Each target calibration channel is matched with a different set first current signal. In step S102 above, "controlling the target detection chip 3 to output a test electrical signal to the target calibration channel and sampling the output electrical signal value" can be implemented as follows: For each established target calibration channel, the target detection chip 3 is controlled to output a corresponding first current signal to the target calibration channel, and the sampled value of the first current signal for correcting the ADC sampling is obtained; Before step S103 above, "determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm," the method further includes: The actual values ​​of the different first current signals output by the target detection chip 3 for each established target calibration channel are obtained through the internal measurement channel 4. In step S103 above, "determining the correction value of the target detection chip 3 based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm" can be implemented as follows: S103B1. For each established target calibration channel, based on the second sample value of the first current signal acquired multiple times and the second set electrical signal value corresponding to the first current signal, determine multiple third calibration points in the third coordinate system. Wherein, the horizontal coordinate of the third calibration point is the second sampled value, and the vertical coordinate of the third calibration point is the second set electrical signal value; S103B2. A third calibration equation is obtained by fitting the third calibration point; wherein, the third calibration equation is a linear equation in two variables with the second sampled value as the independent variable and the second set electrical signal value as the dependent variable. S103B3, The correction coefficient in the third calibration equation is determined as the current output correction value of the detection chip 3; S103B4. For each established target calibration channel, based on the second sampled value of the first current signal and the second actual value of the first current signal, determine multiple fourth calibration points in the fourth coordinate system. Wherein, the vertical coordinate of the fourth calibration point is the second sampled value, and the horizontal coordinate of the second calibration point is the second actual value; S103B5. A fourth calibration equation is obtained by fitting the fourth calibration point; wherein, the fourth calibration equation is a linear equation in two variables with the second actual value as the independent variable and the second sampled value as the dependent variable. S103B6. The correction coefficient in the fourth calibration equation is determined as the current acquisition correction value of the detection chip 3.

[0083] In this embodiment, the process is for calibrating the FI and MI functions of the detection chip 3. In this process, the lower-level machine can send corresponding calibration commands as control signals to the main control chip 1 for each detection chip 3. The main control chip 1 controls the I / O expansion chip in the internal calibration circuit 2 according to the control signal. The I / O expansion chip further controls the relay to switch on and off, obtaining a target calibration channel for that detection chip 3. Further, the main control chip 1 can control the signal channel controller 61 in the signal channel controller array 6, making the output of the detection chip 3 connected to an external signal channel. Further, the signal controller 51 in the signal controller array 5, corresponding to the detection chip 3, controls the output of the detection chip 3 to output a first current signal. It should be noted that since the current output of the detection chip 3 has different levels, the resistance value in the target calibration channel established for each level is also different to match these levels. These different resistance values ​​can be matched with different current levels, providing a corresponding dynamic range to meet the calibration requirements of different current levels.

[0084] After the first current signal is output to the internal calibration circuit 2, it is sampled by the correction ADC in the internal calibration circuit 2. The correction ADC transmits the value of the sampled electrical signal as the second sampled value of the first current signal to the main control chip 1. The main control chip 1 combines the second preset electrical signal value set for the first current signal with the second sampled value, and calibrates the FI function of the detection chip 3 through a preset calibration algorithm.

[0085] Simultaneously, the main control chip 1 acquires the second actual value of the first current signal output from the measurement port of the detection chip 3 through the internal measurement channel 4. This second actual value is then combined with the second sampled value, and a preset calibration algorithm is used to calibrate the MI function of the detection chip 3.

[0086] During the calibration of the FI function, the second sampled value can be considered as the actual current signal value output by the output terminal of the detection chip 3. By determining the deviation between this value and the set value, the deviation between the actual current output capability of the detection chip 3 and the set value of the current output can be obtained, thereby calibrating the FI function. During the calibration of the MI function, the first actual value can be the electrical signal value measured by the detection chip 3 in response to the first current signal. By comparing this value with the first sampled value, the deviation between the measurement capability of the detection chip 3 and the actual output can be determined, thereby calibrating the MI function.

[0087] In one possible implementation, the internal calibration circuit 2 can be equipped with multiple correction ADCs and multiple sets of resistors. During the calibration process, multiple non-interfering target calibration channels can be turned on simultaneously to calibrate multiple detection chips 3 at the same time, thereby improving calibration efficiency.

[0088] After acquiring multiple second sampled values, second actual values, and corresponding second set electrical signal values, multiple third calibration points can be obtained in a third coordinate system using the second sampled values ​​as the abscissa and the second set electrical signal values ​​as the ordinate. By fitting these third calibration points through a lower-level computer, a linear equation in two variables can be obtained, which is the third calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the third calibration equation, thereby obtaining the current output correction value of the detection chip 3.

[0089] Simultaneously, multiple fourth calibration points can be calculated in the fourth coordinate system using the second actual value as the abscissa and the second sampled value as the ordinate. By fitting these fourth calibration points through a lower-level computer, a linear equation in two variables can be obtained, which is the fourth calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the fourth calibration equation, thereby obtaining the current acquisition correction value of the detection chip 3.

[0090] In one possible implementation, the above calibration process can be carried out as follows: Figure 6 The flowchart shown here is for reference only. Figure 6 Taking this as an example, the process of FI and MI calibration described above will be explained.

[0091] Combination such as Figure 1 The test circuit shown can be used to calibrate the FI and MI functions of the detection chip. First, the lower-level computer sends a control signal to the main control chip, and the main control chip initializes the calibration process.

[0092] The main control chip first uses the signal controller array to traverse all the output signal channels of the detection chips, shutting down the output of these channels to prevent any detection chips from still outputting signals upon power-up, which could damage the circuit. After shutting down all signal channels, the initialization of the FI and MI function calibration process is completed. Then, the judgment program can be entered to determine whether the output signal channels of the detection chips requiring calibration have been calibrated. If the selected signal channels are calibrated, the FI and MI calibration process can be terminated. If any of the selected output signal channels are not calibrated, subsequent calibration procedures are executed.

[0093] After the initialization of the calibration process is completed, the measurement port of the target detection chip can be set to determine the type of signal that the measurement port needs to measure and output. Since it is a calibration of FI and MI functions, it can be set to the value of the current that the measurement port needs to measure and output (i.e., the second actual value).

[0094] Furthermore, the output current of the target output signal channel of the target detection chip can be set to 0mA first through the signal controller. Then, the optocoupler relay of the output signal channel is turned on through the relay driver. After that, the output signal channel can be judged again to determine whether all current levels contained in the output signal channel have been tested. If all have been tested, the process can return to the step of judging whether the selected output signal channel has been tested; if there are untested current levels, the calibration procedure is entered to test the untested current levels.

[0095] Furthermore, the test circuit can be switched to a specific calibration mode depending on the calibration content to be performed. Figure 1 For the test circuit in the example, assuming each signal channel can include 5 current output levels: 60mA, 1mA, 100uA, 10uA, and 2uA, the on-board current calibration mode can be divided into 10 modes. The calibration of each current level for the detection chips in groups 1, 3, and 5 can be one on-board current calibration mode, while the calibration of each current level for the detection chips in groups 2, 4, and 6 can be another on-board current calibration mode. (Using the formula...) The on-board current calibration mode corresponding to a given output signal channel can be determined based on the channel number. This is the number of the output signal channel; The current ranges are numbered. Assuming the current ranges of 60mA, 1mA, 100uA, 10uA, and 2uA are numbered 0, 1, 2, 3, and 4 respectively, within the range of the output signal channel numbers, 10 possible modes can be calculated, namely modes 19 to 28. The lower-level computer, using the instructions contained in the control signals, can control the main control chip to enter the corresponding on-board current calibration mode, thus activating the corresponding circuit structure (target calibration channel). Modes 19 to 28 can each represent an on-board current calibration mode, i.e., a calibration mode that performs calibration by acquiring current. The mode numbers here can be set according to actual conditions and are not limited here.

[0096] Furthermore, the correction values ​​of the FI and MI functions for the current range corresponding to the output signal channel, which are pre-stored in the storage space of the main control chip, can be reset. This reset process involves resetting the correction coefficients (i.e., the slope and intercept of the two linear equations) to 1 and 0, respectively.

[0097] After the reset is completed, the target detection chip is controlled to output the corresponding first current signal through the target output signal channel according to the current point set for each current level. The signal is then sampled by the correction ADC and the internal measurement channel. The second sampled value is obtained from the correction ADC and the second actual value is obtained from the internal measurement channel. This process continues until the sampling of the set current point is completed. For each current point, multiple combinations of values ​​can be obtained.

[0098] After sampling the second sampled value and the second actual value at one current level, the test circuit can be switched to the next board-level current calibration mode to activate another target calibration channel for calibration at the next current level. The main control chip can upload multiple pairs of acquired second sampled values ​​and second actual values ​​for the lower-level computer to calculate the correction value. This process continues until all current points at all current levels of the target output signal channel of the target detection chip have acquired the second sampled values ​​and the second actual values. For example, for each current level of each output signal channel, nine different current points can be sampled within that level.

[0099] After sampling is complete, the output of the signal channel can be restored to 0mA, and the optocoupler relay corresponding to the output signal channel can be turned off. During the sampling process of each current point, the sampled second value and the second actual value can be uploaded to the lower-level computer, which calculates the correction value and sends it to the non-volatile storage space connected to the main control chip for storage. Then, switch to the next output signal channel of the target detection chip until the current acquisition correction value and current output correction value of all output signal channels of all detection chips in the test circuit are obtained. After corresponding and recording each output signal channel, the calibration of FI and MI functions is completed.

[0100] After determining the correction value, the calibration effect of that value can be verified. Let's assume the accuracy specification of the FI function is... After applying the correction value to the detection chip, the FI function of the detection chip is controlled to output a current value of 10mA, and the current collected by the correction ADC is 9.9971mA.

[0101] The maximum accuracy error of the chip's FI function is then... The error is The calculated error percentage is: If the error percentage does not exceed the preset threshold of 100%, then the current output correction value of the output signal channel is verified.

[0102] Similarly, assuming the accuracy index of the MI function is At the same time, the current value collected through the internal measurement channel is 9.9988mA, then the error is... The calculated error percentage is: If the error percentage does not exceed the preset threshold of 100%, then the current acquisition correction value of the output signal channel is verified.

[0103] In another embodiment provided in this disclosure, the test electrical signal is a clamping signal; In step S102 above, "controlling the target detection chip 3 to output a test electrical signal to the target calibration channel and sampling the output electrical signal value" can be implemented as follows: S102A1, Set different clamping voltage values ​​for the target detection chip 3; the clamping voltage values ​​include: high clamping voltage value and low clamping voltage value; S102A2, Control the target detection chip 3 to output the corresponding clamping signal to the target calibration channel according to the different clamping voltage values, and obtain the sampled value of the second voltage signal output by the correction ADC respectively; In step S103 above, "determining the correction value of the target detection chip 3 based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm" can be implemented as follows: S103C1. Based on the third set electrical signal value of the high clamping voltage value and the third sampled value of the second voltage signal corresponding to the high clamping voltage value, determine a plurality of fifth calibration points in the fifth coordinate system; wherein, the horizontal coordinate of the fifth calibration point is the third sampled value, and the vertical coordinate of the fifth calibration point is the third set electrical signal value; S103C2. The fifth calibration equation is obtained by fitting the fifth calibration point; wherein the fifth calibration equation is a linear equation in two variables with the third sampled value as the independent variable and the third set electrical signal value as the dependent variable. S103C3, The correction coefficient in the fifth calibration equation is determined as the high clamping correction value of the detection chip 3; S103C4. Based on the fourth set electrical signal value of the low clamping voltage value and the fourth sample value of the second voltage signal corresponding to the low clamping voltage value, determine a plurality of sixth calibration points in the sixth coordinate system; wherein, the horizontal coordinate of the sixth calibration point is the fourth sample value, and the vertical coordinate of the sixth calibration point is the fourth set electrical signal value; S103C5. The sixth calibration equation is obtained by fitting the sixth calibration point; wherein the sixth calibration equation is a linear equation in two variables with the fourth sampled value as the independent variable and the fourth set electrical signal value as the dependent variable. S103C6, The correction coefficient in the sixth calibration equation is determined as the low clamping correction value of the detection chip 3.

[0104] In this embodiment, the process is a calibration process for the clamping function of the detection chip 3. Specifically, clamping is the function of the detection chip 3 to limit and fix the voltage amplitude of the output signal. Its function is to forcibly constrain the voltage level output by the detection chip 3 to a set value. When the voltage in the actual circuit attempts to exceed the set clamping value, the detection chip 3 will clamp the voltage to the set value by adjusting the current.

[0105] In this process, the lower-level computer can send corresponding calibration commands as control signals to the main control chip 1 for each detection chip 3. The main control chip 1 further controls the relay to switch on and off according to the control signal to obtain a target calibration channel for that detection chip 3. Furthermore, the main control chip 1 can control the output terminal of the detection chip 3 to be connected to the external signal channel, and set high clamping voltage values ​​and low clamping voltage values ​​for the output signal channel of each detection chip through the signal controller array 5.

[0106] After setting the clamping value, a clamping signal can be output through the output signal channel. It should be noted that the clamping signal can be a current signal with a specific initial value. This current signal is output to the target calibration channel, generating a voltage value across a resistor in that calibration channel. If this voltage value exceeds the set clamping voltage value, the detection chip 3 will adjust the current value of the output clamping signal to match the set clamping voltage value. The voltage value of the second voltage signal across the adjusted resistor is collected by the calibration ADC as a sample value, and combined with the set value of the clamping signal, the clamping function is calibrated.

[0107] The calibration of the clamping function can include two parts: calibration of the high clamping voltage value and calibration of the low clamping voltage value. The clamping signal for the high clamping voltage value can be a positive current signal. A calibration ADC acquires the voltage output value of the detection chip 3 clamped by the high clamping voltage value (i.e., the third sample value of the second voltage signal). Different high clamping voltage values ​​are set multiple times, and the third sample value is acquired each time. Multiple third sample values ​​and the corresponding third set electrical signal value of the high clamping voltage value are obtained. Multiple fifth calibration points can be obtained in a fifth coordinate system with the third sample value as the abscissa and the third set electrical signal value as the ordinate. By fitting these fifth calibration points through a lower-level computer, a linear equation in two variables can be obtained, which is the fifth calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the fifth calibration equation, thereby obtaining the high clamping correction value of the detection chip 3.

[0108] The clamping signal for the low clamping voltage value can be a negative current signal. The voltage output value of the detection chip 3 clamped by the low clamping voltage value (i.e., the fourth sample value of the second voltage signal) is acquired by a correction ADC. Different low clamping voltage values ​​are set multiple times, and the fourth sample value is acquired each time. Multiple fourth sample values ​​and their corresponding fourth set electrical signal values ​​for the low clamping voltage value are obtained. Multiple sixth calibration points are obtained in the sixth coordinate system, with the fourth sample value as the x-axis and the fourth set electrical signal value as the y-axis. By fitting these sixth calibration points through a lower-level computer, a linear equation in two variables can be obtained, which is the sixth calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the sixth calibration equation, thereby obtaining the low clamping voltage correction value of the detection chip 3.

[0109] In one possible implementation, the above calibration process can be carried out as follows: Figure 7 The flowchart shown here is for reference only. Figure 7 Taking this as an example, the above clamping calibration process will be explained.

[0110] In combination with the above Figure 1 The test circuit shown can be used to calibrate the clamping function of the detection chip. First, the lower-level computer sends a control signal to the main control chip, and the main control chip initializes the calibration process.

[0111] The main control chip can first traverse all the output signal channels of the detection chips through the signal controller array, shutting down the output of these signal channels to complete the initialization of the clamping calibration process. Then, it can enter the judgment program to determine whether the output signal channels of the detection chips to be calibrated have been calibrated. If the selected signal channels are calibrated, the clamping calibration process can end. If there are uncalibrated output signal channels among the selected output signal channels, the subsequent calibration program will be executed.

[0112] After initialization, the test circuit can be switched to a specific calibration mode based on the calibration requirements. Figure 1 For the test circuit in the circuit, calibration for groups 1, 3, and 5 can be a type of on-board voltage calibration mode for clamping, while calibration for groups 2, 4, and 6 can be a type of on-board voltage calibration mode for clamping. This can be achieved through the formula... The on-board voltage calibration mode corresponding to a given output signal channel can be determined based on the channel number. This refers to the output signal channel number. Within the range of these channel numbers, two possible modes, Mode 43 and Mode 44, can be calculated. The lower-level computer, using the instructions contained in the control signals, can control the main control chip to enter the corresponding on-board calibration mode and activate the corresponding circuit structure through these two values ​​(43 and 44). Modes 43 to 44 can each represent an on-board voltage calibration mode, i.e., a calibration mode for clamping calibration. The mode numbers here can be set according to actual conditions and are not limited here.

[0113] After the control test circuit enters the corresponding calibration mode, it can reset the high clamping voltage and low clamping voltage correction values ​​for the target output signal channel that are pre-stored in the main control chip's storage space. This reset process involves resetting the correction coefficients (i.e., the slope and intercept of the two linear equations) to 1 and 0, respectively. Then, the output signal channel can be re-evaluated to determine whether all voltage points within the output signal channel have been tested. If all have been tested, the process returns to the step of determining whether the selected output signal channel has been tested and calculates the corresponding correction value. If there are untested voltage points, the calibration procedure is entered to test these untested voltage points.

[0114] Set high clamping and low clamping values ​​for the target output signal channel of the target detection chip, and turn on the optocoupler relay corresponding to the target output signal channel.

[0115] The detection chip outputs a clamping signal. If calibration is performed for a high clamping value, a positive current is output; if calibration is performed for a low clamping value, a negative current is output. After the clamping signal is input into the target calibration channel, a voltage is generated across the resistor in the target calibration channel. The detection chip can adjust the value of the clamping signal according to the value of this voltage so that the voltage across the resistor can be maintained at the set clamping value.

[0116] The target detection chip outputs a clamping signal through the target output signal channel. The voltage value in the target calibration channel, adjusted by the detection chip, is sampled by a correction ADC. The clamping signal value is then used as the third or fourth sampled value. After sampling the third or fourth sampled value corresponding to one clamping value, the next clamping value can be set, and the corresponding third or fourth sampled value can be obtained, until testing is completed for all clamping value points. It should be noted that when calibrating for high clamping values, the initial value of the clamping signal output by the detection chip is the same for each clamping value point; similarly, when calibrating for low clamping values, the initial value of the clamping signal output by the detection chip is also the same for each clamping value point.

[0117] After sampling is complete, the output of the signal channel can be restored to 0mA, and the corresponding optocoupler relay can be turned off. During calibration, the third or fourth sampled value can be uploaded to the lower-level computer, which calculates the correction value and then sends it to the non-volatile storage space connected to the main control chip. The system then switches to the next output signal channel of the target detection chip until the low-clamping correction value and high-clamping correction value of all output signal channels of all detection chips in the test circuit are obtained. After each output signal channel is mapped and recorded, the clamping function calibration is complete.

[0118] After determining the correction value, the calibration effect of that value can be verified. Let's assume the accuracy specification of the high-clamping function is... After applying the correction value to the detection chip, the high clamping voltage is set to 3V, and the detection chip outputs a 1mA current. If the voltage acquired by the correction ADC is 2.99953V, then the error of the clamping function is... The error percentage is If the error percentage does not exceed the preset threshold of 100%, then the high clamping voltage correction value of the output signal channel is verified. Similarly, a low clamping voltage can be set, and a negative current can be output to verify the low clamping voltage correction value.

[0119] In another embodiment provided in this disclosure, the test electrical signal is a high clamping current signal; In step S101 above, "switching the conduction state of the relay array 22 according to the received control signal to establish a target calibration channel between the output of the target detection chip 3 and the corresponding correction ADC in the internal calibration circuit 2" can be implemented as follows: The relay array 22 is switched on and off multiple times according to the received control signal to establish a target calibration channel between the output of the target detection chip 3 and the corresponding correction ADC in the internal calibration circuit 2. Each target calibration channel is matched with a different set high clamping current value. In step S102 above, "controlling the target detection chip 3 to output a test electrical signal to the target calibration channel and obtaining the electrical signal value of the ADC sampling correction" can be implemented as follows: For each established target calibration channel, the target detection chip 3 is controlled to output a corresponding high clamping current signal to the target calibration channel according to the different high clamping current values, and the sampled value of the second current signal output by the correction ADC is obtained respectively. In step S103 above, "determining the correction value of the target detection chip 3 based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm" can be implemented as follows: S103D1. Based on the fifth set electrical signal value of the high clamping current value and the fifth sampled value of the second current signal corresponding to the high clamping current value, determine a plurality of seventh calibration points in the seventh coordinate system; wherein, the horizontal coordinate of the seventh calibration point is the fifth sampled value, and the vertical coordinate of the seventh calibration point is the fifth set electrical signal value; S103D2. The seventh calibration equation is obtained by fitting the seventh calibration point; wherein the seventh calibration equation is a linear equation in two variables with the fifth sampled value as the independent variable and the fifth set electrical signal value as the dependent variable. S103D3, The correction coefficient in the seventh calibration equation is determined as the high clamping current correction value of the detection chip 3.

[0120] In this embodiment, the process is a calibration process for the clamping function of the detection chip 3. Specifically, clamping is the function of the detection chip 3 to limit and fix the current amplitude of the output signal. Its function is to forcibly constrain the magnitude of the current output by the detection chip 3 to a set value. When the current in the actual circuit attempts to exceed the set clamping value, the detection chip 3 will clamp the current to the set value by adjusting the voltage.

[0121] In this process, the lower-level machine can send corresponding calibration commands as control signals to the main control chip 1 for each detection chip 3. The main control chip 1 further controls the relay to switch on and off according to the control signal to obtain a target calibration channel for that detection chip 3. Furthermore, the main control chip 1 can control the output terminal of the detection chip 3 to be connected to the external signal channel, and set a high clamping current value for the output signal channel of each detection chip through the signal controller array 5.

[0122] After setting the high clamping current value, a clamping signal can be output through the output signal channel of the detection chip. It should be noted that the clamping signal can be a voltage signal with a specific initial value, which is output to the target calibration channel to generate current. If the generated current value exceeds the set high clamping current value, the detection chip 3 will adjust the voltage value of the output clamping signal to match the set clamping current value. The adjusted second current signal value in this calibration channel is collected by the calibration ADC as a sample value, and combined with the set high clamping current value of the clamping signal to calibrate the high clamping current function.

[0123] It should be noted that the clamping signal corresponding to the high clamping current can be a positive voltage signal. For different high clamping current settings, the second current signal also needs to be sampled in the target calibration channel corresponding to the current value's range. For each current value range, multiple high clamping currents can be set for calibration, obtaining multiple fifth sampled values ​​of the second current signal.

[0124] After acquiring multiple fifth sample values ​​and corresponding high-clamping current values, a fifth set electrical signal value is obtained. Multiple seventh calibration points are obtained in the seventh coordinate system, with the fifth sample values ​​as the abscissa and the fifth set electrical signal value as the ordinate. By fitting these seventh calibration points through a lower-level computer, a linear equation in two variables can be obtained, which is the seventh calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the seventh calibration equation, thereby obtaining the high-clamping current correction value of the detection chip 3.

[0125] In another embodiment provided in this disclosure, the test electrical signal is a low clamping current signal; The test circuit further includes: an internal measurement channel 4; the detection chip 3 is connected to the main control chip 1 through the internal measurement channel 4; In step S102 above, "controlling the target detection chip 3 to output a test electrical signal to the target calibration channel and sampling the output electrical signal value" can be implemented as follows: S102B1. Set different low clamping current values ​​for the target detection chip 3; S102B1. Control the target detection chip 3 to output a corresponding low clamping current signal to the target calibration channel according to the different low clamping current values; Before step S103 above, "determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm," the method further includes: The actual value of the third current signal output by the target detection chip 3 for different low clamping current values ​​is obtained through the internal measurement channel 4. In step S103 above, "determining the correction value of the target detection chip 3 based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm" can be implemented as follows: S103E1. Based on the sixth set electrical signal value of the low clamping current value and the sixth sample value of the third current signal corresponding to the low clamping current value, determine a plurality of eighth calibration points in the eighth coordinate system; wherein, the horizontal coordinate of the eighth calibration point is the sixth sample value, and the vertical coordinate of the eighth calibration point is the sixth set electrical signal value. S103E2. The eighth calibration equation is obtained by fitting the eighth calibration point; wherein the eighth calibration equation is a linear equation in two variables with the sixth sampled value as the independent variable and the sixth set electrical signal value as the dependent variable. S103E3, The correction coefficient in the eighth calibration equation is determined as the low clamping current correction value of the detection chip 3.

[0126] In this embodiment of the disclosure, in this low-clamp current calibration process, the lower-level computer can issue a corresponding calibration command as a control signal to the main control chip 1 for each detection chip 3. The main control chip 1 further controls the relay to switch on and off according to the control signal to obtain a target calibration channel for the detection chip 3. Furthermore, the main control chip 1 can control the output terminal of the detection chip 3 to be connected to the external signal channel, and set a low clamp current value for the output signal channel of each detection chip through the signal controller array 5.

[0127] After setting the low clamping current value, a clamping signal is output. If the current value generated by the clamping signal is lower than the set low clamping current value, the detection chip 3 will adjust the voltage value of the output clamping signal to match the set clamping current value.

[0128] It should be noted that the clamping signal corresponding to the low clamping current can be a negative voltage signal. Calibration for the low clamping current value requires a specially designed resistor in the internal calibration circuit 2, and a targeted calibration circuit based on this resistor. This resistor can be a small resistor, for example, a 12.475Ω resistor. The current output from all negative current ranges of the detection chip 3 can be applied to this resistor, forming a loop through the correction ADC. Because the 12.475Ω resistor is too small, the voltage across it is also extremely small, resulting in low accuracy for the correction ADC's sampling of this value. In this case, the MI function of the detection chip 3 can be used to sample this current, obtaining the sixth sampled value of the third current value. Because a small resistor is specifically designed for the low clamping current, the detection chip has a large dynamic range on the negative current side. Assuming a voltage of -1.5V, the actual output current is... The maximum negative clamping current of the 60mA range is -66mA. Since the clamping current setting can only reach a maximum of 85% of the range's maximum current, the maximum current of the range needs to exceed... It can be seen that this small resistor allows the negative current setting to achieve its maximum output current.

[0129] For different low clamping current settings, the second current signal also needs to be sampled in the target calibration channel corresponding to the current value's range. Within each current value range, multiple low clamping currents can be set for calibration, obtaining multiple sixth sample values ​​of the second current signal.

[0130] After acquiring multiple sixth sample values ​​and corresponding low-clamping current values, a sixth set electrical signal value is obtained. Multiple eighth calibration points are obtained in the eighth coordinate system, with the sixth sample values ​​as the abscissa and the sixth set electrical signal value as the ordinate. By fitting these eighth calibration points through a lower-level computer, a linear equation in two variables can be obtained, which is the eighth calibration equation. Furthermore, the slope and intercept of the linear equation in two variables can be determined as correction coefficients for the eighth calibration equation, thereby obtaining the low-clamping current correction value of the detection chip 3.

[0131] In one possible implementation, the above calibration process can be carried out as follows: Figure 8 The flowchart shown here is for reference only. Figure 8 Taking this as an example, the above clamping calibration process will be explained.

[0132] In combination with the above Figure 1 The test circuit shown can be used to calibrate the clamping function of the detection chip. First, the lower-level computer sends a control signal to the main control chip, and the main control chip initializes the calibration process.

[0133] The main control chip can first traverse all the output signal channels of the detection chips through the signal controller array, shutting down the output of these signal channels to complete the initialization of the clamp calibration process. Then, it can enter the judgment program to determine whether the output signal channels of the detection chips to be calibrated have been calibrated. If the selected signal channels are calibrated, the clamp calibration process can end. If there are uncalibrated output signal channels among the selected output signal channels, the subsequent calibration program will be executed.

[0134] After the initialization of the calibration process is completed, it can be further determined whether the current ranges of different clamp currents of the selected output signal channel have been tested. If all current ranges have been tested, the process can return to the above steps of determining the output signal channel. If there are untested current ranges, the calibration procedure can continue to calibrate those ranges.

[0135] After entering a test program at a specific current level, the test circuit can be switched to a specific calibration mode according to the calibration requirements. Figure 1 For the test circuit in the example, assuming each signal channel can include 5 current output levels: 60mA, 1mA, 100uA, 10uA, and 2uA, the on-board current calibration mode for clamp current calibration can be divided into 10 modes. The calibration of each current level for the detection chips in groups 1, 3, and 5 can be one on-board current calibration mode, and the calibration of each current level for the detection chips in groups 2, 4, and 6 can be another on-board current calibration mode. (Using the formula...) The on-board voltage calibration mode for clamp current calibration can be obtained based on the output signal channel number. This is the number of the output signal channel; The current ranges are numbered as follows: Assuming current ranges of 60mA, 1mA, 100uA, 10uA, and 2uA, numbered 0, 1, 2, 3, and 4 respectively, within the range of output signal channel numbers, 10 possible modes can be calculated, namely modes 33 to 42. The lower-level computer can include these values ​​in the instructions contained in the control signals. The main control chip controls the test circuit to enter the corresponding on-board calibration mode based on these values, activating the corresponding circuit structure (target calibration channel). Modes 33 to 42 can each represent an on-board current calibration mode, i.e., a calibration mode for clamping current. The mode numbers here can be set according to actual conditions and are not limited here.

[0136] After the control test circuit enters the corresponding calibration mode, it can reset the high clamping current and low clamping current correction values ​​for the target output signal channel that are pre-stored in the main control chip's storage space. This reset process involves resetting the correction coefficients (i.e., the slope and intercept of the two linear equations) to 1 and 0, respectively. After the reset is complete, the current point determination can be performed. If all current points have been tested under the selected current range, the current range determination step can be returned to, and the correction value can be calculated. If there are untested current points, the test procedure for those points can be entered.

[0137] In the test program at any current point, the measurement port of the target detection chip can be set first to set the type of signal that the measurement port needs to measure and output. Here, it can be set to the value of the current that the measurement port needs to measure and output (i.e., the sixth sampling value).

[0138] Furthermore, a high clamping current value and a low clamping current value are set for the target output signal channel of the target detection chip, and the optocoupler relay corresponding to the target output signal channel is turned on.

[0139] The detection chip outputs a clamping signal. If calibration is performed for a high clamping value, a positive voltage is output; if calibration is performed for a low clamping value, a negative voltage is output. After this clamping signal is input to the target calibration channel, a current value can be generated within that channel. The detection chip can adjust the clamping signal value based on this current value, ensuring that the current value in the target calibration channel is maintained at the set clamping value.

[0140] The target detection chip outputs a clamping signal through the target output signal channel. If the output is a high clamping signal, the current value in the target calibration channel adjusted by the detection chip is sampled by the correction ADC, which is the fifth sampling value.

[0141] If the output is a low clamping current signal, the value of the current in the target calibration channel after adjustment by the detection chip is sampled through the internal measurement channel, which is the sixth sampling value.

[0142] After sampling the fifth or sixth sample value corresponding to a clamping value, the next clamping value can be set, and the fifth or sixth sample value corresponding to that clamping value can be obtained, until all clamping value points have been tested. It should be noted that when calibrating for high clamping values, the initial value of the clamping current signal output by the detection chip at each clamping value point is the same; similarly, when calibrating for low clamping values, the initial value of the clamping current signal output by the detection chip at each clamping value point is also the same.

[0143] After sampling is complete, the output of the signal channel can be restored to 0mA, and the corresponding optocoupler relay can be turned off. During the test, the fifth or sixth sampled value can be uploaded to the lower-level computer, which calculates the correction value and then sends it to the non-volatile storage space connected to the main control chip. The test then switches to the next output signal channel of the target detection chip until the low-clamping current correction value and high-clamping current correction value of all output signal channels of all detection chips in the test circuit are obtained. After each output signal channel is mapped and recorded, the clamping current function calibration is completed.

[0144] After determining the correction value, the calibration effect of that value can be verified. Let's assume the accuracy of the high-clamping current function at the 60mA setting is... After applying the correction value to the detection chip, the high clamping current is set to 30mA, and the detection chip outputs a 5V voltage. If the current acquired by the corrected ADC is 30.0022mA, then the error of the clamping function is... The maximum accuracy error is 3.00022mA, then the error percentage is... If the error percentage does not exceed the preset threshold of 100%, then the high clamping current correction value of the output signal channel is verified. Similarly, a low clamping current can be set, and a negative voltage can be output to verify the low clamping current correction value.

[0145] In another embodiment provided in this disclosure, there are multiple external signal channels; the circuit further includes: a signal controller array 5 and a signal channel controller array 6; The signal controller 51 in the signal controller array 5 is connected to the signal input terminals of the main control chip 1 and the corresponding detection chip 3, respectively; the signal channel controller 61 in the signal channel controller array 6 is connected to the signal output terminal of the corresponding detection chip 3 and the corresponding external signal channel, respectively. Before step S101 above, "switching the conduction state of the relay array according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit," the method further includes: The target detection chip 3 is determined according to the received control signal, and the target detection chip 3 is controlled by the signal controller 51; and / or Based on the received control signal, the conduction relationship of the target detection chip 3 corresponding to the external signal channel is controlled.

[0146] In this embodiment, the main control chip 1 can independently or in conjunction with the generated control signals to adjust the switching states of the signal controller 51 and the signal channel controller 61. When a specific target detection chip 3 needs to be operated, on the one hand, the corresponding signal controller 51 can control the chip to output a test electrical signal; on the other hand, the corresponding signal channel controller 61 can be controlled to be in a conducting state to establish an electrical connection between the output terminal of the target detection chip 3 and the designated external signal channel. At this time, the signal channel controller 61 corresponding to a non-target detection chip 3 can remain disconnected to avoid signal crosstalk. Based on the setting of multiple external signal channels, this embodiment can support a multi-channel parallel detection mode, that is, the main control chip 1 can simultaneously control different groups of signal controllers 51 and signal channel controllers 61 to be on, so that multiple target detection chips 3 can occupy different external signal channels to transmit data simultaneously, improving calibration efficiency.

[0147] In another embodiment provided in this disclosure, after step S103 "determining the correction value of the target detection chip by means of a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value", the following step is further included: A verification equation is established based on the correction value, the calibrated object is verified, and the percentage of error corresponding to the correction value is determined based on the verification result. The error percentage is compared with a first threshold. If the error percentage is less than the first threshold, the calibration object is determined to have passed calibration.

[0148] In this embodiment of the disclosure, after determining the correction value, it is also necessary to verify the correction value to determine whether the calibration using the correction value can meet the accuracy requirements.

[0149] The first threshold can be set to 100%, and the deviation after calibration can meet the corresponding accuracy requirements. The value of the first threshold can be adjusted according to actual needs to adapt to different calibration accuracy requirements.

[0150] Specifically, the verification equation can be a linear equation in two variables constructed using the slope and intercept in the correction coefficients. After sampling the signal output from the corresponding detection chip channel, the main control chip 1 can load the corresponding verification equation, use the sampled value as the independent variable, and output the verification equation to obtain the corresponding calculated value.

[0151] By combining this calculated value with the corresponding accuracy index, the error percentage of each correction value can be calculated, and based on the error percentage, it can be determined whether the correction value can pass the verification.

[0152] This disclosure also provides a testing apparatus, including: a testing circuit as described in any of the above embodiments, and / or a calibration method for a detection chip as described in any of the above embodiments.

[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of this disclosure can be implemented in hardware or by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions of the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0154] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the drawings are not necessarily essential for implementing this disclosure.

[0155] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0156] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0157] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A test circuit, characterized in that, include: The system comprises a main control chip, an internal calibration circuit, and a detection chip; the detection chip is connected to the internal calibration circuit via an external signal channel; the internal calibration circuit includes multiple sets of resistors with preset resistance values, a relay array, and a correction ADC. The main control chip is used to control the relay array according to the received control signal to turn on the calibration channel in the internal calibration circuit; input the test electrical signal generated by the detection chip into the calibration channel, and collect the value of the received test electrical signal through the correction ADC in the calibration channel; The detection chip is calibrated based on the collected electrical signal value and the corresponding set value. The detection chip is used to generate a test electrical signal and output it to the internal calibration circuit through the external signal channel.

2. The circuit as described in claim 1, characterized in that, The internal calibration circuit is also provided with a test signal interface for connecting to an external signal channel. The relays in the relay array are respectively set at the connection nodes between the resistor, the test signal interface and the correction ADC. They are used to switch the conduction relationship according to the first control command of the main control chip when calibrating the voltage-related function of the detection chip, so that the first end of the first target resistor is connected to the test signal interface and the correction ADC respectively, and a calibration channel is established between the test signal interface, the first target resistor and the correction ADC. or This is used to switch the conduction relationship according to the second control command of the main control chip when calibrating the current-related function of the detection chip, so that the test signal interface and the correction ADC are respectively connected to the first end of different second target resistors, and a calibration channel is established between the test signal interface, the second target resistor and the correction ADC.

3. The circuit as described in claim 1, characterized in that, The test circuit also includes: an internal measurement channel; The detection chip is connected to the main control chip through the internal measurement channel, so that the main control chip can obtain the actual value of the generated test electrical signal and send it to the internal measurement channel through the internal measurement channel.

4. The circuit as described in claim 1, characterized in that, The external signal channels are multiple; the circuit also includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are connected to the signal input terminals of the main control chip and the corresponding detection chip, respectively, and are used to control the corresponding detection chip to generate test electrical signals according to the third control instruction of the main control chip, and transmit them through the corresponding external signal channel. The signal channel controllers in the signal channel controller array are connected to the signal output terminals of the corresponding detection chips and the corresponding external signal channels, respectively, and are used to control the conduction relationship between the signal output terminals of the corresponding detection chips and the external signal channels according to the fourth control instruction of the main control chip.

5. The circuit as described in claim 2, characterized in that, The internal calibration circuit includes a preset number of resistor groups, and the resistance value of the resistors in each group is set according to the value range of the test electrical signal; the conduction relationship within each resistor group is switched by a relay array to establish a calibration channel within the group; each resistor group is provided with a test signal interface for connection to an external signal channel. For each resistor group, the first end of the resistor in the group is connected to the first common connection point and the second common connection point of the group, the first common connection point of the group is connected to the test signal interface corresponding to the group, and the second common connection point of the group is connected to the correction ADC corresponding to the group. The second end of the resistor is connected to the ground point; The first common connection point and the second common connection point of each resistor group are switched by a relay array to determine the resistor group connected to the test signal interface.

6. A calibration method for a detection chip, characterized in that, The detection chip is disposed in the test circuit, which also includes a main control chip and an internal calibration circuit; the output terminal of the detection chip is connected to the internal calibration circuit through an external signal channel; the internal calibration circuit includes multiple sets of resistors with preset resistance values, a relay array, and a correction ADC; The method includes: The relay array is switched to switch the conduction state according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit. The target detection chip is controlled to output a test electrical signal to the target calibration channel, and the output electrical signal value is sampled. The calibration value of the target detection chip is determined by a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value.

7. The method as described in claim 6, characterized in that, The test electrical signal is a first voltage signal; the test circuit also includes an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel. The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: The target detection chip is controlled to output different first voltage signals to the target calibration channel multiple times, and the sampled value of the first voltage signal output by the correction ADC is obtained respectively. Before determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: The actual values ​​of the different voltage signals output by the target detection chip are obtained through the internal measurement channel; The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the first sampled value of the first voltage signal and the first set electrical signal value corresponding to the first voltage signal, a plurality of first calibration points are determined in the first coordinate system; wherein, the horizontal coordinate of the first calibration point is the first sampled value, and the vertical coordinate of the first calibration point is the first set electrical signal value; The first calibration equation is obtained by fitting the first calibration point; wherein the first calibration equation is a linear equation in two variables with the first sampled value as the independent variable and the first set electrical signal value as the dependent variable. The correction coefficient in the first calibration equation is determined as the voltage output correction value of the detection chip; Based on the first sampled value and the first actual value of the first voltage signal, a plurality of second calibration points are determined in the second coordinate system; wherein, the vertical coordinate of the second calibration point is the first sampled value, and the horizontal coordinate of the second calibration point is the first actual value; The second calibration equation is obtained by fitting the second calibration point; wherein the second calibration equation is a linear equation in two variables with the first actual value as the independent variable and the first sampled value as the dependent variable. The correction coefficient in the second calibration equation is determined as the voltage acquisition correction value of the detection chip.

8. The method as described in claim 6, characterized in that, The test electrical signal is a first current signal; the test circuit also includes an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel. The step of switching the conduction state of the relay array according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit includes: The relay array is switched on and off multiple times according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit. Each target calibration channel is matched with a different set first current signal. The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: For each established target calibration channel, the target detection chip is controlled to output a corresponding first current signal to the target calibration channel, and the sampled value of the first current signal for correcting the ADC sampling is obtained; Before determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: The actual values ​​of the different first current signals output by the target detection chip for each established target calibration channel are obtained through the internal measurement channel; The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: For each established target calibration channel, based on the second sampled value of the first current signal acquired multiple times and the second set electrical signal value corresponding to the first current signal, multiple third calibration points are determined in the third coordinate system; wherein, the horizontal coordinate of the third calibration point is the second sampled value, and the vertical coordinate of the third calibration point is the second set electrical signal value; The third calibration equation is obtained by fitting the third calibration point; wherein the third calibration equation is a linear equation in two variables with the second sampled value as the independent variable and the second set electrical signal value as the dependent variable. The correction coefficient in the third calibration equation is determined as the current output correction value of the detection chip; For each established target calibration channel, multiple fourth calibration points are determined in the fourth coordinate system based on the second sampled value of the first current signal and the second actual value of the first current signal; wherein, the vertical coordinate of the fourth calibration point is the second sampled value, and the horizontal coordinate of the second calibration point is the second actual value; The fourth calibration equation is obtained by fitting the fourth calibration point; wherein the fourth calibration equation is a linear equation in two variables with the second actual value as the independent variable and the second sampled value as the dependent variable. The correction coefficient in the fourth calibration equation is determined as the current acquisition correction value of the detection chip.

9. The method as described in claim 6, characterized in that, The test electrical signal is a clamping signal; The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: Different clamping voltage values ​​are set for the target detection chip; the clamping voltage values ​​include: a high clamping voltage value and a low clamping voltage value; The target detection chip is controlled to output a corresponding clamping signal to the target calibration channel according to the different clamping voltage values, and the sampled value of the second voltage signal output by the correction ADC is obtained respectively. The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the third set electrical signal value of the high clamping voltage value and the third sampled value of the second voltage signal corresponding to the high clamping voltage value, a plurality of fifth calibration points are determined in the fifth coordinate system; wherein, the horizontal coordinate of the fifth calibration point is the third sampled value, and the vertical coordinate of the fifth calibration point is the third set electrical signal value; The fifth calibration equation is obtained by fitting the fifth calibration point; wherein the fifth calibration equation is a linear equation in two variables with the third sampled value as the independent variable and the third set electrical signal value as the dependent variable. The correction coefficient in the fifth calibration equation is determined as the high clamping correction value of the detection chip; Based on the fourth set electrical signal value of the low clamping voltage value and the fourth sample value of the second voltage signal corresponding to the low clamping voltage value, a plurality of sixth calibration points are determined in the sixth coordinate system; wherein, the horizontal coordinate of the sixth calibration point is the fourth sample value, and the vertical coordinate of the sixth calibration point is the fourth set electrical signal value; The sixth calibration equation is obtained by fitting the sixth calibration point; wherein the sixth calibration equation is a linear equation in two variables with the fourth sampled value as the independent variable and the fourth set electrical signal value as the dependent variable. The correction coefficient in the sixth calibration equation is determined as the low clamping correction value for the detection chip.

10. The method as described in claim 6, characterized in that, The test electrical signal is a high clamping current signal; The relay array is switched on and off according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit; including: The relay array is switched on and off multiple times according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit. Each target calibration channel is matched with a different set high clamping current value. The step of controlling the target detection chip to output a test electrical signal to the target calibration channel and obtaining the electrical signal value of the ADC sampling correction includes: For each established target calibration channel, the target detection chip is controlled to output a corresponding high clamping current signal to the target calibration channel according to the different high clamping current values, and the sampled value of the second current signal output by the correction ADC is obtained respectively. The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the fifth set electrical signal value of the high clamping current value and the fifth sampled value of the second current signal corresponding to the high clamping current value, a plurality of seventh calibration points are determined in the seventh coordinate system; wherein, the horizontal coordinate of the seventh calibration point is the fifth sampled value, and the vertical coordinate of the seventh calibration point is the fifth set electrical signal value; The seventh calibration equation is obtained by fitting the seventh calibration point; wherein the seventh calibration equation is a linear equation in two variables with the fifth sample value as the independent variable and the fifth set electrical signal value as the dependent variable. The correction coefficient in the seventh calibration equation is determined as the high clamping current correction value for the detection chip.

11. The method as described in claim 6, characterized in that, The test electrical signal is a low clamping current signal; The test circuit further includes: an internal measurement channel; the detection chip is connected to the main control chip through the internal measurement channel; The process of controlling the target detection chip to output a test electrical signal to the target calibration channel and sampling the output electrical signal value includes: Different low clamping current values ​​are set for the target detection chip; The target detection chip is controlled to output a corresponding low clamping current signal to the target calibration channel according to the different low clamping current values; Before determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: The actual value of the third current signal output by the target detection chip for different low clamping current values ​​is obtained through the internal measurement channel. The step of determining the correction value of the target detection chip based on the sampled electrical signal value and the corresponding set electrical signal value using a preset calibration algorithm includes: Based on the sixth set electrical signal value of the low clamping current value and the sixth sample value of the third current signal corresponding to the low clamping current value, multiple eighth calibration points are determined in the eighth coordinate system; wherein, the horizontal coordinate of the eighth calibration point is the sixth sample value, and the vertical coordinate of the eighth calibration point is the sixth set electrical signal value; The eighth calibration equation is obtained by fitting the eighth calibration point; wherein the eighth calibration equation is a linear equation in two variables with the sixth sample value as the independent variable and the sixth set electrical signal value as the dependent variable. The correction factor in the eighth calibration equation is determined as the low clamping current correction value for the detection chip.

12. The method as described in claim 6, characterized in that, The external signal channels are multiple; the circuit also includes: a signal controller array and a signal channel controller array; The signal controllers in the signal controller array are respectively connected to the signal input terminals of the main control chip and the corresponding detection chip; the signal channel controllers in the signal channel controller array are respectively connected to the signal output terminal of the corresponding detection chip and the corresponding external signal channel. Before switching the conduction state of the relay array according to the received control signal to establish a target calibration channel between the output of the target detection chip and the corresponding correction ADC in the internal calibration circuit, the method further includes: The target detection chip is determined based on the received control signal, and the target detection chip is controlled by the signal controller; and / or Based on the received control signal, the conduction relationship of the target detection chip corresponding to the external signal channel is controlled.

13. The method as described in claim 6, characterized in that, After determining the correction value of the target detection chip using a preset calibration algorithm based on the sampled electrical signal value and the corresponding set electrical signal value, the method further includes: A verification equation is established based on the correction value, the calibrated object is verified, and the percentage of error corresponding to the correction value is determined based on the verification result. The error percentage is compared with a first threshold. If the error percentage is less than the first threshold, the calibration object is determined to have passed calibration.

14. A testing device, characterized in that, include: The test circuit as described in any one of claims 1-5, and / or the calibration method for the detection chip as described in any one of claims 6-13.

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