Nitride semiconductor equipment

Abstract

The present invention provides a nitride semiconductor device that can introduce Mg at a high concentration while keeping the threshold low. [Solution] The normally-off transistor of the nitride semiconductor device comprises a gate insulating film provided on the first surface side of the nitride semiconductor substrate, a gate electrode provided on the gate insulating film, a p-type layer facing the gate electrode with the gate insulating film in between, and a polarization-doped layer facing the gate electrode with the p-type layer in between and in contact with the p-type layer. The Mg concentration of the p-type layer is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following applies: The effective acceptor concentration in the p-type layer is Np(cm -3 Let the thickness of the p-type layer be dp (nm) and the polarization density of the polarization-doped layer be Npol (cm -3 If we let ) be the thickness of the polarization-doped layer be dpol (nm) and the aluminum (Al) concentration on the surface of the polarization-doped layer be Nal, then equations (1) and (2) hold true, respectively.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a field-effect transistor formed on a SiC substrate. The channel region of this field-effect transistor consists of a p-type gate semiconductor region, an n-type embedded channel region, and a p-type body semiconductor region. Non-Patent Document 1 discloses a DioMOS provided on a SiC substrate. In this DioMOS, the channel region on the surface is formed with N-type delta doping. Furthermore, Non-Patent Document 2 discloses polarization doping of AlGaN. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2003-31802 [Non-patent literature]

[0004] [Non-Patent Document 1] MRS BULLETIN·VOLUME40·MAY 2015·www.mrs.org / bulletin ■425-430 [Non-Patent Document 2] APPLIED PHYSICS LETTERS VOLUME 84, NUMBER 9 1 MARCH 2004 “AlGaN / GaN polarization-doped field-effect transistor for microwavepower applications” pp.1591-1593 [Overview of the project] [Problems that the invention aims to solve]

[0005] In MOSFETs formed on a GaN substrate, a large number of hole traps exist at the interface between the GaN substrate and the gate insulating film. These hole traps can be deactivated by introducing a high concentration of Mg at the interface. However, introducing a high concentration of Mg, which acts as an acceptor, raises the threshold voltage of the MOSFET too high, making it impractical. This disclosure aims to provide a nitride semiconductor device that can introduce a high concentration of Mg while keeping the threshold voltage low. [Means for solving the problem]

[0006] To solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure comprises a nitride semiconductor substrate and a normally-off transistor provided on the nitride semiconductor substrate. The transistor has a gate insulating film provided on the first surface side of the nitride semiconductor substrate, a gate electrode provided on the gate insulating film, a p-type layer facing the gate electrode with the gate insulating film in between, and a polarization-doped layer facing the gate electrode with the p-type layer in between and in contact with the p-type layer. The Mg concentration of the p-type layer is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following applies: In the p-type layer, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). -3 Let the thickness of the p-type layer be dp (nm) and the polarization density of the polarization-doped layer be Npol (cm -3 If we assume that the thickness of the polarization-doped layer is dpol (nm) and the aluminum (Al) concentration on the surface of the polarization-doped layer is Nal, then the following equations (1) and (2) hold true, respectively.

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[0007] According to one aspect of this disclosure, it is possible to provide a nitride semiconductor device that can introduce Mg at a high concentration while keeping the threshold low. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing an example of the configuration of a normally-off lateral MOSFET according to Embodiment 1 of this disclosure. [Figure 2] Figure 2 is a magnified cross-sectional view showing the p+-type well region, the polarization-doped layer, and the p+-type layer. [Figure 3] Figure 3 is a schematic graph showing Example 1 of the impurity distribution and charge distribution in the polarization-doped layer and p+-type layer according to this embodiment. [Figure 4] Figure 4 is a schematic graph showing Example 2 of the impurity distribution and charge distribution in the polarization-doped layer and p+-type layer according to this embodiment. [Figure 5] Figure 5 shows the results of a simulation performed by the Discloser, and is a graph showing the relationship between the effective acceptor concentration of the p+-type layer and the thickness of the polarization-doped layer. [Figure 6] Figure 6 shows the results of a simulation performed by the Discloser, and is a graph showing the relationship between the effective acceptor concentration of the p+-type layer and the thickness of the p+-type layer. [Figure 7] Figure 7 is a cross-sectional view showing a modified example of a horizontal MOSFET according to Embodiment 1 of this disclosure. [Figure 8] Figure 8 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET according to Embodiment 2 of this disclosure. [Figure 9] Figure 9 is a cross-sectional view showing a modified example of a vertical MOSFET according to Embodiment 2 of this disclosure. [Figure 10A] Figure 10A is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 10B] Figure 10B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 10C] Figure 10C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure in order of steps. [Figure 10D]Figure 10D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 10E] Figure 10E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 10F] Figure 10F is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 11] Figure 11 is a cross-sectional view showing an example of the configuration of a normally-off IGBT1B according to Embodiment 4 of this disclosure. [Figure 12] Figure 12 is a cross-sectional view showing a modified example of an IGBT according to Embodiment 4 of this disclosure. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure are described below. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each device and component, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0010] Furthermore, in the following explanation, the terms X-axis, Y-axis, and Z-axis may be used to describe directions. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10, which will be described later. The Z-axis direction is perpendicular to the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0011] Furthermore, in the following explanation, the direction of the Z-axis arrow may be referred to as "up," and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of this disclosure. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0012] Furthermore, in the following explanation, the + and - attached to p and n indicating conductivity types mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - attached. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of each semiconductor region are exactly the same.

[0013] <Embodiment 1> Figure 1 is a cross-sectional view showing an example configuration of a normally-off lateral MOSFET 1 (an example of a "transistor" in this disclosure) according to Embodiment 1 of this disclosure. Normally-off characteristics mean that when no voltage is applied to the gate electrode, there is no channel and no drain current flows. As shown in Figure 1, the lateral MOSFET 1 is provided on a gallium nitride substrate (an example of a "nitride semiconductor substrate" in this disclosure; hereinafter referred to as a GaN substrate) 10. The lateral MOSFET 1 includes a gate insulating film 42 provided on the surface 10a (an example of the "first surface" in this disclosure) side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+ type well region 23 provided on the GaN substrate 10, an n+ type source region 26 and drain region 27 provided on the surface of the well region 23 and in its vicinity, below both sides of the gate electrode 44, a p+ type contact region 25 provided on the surface 10a of the GaN substrate 10 and in contact with the well region 23, a source electrode 54 provided on the surface 10a side of the GaN substrate 10 and in contact with the source region 26 and the contact region 25, and a drain electrode 56 provided on the surface 10a side of the GaN substrate 10 and in contact with the drain region 27. The surfaces of the well region 23, the contact region 25, the source region 26, and the drain region 27 are also the surface 10a of the GaN substrate 10.

[0014] The GaN substrate 10 is, for example, a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a surface 10a and a back surface located on the opposite side of surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1 × 10⁻⁶ 7 cm -2 This is a low-dislocation self-supporting GaN substrate with a dislocation count of less than [value missing].

[0015] The donor (N-type impurity) contained in the GaN substrate 10 may be one or more elements such as Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more elements such as Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

[0016] Because the GaN substrate 10 is a low-dislocation self-supporting GaN substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. In addition, during the heat treatment included in the manufacturing process of the lateral MOSFET 1, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0017] The GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N type, and the GaN layer may be N type or N- type. The surface 10a of the GaN substrate 10 is, for example, a polar surface, which is the C-plane (Ga-plane).

[0018] In the lateral MOSFET 1, the semiconductor material is GaN, but the semiconductor material may also contain one or more elements such as aluminum (Al) and indium (In). The semiconductor material may also be a mixed crystal semiconductor containing trace amounts of Al and In, i.e., AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

[0019] The P+ type well region 23 is provided in the depth direction (for example, in the opposite direction to the Z-axis arrow) from the surface 10a of the GaN substrate 10. For example, the well region 23 is formed by ion implantation of acceptor elements (P-type impurities) to a predetermined depth from the surface 10a of the GaN substrate 10, and activation of the acceptor elements by heat treatment. Alternatively, the P+ type well region 23 may be formed by epitaxial growth on the N-type GaN single crystal substrate or N-type GaN layer of the GaN substrate 10.

[0020] The contact region 25 is a region where acceptor elements are ion-implanted to a predetermined depth from the surface of the well region 23 and the acceptor elements are activated by heat treatment. The contact region 25 is a P+ type region. The contact region 25 has a higher concentration of acceptor elements than the well region 23. Alternatively, the contact region 25 and the well region 23 may have the same concentration of acceptor elements. In that case, the contact region 25 is a part of the well region 23 and may be formed simultaneously with the well region 23 in the same process. The well region 23 and the contact region 25 contain at least one of Mg and Be as acceptor elements.

[0021] For example, the well region 23 and the contact region 25 contain Mg as an acceptor element. The Mg concentration in the well region 23 is 1×10 17 cm -3 or more and 1×10 20 cm -3 or less, and preferably 1×10 19 cm -3 or more and 1×10 20 cm -3 or less. Taking one example, it is 1×10 19 cm -3 . Also, the Mg concentration in the contact region 25 is 1×10 18 cm -3 or more and 2×10 20 cm -3 or less.

[0022] The source region 26 and the drain region 27 are regions where donor elements (N-type impurities) are ion-implanted to a predetermined depth from the surface 10a of the well region 23 and the donor elements are activated by heat treatment. The source region 26 and the drain region 27 are N+ type regions. The source region 26 and the drain region 27 have the same concentration of donor elements. The source region 26 and the drain region 27 are formed simultaneously in the same process. The source region 26 and the drain region 27 contain at least one of Si, Ge, and O as donor elements. For example, the source region 26 and the drain region 27 contain Si as the donor element. The Si concentrations in the source region 26 and the drain region 27 are 1 × 10⁻⁶ each. 19 cm -3 The above 5 x 10 20 cm -3 The following applies:

[0023] The gate insulating film 42 is, for example, a silicon oxide film (SiO2 film). The thickness of the gate insulating film 42 is, for example, 50 nm to 100 nm. The gate insulating film 42 is provided, for example, on a flat surface 10a. The gate electrode 44 is provided on the gate insulating film 42. For example, the gate electrode 44 is a planar type provided on a flat gate insulating film 42. The gate electrode 44 is made of, for example, polysilicon doped with impurities.

[0024] The source electrode 54 and the drain electrode 56 are provided on the surface 10a of the GaN substrate 10, respectively. The source electrode 54 is in contact with the source region 26 and the contact region 25. The drain electrode 56 is in contact with the drain region 27. The source electrode 54 and the drain electrode 56 are made of, for example, an Al or Al-Si alloy. The source electrode 54 and the drain electrode 56 may have a barrier metal layer between the surface 10a of the GaN substrate 10 and the Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer.

[0025] Figure 2 is an enlarged cross-sectional view showing a p+-type well region 23, a polarization-doped layer 61, and a p+-type layer 62 (an example of the "p-type layer" in this disclosure). As shown in Figures 1 and 2, the lateral MOSFET 1 further includes a polarization-doped layer 61 and a p+-type layer 62. The p+-type layer 62 is positioned opposite the gate electrode 44 with the gate insulating film 42 in between, and the polarization-doped layer 61 is positioned opposite the gate electrode 44 with the p+-type layer 62 in between. For example, the polarization-doped layer 61 and the p+-type layer 62 are arranged in this order from the well region 23 toward the gate electrode 44.

[0026] The polarization-doped layer 61 is sandwiched between a p+-type well region 23 and a p+-type layer 62. The polarization-doped layer 61 is in contact with the well region 23 and the p+-type layer 62 in its thickness direction (e.g., the Z-axis direction). The polarization-doped layer 61 is also in contact with the source region 26 and the drain region 27 in its thickness direction (e.g., the Z-axis direction) or in a direction intersecting that thickness direction (e.g., the X-axis direction). Figure 1 illustrates the case where the polarization-doped layer 61 is in contact with the source region 26 and the drain region 27 in the X-axis direction (i.e., in contact with the side surface of the source region 26 and the side surface of the drain region 27).

[0027] The polarization-doped layer 61 is a layer in which aluminum (Al) is doped into GaN (i.e., an AlGaN layer). The polarization-doped layer 61 has a distribution in which the Al concentration decreases linearly from the surface of the polarization-doped layer 61 in the depth direction (for example, in the opposite direction of the Z-axis arrow) (i.e., an Al gradient distribution). The polarization-doped layer 61 is an electron-conducting layer that is polarization-doped due to this Al gradient distribution.

[0028] The polarization-doped layer 61 is formed, for example, by epitaxial growth of a GaN layer containing Al. For example, the ratio of Al in the source gas is gradually increased over time from the start of GaN epitaxial growth. This makes it possible to form a polarization-doped layer 61 having an Al gradient distribution in which the Al concentration gradually increases from the lower layer to the upper layer. The Al gradient distribution will be further explained with reference to Figures 3 and 4 below.

[0029] The p+-type layer 62 is a high-mg concentration layer containing a high concentration of Mg as an acceptor element. The Mg concentration of the p+-type layer 62 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following is true: 1 × 10 19 cm -3 The above 1 x 10 20 cm -3The following is preferable: The p+-type layer 62 may be formed by ion implanting Mg into the surface 10a side of the GaN substrate 10 and activating the Mg by heat treatment. Alternatively, the p+-type layer 62 may be formed by epitaxial growth of a p-type GaN layer containing Mg.

[0030] In the p+ layer 62, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). -3 Let the thickness of the p-type layer be dp (nm). Also, let the polarization density of the polarization-doped layer 61 be Npol (cm -3 Assuming that the thickness of the polarization-doped layer 61 is dpol (nm) and the aluminum (Al) concentration on the surface of the polarization-doped layer 61 is Nal, then the following equations (1) and (2) hold true, respectively. Note that Nal is in atomic percent.

[0031]

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[0032] When equation (2) holds, the p+-type layer 62 is completely depleted when the bias to the gate electrode 44 (gate bias) is 0V. This makes it easy to change the potential of the polarization-doped layer 61 when the gate bias is greater than 0V. To explain in more detail, the potential of the polarization-doped layer 61 cannot be changed unless the p+-type layer 62 is depleted. In order to change the potential of the polarization-doped layer 61, it is necessary to deplete the p+-type layer 62 with the gate bias, which leads to an increase in the threshold voltage (Vth) of the MOSFET. However, when equation (2) holds, the p+-type layer 62 is completely depleted with a gate bias of 0V, so it is not necessary to allocate the gate bias to completely deplete the p+-type layer 62. This makes it possible to change the potential of the polarization-doped layer 61 with a low gate bias, and thus keep the threshold voltage of the MOSFET low.

[0033] Furthermore, when equation (2) and equation (1) hold, the polarization-doped layer 61 is completely depleted when the gate bias is 0V. When the gate bias is 0V, the polarization-doped layer 61 is completely depleted and no drain current flows, so the MOSFET exhibits normally-off characteristics.

[0034] In equation (1), the thickness dpol of the polarization-doped layer 61 is set to be thicker than 3 nm. Similarly, in equation (2), the thickness dp of the p+-type layer 62 is set to be thicker than 3 nm. This is for manufacturing reasons. With current manufacturing technology, there are limitations to thinning (reducing the thickness of the layer), and it is considered necessary to have a thickness of 3 nm or more for the polarization-doped layer 61 and the p+-type layer 62 to be manufactured stably. If future advancements in manufacturing technology make it possible to stably thin (reduc the thickness of the layer) to 3 nm or less, the left-hand terms in equations (1) and (2) may be 2 nm, for example, instead of 3 nm.

[0035] Figure 3 is a schematic graph showing Example 1 of the impurity distribution and charge distribution in the polarization-doped layer 61 and p+-type layer 62 according to this embodiment (Embodiment 1 and Embodiments 2 to 4 described later). The upper graph in Figure 3 shows the impurity distribution, and the lower graph shows the charge distribution. In the upper graph, the vertical axis shows the impurity concentration, and the horizontal axis shows the depth from the surface. In the lower graph, the vertical axis shows the charge density, and the horizontal axis shows the depth from the surface. In the upper and lower graphs of Figure 3, the vertical and horizontal axes are linear scales.

[0036] As shown in the upper graph of Figure 3, the p+-type layer 62 with thickness dp has an Al gradient distribution in which the Al concentration decreases linearly from the surface to the depth. Similarly, the polarization-doped layer 61 with thickness dpol also has an Al gradient distribution in which the Al concentration decreases linearly from the surface to the depth. For example, the gradient t of Al concentration in the depth direction is the same or nearly the same for the p+-type layer 62 and the polarization-doped layer 61. The Al concentration at the interface between the polarization-doped layer 62 and the polarization-doped layer 61 is the same or nearly the same as the Al concentration at the interface between the polarization-doped layer 61 and the p+-type layer 62. The Al concentration at the interface between the polarization-doped layer 61 and the p+-type well region 23 is zero (0) or nearly zero. From the top surface of the p+-type layer 62 (i.e., the interface in contact with the gate insulating film 42) to the bottom surface of the polarization-doped layer 61 (i.e., the interface in contact with the p+-type well region 23 in the polarization-doped layer 61), the Al concentration decreases linearly and continuously.

[0037] As shown in the lower graph of Figure 3, the polarization-doped layer 61 has the Al concentration distribution sloped in the depth direction as described above, resulting in the generation of a negative (-) polarization charge at a constant concentration in the depth direction. Similarly, the p+-type layer 62 also has the Al concentration distribution sloped in the depth direction as described above, resulting in the generation of a negative polarization charge at a constant concentration in the depth direction. In Example 1 shown in Figure 3, the slope t of the Al concentration in the depth direction is the same in the polarization-doped layer 61 and the p+-type layer 62, and the polarization density Npol (cm -3 ) is the same. In the example shown in Figure 3, Np-Npol (i.e., the value obtained by offsetting the donor concentrations of Si, O, etc. from the Mg concentration, and further offsetting the polarization density Npol) becomes the effective acceptor concentration of the p+ type layer 62.

[0038] Figure 4 is a schematic graph showing Example 2 of the impurity distribution and charge distribution in the polarization-doped layer 61 and p+-type layer 62 according to this embodiment. The upper graph in Figure 4 shows the impurity distribution, and the lower graph shows the charge distribution. The vertical and horizontal axes of the upper and lower graphs are the same as in Figure 3. As shown in the upper graph of Figure 4, the polarization-doped layer 61 with thickness dpol has an Al gradient distribution, and the p+-type layer 62 with thickness dp does not necessarily have an Al gradient distribution. That is, the Al concentration in the p+-type layer 62 may be constant in the depth direction. In Example 2 shown in Figure 4, in the polarization-doped layer 61, a negative (-) polarization charge is generated at a constant concentration in the depth direction due to the Al gradient distribution. On the other hand, in the p+-type layer 62, no polarization charge is generated due to the Al gradient distribution, so Np (i.e., the value obtained by offsetting the donor concentrations of Si, O, etc. from the Mg concentration) becomes the effective acceptor concentration of the p+-type layer 62. In the figure, the acceptor concentration is shown as constant in the depth direction. During epitaxial growth, it is desirable for the acceptor concentration to be as steep as possible, but a concentration gradient of a few nanometers until the concentration becomes constant is also acceptable. In particular, a high Mg concentration at the outermost surface is desirable, so it is good to have a high concentration on the surface and a decreasing concentration towards the interior of the substrate.

[0039] Figure 5 is a graph showing the relationship between the effective acceptor concentration Np of the p+-type layer 62 and the thickness dpol of the polarization-doped layer 61, based on the results of a simulation performed by the Discloser. Figure 6 is a graph showing the relationship between the effective acceptor concentration Np of the p+-type layer 62 and the thickness dp of the p+-type layer 62, based on the results of a simulation performed by the Discloser. As shown in Figures 5 and 6, in this simulation, the effective acceptor concentration Np of the p+-type layer 62 was set to 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 20 cm -3 The following settings were used. Additionally, the Al concentration (Nal) on the surface of the polarization-doped layer 61 was set to five different values: 5%, 10%, 15%, 20%, and 30%. These settings were applied to equations (1) and (2) to obtain Figures 5 and 6.

[0040] In Figure 5, under the condition Nal=5%, Np is 1.0 × 10⁻⁶. 18 cm-3 Above 1.0×10 20 cm -3 In the entire range below, since dpol becomes a value greater than 140 nm, its illustration is omitted. Also, "E+" described in FIGS. 5 and 6 indicates the power of 10.

[0041] In this embodiment, the effective acceptor concentration Np of the p+ type layer 62 (for example, the effective Mg concentration obtained by canceling out donor elements from the Mg concentration) is 1.0×10 18 cm -3 Above 1.0×10 20 cm -3 In the case below, as shown in FIG. 5, the thickness dpol of the polarization doping layer 61 is thicker than 3 nm and falls within a range of values smaller than each curve for each Nn. Similarly, the thickness dp of the p+ type layer 62 is thicker than 3 nm and falls within a range of values smaller than each curve for each Nn.

[0042] From the simulation results of FIGS. 5 and 6, the range of Nal in this embodiment is preferably 5% or more and 30% or less, and more preferably 15% or more and 25% or less.

[0043] As an example of this embodiment, assume the case where Np = 1.0×10 19 cm -3 and Nal = 20%. In this assumption, as shown by the arrow in FIG. 5, when the thickness dpol of the polarization doping layer 61 is thicker than 3 nm and thinner than 47 nm, equations (1) and (2) hold. Also, assume Np = 1.0×10 19 cm -3 and Nal = 20%, and further assume dpol = 10 nm. In this assumption, as shown by the arrow in FIG. 6, when the thickness dp of the p+ type layer 62 is thicker than 3 nm and thinner than 15 nm, equations (1) and (2) hold. That is, in the case of Np = 1.0×10 19 cm -3 and Nal = 20%, 3 nm < dpol < 47 nm and 3 nm < dp < 15 nm are the ranges of this embodiment.

[0044] As another example, Np = 2.0×10 19 cm -3When Nal = 20%, equations (1) and (2) hold when dpol is thicker than 3 nm and thinner than 82 nm. In this case, if dpol = 10 nm, then dp < 8 nm is within the range of this embodiment. Similarly, if dpol = 80 nm, then dp < 4 nm is within the range of this embodiment.

[0045] In this embodiment, it is preferable that, in addition to the above equations (1) and (2), the following equation (3) also holds true. dp × Np (cm -2 )-Nal(%)×1×10 12 < (dp+dpol)×1×1e 18 (cm -2 )...(3)

[0046] This keeps the effective surface concentration of the polarization-doped layer 61 and the p+-type layer 62 below a certain level (average acceptor concentration is 1 × 10⁻⁶). 18 cm -3 The following can be achieved, and the threshold voltage of the MOSFET formed on the GaN substrate can be kept within a certain voltage range.

[0047] The left-hand side of equation (3) is the total acceptor concentration of the p+-type layer 62 and the polarization-doped layer 61. The total donor concentration of the polarization-doped layer 61 is shown, for example, by equation (4). Total donor concentration = Npol × dpol = Nal(%) × 1 × 10 12 (cm -2 )...(4)

[0048] (Effects of Embodiment 1) As described above, the nitride semiconductor device according to Embodiment 1 of the present disclosure comprises a GaN substrate 10 and a normally-off lateral MOSFET 1 provided on the GaN substrate 10. The lateral MOSFET 1 has a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+ type layer 62 facing the gate electrode 44 across the gate insulating film 42, and a polarization doped layer 61 facing the gate electrode 44 across the p+ type layer 62 and in contact with the p+ type layer 62. The Mg concentration of the p+ type layer 62 is 1 × 10⁻¹⁶ 18 cm-3 The above 1 x 10 20 cm -3 The following is the effective acceptor concentration of the p+ type layer 62, Np(cm²). -3 Let the thickness of the p+-type layer 62 be dp (nm), and the polarization density of the polarization-doped layer 61 be Npol (cm³). -3 If we assume that the thickness of the polarization-doped layer 61 is dpol (nm) and the Al concentration on the surface of the polarization-doped layer 61 is Nal, then equations (1) and (2) above hold true, respectively.

[0049] According to this, the polarization-doped layer 61 becomes the channel of the lateral MOSFET 1. The polarization-doped layer 61 is completely depleted when the bias to the gate electrode 44 (i.e., the gate bias) is 0V, achieving normally-off operation. This allows for a low threshold voltage for the lateral MOSFET 1 while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0050] (modified version) Figure 7 is a cross-sectional view showing a modified example of the lateral MOSFET 1 according to Embodiment 1 of the present disclosure. As shown in Figure 7, the lateral MOSFET 1 may have multiple polarization-doped layers 61 and multiple p+-type layers 62. For example, if the polarization-doped layer 61 and the p+-type layer 62 are considered as one pair 60, then n (n is an integer of 2 or more) of these pairs 60 may be stacked and arranged opposite the gate electrode 44 with the gate insulating film 42 in between. That is, the polarization-doped layer 61 and the p+-type layer 62 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 7 illustrates the case where there are two pairs 60 of polarization-doped layers 61 and p+-type layers 62 (n=2).

[0051] In the modified example shown in Figure 7, equations (1) and (2) above also hold true. That is, in each of the multiple pairs 60 (hereinafter, each pair 60), the Mg concentration of the p+ type layer 62 is 1 × 10⁻¹⁰ 18 cm -3 The above 1 x 10 20 cm -3The following applies: In each pair 60, the effective acceptor concentration of the p+ type layer 62 is set to Np(cm²). -3 Let the thickness of the p+-type layer 62 be dp (nm), and the polarization density of the polarization-doped layer 61 be Npol (cm³). -3 Let the polarization-doped layer 61 be dpol (nm) and the Al concentration on the surface of the polarization-doped layer 61 be Nal. In this case, in each pair 60, the thickness dpol of the polarization-doped layer 61 and the thickness dp of the p+-type layer 62 satisfy equations (1) and (2) above, respectively. Thus, the modified example shown in Figure 7 also produces the same effects as the embodiment 1 described above.

[0052] <Embodiment 2> In Embodiment 1 described above, a horizontal MOSFET was shown as an example of the "transistor" of this disclosure. However, the "transistor" of this disclosure is not limited to a horizontal type, and may be vertical. Figure 8 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET 1A according to Embodiment 2 of this disclosure. As shown in Figure 8, the vertical MOSFET 1A is provided on a GaN substrate 10.

[0053] The GaN substrate 10 includes, for example, an n+-type GaN single crystal substrate 11 and an n-type GaN layer 22 provided on the GaN single crystal substrate 11. As shown in Figure 8, the GaN substrate 10 has a back surface 10b opposite to the front surface 10a. This back surface 10b is also the back surface of the GaN single crystal substrate 11. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements from Si (silicon), O (oxygen), and Ge (germanium), one example being O. The impurity concentration of O in the GaN single crystal substrate 11 is 2 × 10⁻⁶. 18 / cm 3 That's all.

[0054] The GaN single crystal substrate 11 has, for example, a threading dislocation density of 1 × 10⁻⁶ 7 cm -2The GaN single crystal substrate may be a low-dislocation self-supporting GaN substrate. Because the GaN single crystal substrate 11 is a low-dislocation self-supporting substrate, the dislocation density of the GaN layer 22 formed on the GaN single crystal substrate 11 is also reduced. Furthermore, by using a low-dislocation self-supporting substrate for the GaN single crystal substrate 11, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN single crystal substrate 11. This allows the manufacturing equipment to produce power devices with a high yield rate. Additionally, during heat treatment, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0055] The GaN layer 22 is provided on the GaN single crystal substrate 11. The GaN layer 22 is an n-type GaN single crystal layer, formed on the GaN single crystal substrate 11 by epitaxial growth. The n-type dopant (n-type impurity) contained in the GaN layer 22 is one or more elements from Si (silicon), O (oxygen), and Ge (germanium), for example, O. Furthermore, the surface 10a of the GaN substrate 10 (i.e., the surface of the GaN layer 22) is a polar surface, the C-plane (Ga-plane).

[0056] As shown in Figure 8, the vertical MOSFET 1A includes a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+ type well region 23 provided in the GaN layer 22, an n+ type source region 26 provided on the surface of the well region 23 and in its vicinity, below both sides of the gate electrode 44, a p+ type contact region 25 provided on the surface 10a side of the GaN substrate 10 and in contact with the well region 23, a source electrode 54 provided on the surface 10a side of the GaN substrate 10 and in contact with the source region 26 and the contact region 25, an interlayer insulating film 48 that insulates the space between the source electrode 54 and the gate electrode, and a drain electrode 56 provided on the back surface 10b side of the GaN substrate 10.

[0057] Furthermore, the vertical MOSFET 1A has an n-type JFET region 24 provided in the GaN layer 22. The JFET region 24 is provided in a position facing the gate electrode 44, for example, via a gate insulating film 42. The JFET region 24 faces the surface 10a of the GaN substrate 10 and is in contact with the polarization-doped layer 61 in the thickness direction of the vertical MOSFET 1A (for example, in the Z-axis direction). The JFET region 24 is also in contact with the well region 23 in a direction intersecting the thickness direction of the vertical MOSFET 1A (for example, in the X-axis direction). Figure 8 illustrates the case where the depth of the JFET region 24 from the surface 10a and the depth of the well region 23 from the surface 10a are the same, but the depth of the JFET region 24 from the surface 10a may be greater than the depth of the well region 23 from the surface 10a.

[0058] In the GaN layer 22, the region where the well region 23, source region 26, and contact region 25 are not provided may be called the drift region. The JFET region 24 is also part of the drift region. The drift region functions as a current path between the GaN single crystal substrate 11 and the well region 23.

[0059] As shown in Figure 8, the vertical MOSFET 1A has a polarization-doped layer 61 and a p+-type layer 62 between the surface 10a of the GaN substrate 10 and the gate insulating film 42. Similar to the horizontal MOSFET 1 shown in Figure 1, in the vertical MOSFET 1A shown in Figure 8, the p+-type layer 62 is positioned opposite the gate electrode 44 with the gate insulating film 42 in between. The polarization-doped layer 61 is positioned opposite the gate electrode 44 with the p+-type layer 62 in between. For example, the polarization-doped layer 61 and the p+-type layer 62 are arranged in this order from the well region 23 toward the gate electrode 44.

[0060] The polarization doping layer 61 is sandwiched between the p+-type well region 23 and the p+-type layer 62. The polarization doping layer 61 is in contact with the well region 23 and the p+-type layer 62 respectively in its thickness direction (for example, the Z-axis direction). Also, the polarization doping layer 61 is in contact with the source region 26 in its thickness direction (for example, the Z-axis direction) or in a direction intersecting with its thickness direction (for example, the X-axis direction). In FIG. 8, the case where the polarization doping layer 61 is in contact with the source region 26 in the Z-axis direction (that is, in contact with the upper surface of the source region 26) is illustrated.

[0061] Similar to the lateral MOSFET 1 shown in FIG. 1, in the vertical MOSFET 1A shown in FIG. 8, the polarization doping layer 61 is an AlGaN layer in which GaN is doped with Al. As described with reference to FIGS. 3 and 4, the polarization doping layer 61 has a distribution in which the Al concentration linearly decreases in the depth direction (for example, the opposite direction of the arrow of the Z-axis) from the surface of the polarization doping layer 61 (that is, an Al gradient distribution). The polarization doping layer 61 is an electron conduction layer polarized by this Al gradient distribution. The polarization doping layer 61 is formed, for example, by epitaxially growing a GaN layer containing Al.

[0062] Also, in the vertical MOSFET 1A shown in FIG. 8, the p+-type layer 62 is a Mg high-concentration layer containing Mg at a high concentration as an acceptor element. The Mg concentration of the p+-type layer 62 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less, and it is preferably 1×10 19 cm -3 or more and 1×10 20 cm -3 or less. The p+-type layer 62 may be formed by ion-implanting Mg on the surface 10a side of the GaN substrate 10 and activating Mg by heat treatment. Alternatively, the p+-type layer 62 may be formed by epitaxially growing a p-type GaN layer containing Mg.

[0063] In the vertical MOSFET 1A shown in FIG. 8, the effective acceptor concentration of the p+-type layer 62 is Np (cm -3) and let the polarization density of the polarization doping layer 61 be Npol (cm -3 ) and let the Al concentration on the surface of the polarization doping layer 61 be Nal. Then, the thickness dpol (nm) of the polarization doping layer 61 and the thickness dp (nm) of the p+-type layer 62 satisfy the above equations (1) and (2), respectively. Thus, the examples of the values of Np, dp, Npol, dpol, and Nal in the lateral MOSFET 1 described while referring to FIGS. 5 and 6 are the same in the vertical MOSFET 1A shown in FIG. 8. For example, when Np = 1.0×10 19 cm -3 , and Nal = 20%, 3 nm < dpol < 47 nm and 3 nm < dp < 15 nm are within the scope of this embodiment. The same also applies to the numerical ranges given as "other examples" for Np, dp, Npol, dpol, and Nal.

[0064] Note that the nitride semiconductor device of the present disclosure may have a structure in which, for example, the vertical MOSFET 1A shown in FIG. 8 is used as one unit structure, and this unit structure is repeatedly provided in one direction (for example, the X-axis direction). The same also applies to Embodiments 3 and 4 described later. It may be a structure in which a vertical MOSFET is used as one unit structure and this unit structure is repeatedly provided in one direction.

[0065] (Effect of Embodiment 2) As described above, the nitride semiconductor device according to Embodiment 2 of the present disclosure includes the GaN substrate 10 and the normally-off vertical MOSFET 1A provided on the GaN substrate 10. The vertical MOSFET 1A includes a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+-type layer 62 facing the gate electrode 44 with the gate insulating film 42 interposed therebetween, and a polarization doping layer 61 facing the gate electrode 44 with the p+-type layer 62 interposed therebetween and contacting the p+-type layer 62. The Mg concentration of the p+-type layer 62 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. The effective acceptor concentration of the p+-type layer 62 is Np (cm -3Let the thickness of the p+-type layer 62 be dp (nm), and the polarization density of the polarization-doped layer 61 be Npol (cm³). -3 If we assume that the thickness of the polarization-doped layer 61 is dpol (nm) and the Al concentration on the surface of the polarization-doped layer 61 is Nal, then equations (1) and (2) above hold true, respectively.

[0066] According to this, the polarization-doped layer 61 becomes the channel of the vertical MOSFET 1A. The polarization-doped layer 61 is completely depleted when the gate bias is 0V, achieving normally-off operation. This allows for a low threshold voltage for the vertical MOSFET 1A while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0067] (modified version) (1) Figure 9 is a cross-sectional view showing a modified example of a vertical MOSFET 1A according to Embodiment 2 of the present disclosure. As shown in Figure 9, the vertical MOSFET 1A may have multiple polarization-doped layers 61 and multiple p+-type layers 62. For example, if the polarization-doped layer 61 and the p+-type layer 62 are considered as one pair 60, then n (n is an integer of 2 or more) of these pairs 60 may be stacked and arranged in a manner opposite the gate electrode 44 with the gate insulating film 42 in between. That is, the polarization-doped layer 61 and the p+-type layer 62 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 9 illustrates the case where there are two pairs 60 of polarization-doped layers 61 and p+-type layers 62 (n=2).

[0068] In the modified example shown in Figure 9, equations (1) and (2) above also hold true. That is, in each pair 60, the Mg concentration of the p+ type layer 62 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies: In each pair 60, the effective acceptor concentration of the p+ type layer 62 is set to Np(cm²). -3 Let the thickness of the p+-type layer 62 be dp (nm), and the polarization density of the polarization-doped layer 61 be Npol (cm³). -3Let the polarization-doped layer 61 be dpol (nm) and the Al concentration on the surface of the polarization-doped layer 61 be Nal. In this case, in each pair 60, the thickness dpol of the polarization-doped layer 61 and the thickness dp of the p+-type layer 62 satisfy equations (1) and (2) above, respectively. Thus, the modified example shown in Figure 9 also produces the same effects as the embodiment 2 described above.

[0069] (2) Figures 8 and 9 show an embodiment in which the polarization-doped layer 61 and the p+-type layer 62 are arranged on the JFET region 24. However, the polarization-doped layer 61 and the p+-type layer 62 do not necessarily have to be arranged on the JFET region 24. That is, the polarization-doped layer 61 and the p+-type layer 62 are arranged on the well region 23 and do not have to be arranged on the JFET region 24. Even in this embodiment, the effects of the above embodiment 2 are achieved.

[0070] (3) Figures 8 and 9 show an embodiment in which the vertical MOSFET 1A has a JFET region 24. However, the JFET region 24 is not required. In Figures 8 and 9, an n-type GaN layer 22 may be placed between one well region and the other adjacent well region in the X-axis direction instead of a JFET region. Even in this embodiment, the on-resistance will increase, but the effects of Embodiment 2 described above will be achieved.

[0071] (4) Figures 8 and 9 show an embodiment in which the polarization-doped layer 61 and the p+-type layer 62 are arranged on the surface 10a of the GaN substrate 10. However, the polarization-doped layer 61 and the p+-type layer 62 may be provided inside the GaN substrate 10, as in the lateral MOSFET 1 shown in Figure 1, rather than on the surface 10a of the GaN substrate 10. In this case, the polarization-doped layer 61 may be in contact with the side surface of the source region 26. Even in this embodiment, the effects of the above embodiment 2 can be achieved.

[0072] (5) The p+ type contact region 25 may have the same acceptor concentration (or effective acceptor concentration) as the p+ type well region 23. In this case, the p+ type contact region 25 may be a part of the p+ type well region 23. That is, in Figures 8 and 9, the contact region 25 may be a part of the well region 23, and the source electrode 54 may be in contact with this part. Even in this configuration, the effects of the above embodiment 2 are achieved.

[0073] <Embodiment 3> As Embodiment 3 of this disclosure, a method for manufacturing a planar gate type vertical MOSFET (vertical DMOS) will be described. Figures 10A to 10F are cross-sectional views showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure in order of steps. Vertical MOSFETs are manufactured using various devices such as a film deposition apparatus, an exposure apparatus, an ion implantation apparatus, an etching apparatus, and a heat treatment apparatus. Hereinafter, these devices will be collectively referred to as manufacturing apparatus.

[0074] As shown in Figure 10A, the manufacturing apparatus epitaxially grows an n-type GaN layer 22 on an n+-type GaN single crystal substrate 11. Next, as shown in Figure 10B, the manufacturing apparatus sequentially ion-implants acceptor elements (e.g., Mg) and donor elements (e.g., O, Si) into the GaN layer 22 using photolithography and ion implantation techniques, and then heat-treats the layer to form a p+-type well region 23, an n-type JFET region 24, a p+-type contact region 25, and an n+-type source region 26. In this example, the formation of the p+-type contact region 25 is shown, but the formation of the contact region 25 may be omitted. In this case, the p+-type well region 23 is extended to the position of the contact region 25.

[0075] Next, as shown in Figure 10C, the manufacturing apparatus epitaxially grows a polarization-doped layer 61 and a p+-type layer 62 on the surface 10a of the GaN substrate 10 in this order. Here, the Mg concentration of the p+-type layer 62 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following (preferably 1 × 10)19 cm -3 The above 1 x 10 20 cm -3 The following conditions apply, and the effective acceptor concentration Np(cm) of the p+-type layer 62 is also the same. -3 ) and its thickness dp (nm), polarization density Npol (cm³) of the polarization-doped layer 61 -3 The polarization-doped layer 61 and the p+-type layer 62 are epitaxially grown in succession such that the thickness of the polarization-doped layer 61 is dpol (nm) and the Al concentration Nal on the surface of the polarization-doped layer 61 satisfies the above equations (1) and (2).

[0076] Next, as shown in Figure 10D, the manufacturing apparatus sequentially forms a gate insulating film 42 and a gate electrode 44 on the p+ type layer 62. Then, as shown in Figure 10E, the manufacturing apparatus forms an interlayer insulating film 48 on the surface 10a side of the GaN substrate 10.

[0077] Next, as shown in Figure 10F, the manufacturing apparatus partially removes the interlayer insulating film 48, the gate insulating film 42, the p+ type layer 62, and the polarization doping layer 61 in that order using photolithography and etching techniques to form contact holes H1 on the contact region 25 and the source region 26. Subsequently, the manufacturing apparatus forms a source electrode 54 (see Figure 8) on the surface 10a side of the GaN substrate 10 and brings the source electrode 54 into contact with the n+ type source region 26 and the p+ type well region 23. In addition, a drain electrode 56 (see Figure 8) is formed on the back surface 10b side of the GaN substrate 10 and brings the drain electrode 56 into contact with the n+ type GaN single crystal substrate 11. Through these steps, a planar gate type vertical MOSFET as shown in Figure 8 is completed.

[0078] (modified version) (1) In the process of forming the polarization-doped layer 61 and the p+-type layer 62 shown in Figure 10C, the polarization-doped layer 61 and the p+-type layer 62 may be formed in multiple layers by alternating doping of Al and an acceptor element (e.g., Mg) by epitaxial growth. This makes it possible to manufacture a planar gate type vertical MOSFET in which the polarization-doped layer 61 and the p+-type layer 62 are formed in multiple layers, as shown in Figure 9.

[0079] (2) In the process of forming the polarization-doped layer 61 and the p+-type layer 62 shown in Figure 10C, the polarization-doped layer 61 and the p+-type layer 62 may be formed in multiple layers by combining doping with an acceptor element (e.g., Mg) by epitaxial growth and implantation of Al by ion implantation. Even with this method, a planar gate type vertical MOSFET with multiple layers of polarization-doped layer 61 and p+-type layer 62 as shown in Figure 9 can be manufactured.

[0080] <Embodiment 4> In Embodiment 1 described above, a lateral MOSFET was shown as an example of the "transistor" of the present disclosure. In Embodiment 2 described above, a lateral MOSFET was shown as an example of the "transistor" of the present disclosure. However, the "transistor" of the present disclosure is not limited to a MOSFET, but may also be an IGBT. Figure 11 is a cross-sectional view showing an example configuration of a normally-off IGBT1B according to Embodiment 4 of the present disclosure. As shown in Figure 11, the IGBT1B is provided on a GaN substrate 10.

[0081] In the IGBT1B shown in Figure 11, the differences from the vertical MOSFET1A shown in Figure 8 are that it has an n+ type emitter region 126 instead of a source region 26, an emitter electrode 154 instead of a source electrode 54, a collector electrode 156 instead of a drain electrode 56, and a p+ type collector layer 29 provided on the back side of the n+ type GaN single crystal substrate 11 (i.e., the back side 10b of the GaN substrate 10). The other configurations are the same as the vertical MOSFET1A shown in Figure 8.

[0082] The emitter region 126 has the same configuration as the source region 26, the emitter electrode 154 has the same configuration as the source electrode 54, and the collector electrode 156 has the same configuration as the drain electrode 56.

[0083] The collector layer 29 is a p+ type GaN layer doped with p-type impurities such as Mg. The collector layer 29 is sandwiched between an n+ type GaN single crystal substrate 11 and a collector electrode 156, and is in contact with both the GaN single crystal substrate 11 and the collector electrode 156. The method for manufacturing the collector layer 29 is not particularly limited, but for example, it can be formed by epitaxial growth on the back surface of the GaN single crystal substrate 11.

[0084] Similar to the horizontal MOSFET1 and vertical MOSFET1A described above, the IGBT1B shown in Figure 11 also has a polarization-doped layer 61 and a p+-type layer 62. In the IGBT1B as well, the polarization-doped layer 61 is an AlGaN layer in which Al is doped into GaN. As explained with reference to Figures 3 and 4, the polarization-doped layer 61 has an Al gradient distribution in which the Al concentration decreases linearly from the surface in the depth direction. The polarization-doped layer 61 is an electron conduction layer that is polarization-doped by this Al gradient distribution. The polarization-doped layer 61 is formed, for example, by epitaxial growth of an Al-containing GaN layer.

[0085] (Effects of Embodiment 4) In Embodiment 4 of this disclosure, the Mg concentration of the p+-type layer 62 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following are preferred, preferably 1 × 10 19 cm -3 The above 1 x 10 20 cm -3 The following is the effective acceptor concentration of the p+ type layer 62, Np(cm²). -3 Let the thickness of the p+-type layer 62 be dp (nm), and the polarization density of the polarization-doped layer 61 be Npol (cm³). -3 If we assume that the thickness of the polarization-doped layer 61 is dpol (nm) and the Al concentration on the surface of the polarization-doped layer 61 is Nal, then equations (1) and (2) above hold true, respectively.

[0086] According to this, the polarization-doped layer 61 becomes the channel of the IGBT1B. The polarization-doped layer 61 is completely depleted when the gate bias is 0V, achieving normally-off operation. This allows for a low threshold voltage for the IGBT1B while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0087] (modified version) Figure 12 is a cross-sectional view showing a modified example of the IGBT 1B according to Embodiment 4 of the present disclosure. As shown in Figure 12, the IGBT 1B may have multiple polarization-doped layers 61 and multiple p+-type layers 62. For example, if the polarization-doped layer 61 and the p+-type layer 62 are considered as one pair 60, then n (n is an integer of 2 or more) of these pairs 60 may be stacked and arranged opposite the gate electrode 44 with the gate insulating film 42 in between. That is, the polarization-doped layer 61 and the p+-type layer 62 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 12 illustrates the case where there are two pairs 60 of polarization-doped layer 61 and p+-type layer 62 (n=2). In the modified example shown in Figure 12, equations (1) and (2) above also hold true for each pair 60. Thus, the modified example shown in Figure 12 also produces the same effects as Embodiment 2 described above.

[0088] Furthermore, modifications (2) to (4) of the vertical MOSFET 1A according to Embodiment 2 are also applicable to the IGBT 1B according to Embodiment 4.

[0089] <Other Embodiments> As described above, this disclosure is described by embodiments and modifications thereof, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, the gate insulating film 42 is not limited to an SiO2 film, but may be other insulating films. Silicon oxynitride (SiON) films, strontium oxide (SrO) films, silicon nitride (Si3N4) films, and aluminum oxide (Al2O3) films can also be used for the gate insulating film 42. Furthermore, composite films, such as those made by stacking several single-layer insulating films, can also be used for the gate insulating film 42.

[0090] Thus, this technology naturally includes various embodiments and modifications not described herein. Within the scope of the embodiments and modifications described above, at least one of various omissions, substitutions, and modifications of the components can be made. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0091] Furthermore, this disclosure may also adopt the following structure. (1) Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, It has a polarization-doped layer that faces the gate electrode with the p-type layer in between and is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following: In the aforementioned p-type layer, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). -3) and the thickness of the p-type layer is dp (nm), The polarization density of the aforementioned polarization-doped layer is Npol(cm -3 Let ) be the thickness of the polarization-doped layer be dpol (nm), and let the aluminum (Al) concentration on the surface of the polarization-doped layer be Nal, A nitride semiconductor device that satisfies equations (1) and (2) above. (2) The aforementioned transistor is The nitride semiconductor substrate further comprises a p-type well region provided at a position facing the gate electrode via the polarization-doped layer and in contact with the polarization-doped layer, The Mg concentration in the aforementioned well region is 1 × 10 17 cm -3 The above 1 x 10 20 cm -3 The nitride semiconductor device described in (1) above, which is as follows: (3) If the p-type layer and the polarization-doped layer are considered as one pair, The nitride semiconductor device according to (1) or (2), wherein the pair is arranged in n (where n is an integer of 2 or more) layers in a stack at a position facing the gate electrode with the gate insulating film in between. (4) The aforementioned transistor is An n-type source region provided on the first surface side of the nitride semiconductor substrate, The system further comprises a source electrode provided on the first surface side and in contact with the source region, The nitride semiconductor device according to any one of (1) to (3), wherein the polarization-doped layer is in contact with the source region. (5) The nitride semiconductor device described in any one of the above (1 to 4) satisfies the following equation (3). dp(nm) × Np(cm -2 )-Nal(%)×1×10 12 < (dp(nm)+dpol(nm))×1×10 18 (cm -2 )...(3) (6) The aforementioned transistor is an IGBT, The aforementioned transistor is An n-type emitter layer provided on the first surface side of the nitride semiconductor substrate, An emitter electrode provided on the first surface side and in contact with the emitter layer, A p-type collector layer is provided on the second surface side of the nitride semiconductor substrate, which is opposite to the first surface, A nitride semiconductor device according to any one of (1) to (5), further comprising: a collector electrode provided at a position facing the nitride semiconductor substrate across the collector layer and in contact with the collector layer. (7) Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, It has a polarization-doped layer that faces the gate electrode with the p-type layer in between and is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following: A nitride semiconductor device in which the polarization-doped layer is completely depleted when the bias to the gate electrode is 0V. (8) The Mg concentration in the aforementioned p-type layer is 1 × 10 19 cm -3 The above 1 x 10 20 cm -3 A nitride semiconductor device as described in any one of items (1) to (7) above, which is as follows: (9) The nitride semiconductor device according to any one of (1) to (8), wherein the first surface of the nitride semiconductor substrate is the c-plane. (10) The nitride semiconductor device according to any one of (1) to (9), wherein the polarization-doped layer has a distribution in which the Al concentration decreases linearly in the depth direction from the surface of the polarization-doped layer. [Explanation of Symbols]

[0092] 1. Lateral MOSFET 1A Vertical MOSFET 1B IGBT 10 GaN substrates 10a surface 10b back side 11 GaN single crystal substrate 22 GaN layer 23 well area 24 JFET area 25 Contact area 26 Source Area 27 Drain region 29 Collector layer 42 Gate insulating film 44 gate 48 Interlayer insulating film 54 Source electrodes 56 Drain electrode 60 pairs 61 Polarization-doped layer 62 p+ type layer 126 Emitter Region 154 Emitter Electrode 156 Collector electrode H1 Contact Hole

Claims

1. Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, It has a polarization-doped layer that faces the gate electrode with the p-type layer in between and is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following: In the aforementioned p-type layer, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). －３ ) and the thickness of the p-type layer is dp (nm), The polarization density of the polarization-doped layer is Npol (cm³). －３ If we assume that the thickness of the polarization-doped layer is dpol (nm) and the aluminum (Al) concentration on the surface of the polarization-doped layer is Na, A nitride semiconductor device such that the following equations (1) and (2) hold true. [Math 1]

2. The aforementioned transistor is The nitride semiconductor substrate further comprises a p-type well region provided at a position facing the gate electrode via the polarization-doped layer and in contact with the polarization-doped layer, The Mg concentration in the well region is 1×10 １７ cm －３ or more and 1×10 ２０ cm －３ or less. The nitride semiconductor device according to claim 1.

3. If the p-type layer and the polarization-doped layer are considered as one pair, The nitride semiconductor device according to claim 1 or 2, wherein the pair is arranged in n (where n is an integer of 2 or more) layers in a stack at a position facing the gate electrode with the gate insulating film in between.

4. The aforementioned transistor is An n-type source region provided on the first surface side of the nitride semiconductor substrate, The system further comprises a source electrode provided on the first surface side and in contact with the source region, The nitride semiconductor device according to claim 1 or 2, wherein the polarization-doped layer is in contact with the source region.

5. The nitride semiconductor device according to claim 1 or 2, wherein the following equation (3) holds true. dp(nm)×Np(cm －２ )-Nal(%)×1×10 １２ < (dp(nm)+dpol(nm))×1×10 １８ (cm －２ )…(3)

6. The aforementioned transistor is an IGBT, The aforementioned transistor is An n-type emitter layer provided on the first surface side of the nitride semiconductor substrate, An emitter electrode provided on the first surface side and in contact with the emitter layer, A p-type collector layer is provided on the second surface side of the nitride semiconductor substrate, which is opposite to the first surface, The nitride semiconductor device according to claim 1 or 2, further comprising: a collector electrode provided at a position facing the nitride semiconductor substrate across the collector layer and in contact with the collector layer.

7. Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, It has a polarization-doped layer that faces the gate electrode with the p-type layer in between and is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following: A nitride semiconductor device in which the polarization-doped layer is completely depleted when the bias to the gate electrode is 0V.

8. The Mg concentration in the p-type layer is 1 × 10 １９ cm －３ The above 1 x 10 ２０ cm －３ The nitride semiconductor device according to claim 1 or 7, which is as follows:

9. The nitride semiconductor device according to claim 1 or 7, wherein the first surface of the nitride semiconductor substrate is a c-plane.

10. The nitride semiconductor device according to claim 1 or 7, wherein the polarization-doped layer has a distribution in which the Al concentration decreases linearly in the depth direction from the surface of the polarization-doped layer.

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