Multilayer ceramic electronic components

Abstract

To provide multilayer ceramic electronic components that can reduce ESR. [Solution] The multilayer ceramic capacitor 1 has a first external electrode 40A and a second external electrode 40B. The first external electrode 40A has a first base electrode layer 50A, a first conductive resin layer 60A containing a thermosetting resin and metal components arranged to cover the first base electrode layer 50A, and a first Ni plating layer 71A arranged to cover the first conductive resin layer 60A. The second external electrode 40B has a second base electrode layer 50B, a second conductive resin layer 60B containing a thermosetting resin and metal components arranged to cover the second base electrode layer 50B, and a second Ni plating layer 71B arranged to cover the second conductive resin layer 60B. Tensile stress remains as internal stress inside the first Ni plating layer 71A and the second Ni plating layer 71B, and the tensile stress is between 10 MPa and 206 MPa.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] In recent years, multilayer ceramic electronic components typified by multilayer ceramic capacitors have been required to have durability in harsh environments such as bending stress due to thermal expansion. As a countermeasure, a technique using a thermosetting conductive resin paste for the external electrodes of multilayer ceramic electronic components is known. Patent Document 1 is cited as an example of this type of technique. In Patent Document 1, a multilayer ceramic capacitor having an external electrode with a layer structure in which a conductive paste is dipped and applied, and an electrode layer obtained by baking it, a conductive epoxy-based thermosetting resin layer, a nickel plating layer, and a tin-based layer are sequentially laminated is described.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in order to satisfy the required performance while ensuring the durability of multilayer ceramic electronic components in harsh environments, various measures such as reduction of ESR have been taken, and further performance improvement is required.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component capable of reducing ESR.

Means for Solving the Problems

[0006] The multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction; a first internal conductor layer disposed on the plurality of ceramic layers and exposed on the first end surface; a second internal conductor layer disposed on the plurality of ceramic layers and exposed on the second end surface; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface. The first external electrode comprises a first base electrode layer containing a metal component, a first conductive resin layer containing a thermosetting resin and a metal component disposed on the first base electrode layer, and a first Ni plating layer disposed on the first conductive resin layer. The second external electrode comprises a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer. Tensile stress remains as internal stress inside the first Ni plating layer, and tensile stress remains as internal stress inside the second Ni plating layer. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide multilayer ceramic electronic components capable of reducing ESR. [Brief explanation of the drawing]

[0008] [Figure 1] This is an external perspective view of the multilayer ceramic capacitor of this embodiment. [Figure 2] Figure 1 is a cross-sectional view of the multilayer ceramic capacitor along the line II-II. [Figure 3] Figure 2 is a cross-sectional view of the multilayer ceramic capacitor along line III-III. [Figure 4] Figure 2 is a cross-sectional view of the multilayer ceramic capacitor along the IV-IV line. [Figure 5] Figure 2 is an enlarged view of the V-section of the multilayer ceramic capacitor, and is a schematic diagram to explain the state of force generated on the end face side of the multilayer ceramic capacitor. [Figure 6] This is a schematic diagram showing an example of the configuration of a dual-gang multilayer ceramic capacitor. [Figure 7] This is a schematic diagram showing an example of the configuration of a triple-gang multilayer ceramic capacitor. [Figure 8] This is a schematic diagram showing an example of the configuration of a four-gang multilayer ceramic capacitor. [Modes for carrying out the invention]

[0009] <Embodiment> Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the first embodiment of this disclosure will be described with reference to Figures 1 to 4. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IV-IV.

[0010] The multilayer ceramic capacitor 1 comprises a laminated body 10 and external electrodes 40.

[0011] Figures 1 to 4 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross section shown in Figure 4 is also called the LW cross section.

[0012] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that are opposite to the lamination direction T, a first side surface WS1 and a second side surface WS2 that are opposite to the width direction W which is perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 that are opposite to the length direction L which is perpendicular to the lamination direction T and the width direction W.

[0013] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the points where three faces of the laminate intersect, and the edges are the points where two faces intersect. Furthermore, some or all of the surfaces constituting the laminate 10 may have irregularities or other features.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the length L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 10 mm or less. If the width W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12A and a second main surface-side outer layer 12B, which are arranged to sandwich the inner layer 11 in the lamination direction T.

[0016] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0017] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Further, the dielectric material may be those obtained by adding sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds to these main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of the dielectric layers 20 to be laminated is preferably 10 or more and 700 or less. Note that the number of the dielectric layers 20 is the total number of the number of the dielectric layers in the inner layer portion 11 and the number of the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The plurality of internal electrode layers 30 include a first internal electrode layer 31 as a plurality of first internal conductor layers and a second internal electrode layer 32 as a plurality of second internal conductor layers. The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged via the dielectric layers 20 in the stacking direction T of the laminate 10. The first internal electrode layer 31 and the second internal electrode layer 32 are arranged so as to sandwich the dielectric layer 20.

[0020] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32 and a first lead-out portion 31B led out from the first opposing portion 31A to the first end face LS1. The first lead-out portion 31B is exposed on the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead-out portion 32B led out from the second opposing portion 32A to the second end face LS2. The second lead-out portion 32B is exposed on the second end face LS2.

[0022] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0024] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 700 or less.

[0027] The first main surface-side outer layer 12A is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12A is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12A may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0028] The second main surface-side outer layer 12B is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 12B is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 12B may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4 shows the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0030] The laminate 10 has a side outer layer. The side outer layer comprises a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3 and 4 show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0031] The laminate 10 has an end-face outer layer. The end-face outer layer comprises a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is the portion that includes the dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is the portion that includes the dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2 and 4 show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called the L gap or end gap.

[0032] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0033] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] As described above, within the laminate 10, capacitance is formed by the opposition of the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0036] The first external electrode 40A includes a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A includes a first Ni plating layer 71A as an under-plating layer and a first Sn plating layer 72A as an over-plating layer.

[0037] The second external electrode 40B includes a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B includes a second Ni plating layer 71B as an under-plating layer and a second Sn plating layer 72B as an over-plating layer.

[0038] The first Ni plating layer 71A has a first end-face Ni plating layer 71A1 and a first side-face Ni plating layer 71A2, as shown in Figures 2 and 4. The first end of the first Ni plating layer 71A refers to the portion of the first Ni plating layer 71A that is on the second end face LS2 side of the first conductive resin layer 60A in the longitudinal direction L.

[0039] The second Ni plating layer 71B has a second end-face Ni plating layer 71B1 and a second side-face Ni plating layer 71B2, as shown in Figures 2 and 4. The second end of the second Ni plating layer 71B refers to the portion of the second Ni plating layer 71B that is on the first end face LS1 side of the second conductive resin layer 60B in the longitudinal direction L.

[0040] Here, the basic configuration of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Also, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the LW cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, when there is no need to specifically distinguish between the first external electrode 40A and the second external electrode 40B, they may be collectively referred to as the external electrode 40. Similarly, when there is no need to specifically distinguish between the first base electrode layer 50A and the second base electrode layer 50B, they may be collectively referred to as the base electrode layer 50. Furthermore, if there is no need to distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, they may be collectively referred to as the conductive resin layer 60. Similarly, if there is no need to distinguish between the first plating layer 70A and the second plating layer 70B, they may be collectively referred to as the plating layer 70. Furthermore, if there is no need to distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, they may be collectively referred to as the Ni plating layer 71. Furthermore, if there is no need to specifically distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72. If there is no need to specifically distinguish between the first end-face Ni plating layer 71A1 and the second end-face Ni plating layer 71B1, the first end-face Ni plating layer 71A1 and the second end-face Ni plating layer 71B1 may be collectively referred to as the end-face Ni plating layer 711. If there is no need to specifically distinguish between the first side-side Ni plating layer 71A2 and the second side-side Ni plating layer 71B2, the first side-side Ni plating layer 71A2 and the second side-side Ni plating layer 71B2 may be collectively referred to as the side-side Ni plating layer 712.Furthermore, when there is no need to specifically distinguish between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 may be collectively referred to as end face LS.

[0041] The base electrode layer 50 has a first base electrode layer 50A and a second base electrode layer 50B.

[0042] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. The first base electrode layer 50A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0043] The second base electrode layer 50B is located on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. The second base electrode layer 50B may also be located on a portion of the first main surface TS1 and a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0044] The first base electrode layer 50A and the second base electrode layer 50B in this embodiment are baked layers. Preferably, the baked layers contain a metal component and either a glass component or a ceramic component, or both. This improves the adhesion between the laminate 10 and the base electrode layer. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. When a glass component is present, it helps sinter the metal component in the base electrode layer and promotes sintering. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material may be used. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0045] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer may be formed by simultaneously firing a laminate chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminate chip, or by firing a laminate chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When firing a laminate chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminate chip simultaneously, it is preferable to form the baked layer by baking a material with a ceramic component added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0046] The longitudinal thickness of the first base electrode layer 50A located at the first end face LS1 is preferably, for example, 2 μm to 220 μm at the center of the first base electrode layer 50A in the lamination direction T and width direction W.

[0047] The longitudinal thickness of the second base electrode layer 50B located at the second end face LS2 is preferably, for example, 2 μm to 220 μm at the center of the second base electrode layer 50B in the lamination direction T and width direction W.

[0048] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A in the lamination direction provided in this part is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this part.

[0049] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided in this portion is preferably, for example, 4 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided in this portion in the length direction L and the lamination direction T.

[0050] When a second base electrode layer 50B is provided on at least one of the surfaces of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided in this portion in the lamination direction is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0051] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B in the width direction provided in this portion is preferably, for example, 4 μm or more and 40 μm or less in the central part of the second base electrode layer 50B in the length direction L and the lamination direction T.

[0052] The external electrode 40 has a conductive resin layer 60 containing resin and metal components, which is placed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0053] The first conductive resin layer 60A is arranged to cover the first base electrode layer 50A. Preferably, the end of the first conductive resin layer 60A is in contact with the laminate 10. The end of the first conductive resin layer 60A refers to the portion of the first conductive resin layer 60A that is on the second end face LS2 side of the first base electrode layer 50A in the length direction L. The second conductive resin layer 60B is arranged to cover the second base electrode layer 50B. Preferably, the end of the second conductive resin layer 60B is in contact with the laminate 10. The end of the second conductive resin layer 60B refers to the portion of the second conductive resin layer 60B that is on the first end face LS1 side of the second base electrode layer 50B in the length direction L.

[0054] The longitudinal thickness of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, 10 μm to 200 μm at the center of the first conductive resin layer 60A in the lamination direction T and width direction W.

[0055] The longitudinal thickness of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, 10 μm to 200 μm at the center of the second conductive resin layer 60B in the lamination direction T and width direction W.

[0056] When the first conductive resin layer 60A is also provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the first conductive resin layer 60A in the lamination direction T provided in these portions is preferably, for example, 10 μm to 200 μm at the center of the length direction L and width direction W of the first conductive resin layer 60A provided in these portions.

[0057] When the first conductive resin layer 60A is also provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, the thickness of the first conductive resin layer 60A in the width direction W provided on this portion is preferably, for example, 10 μm or more and 200 μm or less at the center of the first conductive resin layer 60A in the length direction L and the lamination direction T provided on this portion.

[0058] When a second conductive resin layer 60B is provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the second conductive resin layer 60B provided in this portion in the lamination direction T is preferably, for example, 10 μm to 200 μm at the center of the length direction L and width direction W of the second conductive resin layer 60B provided in this portion.

[0059] When a second conductive resin layer 60B is provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, the thickness of the second conductive resin layer 60B in the width direction W provided on this portion is preferably, for example, 10 μm to 200 μm at the center of the second conductive resin layer 60B in the length direction L and the lamination direction T.

[0060] The conductive resin layer 60 is placed on the underlying electrode layer 50. The plating layer 70 is then placed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0061] The conductive resin layer 60 has a resin portion and a conductive filler dispersed within the resin portion.

[0062] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin portion of the conductive resin layer 60 contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0063] Because the conductive resin layer 60 includes such resin components, it is more flexible than, for example, the base electrode layer 50 which consists of a plated film or a fired product of metal and glass components. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer 60 functions as a buffer layer. Thus, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0064] The conductive filler is dispersed within the resin portion in a substantially uniform distribution. The conductive filler is primarily responsible for the conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer 60, and electrical conductivity is established between the base electrode layer 50 and the plating layer 70.

[0065] The metal constituting the conductive filler may be pure silver (Ag), an alloy containing Ag, or a metal powder with an Ag coating on its surface. Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or alloy powders containing these as the metal powder.

[0066] Furthermore, the conductive filler may be Cu or Ni that has been treated to prevent oxidation. Alternatively, the conductive filler may be a metal powder coated with Sn, Ni, or Cu on its surface. When using a metal powder coated with Sn, Ni, or Cu on its surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0067] The shape of the conductive filler is not particularly limited. Conductive fillers can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0068] The average particle size of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0069] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated using the laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0070] The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0071] The first plating layer 70A is arranged to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2. More specifically, the first plating layer 70A is arranged such that the first end face Ni plating layer 71A1 described above is arranged on the first end face LS1, and the first side surface Ni plating layer 71A2 described above extends from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2.

[0072] The second plating layer 70B is arranged to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2. More specifically, the second plating layer 70B is arranged such that the second end face Ni plating layer 71B1 described above is arranged on the second end face LS2, and the second side surface Ni plating layer 71B2 described above extends from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2.

[0073] The plating layer 70 preferably has a two-layer structure consisting of a Ni plating layer 71 and a Sn plating layer 72. Preferably, the first Sn plating layer 72A is placed on the first Ni plating layer 71A, and preferably, the second Sn plating layer 72B is placed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the underlying electrode layer 50 and the conductive resin layer 60 from being corroded by the solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0074] The thickness of the first Ni plating layer 71A and the first Sn plating layer 72A are preferably 1 μm or more and 15 μm or less.

[0075] The thickness of the second Ni plating layer 71B and the second Sn plating layer 72B are preferably 1 μm or more and 15 μm or less.

[0076] Figure 5 is an enlarged view of the V section of the multilayer ceramic capacitor 1 shown in Figure 2, and is a schematic diagram for explaining the state of force generated on the LS side of the end face of the multilayer ceramic capacitor 1. As mentioned above, the basic configuration of the first Ni plating 71A and the second Ni plating 71B are the same, so they will be described together as Ni plating 71 using Figure 5. The same applies to the other layers that make up the first external electrode 40A and the second external electrode 40B. As shown in Figure 5, the conductive resin layer 60 is placed on the base electrode layer 50. The plating layer 70, which will be described later, is placed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72. The Ni plating layer 71 has an end face side Ni plating layer 711 and a side side Ni plating layer 712.

[0077] The Ni plating layer 71 is formed such that tensile stress is uniformly generated throughout the layer in a direction intersecting the thickness direction of the plating layer 70. In other words, tensile stress remains as internal stress within the Ni plating layer 71. The end face Ni plating layer 711 has tensile stress in a direction intersecting the thickness direction of the plating layer 70, and the end face Ni plating layer 711 tends to contract in a direction intersecting the thickness direction of the plating layer 70. As shown in Figure 5, the side Ni plating layers 712 formed on both sides of the end face Ni plating layer 711 are each pulled toward the center of the end face Ni plating layer 711. That is, the side Ni plating layers 712 formed on both sides of the end face Ni plating layer 711 are each subjected to a force that presses the conductive resin layer 60 against the underlying electrode layer 50. As a result, the conductive resin layer 60 has improved conductivity and the ESR (Equivalent Series Resistance) is reduced.

[0078] Furthermore, tensile stress is generated in the side Ni plating layer 712 in a direction intersecting the thickness direction of the plating layer 70, causing the side Ni plating layer 712 to shrink in a direction intersecting the thickness direction of the plating layer 70. As a result, the side Ni plating layer 712 is tightened against the conductive resin layer 60 in the circumferential direction, and in the longitudinal direction L, it pulls the end face Ni plating layer 711, pressing the conductive resin layer 60 against the underlying electrode layer 50. This improves the conductivity of the conductive resin layer 60 and reduces ESR.

[0079] Furthermore, it is preferable that the tensile stress be 50 MPa or higher. This further enhances the ESR reduction effect.

[0080] Furthermore, if the stress in the Ni plating layer 71 exceeds 206 MPa, it becomes difficult to manufacture the multilayer ceramic capacitor 1; therefore, it is preferable that the tensile stress be 206 MPa or less. This makes it possible to easily manufacture the multilayer ceramic capacitor 1 while further enhancing the ESR reduction effect.

[0081] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Also, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. In addition, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0082] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described.

[0083] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known.

[0084] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0085] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12A on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 12B on the second main surface TS2 side. This completes the production of the laminated sheet.

[0086] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0087] The laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0088] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0089] A conductive paste, which will become the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. After that, a baking process is performed to form the base electrode layer 50. The temperature of this baking process is preferably 700°C to 950°C.

[0090] Next, a conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the underlying electrode layer 50, or it may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the underlying electrode layer 50.

[0091] First, a conductive resin paste is prepared by dispersing a conductive filler in a thermosetting resin, which serves as the base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, a silver (Ag) metal powder.

[0092] Subsequently, the conductive resin paste is applied to the base electrode layer 50 using a dipping method, and heat treatment is performed at a temperature of 200°C to 550°C. This causes the resin to heat-cur, forming a conductive resin layer 60. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0093] Subsequently, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electroplating method. For example, barrel plating is preferred as the plating method.

[0094] Furthermore, the stress generated throughout the first Ni plating layer 71A and the second Ni plating layer 71B of the present invention can be controlled by the following method.

[0095] It is known that the stress generated in the plating varies depending on the current density applied during film formation. The current density applied to the multilayer ceramic capacitor 1 is random. At the leading edge of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2, the average current density applied to each leading edge from the initial stage of Ni plating formation until, for example, a thickness of 3 μm is reached is the same on any of the leading edges of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2. Therefore, the same stress is applied to any of the surfaces of the Ni plating layer 70 on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2.

[0096] The first Ni layer 71A and the second Ni plating layer 71B can be formed using a plating bath prepared by adjusting the amounts of nickel sulfate and nickel sulfamate added. By adjusting the ratio of nickel sulfate to nickel sulfamate in the plating solution, the residual stress value inside the formed Ni plating layer 71 can be adjusted.

[0097] In this embodiment, a Sn plating layer 72 is further formed on the Ni plating layer 71, with a first Sn plating layer 72A formed on the first Ni plating layer 71A and a second Sn plating layer 72B formed on the second Ni plating layer 71B. Electrolytic plating is used to form the Sn plating layer 72. Barrel plating is preferred as the plating method. This improves the wettability of the solder used for mounting the multilayer ceramic capacitor 1, making mounting easier. The multilayer ceramic capacitor 1 is manufactured by the above manufacturing method.

[0098] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0099] In recent years, ceramic electronic components, such as multilayer ceramic capacitors, have been used in more demanding environments than before. For example, electronic components used in mobile devices such as mobile phones and portable music players are required to withstand impact from drops. Specifically, they must not detach from the mounting board or crack even when subjected to impact from a drop.

[0100] Furthermore, electronic components used in automotive equipment such as ECUs (Electronic Control Units) are required to withstand the shocks of thermal cycling. Specifically, it is necessary to ensure that cracks do not occur in the electronic components even when subjected to flexural stress caused by the thermal expansion and contraction of the mounting substrate due to thermal cycling.

[0101] In response to this, it has been proposed to use a thermosetting conductive resin paste on the external electrodes of ceramic electronic components as a measure to prevent cracking of the ceramic electronic component body even under harsh conditions. For example, an epoxy-based thermosetting resin layer is formed between the conventional electrode layer and the Ni plating layer.

[0102] In this configuration, when stress is generated due to impact during a fall or flexural stress caused by thermal expansion and contraction of the mounting substrate due to thermal cycling, the epoxy thermosetting resin layer releases the stress transmitted to the mounting substrate due to the distortion of the substrate, thereby suppressing crack formation in the ceramic electronic component itself.

[0103] However, in multilayer ceramic electronic components such as those described in Patent Document 1, the stress in the Ni plating layer placed on top of the conductive resin layer is not specified.

[0104] In this invention, residual tensile stress within the Ni plating layer causes the Ni plating layer to press against the underlying electrode layer, compressing the conductive resin layer and increasing the amount of contact between conductive fillers within the conductive resin layer, thereby improving the conductivity of the conductive resin layer. Therefore, it is possible to provide multilayer ceramic electronic components with reduced ESR and improved initial characteristics.

[0105] (1) The multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a plurality of stacked dielectric layers 20 (ceramic layers 20), a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, a first internal electrode layer 31 (first internal conductor layer 31) disposed on the plurality of dielectric layers 20 and exposed on the first end surface LS1, a second internal electrode layer 32 (second internal conductor layer 32) disposed on the plurality of dielectric layers 20 and exposed on the second end surface LS2, a first external electrode 40A disposed on the first end surface LS1, and a second internal electrode 40A disposed on the second end surface LS2 In a multilayer ceramic capacitor 1 having a first external electrode 40A and a second external electrode 40B, the first external electrode 40A comprises a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A containing a thermosetting resin and a metal component disposed on the first base electrode layer 50A, and a first Ni plating layer 71A disposed on the first conductive resin layer 60A. The second external electrode 40B comprises a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B containing a thermosetting resin and a metal component disposed on the second base electrode layer 50B, and a second Ni plating layer 71B disposed on the second conductive resin layer 60B. Tensile stress remains as internal stress inside the first Ni plating layer 71A, and tensile stress remains as internal stress inside the second Ni plating layer 71B.

[0106] This makes it possible to provide multilayer ceramic electronic components that can reduce ESR.

[0107] (2) In the multilayer ceramic capacitor 1 of this embodiment, the tensile stress generated in the first Ni plating layer 71A and the second Ni plating layer 71B is 50 MPa or more.

[0108] This allows for further reduction of ESR.

[0109] (3) The multilayer ceramic capacitor 1 of this embodiment has a first Sn plating layer 72A disposed on a first Ni plating layer 71A and a second Sn plating layer 72B disposed on a second Ni plating layer 71B.

[0110] This allows for improved solder wettability while reducing ESR.

[0111] (4) In this embodiment, the multilayer ceramic capacitor 1 has a first base electrode layer 50A which contains a glass component or a ceramic component, and a second base electrode layer 50B which contains a glass component or a ceramic component.

[0112] This improves the adhesion between the laminate and the underlying electrode layer while reducing ESR.

[0113] <Examples> Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors with the structures shown in Figures 1 to 4 were fabricated as examples and comparative examples. For the samples, the stress of the Ni plating layer was controlled using the manufacturing method described above to achieve the stresses shown in Table 1. Twenty-two samples were prepared for each stress condition. The specifications of the multilayer ceramic capacitors are as follows. • Dimensions of the multilayer ceramic capacitor: 3.2mm (length L) x 2.5mm (width W) x 2.5mm (thickness T) • Ceramic material: BaTiO3 Capacitance: 0.01μF • Rated voltage: 50V • Structure of the external electrodes (1) Underlayment electrode layer: Electrode containing conductive metal (Cu) and glass components Thickness of the base electrode layer at the center of the height direction of the base electrode layer located at the first and second end faces: 15 μm Thickness of the base electrode layer at the longitudinal center of the base electrode layer located on the first main surface and the second main surface, the first side surface and the second side surface: 4 μm (2) Conductive resin layer Conductive resin layer: Conductive filler: Ag Resin: Epoxy-based Heat curing temperature: 200℃ Thickness of the first conductive resin layer at the center in the height direction, located at the first and second end faces: 20 μm Thickness of the base electrode layer at the longitudinal center of the base electrode layer located on the first main surface and the second main surface, the first side surface and the second side surface: 20 μm (3) Ni plating layer Ni plating layer thickness: Thickness of the Ni plating layer at the center of the height direction of the Ni plating layer located at the first and second end faces: 2 μm Thickness of the Ni plating layer in the longitudinal center of the Ni plating layer located on the first main surface and the second main surface, and the first side surface and the second side surface: 2.0 μm (4) Sn plating layer Sn plating layer thickness: Thickness of the Sn plating layer at the center of the height direction of the Sn plating layer located at the first and second end faces: 1.5 μm Thickness of the Sn plating layer in the longitudinal center of the Sn plating layer located on the first main surface and the second main surface, the first side surface and the second side surface: 1.0 μm

[0114] Next, for the samples of the examples and comparative examples, stress measurements of Ni plating and ESR measurements were performed. The stress measurements of Ni plating and the ESR measurements were carried out using different multilayer ceramic capacitors among the multilayer ceramic capacitors manufactured in the same lot. For the stress measurement of the Ni plating layer, the average value of the data with n = 2 was used as the measurement result. For the ESR of each of the examples and comparative examples, the average value of the data with n = 20 at a measurement frequency of 1 MHz was used as the measurement result. And as the judgment criteria, a numerical value of ESR of 8 mΩ or less was judged as "〇", a numerical value of 10 mΩ or less was judged as "△", and a numerical value greater than 10 mΩ was judged as "×".

Table 1

[0115] <Stress Measurement of Ni Plating> Hereinafter, the stress measurement of Ni plating in this example will be described. The stress of the Ni plating layer was measured by the following method.

[0116] First, using a metal stripping agent (Melt Strip (registered trademark) HN980M, manufactured by Meltex Co., Ltd.), the multilayer ceramic capacitor 1 was immersed in the liquid for 5 minutes, and then washed with water to strip the Sn plating layer. For each of the Ni plating layers on the first end face LS1 side and the second end face LS2 side of the multilayer ceramic capacitor 1, at approximately the center of the surface of each Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2, measurement was performed using the X-ray diffraction method (μ-XRD (X-ray Diffraction)) within a range of φ100 μm each.

[0117] More specifically, the stress of the Ni plating layer on the first main surface TS1 was measured at the center of the length L and width W of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the first main surface TS1. Similarly, the stress of the Ni plating layer on the second main surface TS2 was measured at the center of the length L and width W of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the second main surface TS2. Furthermore, the stress of the Ni plating layer on the first side surface WS1 was measured at the center of the length L and stacking direction T of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the first side surface WS1. Furthermore, the stress of the Ni plating layer on the second side surface WS2 was measured at the center of the length L and stacking direction T of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the second side surface WS2. The two prepared samples were measured, and the average of the measurements at the eight locations mentioned above was used as the stress measurement value.

[0118] <Measurement of ESR of multilayer ceramic capacitors> The measurement of ESR in this embodiment is described below. The ESR of the multilayer ceramic capacitor 1 was measured by heat treatment at 150°C in an air atmosphere for 1 hour before measurement. Afterward, it was mounted on a measurement substrate, and 24 ± 2 hours after the completion of the heat treatment, the measurement frequency was set to 1 MHz and measured using a network analyzer. Twenty fabricated samples were measured, and the average value was taken as the value in Table 1 above.

[0119] From the above results, it has been shown that in the present invention, by making the stress of the Ni plating layer placed on the conductive resin layer a tensile stress, the Ni plating presses the conductive resin layer toward the underlying electrode layer, compressing the conductive resin layer, increasing the amount of contact between conductive fillers in the conductive resin layer, and thus improving the conductivity of the conductive resin layer.

[0120] Furthermore, by setting the stress of the Ni plating layer to 50 MPa or higher, the effects of the present invention can be made more pronounced, and a multilayer ceramic capacitor with improved initial characteristics can be provided.

[0121] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 6, 7, and 8.

[0122] The multilayer ceramic capacitor 1 shown in Figure 6 is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 7 is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 8 is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0123] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0124] In the embodiments described above, a multilayer ceramic capacitor was given as an example, in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, thermistors using semiconductor ceramic as the ceramic layer, and inductors using magnetic ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite and other ceramics.

[0125] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0126] <1> A laminate comprising multiple stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A first internal conductor layer is disposed on the plurality of ceramic layers and is exposed on the first end face, A second internal conductor layer is disposed on the plurality of ceramic layers and is exposed on the second end face, A first external electrode disposed on the first end face, A second external electrode disposed on the second end face, In a multilayer ceramic electronic component having, The first external electrode comprises a first base electrode layer containing a metal component, a first conductive resin layer containing a thermosetting resin and a metal component disposed on the first base electrode layer, and a first Ni plating layer disposed on the first conductive resin layer. The second external electrode comprises a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer. Within the first Ni plating layer, tensile stress remains as internal stress. Within the second Ni plating layer, tensile stress remains as internal stress. Multilayer ceramic electronic components. <2> The aforementioned tensile stress is 50 MPa or more. <1> Multilayer ceramic electronic components as described above. <3> A first Sn plating layer is placed on the first Ni plating layer. A second Sn plating layer is placed on the aforementioned second Ni plating layer. <1> or <2> Multilayer ceramic electronic components as described above. <4> The first base electrode layer contains a glass component or a ceramic component, The second base electrode layer contains a glass component or a ceramic component. <1> ~ <3> A multilayer ceramic electronic component as described in any one of the following. <5> A laminate comprising multiple stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, A first internal conductor layer is disposed on the plurality of ceramic layers and is exposed on the first end face, A second internal conductor layer is disposed on the plurality of ceramic layers and is exposed on the second end face, The first external electrode is positioned on the first end face side, A second external electrode positioned on the second end face side, In a multilayer ceramic electronic component having, The first external electrode comprises a first base electrode layer containing a metal component, a first conductive resin layer containing a thermosetting resin and a metal component disposed to cover the first base electrode layer, and a first Ni plating layer disposed to cover the first conductive resin layer. The second external electrode comprises a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component disposed to cover the second base electrode layer, and a second Ni plating layer disposed to cover the second conductive resin layer. Within the first Ni plating layer, which is arranged to cover the first conductive resin layer, tensile stress remains as internal stress. Within the second Ni plating layer, which is positioned to cover the second conductive resin layer, tensile stress remains as internal stress. The tensile stress is between 10 MPa and 206 MPa. <6> The aforementioned tensile stress is 50 MPa or more. <5> Multilayer ceramic electronic components as described above. <7> A first Sn plating layer is placed on the first Ni plating layer. A second Sn plating layer is placed on the aforementioned second Ni plating layer. <5> or <6> Multilayer ceramic electronic components as described above. <8> The first base electrode layer contains a glass component or a ceramic component, The second base electrode layer contains a glass component or a ceramic component. <5> ~ <7> A multilayer ceramic electronic component as described in any one of the following. [Explanation of Symbols]

[0127] 1. Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 40A First external electrode 40B Second external electrode 50A First base electrode layer 50B Second Underlay Electrode Layer 60A First conductive resin layer 60B Second conductive resin layer 71A First Ni plating layer 71B Second Ni plating layer T (height direction) TS1 First main surface TS2 Second main surface W (width direction) WS1 First Aspect WS2 Second Aspect L (Length direction) LS1 First end face LS2 Second end face

Claims

1. A laminate comprising a plurality of stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and width direction, Disposed on the plurality of ceramic layers, a first internal conductor layer exposed on the first end face, A second internal conductor layer is disposed on the plurality of ceramic layers and is exposed on the second end face, The first external electrode is positioned on the first end face side, The second external electrode, which is positioned on the second end face side, In a multilayer ceramic electronic component having, The first external electrode comprises a first base electrode layer containing a metal component, a first conductive resin layer containing a thermosetting resin and a metal component disposed to cover the first base electrode layer, and a first Ni plating layer disposed to cover the first conductive resin layer. The second external electrode comprises a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component disposed to cover the second base electrode layer, and a second Ni plating layer disposed to cover the second conductive resin layer. Within the first Ni plating layer, which is arranged to cover the first conductive resin layer, tensile stress remains as internal stress. Within the second Ni plating layer, which is arranged to cover the second conductive resin layer, tensile stress remains as internal stress. The tensile stress is between 10 MPa and 206 MPa. Multilayer ceramic electronic components.

2. The multilayer ceramic electronic component according to claim 1, wherein the tensile stress is 50 MPa or more.

3. A first Sn plating layer is placed on the first Ni plating layer. The multilayer ceramic electronic component according to claim 1 or 2, wherein a second Sn plating layer is disposed on the second Ni plating layer.

4. The first base electrode layer contains a glass component or a ceramic component. The multilayer ceramic electronic component according to claim 1 or 2, wherein the second base electrode layer includes a glass component or a ceramic component.

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