Multilayer electronic component

Abstract

A multilayer electronic component according to example embodiments of the present disclosure can include a main body including a capacitance forming portion including a dielectric layer and an internal electrode, the main body including a first surface and a second surface opposite to each other in a first direction, a third surface and a fourth surface opposite to each other in a second direction, and a fifth surface and a sixth surface opposite to each other in a third direction; an external electrode disposed on each of the third surface and the fourth surface; a side edge portion disposed on each of the fifth surface and the sixth surface and including a plurality of dielectric grains. For each of M cross sections of the side edge portion in the first direction and the third direction, when an average size of the plurality of dielectric grains is measured in N regions, a standard deviation of the average size measured M x N times is greater than or equal to 5.3 nm and less than or equal to 8.3 nm.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0191097, filed on December 19, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a multilayer electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs), as multilayer electronic components, are chip capacitors mounted on printed circuit boards of various types of electronic products (such as image display devices like liquid crystal displays (LCDs) or plasma display panels (PDPs), computers, smartphones, mobile phones, and circuits for on-board chargers (OBCs) or DC-DC converters in electric vehicles) and function as charging or discharging devices.

[0004] To miniaturize MLCCs and increase their capacitance, it is necessary to maximize the effective area of ​​the internal electrodes. To this end, methods for maximizing the width dimension of the internal electrodes have been investigated. Specifically, a method has been applied where a sheet for forming the side edges is individually attached to the width-direction side surface of the stacked wafer before sintering. Since the microstructure of the side edges has a significant impact on the reliability of MLCCs, further research on this aspect is necessary.

[0005] [Prior Art References] [Patent Literature] (Patent Document 1) Korean Patent Publication No. 10-2015-0135092 Summary of the Invention

[0006] One aspect of this disclosure is to provide a highly reliable multilayer electronic component.

[0007] However, the aspects of this disclosure are not limited to the foregoing and can be more readily understood in the process of describing specific embodiments of this disclosure.

[0008] A multilayer electronic component according to an exemplary embodiment of the present disclosure may include: a body including a capacitor forming portion, the capacitor forming portion including a dielectric layer and an inner electrode alternately disposed with respect to the dielectric layer in a first direction; the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in the third direction; an outer electrode disposed on each of the third surface and the fourth surface; and a side edge portion disposed on each of the fifth surface and the sixth surface. The device includes a plurality of dielectric grains, wherein each of the M cross sections of the side edge portion in the first direction and the third direction is located at a different position in the second direction, wherein M is an integer greater than or equal to 2, each of the M cross sections includes N regions, wherein N is an integer greater than or equal to 2, each of the N regions in each of the M cross sections is located at a different position in the first direction, the plurality of dielectric grains in each of the N regions in the M cross sections have an average size, and the standard deviation of the average size of the plurality of dielectric grains in the total M×N regions in the M cross sections is greater than or equal to 5.3 nm and less than or equal to 8.3 nm.

[0009] A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a capacitor forming portion, the capacitor forming portion including a dielectric layer and an inner electrode alternately disposed with respect to the dielectric layer in a first direction; the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in a second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in a third direction; an outer electrode disposed on each of the third surface and the fourth surface; and a side edge portion disposed on each of the fifth surface and the sixth surface and including a plurality of dielectric grains, wherein the side edge portion has a first cross section in the first direction and the third direction, and the side edge portion has a first cross section in the first direction and the third direction. The second cross-section in the first direction and the third cross-section of the side edge in the third direction are respectively located at 1 / 10, 1 / 4 and 1 / 2 of the length of the side edge in the second direction. In the first cross-section, the average size of multiple dielectric grains measured in three first cross-section regions at different positions in the first direction is defined as GS1, GS2 and GS3 respectively. In the second cross-section, the average size of multiple dielectric grains measured in three second cross-section regions at different positions in the first direction is defined as GS4, GS5 and GS6 respectively. And in the third cross-section, the average size of multiple dielectric grains measured in three third cross-section regions at different positions in the first direction is defined as GS7, GS8 and GS9 respectively. The standard deviation of GS1 to GS9 can be greater than or equal to 5.3 nm and less than or equal to 8.3 nm.

[0010] One effect of this disclosure is to provide a highly reliable multilayer electronic component. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view schematically illustrating a multilayer electronic assembly according to an exemplary embodiment of the present disclosure; Figure 2 It is shown schematically. Figure 1 A three-dimensional view of the main body and side edges; Figure 3 It is shown schematically. Figure 1 A three-dimensional view of the main body; Figure 4 It is along Figure 1 A cross-sectional view taken from line I-I'; Figure 5A It is along Figure 2 A cross-sectional view taken from line II-II'; Figure 5B It is along Figure 2 A cross-sectional view taken from line III-III'; Figure 5C It is along Figure 2 A cross-sectional view taken from line IV-IV'; Figure 6A The image is a side edge of Comparative Example 1, taken with a scanning electron microscope (SEM). Figure 6B This is an image of the side edge of the example, taken using a scanning electron microscope (SEM); Figure 6C The image is a side edge of Comparative Example 2, taken using a scanning electron microscope (SEM). Figure 7A This is a graph showing the results of the moisture-proof reliability assessment of Comparative Example 1; Figure 7B This is a graph showing the results of an example moisture-proof reliability assessment; Figure 8 This is a graph showing the results of the insulation breakdown voltage (BDV) evaluation for Example and Comparative Example 2; and Figure 9 This is a diagram showing the accelerated lifetime distribution of Example 1 and Comparative Example 2. Detailed Implementation

[0012] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to specific example embodiments and accompanying drawings. However, exemplary embodiments of the present disclosure may be exemplified in many different forms and should not be construed as limited to the specific embodiments set forth herein. Furthermore, the exemplary embodiments disclosed herein are provided to explain the present disclosure more completely to those skilled in the art. Therefore, in the accompanying drawings, the shape and size of elements may be exaggerated for clarity, and the same reference numerals will always be used to denote the same or similar elements.

[0013] Furthermore, in the accompanying drawings, details irrelevant to the description have been omitted for clarity, and the disclosure is not limited thereto because the dimensions (e.g., thickness) of each component shown in the drawings are arbitrarily illustrated for ease of description. Additionally, the same reference numerals are used to describe components having the same function within the same conceptual scope. Throughout the specification, unless otherwise stated, when a part “comprises” or “includes” a component, this indicates that other components are not excluded and may be included.

[0014] In the accompanying drawings, the first direction (X direction) can be defined as the thickness direction, the second direction (Y direction) can be defined as the length direction, and the third direction (Z direction) can be defined as the width direction.

[0015] Multilayer electronic components Figure 1 This is a perspective view schematically illustrating a multilayer electronic assembly according to an exemplary embodiment of the present disclosure.

[0016] Figure 2 It is shown schematically. Figure 1 A three-dimensional view of the main body and side edges.

[0017] Figure 3 It is shown schematically. Figure 1 A three-dimensional view of the main body.

[0018] Figure 4 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0019] Figure 5A It is along Figure 2 The cross-sectional view taken from line II-II'.

[0020] Figure 5B It is along Figure 2 The cross-sectional view taken from line III-III'.

[0021] Figure 5C It is along Figure 2 A cross-sectional view taken from line IV-IV'.

[0022] Figure 6A This is an image of the lateral edge of Comparative Example 1 taken using a scanning electron microscope (SEM).

[0023] Figure 6B This is an image of the side edge of an example, taken using a scanning electron microscope (SEM).

[0024] Figure 6C This is an image of the lateral edge of Comparative Example 2 taken using a scanning electron microscope (SEM).

[0025] Figure 7A This is a diagram showing the results of the moisture-proof reliability assessment of Comparative Example 1.

[0026] Figure 7B This is a diagram showing the results of an example moisture-proof reliability assessment.

[0027] Figure 8 This is a graph showing the results of the insulation breakdown voltage (BDV) evaluation for Example and Comparative Example 2.

[0028] Figure 9 This is a diagram showing the accelerated lifetime distribution of Example 1 and Comparative Example 2.

[0029] In the following text, reference will be made to Figures 1 to 9 A multilayer electronic assembly 100 according to an exemplary embodiment of the present disclosure is described in detail. Additionally, a multilayer ceramic capacitor will be described as an example of a multilayer electronic assembly, but the present disclosure is not limited thereto, and is applicable to various multilayer electronic assemblies such as inductors, piezoelectric elements, varistors, or thermistors.

[0030] A multilayer electronic assembly 100 according to an example embodiment of the present disclosure may include a body 110, external electrodes 131 and 132, and side edge portions 114 and 115.

[0031] There are no particular restrictions on the specific shape of the main body 110, but as Figures 1 to 3 As shown, the body 110 may be formed in a hexahedral shape or a shape similar to a hexahedron. Due to the shrinkage of the ceramic particles included in the body 110 during the sintering process or the polishing of the corners of the body 110 during the polishing process, the body 110 may not have a perfectly straight hexahedral shape, but may have a generally hexahedral shape.

[0032] The main body 110 may have a first surface 1 and a second surface 2 that are opposite to each other in a first direction, a third surface 3 and a fourth surface 4 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 that are connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and are opposite to each other in a third direction.

[0033] The main body 110 may include a capacitor forming portion Ac by including a dielectric layer 111 and internal electrodes 121 and 122 alternately disposed with the dielectric layer 111 in a first direction. The capacitor forming portion Ac is disposed inside the main body 110 and has a capacitor formed therein. The plurality of dielectric layers 111 forming the main body 110 are in a sintered state, and adjacent dielectric layers 111 may be integrated, making it difficult to distinguish the boundary between adjacent dielectric layers 111 without using a scanning electron microscope (SEM).

[0034] The dielectric layer 111 may include, for example, a perovskite-type compound represented by ABO3 as a main component. The perovskite-type compound represented by ABO3 may include, for example, BaTiO3, (Ba 1-x Ca x TiO3 (0) <x<1)、Ba(Ti 1-y Ca y )O3(0 <y<1)、(Ba 1- x Ca x (Ti)1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), or one or more of them.

[0035] The inner electrodes 121 and 122 may include, for example, a first inner electrode 121 and a second inner electrode 122. The first inner electrode 121 and the second inner electrode 122 are alternately arranged in the first direction, and the dielectric layer 111 is interposed between the first inner electrode 121 and the second inner electrode 122. The first inner electrode 121 and the second inner electrode 122 may be electrically isolated from each other through the dielectric layer 111 provided between them.

[0036] The first inner electrode 121 may extend to the third surface 3, the fifth surface 5, and the sixth surface 6, but may be spaced apart from the fourth surface 4. The first inner electrode 121 may be connected to the first outer electrode 131. The second inner electrode 122 may extend to the fourth surface 4, the fifth surface 5, and the sixth surface 6, but may be spaced apart from the third surface 3. The second inner electrode 122 may be connected to the second outer electrode 132.

[0037] The conductive metal included in the inner electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and their alloys, and may more preferably include Ni, but the present invention is not limited thereto.

[0038] The main body 110 may include covering portions 112 and 113 provided on two surfaces of the capacitance forming portion Ac that face each other in the first direction.

[0039] The side edge portions 114 and 115 may be provided on the fifth surface 5 and the sixth surface 6 of the main body 110, respectively. The multilayer electronic component 100 may include a first side edge portion 114 provided on the fifth surface 5 and a second side edge portion 115 provided on the sixth surface 6.

[0040] The covering portions 112 and 113 and the side edge portions 114 and 115 may include, for example, a perovskite-type compound represented by ABO3 as a main component. The perovskite-type compound represented by ABO3 may include, for example, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Cax )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), or one or more of these.

[0041] The outer electrodes 131 and 132 can be respectively disposed on the third surface 3 and the fourth surface 4 of the main body 110. The multilayer electronic component 100 can include a first outer electrode 131 disposed on the third surface 3 and a second outer electrode 132 disposed on the fourth surface 4. The first outer electrode 131 can be disposed on the third surface 3 and can extend to a part of the first surface 1, a part of the second surface 2, a part of the fifth surface 5, and a part of the sixth surface 6, and the second outer electrode 132 can be disposed on the fourth surface 4 and can extend to a part of the first surface 1, a part of the second surface 2, a part of the fifth surface 5, and a part of the sixth surface 6.

[0042] The type or shape of the outer electrodes 131 and 132 is not particularly limited and can have a multilayer structure. For example, the outer electrodes 131 and 132 can include a base electrode layer 131a and 132a in contact with the inner electrodes 121 and 122, and plating layers 131b and 132b disposed on the base electrode layers 131a and 132a.

[0043] The base electrode layers 131a and 132a can be sintered electrode layers including metal and glass. The metal included in the base electrode layers 131a and 132a can include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, and / or alloys containing them. The glass included in the base electrode layers 131a and 132a can include, for example, one or more oxides of Ba, Ca, Zn, Al, B, and Si.

[0044] The base electrode layers 131a and 132a can be composed only of sintered electrode layers, but the present disclosure is not limited thereto. The base electrode layers 131a and 132a can include sintered electrode layers containing metal and glass, and resin-based electrode layers disposed on the sintered electrode layers and including metal particles and resin.

[0045] The metal particles included in the resin-based electrode layer can include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn, and / or alloys containing them. The resin included in the resin-based electrode layer can include, for example, one or more of epoxy resin, acrylic resin, and ethyl cellulose.

[0046] The plating layers 131b and 132b may comprise, for example, Ni, Sn, Pd, and / or alloys comprising them, and may be formed as multiple layers. The plating layers 131b and 132b may be, for example, Ni plating layers or Sn plating layers, or may be formed in a manner in which Ni plating layers and Sn plating layers are formed sequentially. The plating layers 131b and 132b may comprise multiple Ni plating layers and / or multiple Sn plating layers.

[0047] The accompanying drawings depict a multilayer electronic assembly 100 having two external electrodes 131 and 132, but this disclosure is not limited thereto, and the number or shape of the external electrodes 131 and 132 may be changed according to the shape of the internal electrodes 121 and 122 or for other purposes.

[0048] Side edge portions 114 and 115 may include a plurality of dielectric grains G1, G2, G3, G4, G5, G6, G7, G8, and G9. Side edge portions 114 and 115 essentially function to protect the capacitor formation portion Ac. By suppressing the grain growth of the plurality of dielectric grains G1 to G9 included in side edge portions 114 and 115, the density of side edge portions 114 and 115 can be improved, thus preventing external moisture from penetrating into the capacitor formation portion Ac, thereby improving the reliability of the multilayer electronic assembly 100.

[0049] To more effectively improve the reliability of the multilayer electronic component 100, it may be necessary to uniformly suppress the grain growth of multiple dielectric grains G1 to G9. This would allow for a uniform improvement in the density at each location of the side edges 114 and 115.

[0050] Therefore, in the multilayer electronic assembly 100 according to an exemplary embodiment of the present disclosure, for each of the M cross-sections of the side edges 114 and 115 located at different positions in the second direction in the first direction and the third direction, when the average size of a plurality of dielectric grains G1 to G9 is measured in N regions located at different positions in the first direction, the standard deviation of the average size of the M×N measurements can satisfy greater than or equal to 5.3 nm and less than or equal to 8.3 nm. Each of M and N can be an integer greater than or equal to 2.

[0051] In other words, the side edges 114 and 115 of the multilayer electronic component 100 according to the exemplary embodiment of this disclosure can satisfy a standard deviation of the average size of the grains measured in multiple cross sections × multiple regions that is greater than or equal to 5.3 nm and less than or equal to 8.3 nm. When the standard deviation meets this range, the reliability of the multilayer electronic component 100 can be effectively improved.

[0052] When the standard deviation exceeds 8.3 nm, the growth of dielectric grains included in the side edges 114 and 115 may not be uniformly suppressed, which may degrade the BDV distribution and lifetime characteristics of the multilayer electronic component 100. When the standard deviation is less than 5.3 nm, the growth of dielectric grains included in the side edges 114 and 115 may be excessively suppressed, and the porosity in the side edges 114 and 115 may increase. As a result, the moisture resistance reliability of the multilayer electronic component 100 may be reduced.

[0053] The standard deviation can be calculated using the following mathematical expression 1. The standard deviation is measured by squaring the deviation, summing the squares of the deviations, dividing the sum by the number of measurements, and calculating the square root. It can be expressed as the square root of the mean of the squares of the deviations.

[0054] [Mathematical Expression 1]

[0055] There are no particular restrictions on the number of M cross-sections, but if Figure 2 as well as Figures 5A to 5C As shown, the M sections may include a first section CS1 cut at 1 / 10 of the length L in the second direction of the side edges 114 and 115, a second section CS2 cut at 1 / 4 of the length L in the second direction of the side edges 114 and 115, and a third section CS3 cut at 1 / 2 of the length L in the second direction of the side edges 114 and 115.

[0056] The fact that the M cross sections may include a first cross section CS1, a second cross section CS2, and a third cross section CS3 cut at 1 / 10, 1 / 4, and 1 / 2 points of the length L in the second direction of the side edges 114 and 115 means that the average size and standard deviation of the dielectric grains G1 to G9 are measured at various locations in the second direction (e.g., at any location in the second direction), rather than limiting the first, second, and third cross sections to cross sections cut at 1 / 10, 1 / 4, and 1 / 2 points of the length L in the second direction of the side edges 114 and 115, respectively. In other words, when the M cross sections include the first cross section CS1, the second cross section CS2, and the third cross section CS3 and the standard deviation satisfies ≥5.3 nm and ≤8.3 nm, the side edges 114 and 115 may include dielectric grains G1 to G9 with a certain level of dimensional uniformity, regardless of the location in the second direction, thus more effectively improving the reliability of the multilayer electronic assembly 100.

[0057] In this disclosure, the points at 1 / 10, 1 / 4, and 1 / 2 of the length L in the second direction for the side edges 114 and 115 can be considered by those skilled in the art to be near the points at 1 / 10, 1 / 4, and 1 / 2 of the length L in the second direction for the side edges 114 and 115. Therefore, taking into account errors such as those in the polishing process used for measurement, the 1 / 10 point can represent a point within the range of 1 / 10 ± 1 / 50 of the length L in the second direction for the side edges 114 and 115, the 1 / 4 point can represent a point within the range of 1 / 4 ± 1 / 50 of the length L in the second direction for the side edges 114 and 115, and the 1 / 2 point can represent a point within the range of 1 / 2 ± 1 / 50 of the length L in the second direction for the side edges 114 and 115. The points at 1 / 10, 1 / 4, and 1 / 2 of the length L in the second direction can be determined by scanning electron microscopy (SEM). Other methods and / or tools understood by those skilled in the art can be used even if not described in this disclosure.

[0058] There are no particular restrictions on the number of N regions, but they can include three regions that are located differently from each other in the first direction.

[0059] For example, when the average dimensions of multiple dielectric grains G1 to G3 measured in three first cross-sectional regions UR1, CR1, and LR1 located at different positions in the first direction in the first cross-section CS1 are defined as GS1, GS2, and GS3; the average dimensions of multiple dielectric grains G4 to G6 measured in three second cross-sectional regions UR2, CR2, and LR2 located at different positions in the first direction in the second cross-section CS2 are defined as GS4, GS5, and GS6; and the average dimensions of multiple dielectric grains G7 to G9 measured in three third cross-sectional regions UR3, CR3, and LR3 located at different positions in the first direction in the third cross-section CS3 are defined as GS7, GS8, and GS9, the standard deviation of GS1 to GS9 can be greater than or equal to 5.3 nm and less than or equal to 8.3 nm. That is, for example, the standard deviation of GS1 to GS9 can refer to the standard deviation between nine average dimensions measured in a total of nine regions. In this disclosure, the average dimension can represent the value of the average dimension.

[0060] For example, the N regions may include the upper regions (e.g., first regions) UR1, UR2, and UR3 of the side edge portions 114 and 115, the central regions CR1, CR2, and CR3, and the lower regions (e.g., second regions) LR1, LR2, and LR3. Here, the central regions CR1, CR2, and CR3 may correspond to the central region of the capacitor forming portion Ac in the first direction, the upper regions (e.g., first regions) UR1, UR2, and UR3 may correspond to the uppermost region of the capacitor forming portion Ac in the first direction, and the lower regions (e.g., second regions) LR1, LR2, and LR3 may correspond to the lowermost region of the capacitor forming portion Ac in the first direction.

[0061] In other words, the first cross-sectional regions UR1, CR1 and LR1 may include a first central region CR1 corresponding to the central region of the capacitor forming part Ac in the first direction, a first upper region (e.g., the first-first region) UR1 corresponding to the uppermost region of the capacitor forming part Ac in the first direction, and a first lower region (e.g., the first-second region) LR1 corresponding to the lowermost region of the capacitor forming part Ac in the first direction.

[0062] The second cross-sectional regions UR2, CR2 and LR2 may include a second central region CR2 corresponding to the central region of the capacitor forming part Ac in the first direction, a second upper region (e.g., second-first region) UR2 corresponding to the uppermost region of the capacitor forming part Ac in the first direction, and a second lower region (e.g., second-second region) LR2 corresponding to the lowermost region of the capacitor forming part Ac in the first direction.

[0063] The third cross-sectional regions UR3, CR3 and LR3 may include a third central region CR3 corresponding to the central region of the capacitor forming part Ac in the first direction, a third upper region (e.g., the third-first region) UR3 corresponding to the uppermost region of the capacitor forming part Ac in the first direction, and a third lower region (e.g., the third-second region) LR3 corresponding to the lowermost region of the capacitor forming part Ac in the first direction.

[0064] The fact that the N regions may include upper regions UR1, UR2, and UR3, central regions CR1, CR2, and CR3, and lower regions LR1, LR2, and LR3 means that the average size and standard deviation of the dielectric grains G1 to G9 can be measured at various first-direction locations (e.g., at any location in the first direction), rather than restricting the upper, central, and lower regions to specific locations. That is, when the N regions include upper regions UR1, UR2, and UR3, central regions CR1, CR2, and CR3, and lower regions LR1, LR2, and LR3, and the standard deviation satisfies a value greater than or equal to 5.3 nm and less than or equal to 8.3 nm, the side edges 114 and 115 may include dielectric grains G1 to G9 with a certain level of dimensional uniformity, regardless of their first-direction location, thus more effectively improving the reliability of the multilayer electronic assembly 100.

[0065] In addition, to more accurately measure the average size of dielectric grains G1 to G9, each of the N regions may include 500 or more dielectric grains G1 to G9. There is no specific upper limit to the number of dielectric grains G1 to G9 included in each of the N regions, but for example, the number of dielectric grains G1 to G9 included in each of the N regions may be less than or equal to 1000.

[0066] The following describes an example of a method for measuring the standard deviation. First, the external electrodes 131 and 132 of the multilayer electronic assembly 100 are removed, and then a first and third directional cross section (first cross section CS1) is exposed at a point 1 / 10 of the length L in the second direction, polished to the side edges 114 and 115. In the first cross section CS1, a first central region CR1, a first upper region UR1, and a first lower region LR1 are defined. To prevent interference from the inner electrodes, the first cross section regions UR1, CR1, and LR1 may be defined at positions spaced a specific distance d from the capacitor forming portion Ac. For example, d may be greater than or equal to 100 nm and less than or equal to 500 nm. The first central region CR1 may be configured to overlap with the central portion of the capacitor forming portion Ac in the first direction in the third directional direction, the first upper region UR1 may be configured to overlap with the inner electrodes 121 and / or 122 disposed in the uppermost portion based on the first direction in the third directional direction, and the first lower region LR1 may be configured to overlap with the inner electrodes 121 and / or 122 disposed in the lowermost portion based on the first direction in the third directional direction. Next, images of the first central region CR1, the first upper region UR1, and the first lower region LR1 were obtained by scanning electron microscopy (SEM) at a magnification of 50,000x. Each image was constructed to have 500 or more dielectric grains. The number of GS1 to GS3 and dielectric grains G1 to G3 can be derived by analyzing each image using an image analysis program. Other methods and / or tools understood by those skilled in the art may be used, even if not described in this disclosure.

[0067] Next, the sheet polished to 1 / 10 of the length L in the second direction of the side edges 114 and 115 is polished again to 1 / 4 of the length L in the second direction of the side edges 114 and 115, thereby exposing the cross-section in the first and third directions (second cross-section CS2). In the second cross-section CS2, a second central region CR2, a second upper region UR2, and a second lower region LR2 are defined. The same method as that used to measure the average grain size in the first cross-section CS1 can be performed in the second cross-section CS2, so that GS4 to GS6 can be calculated.

[0068] Next, the sheet polished to 1 / 4 of the length L in the second direction at the side edges 114 and 115 is polished again to 1 / 2 of the length L in the second direction at the side edges 114 and 115, thereby exposing the cross-section in the first and third directions (third cross-section CS3). In the third cross-section CS3, a third central region CR3, a third upper region UR3, and a third lower region LR3 are defined. The same method as that used to measure the average grain size in the first cross-section CS1 can be performed in the third cross-section CS3, so that GS7 to GS9 can be calculated.

[0069] Therefore, the standard deviation of the average dimensions of GS1 to GS9 can be calculated. However, this disclosure is not limited thereto, and M×N can have various values, such as 3×4, 4×3, 4×4, 5×5, etc.

[0070] In the example embodiment, the average sizes GS2, GS5, and GS8 of the plurality of dielectric grains measured in the central regions CR1, CR2, and CR3 may be greater than the average sizes GS1, GS4, and GS7 of the plurality of dielectric grains measured in the upper regions UR1, UR2, and UR3 and / or the average sizes GS3, GS6, and GS9 of the plurality of dielectric grains measured in the lower regions LR1, LR2, and LR3. That is, GS1 to GS9 may satisfy one or more of the following: GS2>GS1, GS2>GS3, GS5>GS4, GS5>GS6, GS8>GS7, and GS8>GS9.

[0071] Due to the influence of the sintering agent diffused from the covering portions 112 and 113, the growth of dielectric grains G1, G4, and G7 in the upper regions UR1, UR2, and UR3, and dielectric grains G3, G6, and G9 in the lower regions LR1, LR2, and LR3, can be more suppressed compared to dielectric grains G2, G5, and G8 in the central regions CR1, CR2, and CR3. Therefore, one or more of the following conditions can be satisfied: GS2>GS1, GS2>GS3, GS5>GS4, GS5>GS6, GS8>GS7, and GS8>GS9.

[0072] However, the side edges 114 and 115 of the multilayer electronic assembly 100 according to an exemplary embodiment of this disclosure may include dielectric grains G1 to G9 with a certain level of dimensional uniformity, regardless of their position in the first direction. Therefore, the ratio of the average dimensions GS1, GS4, and GS7 of the plurality of dielectric grains measured in the upper regions UR1, UR2, and UR3 and / or the average dimensions GS3, GS6, and GS9 of the plurality of dielectric grains measured in the lower regions LR1, LR2, and LR3 to the average dimensions GS2, GS5, and GS8 of the plurality of dielectric grains measured in the central regions CR1, CR2, and CR3 may be greater than or equal to 0.923 and less than or equal to 0.987. That is, it can satisfy one or more of the following values: 0.923≤GS1 / GS2≤0.987, 0.923≤GS3 / GS2≤0.987, 0.923≤GS4 / GS5≤0.987, 0.923≤GS6 / GS5≤0.987, 0.923≤GS7 / GS8≤0.987, and 0.923≤GS9 / GS8≤0.987. When this range of values ​​is met, the reliability of the multilayer electronic component 100 can be improved more effectively.

[0073] For example, the average sizes of multiple dielectric grains measured in the central regions CR1, CR2, and CR3, GS2, GS5, and GS8, can be greater than or equal to 200 nm and less than or equal to 300 nm.

[0074] In addition to the ABO3 main component, the dielectric layer 111 and the side edge portions 114 and 115 may also include the following secondary components to achieve a multilayer electronic assembly 100 with desired characteristics.

[0075] The secondary components are described based on the molar number of elements and can be calculated by converting them into the amount of oxides or carbonates added as additives before sintering. Unless there are special circumstances, the content of elements before and after sintering can be without large error values, and the type and content of elements included in the dielectric layer 111 and the side edges 114 and 115 can be measured after sintering using various measuring devices such as scanning electron microscopy-energy dispersive X-ray spectroscopy (SEM-EDS), transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS), and scanning transmission electron microscopy-energy dispersive X-ray spectroscopy (STEM-EDS) through various measurement methods.

[0076] As an example of a more specific method for measuring the content of each element included in the side edges 114 and 115, a thinned analytical sample is prepared using a focused ion beam (FIB) apparatus for the region corresponding to the side edges 114 and 115 in a cross-section of the multilayer electronic assembly 100. The damaged layer on the surface of the thinned sample is then removed using Ar ion milling, and each component is mapped from the acquired image using TEM-EDS (or STEM-EDS) for qualitative / quantitative analysis. In this case, the qualitative / quantitative analysis map of each component can be converted into the mass fraction (wt%), atomic percentage (at%), or mole fraction (mol%) of each element.

[0077] 1) First secondary component The dielectric layer 111 and the side edges 114 and 115 may include a first secondary component comprising one or more of Dy, Y, Tb, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu. The first secondary component can be used to improve the reliability of the multilayer electronic assembly 100. For example, relative to 100 mol of Ti, the total content of the first secondary component included in the side edges 114 and 115 may be greater than or equal to 0.6 mol and less than or equal to 3.0 mol.

[0078] 2) Second sub-component The dielectric layer 111 and the side edge portions 114 and 115 may include a second secondary component comprising one or both of Mg and Zr. The second secondary component may be included in the side edge portions 114 and 115 to lower the sintering temperature of the side edge portions 114 and 115 and to suppress grain growth. For example, the total content of the second secondary component included in the side edge portions 114 and 115 may be greater than or equal to 0.1 mol and less than or equal to 3.0 mol relative to 100 mol of Ti. For example, the side edge portions 114 and 115 may include Ti and Mg, and the amount of Mg in the side edge portions 114 and 115 may be greater than or equal to 0.1 mol and less than or equal to 3.0 mol relative to 100 mol of Ti.

[0079] 3) Third sub-component The dielectric layer 111 and the side edges 114 and 115 may include a third secondary component comprising one or more of Mn, V, Cr, Fe, Ni, Co, and Zn. The third secondary component is an atomically variable valence acceptor element and can be used to improve the dielectric properties and high-temperature accelerated lifetime characteristics of the multilayer electronic component 100. For example, relative to 100 mol of Ti, the total content of the third secondary component included in the side edges 114 and 115 may be greater than or equal to 0.01 mol and less than or equal to 8.0 mol.

[0080] 4) Fourth sub-component The dielectric layer 111 and the side edges 114 and 115 may include a fourth sub-component comprising one or both of Si and Al. Si can suppress the grain growth of dielectric grains included in the side edges 114 and 115, thereby improving the density of the side edges 114 and 115. Al can contribute to low-temperature densification through liquefaction during sintering and can improve the high-temperature withstand voltage characteristics of the multilayer electronic component 100.

[0081] In order to properly control the microstructure of the side edge portions 114 and 115, the side edge portions 114 and 115 may include one or more of, for example, Dy, Mn, Mg, V, Si and Al, and may also include all of Dy, Mn, Mg, V, Si and Al.

[0082] There are no particular limitations on the size of the multilayer electronic component 100, but the maximum length of the multilayer electronic component 100 in the second direction can be from 0.1 mm to 6.0 mm, the maximum width of the multilayer electronic component 100 in the third direction can be from 0.1 mm to 5.0 mm, and the maximum thickness of the multilayer electronic component 100 in the first direction can be from 0.05 mm to 3.5 mm.

[0083] There is no particular limitation on the average thickness of the dielectric layer 111, but for example, the average thickness of the dielectric layer 111 can be 0.1 μm to 20 μm, 0.1 μm to 10 μm, 0.1 μm to 5 μm, 0.1 μm to 2 μm or 0.1 μm to 0.4 μm.

[0084] There is no particular limitation on the average thickness of the inner electrodes 121 and 122, but for example, the average thickness of the inner electrodes 121 and 122 can be 0.1 μm to 3.0 μm, 0.1 μm to 1.0 μm, or 0.1 μm to 0.4 μm.

[0085] The average thickness of dielectric layer 111 and the average thickness of inner electrodes 121 and 122 refer to the average thickness of dielectric layer 111 and inner electrodes 121 and 122 in the first direction, respectively. The average thickness of dielectric layer 111 and the average thickness of inner electrodes 121 and 122 can be measured by scanning the cross-sections of the multilayer electronic assembly 100 in the first and third directions using a scanning electron microscope (SEM) at a magnification of 10,000x. More specifically, the average thickness of dielectric layer 111 can be measured by averaging the thickness at multiple points of dielectric layer 111 (e.g., five points spaced equally apart in the third direction). Similarly, the average thickness of inner electrodes 121 and 122 can be measured by averaging the thickness at multiple points of inner electrode 121 or 122 (e.g., five points spaced equally apart in the third direction). The five points spaced equally apart can be specified in the capacitor forming section Ac. In addition, by performing an average measurement on each of the 10 dielectric layers 111 and the 10 inner electrodes 121 and 122 and then taking their average, the average thickness of the dielectric layer 111 and the average thickness of the inner electrodes 121 and 122 can be made more generalized.

[0086] There is no particular limitation on the average thickness tc of the covering portions 112 and 113. For example, the average thickness tc of the covering portions 112 and 113 may be less than or equal to 150 μm, less than or equal to 100 μm, less than or equal to 30 μm, or less than or equal to 20 μm. For example, the average thickness tc of the covering portions 112 and 113 may be greater than or equal to 5 μm, greater than or equal to 10 μm, or greater than or equal to 30 μm. Here, the average thickness tc of the covering portions 112 and 113 refers to the average thickness of each of the first covering portion 112 and the second covering portion 113.

[0087] The average thickness tc of the covers 112 and 113 may refer to the average thickness of the covers 112 and 113 in the first direction, and may be the average thickness in the first direction measured at 5 points spaced apart from each other at equal intervals in the first and third directional sections of the multilayer electronic assembly 100.

[0088] The average thickness wm of the side edge portions 114 and 115 is not particularly limited. For example, the average thickness wm of the side edge portions 114 and 115 may be greater than or equal to 3 μm and less than or equal to 100 μm. For example, when the multilayer electronic component 100 has a size of 1005 dimensions (length: about 1.0 mm, width: about 0.5 mm, thickness: about 0.5 mm) or less, the average thickness wm of the side edge portions 114 and 115 may be greater than or equal to 3 μm and less than or equal to 25 μm, for example, greater than or equal to 14 μm and less than or equal to 20 μm. The average thickness wm of the side edge portions 114 and 115 refers to the average thickness of each of the first side edge portion 114 and the second side edge portion 115.

[0089] The average thickness wm of the side edge portions 114 and 115 may refer to the average thickness of the side edge portions 114 and 115 in the third direction, and may be the average value of the thicknesses in the third direction measured at five points spaced apart from each other at equal intervals in the first direction in a cross-section in the first direction and the third direction of the multilayer electronic component 100. For example, the average thickness wm of the side edge portions 114 and 115 may be measured in the third cross-section CS3.

[0090] Hereinafter, an example of a method for forming the multilayer electronic component 100 will be described. However, the manufacturing method of the multilayer electronic component 100 is not limited thereto.

[0091] First, ceramic particles for forming the dielectric layer 111 are prepared. The ceramic particles may include, for example, BaTiO3, (Ba 1- x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) or Ba(Ti 1- y Zr y )O3 (0 < y < 1). For example, BaTiO3 particles may be synthesized by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. For example, the method for synthesizing ceramic particles includes a solid-phase method, a sol-gel method, and a hydrothermal synthesis method, but the present invention is not limited thereto. Then, after drying and grinding the prepared ceramic particles, an organic solvent such as ethanol, a binder such as polyvinyl butyral, and other auxiliary components are mixed to prepare a ceramic slurry, and then the ceramic slurry is coated on a carrier film and dried to prepare a sheet for forming the dielectric layer.

[0092] Next, a conductive paste for the internal electrode, comprising metal particles, adhesives, and organic solvents, is printed to a predetermined thickness onto a sheet for forming a dielectric layer using screen printing or gravure printing, thereby forming an internal electrode pattern.

[0093] Then, a sheet with an internal electrode pattern printed on it for forming a dielectric layer is peeled off from the carrier film, and a ceramic laminate is formed by stacking a predetermined number of these sheets and pressing them. To form the covers 112 and 113 after sintering, a predetermined number of sheets without internal electrode patterns for forming the covers can be stacked on the upper and lower parts of the ceramic laminate. The ceramic laminate is then cut to a predetermined sheet size. In this case, the ends of the internal electrode patterns are exposed on the two third-direction surfaces of the cut sheets.

[0094] Next, the sheet used to form the edge portions is attached to the two third-direction surfaces of the cut sheet, and then sintered to form the body 110 and the side edge portions 114 and 115. For example, sintering can be carried out for 1 to 3 hours in an atmosphere of 1.0% H2 / 99.0% N2 to 3.5% H2 / 96.5% N2 (H2O / H2 / N2 atmosphere) at a temperature greater than or equal to 1000°C and less than or equal to 1400°C.

[0095] In addition, the sheet used to form the edge portion can be formed in a similar manner to the sheet used to form the dielectric layer, but the type and content of the secondary components included in the sheet used to form the edge portion may be different from the type and content of the secondary components included in the sheet used to form the dielectric layer.

[0096] The sheet used to form the edge portion may include a predetermined amount of first to fourth secondary component particles. For example, the sheet used to form the edge portion may include one or more of Dy, Mn, Mg, V, Si, and Al. The secondary component particles may be added to the sheet used to form the edge portion in the form of oxides and / or carbonates, but this disclosure is not limited thereto.

[0097] Next, external electrodes 131 and 132 are formed. For example, when the substrate electrode layers 131a and 132a include sintered electrode layers, the body 110 can be immersed in a conductive paste for external electrodes comprising metal particles, glass frit, binder and organic solvent, and then the conductive paste for external electrodes can be sintered at a temperature of 500°C to 900°C to form sintered electrode layers.

[0098] For example, when the substrate electrode layers 131a and 132a include resin-based electrode layers, the body 110 can be impregnated in a conductive resin composition including metal particles, resin, adhesive and organic solvent, and then cured at a temperature of 250°C to 550°C to form a resin-based electrode layer.

[0099] Alternatively, an electrolytic plating method and / or an electroless plating method may be performed to form plating layers 131b and 132b on the substrate electrode layers 131a and 132a.

[0100] (Example) A sample sheet with dimensions of 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) was prepared using the above manufacturing method. Then, polishing was performed to 1 / 10 of the length of the side edges in the second direction to expose a cross-section (first cross-section) in both the first and third directions. In the first cross-section, the upper, central, and lower regions of the side edges were analyzed using a scanning electron microscope (SEM) at 50,000x magnification, and the average sizes GS1, GS2, and GS3 of the dielectric grains included in each region were calculated. The number of dielectric grains included in each region was approximately 700 to 800.

[0101] Next, polishing is performed to 1 / 4 of the length of the side edge in the second direction to expose the second section, and the average sizes GS4, GS5 and GS6 of the dielectric grains included in the upper, central and lower regions of the side edge are calculated in the same way.

[0102] Then, polishing is performed to half the length of the side edge in the second direction to expose the third section, and the average sizes GS7, GS8, and GS9 of the dielectric grains included in the upper, central, and lower regions of the side edge are calculated using the same method. Finally, the standard deviations of the nine measurements (GS1 to GS9) are calculated.

[0103] The standard deviation of Comparative Example 1 is less than 5.3 nm, the standard deviation of the example satisfies greater than or equal to 5.3 nm and less than or equal to 8.3 nm, and the standard deviation of Comparative Example 2 is greater than 8.3 nm.

[0104] Reference Figures 6A to 6C It can be confirmed that the number of holes in Comparative Example 1 is greater than the number of holes in the example. Figures 6A to 6C In the diagram, the holes are the areas marked with bright light. Also, refer to... Figure 6C It can be confirmed that many empty spaces appear as black. This is because, compared to the example, the side edges in Comparative Example 2 are not densified.

[0105] Moisture resistance reliability was evaluated on the sample pieces of Comparative Example 1 and the Example. The moisture resistance reliability was evaluated for approximately 2 hours on 20 sample pieces of each of Comparative Example 1 and the Example in an environment of 85°C, 85% humidity, and 1Vr. (Refer to...) Figure 7A and Figure 7BIn the example case, no sample sheet with reduced insulation resistance (IR) was found, but in Comparative Example 1, a sample sheet with drastically reduced insulation resistance (IR) was found. This is because when the standard deviation is less than 5.3 nm, the grain growth of dielectric grains, including those in the side edges, is excessively suppressed, resulting in a large number of pores, which is expected to reduce the moisture resistance reliability of the sample sheet.

[0106] Next, insulation breakdown voltage (BDV) and accelerated lifetime assessments were performed on Examples and Comparative Examples 2. The BDV assessment was performed by applying a DC voltage to 40 samples from each of Examples and Comparative Examples 2 at a current of 0.01 A and a measurement time of 50 ms, and measuring the voltage value at the occurrence of leakage current. The accelerated lifetime assessment was performed by measuring the lifetime of 40 samples from each of Examples and Comparative Examples 2 at 125 °C and 1.5 Vr.

[0107] Reference Figure 8 and Figure 9 It can be confirmed that Comparative Example 2 exhibits poorer BDV distribution and lifetime characteristics compared to the example. In the case of Comparative Example 2, the grain growth of dielectric grains, including those in the side edges, was not uniformly suppressed, resulting in a standard deviation exceeding 8.3 nm. Therefore, it is expected that the BDV distribution and lifetime characteristics will deteriorate as the density in the side edges decreases.

[0108] In other words, when the standard deviation is greater than or equal to 5.3 nm and less than or equal to 8.3 nm, it can be confirmed that the reliability of the multilayer electronic components has been improved.

[0109] Although exemplary embodiments of this disclosure have been described in detail above, this disclosure is not limited to the above embodiments and drawings, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, or changes without departing from the technical concept of this disclosure as defined by the appended claims, and such substitutions, modifications, or changes should be construed as being included in the technical concept of this disclosure.

[0110] Furthermore, the expression "example embodiment" as used in this disclosure does not imply the same embodiment and is provided to emphasize and explain different unique features. However, the example embodiments presented above do not preclude implementation in combination with features of another embodiment. For example, although items described in a particular example embodiment are not described in another example embodiment, these items may be understood as descriptions relating to another example embodiment, unless the other example embodiment has descriptions that contradict or contradict these items.

[0111] In this disclosure, the term "connection" encompasses not only direct connections but also indirect connections such as those via adhesive layers. Furthermore, the term "electrical connection" includes both physical and non-physical connections. Additionally, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

Claims

1. A multilayer electronic component, comprising: The body includes a capacitor forming portion, the capacitor forming portion including a dielectric layer and an inner electrode alternately disposed with the dielectric layer in a first direction, the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in the third direction; External electrodes are disposed on each of the third and fourth surfaces; as well as The side edge portion is disposed on each of the fifth and sixth surfaces and includes a plurality of dielectric grains. Wherein, each of the M cross-sections of the side edge portion in the first direction and the third direction is located at a different position in the second direction, where M is an integer greater than or equal to 2. Each of the M cross sections comprises N regions, where N is an integer greater than or equal to 2. In each of the M cross sections, each of the N regions is located at a different position in the first direction. The plurality of dielectric grains in each of the N regions of the M cross sections have an average size, and The standard deviation of the average size of the multiple dielectric grains in the total M×N regions of the M cross sections is greater than or equal to 5.3 nm and less than or equal to 8.3 nm.

2. The multilayer electronic component according to claim 1, wherein, The M sections include a first section cut at 1 / 10 of the length of the side edge in the second direction, a second section cut at 1 / 4 of the length of the side edge in the second direction, and a third section cut at 1 / 2 of the length of the side edge in the second direction.

3. The multilayer electronic component according to claim 2, wherein, The N regions include a first region of the side edge portion, a central region of the side edge portion, and a second region of the side edge portion, and The central region of the side edge portion is disposed between the first region of the side edge portion and the second region of the side edge portion.

4. The multilayer electronic component according to claim 3, wherein, The average size of the plurality of dielectric grains measured in the central region is greater than the average size of the plurality of dielectric grains measured in the first region and / or the second region.

5. The multilayer electronic component according to claim 3, wherein, The ratio of the average size of the plurality of dielectric grains measured in the first region and / or the second region to the average size of the plurality of dielectric grains measured in the central region is greater than or equal to 0.923 and less than or equal to 0.

987.

6. The multilayer electronic component according to claim 3, wherein, The average size of the plurality of dielectric grains measured in the central region is greater than or equal to 200 nm and less than or equal to 300 nm.

7. The multilayer electronic component according to claim 3, wherein, The central region corresponds to the central region of the capacitor forming portion in the first direction. The first region corresponds to the first region of the capacitor forming portion in the first direction. The second region corresponds to the second region of the capacitor forming portion in the first direction, and The central region of the capacitor forming portion is disposed between the first region and the second region of the capacitor forming portion.

8. The multilayer electronic component according to claim 1, wherein, Each of the N regions includes 500 or more dielectric grains from the plurality of dielectric grains.

9. The multilayer electronic component according to claim 1, wherein, The side edge portion includes one or more selected from the group consisting of Dy, Y, Tb, Sc, La, Nd, Eu, Gd, Ho, Er, Yb and Lu.

10. The multilayer electronic assembly according to claim 1, wherein, The side edge portion includes one or both selected from the group consisting of Mg and Zr.

11. The multilayer electronic assembly according to claim 1, wherein, The side edge portion includes one or more selected from the group consisting of Mn, V, Cr, Fe, Ni, Co and Zn.

12. The multilayer electronic assembly according to claim 1, wherein, The side edge portion includes one or both selected from the group consisting of Si and Al.

13. A multilayer electronic component, comprising: The body includes a capacitor forming portion, the capacitor forming portion including a dielectric layer and an inner electrode alternately disposed with the dielectric layer in a first direction, the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and opposite to each other in the third direction; External electrodes are disposed on each of the third and fourth surfaces; as well as The side edge portion is disposed on each of the fifth and sixth surfaces and includes a plurality of dielectric grains. Wherein, the first cross-section of the side edge portion in the first direction and the third direction, the second cross-section of the side edge portion in the first direction and the third direction, and the third cross-section of the side edge portion in the first direction and the third direction are respectively located at 1 / 10, 1 / 4, and 1 / 2 points of the length of the side edge portion in the second direction. In the first cross-section, the average size of multiple dielectric grains measured in three first cross-sectional regions located at different positions in the first direction are defined as GS1, GS2, and GS3, respectively. In the second cross-section, the average sizes of multiple dielectric grains measured in three second cross-sectional regions located at different positions in the first direction are defined as GS4, GS5, and GS6, respectively. In the third cross section, the average sizes of multiple dielectric grains measured in three third cross section regions located at different positions in the first direction are defined as GS7, GS8, and GS9, respectively. The standard deviation of GS1 to GS9 is greater than or equal to 5.3 nm and less than or equal to 8.3 nm.

14. The multilayer electronic assembly according to claim 13, wherein, The capacitor forming section includes a first region, a second region, and a central region between the first region and the second region. The first cross-sectional region includes: a first central region corresponding to the central region of the capacitor forming portion in the first direction; a first-first region corresponding to the first region of the capacitor forming portion in the first direction; and a first-second region corresponding to the second region of the capacitor forming portion in the first direction, wherein the first central region is disposed between the first-first region and the first-second region. The second cross-sectional region includes: a second central region corresponding to the central region of the capacitor forming portion in the first direction; a second-first region corresponding to the first region of the capacitor forming portion in the first direction; and a second-second region corresponding to the second region of the capacitor forming portion in the first direction, wherein the second central region is disposed between the second-first region and the second-second region, and The third cross-sectional region includes: a third central region, corresponding to the central region of the capacitor forming portion in the first direction; a third-first region, corresponding to the first region of the capacitor forming portion in the first direction; and a third-second region, corresponding to the second region of the capacitor forming portion in the first direction, wherein the third central region is disposed between the third-first region and the third-second region.

15. The multilayer electronic assembly according to claim 13, wherein, GS1 to GS9 satisfy one or more of the following: GS2 > GS1, GS2 > GS3, GS5 > GS4, GS5 > GS6, GS8 > GS7, and GS8 > GS9.

16. The multilayer electronic assembly according to claim 13, wherein, The side edge portion includes Ti and Mg, wherein the amount of Mg in the side edge portion is greater than or equal to 0.1 mol and less than or equal to 3.0 mol relative to 100 mol of Ti.

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