Multilayer ceramic capacitor

Abstract

This invention provides a multilayer ceramic capacitor that is less prone to tilting and can be mounted stably when mounted vertically. [Solution] The multilayer ceramic capacitor 10 is a laminate 12 consisting of a first surface 12a and a second surface 12b opposite to the stacking direction x, and a third surface 12c and a fourth surface 12d, a fifth surface 12e and a sixth surface 12f opposite to each other in directions y and z perpendicular to the stacking direction, respectively. The third to sixth surfaces are provided with first to fourth external electrodes 30a to 30d formed thereon, and the first and second external electrodes have first and second folded portions 30a2 that wrap around to the fifth surface and the sixth surface, respectively. The fifth surface is positioned on the substrate mounting side. The first and second folded portions on the fifth surface each have first and second maximum thickness points, which are the regions with the greatest thickness, and the third external electrode has a third maximum thickness point, which is the region with the greatest thickness. The shortest distance between the line connecting the first maximum thickness point and the second maximum thickness point and the third maximum thickness point is 50 μm or more.

Description

Technical Field

[0001] This invention relates to a multilayer ceramic capacitor.

Background Art

[0002] A decoupling capacitor used to stabilize the power supply voltage supplied to an integrated circuit component (IC) operating at high speed, and a through-type multilayer ceramic capacitor is known as a noise countermeasure component for a power supply line. The through-type multilayer ceramic capacitor generally includes a ceramic substrate (dielectric body) having an outer surface composed of a first and a second main surfaces facing each other, a first and a second side surfaces facing each other, and a first and a second end surfaces facing each other. Inside the ceramic substrate, a plurality of first internal electrodes and second internal electrodes are alternately arranged in the stacking direction. The two ends of the first internal electrode are led out to the first end surface and the second end surface, and are connected to the first and second external electrodes located on both end surfaces, respectively. The two ends of the second internal electrode are led out to the first side surface and the second side surface, and are connected to the third and fourth external electrodes located on both side surfaces, respectively.

[0003] In recent years, it has become difficult to secure space for mounting a through-type multilayer ceramic capacitor on a circuit board due to the miniaturization of electronic devices. Therefore, in order to reduce the mounting area, in a through-type multilayer ceramic capacitor in which the length in the stacking direction is smaller than the length in the height direction, there are cases where it is vertically mounted so that the first side surface or the second side surface is arranged on the circuit board side.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when mounting through-type multilayer ceramic capacitors vertically, the chip may be mounted at an angle due to the height relationship between the external electrodes located on the side and the folded portion of the external electrodes located on the end face.

[0006] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can be mounted stably and without tilting when mounted on a mounting substrate. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to this invention includes a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and comprises a laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, a first internal electrode layer disposed on the plurality of dielectric layers and drawn out to the third surface and the fourth surface, and a second internal electrode layer disposed on the plurality of dielectric layers and drawn out to the fifth surface and the sixth surface The device comprises an electrode layer, a first external electrode positioned on a third surface and connected to a first internal electrode layer, a second external electrode positioned on a fourth surface and connected to the first internal electrode layer, a third external electrode positioned on a fifth surface and connected to a second internal electrode layer, and a fourth external electrode positioned on a sixth surface and connected to a second internal electrode layer, wherein the first external electrode has a first folded portion that wraps around a part of the fifth surface and a part of the sixth surface, and the second external electrode has a second folded portion that wraps around a part of the fifth surface and a part of the sixth surface. A multilayer ceramic capacitor in which the fifth or sixth surface is positioned on the substrate mounting side, wherein the first external electrode has a first maximum thickness point which is the region with the greatest thickness in the second direction of the first folded portion located on the fifth surface, the second external electrode has a second maximum thickness point which is the region with the greatest thickness in the second direction of the second folded portion located on the fifth surface, and the third external electrode has a third maximum thickness point which is the region with the greatest thickness in the second direction of the third external electrode, and the first folded portion The shortest distance between the line connecting the maximum thickness point of the first external electrode and the second maximum thickness point of the second folded portion, and the third maximum thickness point of the third external electrode located on the first or second surface side in the stacking direction, is 50 μm or more, and / or the first external electrode has a first maximum thickness point which is the region with the greatest thickness in the second direction of the first folded portion located on the sixth surface, and the second external electrode has a second maximum thickness point which is the region with the greatest thickness in the second direction of the second folded portion located on the sixth surface, and the fourth external electrode isThis is a multilayer ceramic capacitor having a fourth maximum thickness point, which is the region with the greatest thickness in the second direction of the fourth external electrode, and the shortest distance between the line connecting the first maximum thickness point of the first folded portion and the second maximum thickness point of the second folded portion and the fourth maximum thickness point of the fourth external electrode located on the first or second surface side in the stacking direction is 50 μm or more.

[0008] According to the multilayer ceramic capacitor of this invention, the first external electrode has a first maximum thickness point, which is the region with the greatest thickness in the second direction of the first folded portion located on the fifth surface; the second external electrode has a second maximum thickness point, which is the region with the greatest thickness in the second direction of the second folded portion located on the fifth surface; the third external electrode has a third maximum thickness point, which is the region with the greatest thickness in the second direction of the third external electrode; and the shortest distance between the line connecting the first maximum thickness point of the first folded portion and the second maximum thickness point of the second folded portion and the third maximum thickness point of the third external electrode located on the first surface side or the second surface side in the stacking direction is 50 μm or more. Therefore, when the mounting surface side is the fifth surface side, three maximum thickness points are arranged, which makes it relatively easy to mount the multilayer ceramic capacitor on a mounting substrate, thus enabling stable mounting. Furthermore, according to the multilayer ceramic capacitor of this invention, the first external electrode has a first maximum thickness point, which is the region with the greatest thickness in the second direction of the first folded portion located on the sixth surface; the second external electrode has a second maximum thickness point, which is the region with the greatest thickness in the second direction of the second folded portion located on the sixth surface; the fourth external electrode has a fourth maximum thickness point, which is the region with the greatest thickness in the second direction of the fourth external electrode; and the shortest distance between the line connecting the first maximum thickness point of the first folded portion and the second maximum thickness point of the second folded portion and the fourth maximum thickness point of the fourth external electrode located on the first surface side or the second surface side in the stacking direction is 50 μm or more. Therefore, when the mounting surface side is the sixth surface side, three maximum thickness points are arranged, which makes it relatively easy to mount the multilayer ceramic capacitor on a mounting substrate, thus enabling stable mounting. [Effects of the Invention]

[0009] According to this invention, it is possible to provide a multilayer ceramic capacitor that can be mounted on a mounting substrate in a way that makes it less likely to tilt and allows for stable mounting.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is an external perspective view showing an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of this invention. [Figure 2] This is a bottom view showing an example of a multilayer ceramic capacitor according to the first embodiment of this invention. [Figure 3] This is a top view showing an example of a multilayer ceramic capacitor according to the first embodiment of this invention. [Figure 4]It is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 5] It is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 6] It is a cross-sectional view taken along line VI-VI of FIG. 4. [Figure 7] It is a cross-sectional view taken along line VII-VII of FIG. 4. [Figure 8] It is a cross-sectional view taken along line VIII-VIII of FIG. 5. [Figure 9] It is a cross-sectional view taken along line IX-IX of FIG. 5. [Figure 10] It is an external perspective view showing a multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 11] It is a bottom view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 12] It is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 13] It is a right side view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 14] It is a schematic cross-sectional view taken along line XIV-XIV related to FIG. 11. [Figure 15] It is a schematic cross-sectional view taken along line XV-XV related to FIG. 11. [Figure 16] It is a schematic cross-sectional view taken along line XVI-XVI related to FIG. 12. [Figure 17] It is a schematic cross-sectional view taken along line XVII-XVII related to FIG. 12. [Figure 18] It is a perspective view showing the arrangement state of the internal electrode layers inside the laminate of a multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 19] It is an explanatory view showing the method of measuring the amount of inclination of each sample in the experimental example.

Embodiments for Carrying Out the Invention

[0012] 1. Multilayer ceramic capacitor The multilayer ceramic capacitor according to the embodiment of the present invention will be described. The multilayer ceramic capacitor 10 is a through-type multilayer ceramic capacitor (a 3-terminal multilayer ceramic capacitor).

[0013] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of the present invention. FIG. 2 is a bottom view showing an example of the multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a top view showing an example of the multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a front view showing an example of the multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 5 is a side view showing an example of the multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 5.

[0014] As shown in FIGS. 1 to 9, the multilayer ceramic capacitor 10 includes, for example, a laminate 12 and external electrodes 30.

[0015] The laminate 12 has a plurality of dielectric layers 14 laminated thereon and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0016] The laminate 12 has a first surface 12a and a second surface 12b facing each other in the lamination direction x, a third surface 12c and a fourth surface 12d facing each other in a first direction y orthogonal to the lamination direction x, and a fifth surface 12e and a sixth surface 12f facing each other in a second direction z orthogonal to the lamination direction x and the first direction y.

[0017] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f may have irregularities or other features formed on them.

[0018] The laminate 12 includes a volume-forming portion 18, and a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged to sandwich the volume-forming portion 18 in the stacking direction x.

[0019] In the capacitance forming section 18, a first internal electrode layer 16a and a second internal electrode layer 16b are alternately stacked via a dielectric layer 14.

[0020] The first outer layer 20a is located on the first surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The second outer layer 20b is located on the second surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. Furthermore, the region sandwiched between the first outer layer 20a and the second outer layer 20b is the capacitance forming portion 18.

[0021] The volume-forming section 18 is positioned in the center of the stacking direction x. More specifically, in the stacking direction x connecting the first surface 12a and the second surface 12b, the center position of the laminate 12 and the center position of the volume-forming section 18 are approximately the same.

[0022] As shown in Figure 7, the laminate 12 is located between the capacitance forming portion 18 and the fifth surface 12e, and between the capacitance forming portion 18 and the sixth surface 12f, and has side regions (W gaps) 22a and 22b of the laminate 12, including the first extension portion 28a and the second extension portion 28b of the second internal electrode layer 16b.

[0023] Furthermore, as shown in Figure 6, the laminate 12 is located between the volume-forming portion 18 and the third surface 12c, and between the volume-forming portion 18 and the fourth surface 12d, and has end regions (L gaps) 24a, 24b of the laminate 12 that include the first lead portion 26a and the second lead portion 26b of the first internal electrode layer 16a.

[0024] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0025] The thickness of the dielectric layer 14 is preferably 0.30 μm or more and 1.00 μm or less. Furthermore, the number of dielectric layers 14 to be stacked is preferably 100 or more and 1000 or less. Note that this number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the capacitance forming section 18 and the number of dielectric layers 14 in the first outer layer section 20a and the second outer layer section 20b.

[0026] (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b.

[0027] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14. The first internal electrode layer 16a is also drawn out to the third surface 12c and the fourth surface 12d.

[0028] More specifically, as shown in Figure 8, the first internal electrode layer 16a extends between the third surface 12c and the fourth surface 12d of the laminate 12 and has a first opposing portion 25a located in its central part, a first leading portion 26a extending from the first opposing portion 25a and leading out to the third surface 12c of the laminate 12, and a second leading portion 26b extending from the first opposing portion 25a and leading out to the fourth surface 12d of the laminate 12. The first opposing portion 25a is located in the central part of the dielectric layer 14. The first leading portion 26a is exposed to the third surface 12c of the laminate 12, and the second leading portion 26b is exposed to the fourth surface 12d of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the fifth surface 12e and the sixth surface 12f of the laminate 12.

[0029] The shape of the first internal electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. Similarly, the shapes of the first opposing portion 25a, the first leading portion 26a, and the second leading portion 26b of the first internal electrode layer 16a are not particularly limited, but they are preferably rectangular in plan view. However, the corners may be rounded.

[0030] The second internal electrode layer 16b is arranged on a plurality of dielectric layers 14. Furthermore, the second internal electrode layer 16b is extended to the fifth surface 12e and the sixth surface 12f. The second internal electrode layer 16b is arranged on a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged.

[0031] More specifically, as shown in Figure 9, the second internal electrode layer 16b extends between the fifth surface 12e and the sixth surface 12f of the laminate 12 and has a second opposing portion 25b located in its central part, a first extension portion 28a extending from the second opposing portion 25b and drawn out to the fifth surface 12e, and a second extension portion 28b extending from the second opposing portion 25b and drawn out to the sixth surface 12f. The second opposing portion 25b is formed in a rectangular shape so as to extend in the direction of the third surface 12c and the direction of the fourth surface 12d. The second opposing portion 25b is located in the central part of the dielectric layer 14. The first extension portion 28a is exposed to the fifth surface 12e of the laminate 12, and the second extension portion 28b is exposed to the sixth surface 12f of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed to the third surface 12c and the fourth surface 12d of the laminate 12.

[0032] The shapes of the second opposing portion 25b, the first extension portion 28a, and the second extension portion 28b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded.

[0033] The first opposing portion 25a of the first internal electrode layer 16a and the second opposing portion 25b of the second internal electrode layer 16b are facing each other. In this embodiment, the first opposing portion 25a of the first internal electrode layer 16a and the second opposing portion 25b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0034] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 50 to 500. Similarly, the number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 50 to 500. Therefore, the combined number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 100 to 1000.

[0035] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.20 μm or more and 0.80 μm or less. Similarly, the thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.20 μm or more and 0.80 μm or less.

[0036] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys. Furthermore, by including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0037] (external electrode) External electrodes 30 are arranged on the third surface 12c and the fourth surface 12d, as well as the fifth surface 12e and the sixth surface 12f of the laminate 12. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0038] The first external electrode 30a is positioned on the third surface 12c side. The first external electrode 30a is also connected to the first internal electrode layer 16a. The first external electrode 30a is positioned on the third surface 12c and has a first covering portion 30a1 that covers the first internal electrode layer 16a exposed on the third surface 12c, and a first folded portion 30a2 that extends from the first covering portion 30a1 and is also positioned on a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0039] The second external electrode 30b is positioned on the fourth surface 12d. The second external electrode 30b is also connected to the first internal electrode layer 16a. The second external electrode 30b is positioned on the fourth surface 12d and has a second covering portion 30b1 that covers the first internal electrode layer 16a exposed on the fourth surface 12d, and a second folded portion 30b2 that extends from the second covering portion 30b1 and is also positioned on a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0040] The third external electrode 30c is positioned on the fifth surface 12e. The third external electrode 30c is also connected to the second internal electrode layer 16b. The third external electrode 30c has a third covering portion 30c1 that covers the second internal electrode layer 16b exposed on the fifth surface 12e, and a third folded portion 30c2 that extends from the third covering portion 30c1 and is formed parallel to the second internal electrode layer 16b on the first surface 12a and the second surface 12b. The third external electrode 30c does not necessarily have to have the third folded portion 30c2.

[0041] The fourth external electrode 30d is positioned on the sixth surface 12f. The fourth external electrode 30d is also connected to the second internal electrode layer 16b. Furthermore, the fourth external electrode 30d has a fourth covering portion 30d1 that covers the second internal electrode layer 16b exposed on the sixth surface 12f, and a fourth folded portion 30d2 that extends from the fourth covering portion 30d1 and is formed parallel to the second internal electrode layer 16b on the first surface 12a and the second surface 12b. Note that the fourth external electrode 30d does not necessarily have to have the fourth folded portion 30d2.

[0042] In the multilayer ceramic capacitor 10, the fifth surface 12e or the sixth surface 12f of the laminate 12 is positioned on the mounting substrate as the substrate mounting side.

[0043] In the first external electrode 30a, the first folded portion 30a2 located on the fifth surface 12e side has one first maximum thickness point 30aP1, which is the region with the greatest thickness in the second direction z of the first folded portion 30a2. The first maximum thickness point 30aP1 of the first folded portion 30a2 located on the fifth surface 12e side is located approximately in the center of the first folded portion 30a2. Alternatively, in the first external electrode 30a, the first folded portion 30a2 located on the sixth surface 12f side has the other first maximum thickness point 30aP2, which is the region with the greatest thickness in the second direction z of the first folded portion 30a2. The other first maximum thickness point 30aP2 of the first folded portion 30a2 located on the sixth surface 12f side is located approximately in the center of the first folded portion 30a2.

[0044] In the second external electrode 30b, the second folded portion 30b2 located on the fifth surface 12e side has one second maximum thickness point 30bP1, which is the region with the greatest thickness in the second direction z of the second folded portion 30b2. The one second maximum thickness point 30bP1 of the second folded portion 30b2 located on the fifth surface 12e side is located approximately in the center of the second folded portion 30b2. In the second external electrode 30b, the second folded portion 30b2 located on the sixth surface 12f side has the other second maximum thickness point 30bP2, which is the region with the greatest thickness in the second direction z of the second folded portion 30b2. The other second maximum thickness point 30bP2 of the second folded portion 30b2 located on the sixth surface 12f side is located approximately in the center of the second folded portion 30b2.

[0045] The third external electrode 30c has a third maximum thickness point 30cP, which is the region with the greatest thickness in the second direction z of the third covering portion 30c1 of the third external electrode 30c located on the fifth surface 12e side. The fourth external electrode 30d has a fourth maximum thickness point 30dP, which is the region with the greatest thickness in the second direction z of the fourth covering portion 30d1 of the fourth external electrode 30d located on the sixth surface 12f side.

[0046] The third maximum thickness point 30cP of the third external electrode 30c located on the fifth surface 12e side is located on the first surface 12a side or the second surface 12b side in the stacking direction x, relative to the line m connecting the first maximum thickness point 30aP1 of the first folded portion 30a2 located on the fifth surface 12e side and the second maximum thickness point 30bP1 of the second folded portion 30b2 located on the fifth surface 12e side. Furthermore, the shortest distance d between the line m connecting one of the first maximum thickness points 30aP1 of the first folded portion 30a2 located on the fifth surface 12e side and one of the second maximum thickness points 30bP1 of the second folded portion 30b2 located on the fifth surface 12e side, and the third maximum thickness point 30cP of the third external electrode 30c located on the first surface 12a side or the second surface 12b side in the stacking direction x, is 50 μm or more. Alternatively, the fourth maximum thickness point 30dP of the fourth external electrode 30d located on the sixth surface 12f side is located on the first surface 12a side or the second surface 12b side in the stacking direction x, relative to the line m connecting the first maximum thickness point 30aP2 of the other side of the first folded portion 30a2 located on the sixth surface 12f side and the second maximum thickness point 30bP2 of the other side of the second folded portion 30b2 located on the sixth surface 12f side. Furthermore, the shortest distance d between the line m connecting the first maximum thickness point 30aP2 of the other side of the first folded portion 30a2 located on the sixth surface 12f side and the second maximum thickness point 30bP2 of the other side of the second folded portion 30b2 located on the sixth surface 12f side, and the fourth maximum thickness point 30dP of the fourth external electrode 30d located on the first surface 12a side or the second surface 12b side in the stacking direction x, is 50 μm or more.

[0047] Preferably, the maximum thickness of the third external electrode 30c and the fourth external electrode 30d in the second direction z is greater than the maximum thickness of the first folded portion 30a2 and the second folded portion 30b2 in the second direction z. Furthermore, it is preferable that the average thickness of the third external electrode 30c and the fourth external electrode 30d in the second direction z is greater than the average thickness of the first folded portion 30a2 and the second folded portion 30b2 in the second direction z.

[0048] With the above configuration, the third maximum thickness point 30cP of the third external electrode 30c, the first maximum thickness point 30aP1 of one of the first folded portion 30a2 of the first external electrode 30a, and the second maximum thickness point 30bP1 of one of the second folded portion 30b2 of the second external electrode 30b are arranged at three points. As a result, when the multilayer ceramic capacitor 10 is mounted on the mounting substrate with the fifth surface 12e as the mounting surface, the amount of tilt of the multilayer ceramic capacitor 10 can be reduced. Similarly, by arranging the fourth maximum thickness point 30dP of the fourth external electrode 30d, the first maximum thickness point 30aP2 of the other side of the first folded portion 30a2 of the first external electrode 30a, and the second maximum thickness point 30bP2 of the other side of the second folded portion 30b2 of the second external electrode 30b, the amount of tilt of the multilayer ceramic capacitor 10 can be reduced when the multilayer ceramic capacitor 10 is mounted on the mounting substrate with the sixth surface 12f as the mounting surface.

[0049] The multilayer ceramic capacitor 10 includes, on the fifth surface 12e side, a third maximum thickness point 30cP of the third external electrode 30c, a first maximum thickness point 30aP1 of one of the first folded portion 30a2 of the first external electrode 30a, and a second maximum thickness point 30bP1 of one of the second folded portion 30b2 of the second external electrode 30b; and on the sixth surface 12f side, a fourth maximum thickness point 30dP of the fourth external electrode 30d, a first maximum thickness point 30aP2 of the other of the first folded portion 30a2 of the first external electrode 30a, and a second maximum thickness point 30bP2 of the other of the second folded portion 30b2 of the second external electrode 30b; however, it is sufficient that this configuration is provided on at least one of the fifth surface 12e side and the sixth surface 12f side.

[0050] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0051] The base electrode layer 32 comprises a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0052] The plating layer 34 has a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0053] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b. The third external electrode 30c has a third base electrode layer 32c and a third plating layer 34c. The fourth external electrode 30d has a fourth base electrode layer 32d and a fourth plating layer 34d.

[0054] The first underlay electrode layer 32a is positioned on the surface of the third surface 12c of the laminate 12 and is formed to extend from the third surface 12c and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The second base electrode layer 32b is positioned on the surface of the fourth surface 12d of the laminate 12 and is formed to extend from the fourth surface 12d and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f.

[0055] The third underlay electrode layer 32c is positioned on the surface of the fifth surface 12e of the laminate 12 and is formed to extend from the fifth surface 12e and cover the second surface 12b. The fourth base electrode layer 32d is positioned on the surface of the sixth surface 12f of the laminate 12 and is formed to extend from the sixth surface 12f and cover the second surface 12b.

[0056] The base electrode layer 32 includes at least one selected from a baked layer and a conductive resin layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer and the conductive resin layer described above.

[0057] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0058] The thickness of the first underlay electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d in the central part of the lamination direction x is preferably 6 μm or more and 60 μm or less. Furthermore, the thickness of the second underlay electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x is preferably 6 μm or more and 60 μm or less.

[0059] When the first base electrode layer 32a is provided on a portion of the first surface 12a and a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the first surface 12a and the second surface 12b is preferably, for example, 10 μm or more and 50 μm or less. Furthermore, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 10 μm or more and 50 μm or less.

[0060] Furthermore, when a second base electrode layer 32b is provided on a part of the first surface 12a and a part of the second surface 12b, and a part of the fifth surface 12e and a part of the sixth surface 12f, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the first surface 12a and the second surface 12b is preferably, for example, 10 μm or more and 50 μm or less. Moreover, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 10 μm or more and 50 μm or less.

[0061] The thickness in the second direction z, which connects the fifth surface 12e and the sixth surface 12f, located on the fifth surface 12e and in the central part of the first direction y, which connects the third surface 12c and the fourth surface 12d of the third underlay electrode layer 32c, is preferably 10 μm or more and 60 μm or less. Furthermore, the thickness in the second direction z, which connects the fifth surface 12e and the sixth surface 12f, located at the center of the first direction y, which connects the third surface 12c and the fourth surface 12d of the fourth underlay electrode layer 32d, is preferably 10 μm or more and 60 μm or less.

[0062] The thickness of the third underlay electrode layer 32c located on the second surface 12b in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 5 μm or more and 25 μm or less. Furthermore, the thickness of the fourth underlay electrode layer 32d located on the second surface 12b in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 5 μm or more and 25 μm or less.

[0063] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0064] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 10.

[0065] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0066] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0067] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0068] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0069] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0070] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0071] The thickest part of the conductive resin layer is preferably, for example, 10 μm or more and 50 μm or less.

[0072] The plating layer 34 is positioned to cover the underlying electrode layer 32.

[0073] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0074] The plating layer 34 may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 10 μm or less.

[0075] The dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, in the first direction y is defined as dimension L. Dimension L is preferably 0.10 mm or more and 3.50 mm or less, and more preferably 0.40 mm or more and 2.20 mm or less. The dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, in the second direction z is defined as dimension T. Dimension T is preferably 0.07 mm or more and 3.00 mm or less, and more preferably 0.25 mm or more and 1.50 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, including the laminated body 12 and the external electrodes 30, is defined as the W dimension. The W dimension is preferably 0.05 mm or more and 2.80 mm or less, and more preferably 0.20 mm or more and 1.45 mm or less. Furthermore, in the multilayer ceramic capacitor 10, the dimension W, which is the length in the stacking direction x, is smaller than the dimension T in the second direction z.

[0076] In the multilayer ceramic capacitor 10 shown in Figure 1, the third maximum thickness point 30cP of the third external electrode 30c located on the fifth surface 12e side is located on the first surface 12a side or the second surface 12b side in the stacking direction x, relative to the line m connecting the first maximum thickness point 30aP1 of the first folded portion 30a2 located on the fifth surface 12e side and the second maximum thickness point 30bP1 of the second folded portion 30b2 located on the fifth surface 12e side, and the first maximum thickness point 30aP1 of the first folded portion 30a2 located on the fifth surface 12e side Since the shortest distance d between the line m connecting the second maximum thickness point 30bP1 of the second folded portion 30b2 located on the fifth surface 12e side and the third maximum thickness point 30cP of the third external electrode 30c located on the first surface 12a side or the second surface 12b side in the stacking direction x is 50 μm or more, when the mounting surface side is the fifth surface 12e side, three maximum thickness points are arranged, so when the multilayer ceramic capacitor 10 is mounted on the mounting substrate, the amount of tilt becomes relatively small and it becomes less prone to tilting, allowing for stable mounting.

[0077] Similarly, in the multilayer ceramic capacitor 10 shown in Figure 1, the fourth maximum thickness point 30dP of the fourth external electrode 30d located on the sixth surface 12f side is located on the first surface 12a side or the second surface 12b side in the stacking direction x, relative to the line m connecting the first maximum thickness point 30aP2 of the other side of the first folded portion 30a2 located on the sixth surface 12f side and the second maximum thickness point 30bP2 of the other side of the second folded portion 30b2 located on the sixth surface 12f side, and the fourth maximum thickness point 30dP of the other side of the first folded portion 30a2 located on the sixth surface 12f side Since the shortest distance d between the line m connecting 2 and the other second maximum thickness point 30bP2 of the second folded portion 30b2 located on the sixth surface 12f side, and the fourth maximum thickness point 30dP of the fourth external electrode 30d located on the first surface 12a side or the second surface 12b side in the stacking direction x is 50 μm or more, when the mounting surface side is the sixth surface 12f side, three maximum thickness points are arranged, so when the multilayer ceramic capacitor 10 is mounted on the mounting substrate, the amount of tilt becomes relatively small and it is less likely to tilt, allowing for stable mounting.

[0078] 2. Manufacturing method of multilayer ceramic capacitors Next, a method for manufacturing a multilayer ceramic capacitor 10 according to an embodiment of this invention will be described.

[0079] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances.

[0080] A conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it.

[0081] More specifically, a gravure printing plate can be prepared for printing the first internal electrode layer and the second internal electrode layer, and each internal electrode layer of the present invention can be printed.

[0082] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form a portion that will become the second outer layer 20b on the second surface 12b side. Then, a portion that will become the capacitance forming portion 18 is formed by alternately stacking sheets with printed first internal electrode layers and sheets with printed second internal electrode layers on the portion that will become the second outer layer 20b. The portion that will become the capacitance forming portion 18 formed by the above process is stacked on top of the portion that will become the second outer layer 20b. Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the portion that will become the capacitance forming portion 18 to form a portion that will become the first outer layer 20a on the first surface 12a side. This completes the production of the laminated sheet.

[0083] Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block.

[0084] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0085] The laminated body 12 is then fabricated by firing the cut-out laminated chips. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0086] (base electrode layer) Next, a third base electrode layer 32c of the third external electrode 30c is formed on the fifth surface 12e of the laminate 12 obtained by firing, and a fourth base electrode layer 32d of the fourth external electrode 30d is formed on the sixth surface 12f of the laminate 12.

[0087] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0088] Here, various methods can be used to form the baked layer. For example, it can be formed using the roller transfer method. In the case of the roller transfer method, when forming the base electrode layer 132 not only on the fifth surface 12e and the sixth surface 12f, but also on a part of the first surface 12a and a part of the second surface 12b, the positions of the third and fourth maximum thickness points located on the fifth surface 12e and the sixth surface 12f, respectively, can be adjusted by adjusting the pressing pressure and roller speed during roller transfer. Furthermore, by increasing the pressing pressure during roller transfer, it becomes possible to form the base electrode layer 132 on a part of the first surface 12a and a part of the second surface 12b.

[0089] Next, a first base electrode layer 32a of the first external electrode 30a is formed on the third surface 12c of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on the fourth surface 12d of the laminate 12. In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using the DIP method so as to extend not only to the third surface 12c and the fourth surface 12d, but also to a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0090] The baking process may involve baking the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d simultaneously, or the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d separately.

[0091] (Conductive resin layer) Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0092] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0093] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, for example, by extruding the conductive resin paste through a slit.

[0094] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer, and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0095] As described above, the multilayer ceramic capacitor 10 according to the first embodiment is manufactured.

[0096] B. Second Embodiment 1. Multilayer ceramic capacitor An example of a multilayer ceramic capacitor 110 according to a second embodiment of this invention will be described.

[0097] Figure 10 is an external perspective view showing a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 11 is a bottom view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 12 is a front view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 13 is a right side view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 14 is a schematic cross-sectional view along line XIV-XIV in Figure 11. Figure 15 is a schematic cross-sectional view along line XV-XV in Figure 11. Figure 16 is a schematic cross-sectional view along line XVI-XVI in Figure 12. Figure 17 is a schematic cross-sectional view along line XVII-XVII in Figure 12. Figure 18 is a transparent perspective view showing the arrangement of the internal electrode layers inside the laminate of a multilayer ceramic capacitor according to a second embodiment of the present invention.

[0098] As shown in Figures 10 to 17, the multilayer ceramic capacitor 110 includes, for example, a laminate 112 and an external electrode 130.

[0099] The laminate 112 has a plurality of stacked dielectric layers 114 and a plurality of internal electrode layers 116 stacked on the dielectric layers 114. The internal electrode layers 116 have a first internal electrode layer 116a and a second internal electrode layer 116b. Details of the first internal electrode layer 116a and the second internal electrode layer 116b will be described later.

[0100] The laminate 112 has a first surface 112a and a second surface 112b that are opposite to the stacking direction x, a third surface 112c and a fourth surface 112d that are opposite to a first direction y that is perpendicular to the stacking direction x, and a fifth surface 112e and a sixth surface 112f that are opposite to a second direction z that is perpendicular to both the stacking direction x and the first direction y.

[0101] The laminate 112 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 112 are rounded. The corners are the parts where three faces of the laminate 112 intersect, and the edges are the parts where two faces of the laminate 112 intersect. In addition, some or all of the first face 112a and the second face 112b, the third face 112c and the fourth face 112d, and the fifth face 112e and the sixth face 112f may have irregularities or other features formed on them.

[0102] The laminate 112 includes a volume-forming portion 118, and a first outer layer portion 120a located on the first surface 112a side and a second outer layer portion 120b located on the second surface 112b side, which are arranged to sandwich the volume-forming portion 118 in the stacking direction x.

[0103] In the capacitance forming section 118, a first internal electrode layer 116a and a second internal electrode layer 116b are alternately stacked via a dielectric layer 114.

[0104] The first outer layer 120a is located on the first surface 112a side of the laminate 112 and is an assembly of multiple dielectric layers 114 located between the first surface 112a and the capacitance forming portion 118 closest to the first surface 112a. The second outer layer 120b is located on the second surface 112b side of the laminate 112 and is an assembly of multiple dielectric layers 114 located between the second surface 112b and the capacitance forming portion 118 closest to the second surface 112b. Furthermore, the region sandwiched between the first outer layer 120a and the second outer layer 120b is the capacitance forming portion 118.

[0105] As shown in Figure 15, the laminate 112 is located between the volume-forming portion 118 and the fifth surface 112e and has a side region 122a including the first lead portion 126a of the first internal electrode layer 116a and the second lead portion 128a and third lead portion 128b of the second internal electrode layer 16b, and a side region 122b located between the volume-forming portion 118 and the sixth surface 112f.

[0106] Furthermore, as shown in Figure 14, the laminate 112 has end regions 124a and 124b located between the volume-forming portion 118 and the third surface 112c, and between the volume-forming portion 118 and the fourth surface 112d.

[0107] The dielectric layer 114 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0108] The thickness of the dielectric layer 114 is preferably 0.30 μm or more and 1.00 μm or less. Furthermore, the number of dielectric layers 114 to be stacked is preferably 100 or more and 1000 or less. This number of dielectric layers 114 is the sum of the number of dielectric layers 14 in the capacitance forming section 118 and the number of dielectric layers 114 in the first outer layer section 120a and the second outer layer section 120b.

[0109] (Internal electrode layer) The internal electrode layer 116 has a first internal electrode layer 116a and a second internal electrode layer 116b.

[0110] The first internal electrode layer 116a is arranged on a plurality of dielectric layers 114. The first internal electrode layer 116a is also drawn out to a fifth surface 112e.

[0111] More specifically, as shown in Figure 16, the first internal electrode layer 116a has a first opposing portion 125a facing the second internal electrode layer 116b, and a first leading portion 126a extending from the first opposing portion 125a and leading out to the fifth surface 112e. The first opposing portion 125a is located in the central part of the dielectric layer 114. The first leading portion 126a is exposed to the fifth surface 112e of the laminate 112. Therefore, the first internal electrode layer 116a is not exposed to the third surface 112c, the fourth surface 112d, and the sixth surface 112f of the laminate 112. The shape of the first opposing portion 125a and the shape of the first leading portion 126a are not particularly limited, but are preferably rectangular. However, the corners of the first opposing portion 125a may be rounded.

[0112] As shown in Figure 17, the second internal electrode layer 116b has a second opposing portion 125b facing the first internal electrode layer 116a, and second and third leading portions 128a and 128b extending from the second opposing portion 126b and leading out to the fifth surface 112e. The second opposing portion 125b is located in the central part of the dielectric layer 114. The second leading portion 128a is exposed to the fifth surface 112e on the third surface 112c side. The third leading portion 128b is exposed to the fifth surface 112e on the fourth surface 112d side. Therefore, the second internal electrode layer 116b is not exposed to the third surface 112c, the fourth surface 112d, and the sixth surface 112f of the laminate 112. The shape of the second opposing portion 125b, the second and third drawer portions 128a and 128b is not particularly limited, but is preferably rectangular. However, the corners of the second opposing portion 125b may be rounded.

[0113] The first opposing portion 125a of the first internal electrode layer 116a and the second opposing portion 125b of the second internal electrode layer 116b are facing each other. In this embodiment, the first opposing portion 125a of the first internal electrode layer 116a and the second opposing portion 125b of the second internal electrode layer 116b face each other via the dielectric layer 114, thereby forming capacitance and exhibiting capacitor characteristics.

[0114] The number of first internal electrode layers 116a is not particularly limited, but is preferably, for example, 50 to 500. Similarly, the number of second internal electrode layers 116b is not particularly limited, but is preferably, for example, 50 to 500. Therefore, the combined number of first internal electrode layers 116a and second internal electrode layers 116b is preferably 100 to 1000.

[0115] The thickness of the first internal electrode layer 116a is not particularly limited, but is preferably, for example, 0.20 μm or more and 0.80 μm or less. Similarly, the thickness of the second internal electrode layer 116b is not particularly limited, but is preferably, for example, 0.20 μm or more and 0.80 μm or less.

[0116] The first internal electrode layer 116a and the second internal electrode layer 116b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0117] Furthermore, by including a Sn layer between the first internal electrode layer 116a and the second internal electrode layer 116b and the dielectric layer 114, electric field concentration at the interface between the internal electrode layer 116 and the dielectric layer 114 can be mitigated, leading to improved high-temperature load reliability.

[0118] (external electrode) The external electrode 130 has a first external electrode 130a, a second external electrode 130b, and a third external electrode 130c.

[0119] The first external electrode 130a is positioned on the fifth surface 112e. The first external electrode 130a is also connected to the first lead-out portion 126a of the first internal electrode layer 116a. Furthermore, the first external electrode 130a may have a first covering portion 130a1 that covers the first lead-out portion 126a of the first internal electrode layer 116a that is exposed on the fifth surface 112e, and a first folded portion 130a2 that extends from the first covering portion 130a1 and is formed parallel to the first internal electrode layer 116a on the first surface 112a and the second surface 112b.

[0120] The second external electrode 130b is positioned on the fifth surface 112e. The second external electrode 130b is also connected to the second lead portion 128a of the second internal electrode layer 116b. Furthermore, the second external electrode 130b has a second covering portion 130b1 that covers the second lead portion 128a of the second internal electrode layer 116b that is exposed on the fifth surface 112e, and a second folded portion 130b2 that extends from the second covering portion 130b1 and is positioned on a part of the first surface 112a, a part of the second surface 112b, and a part of the third surface 112c.

[0121] The third external electrode 130c is positioned on the fifth surface 112e. The third external electrode 130c is also connected to the third lead-out portion 128b of the second internal electrode layer 116b. Furthermore, the third external electrode 130c has a third covering portion 130c1 that covers the third lead-out portion 128b of the second internal electrode layer 116b that is exposed on the fifth surface 112e, and a third folded portion 130c2 that extends from the third covering portion 130c1 and is positioned on a part of the first surface 112a, a part of the second surface 112b, and a part of the fourth surface 112d.

[0122] In the multilayer ceramic capacitor 110, the fifth surface 112e of the laminate 112 is positioned on the mounting substrate as the substrate mounting side.

[0123] The first external electrode 130a has a first maximum thickness point 130aP, which is the region with the greatest thickness in the second direction z of the first external electrode 130a located on the fifth surface 12e side.

[0124] The second external electrode 130b has a second maximum thickness point 130bP, which is the region with the greatest thickness in the second direction z of the second external electrode 130b located on the fifth surface 12e side.

[0125] The third external electrode 130c has a third maximum thickness point 130cP, which is the region with the greatest thickness in the second direction z of the third external electrode 130c located on the fifth surface 12e side.

[0126] The first maximum thickness point 130aP of the first external electrode 130a is located on the side of either the first surface 112a or the second surface 112b in the stacking direction x, relative to the line m connecting the second maximum thickness point 130bP of the second external electrode 130b and the third maximum thickness point 130cP of the third external electrode 130c. The shortest distance d between the line m connecting the second maximum thickness point 130bP of the second external electrode 130b and the third maximum thickness point 130cP of the third external electrode 130c, and the first maximum thickness point 130aP of the first external electrode 130a, which is located on the side of either the first surface 112a or the second surface 112b in the stacking direction x, is 50 μm or more.

[0127] The second maximum thickness point 130bP of the second external electrode 130b is located approximately in the center of the second external electrode 130b, which is on the fifth surface 112e side. The third maximum thickness point 130cP of the third external electrode 130c is located approximately in the center of the third external electrode 130c, which is on the fifth surface 112e side.

[0128] Preferably, the maximum thickness of the first external electrode 130a in the second direction z is greater than the maximum thickness of the second external electrode 130b and the third external electrode 130c in the second direction z. Preferably, the average thickness of the first external electrode 130a in the second direction z is greater than the average thickness of the second external electrode 130b and the third external electrode 130c in the second direction z.

[0129] The external electrode 130 includes a base electrode layer 132 placed on the surface of the laminate 112 and a plating layer 134 placed so as to cover the base electrode layer 132.

[0130] The base electrode layer 132 has a first base electrode layer 132a, a second base electrode layer 132b, and a third base electrode layer 132c.

[0131] The plating layer 134 has a first plating layer 134a, a second plating layer 134b, and a third plating layer 34c.

[0132] In other words, the first external electrode 130a has a first base electrode layer 132a and a first plating layer 134a. The second external electrode 130b has a second base electrode layer 132b and a second plating layer 134b. The third external electrode 130c has a third base electrode layer 132c and a third plating layer 134c.

[0133] The first underlay electrode layer 132a is positioned on the surface of the fifth surface 112e of the laminate 112 and is formed to extend from the fifth surface 112e and cover a portion of the first surface 112a and the second surface 112b, respectively. The second underlay electrode layer 132b is positioned on the surface of the fifth surface 112e of the laminate 112 and is formed to extend from the fifth surface 112e and cover a portion of the first surface 112a, the second surface 112b, and the third surface 112c, respectively. The third underlay electrode layer 132c is positioned on the surface of the fifth surface 112e of the laminate 112 and is formed to extend from the fifth surface 112e and cover a portion of the first surface 112a, the second surface 112b, and the fourth surface 112d, respectively.

[0134] The base electrode layer 132 includes at least one selected from a baked layer and a conductive resin layer, etc. The following describes the configurations when the base electrode layer 132 is the baked layer and the conductive resin layer described above.

[0135] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 112 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 116 and the dielectric layer 114 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 116 and the dielectric layer 114 to obtain the laminate 112, and then applying the conductive paste to the laminate 112 and baking it. Furthermore, when the baked layer is formed by simultaneously baking a laminated chip having an internal electrode layer 116 and a dielectric layer 114 and a conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material with a dielectric material added instead of a glass component.

[0136] In the first base electrode layer 132a located on the fifth surface 112e and extending in the lamination direction x at the center of the first direction y connecting the third surface 112c and the fourth surface 112d, the thickness in the second direction z connecting the fifth surface 112e and the sixth surface 112f is preferably 10 μm or more and 60 μm or less. In the second base electrode layer 132b located on the fifth surface 112e and extending in the lamination direction x at one end of the first direction y connecting the third surface 112c and the fourth surface 112d, the thickness in the second direction z connecting the fifth surface 112e and the sixth surface 112f is preferably 10 μm or more and 60 μm or less. In the third base electrode layer 132c located on the fifth surface 112e and extending in the lamination direction x at the other end of the first direction y connecting the third surface 112c and the fourth surface 112d, the thickness in the second direction z connecting the fifth surface 112e and the sixth surface 112f is preferably 10 μm or more and 60 μm or less.

[0137] Furthermore, the thickness in the lamination direction x connecting the first surface 112a and the second surface 112b at the center of the first underlay electrode layer 132a of the first folded portion 130a2 located in a part of the first surface 112a and a part of the second surface 112b, in the first direction y connecting the third surface 112c and the fourth surface 112d, is preferably, for example, 3 μm or more and 10 μm or less. The thickness of the second base electrode layer 132b of the second folded portion 130b2, located in a part of the first surface 112a and a part of the second surface 112b, in the lamination direction x connecting the first surface 112a and the second surface 112b at the center of the first direction y connecting the third surface 112c and the fourth surface 112d, is preferably, for example, 3 μm or more and 10 μm or less. The thickness of the third base electrode layer 132c of the third folded portion 130c2, located in a part of the first surface 112a and a part of the second surface 112b, in the lamination direction x connecting the first surface 112a and the second surface 112b at the center of the first direction y connecting the third surface 112c and the fourth surface 112d, is preferably, for example, 3 μm or more and 10 μm or less.

[0138] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 112 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0139] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 110 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 110.

[0140] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0141] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0142] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0143] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0144] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0145] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0146] The thickest part of the conductive resin layer is preferably, for example, 10 μm or more and 60 μm or less.

[0147] The plating layer 134 is positioned to cover the underlying electrode layer 132.

[0148] The plating layer 134 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0149] The plating layer 134 may be formed from multiple layers. In this case, the plating layer 134 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 132 from being corroded by the solder when mounting the multilayer ceramic capacitor 110. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 110, thereby facilitating mounting. The thickness of each layer of the plating layer 134 is preferably 1 μm or more and 6 μm or less.

[0150] The dimension of the multilayer ceramic capacitor 110, including the laminate 112 and the external electrode 130, in the first direction y is defined as dimension L. Dimension L is preferably 0.10 mm or more and 3.50 mm or less, and more preferably 0.40 mm or more and 2.20 mm or less. The dimension of the multilayer ceramic capacitor 110, including the laminate 112 and the external electrode 130, in the second direction z is defined as dimension T. Dimension T is preferably 0.07 mm or more and 3.00 mm or less, and more preferably 0.25 mm or more and 1.50 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 110, including the laminated body 112 and the external electrode 130, is defined as the W dimension. The W dimension is preferably 0.05 mm or more and 2.80 mm or less, and more preferably 0.20 mm or more and 1.45 mm or less. Furthermore, in the multilayer ceramic capacitor 110, the dimension W, which is the length in the stacking direction x, is smaller than the dimension T in the second direction z.

[0151] Furthermore, in the multilayer ceramic capacitor 110 shown in Figure 10, the first maximum thickness point 130aP of the first external electrode 130a is located on the side of the first surface 112a or the second surface 112b in the stacking direction x, relative to the line m connecting the second maximum thickness point 130bP of the second external electrode 130b and the third maximum thickness point 130cP of the third external electrode 130c. Furthermore, the shortest distance d between the line m connecting the second maximum thickness point 130bP of the second external electrode 130b and the third maximum thickness point 130cP of the third external electrode 130c, and the first maximum thickness point 130aP of the first external electrode 130a located on the first surface 112a side or the second surface 112b side in the stacking direction x, is 50 μm or more. Therefore, with the mounting surface on the fifth surface 112e side, the three maximum thickness points are arranged, which means that when mounting the multilayer ceramic capacitor 110 onto the mounting substrate, the amount of tilt becomes relatively small and it becomes less prone to tilting, allowing for stable mounting.

[0152] 2. Manufacturing method of multilayer ceramic capacitors Next, we will explain the manufacturing method of this multilayer ceramic capacitor. The manufacturing method of the multilayer ceramic capacitor 110 will be described below.

[0153] First, prepare the dielectric sheet and the conductive paste for the internal electrodes. The ceramic green sheet and the conductive paste for the internal electrodes contain a binder (e.g., a known organic binder) and a solvent (e.g., an organic solvent).

[0154] Next, a conductive paste for internal electrodes is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer formed on it and a dielectric sheet with the pattern of the second internal electrode layer formed on it.

[0155] More specifically, a gravure printing plate can be prepared for printing the first internal electrode layer and the second internal electrode layer, and each internal electrode layer of the present invention can be printed.

[0156] Here, a portion that will form a capacitance-forming area is formed by alternately stacking dielectric sheets on which a first internal electrode layer and a second internal electrode layer are printed, in order to obtain the desired structure.

[0157] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second outer layer portion 120b on the second surface 112b side. Subsequently, the portion that will become the capacitance forming portion 118, formed by the above process, is stacked on top of the portion that will become the second outer layer portion 20b. Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of the portion that will become the capacitance forming portion 118 to form the first outer layer portion 120a on the first surface 112a side. This completes the production of the laminated sheet.

[0158] Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block.

[0159] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0160] The cut laminated chips are then fired to produce the laminated body 112. The firing temperature depends on the materials of the dielectric layer 114 and the internal electrode layer 116, but is preferably between 900°C and 1400°C.

[0161] (base electrode layer) Next, the first base electrode layer 132a of the first external electrode 130a, the second base electrode layer 132b of the second external electrode 130b, and the third base electrode layer 132c of the third external electrode 130c are formed on the fifth surface 112e of the laminate 112 obtained by firing.

[0162] When forming a baked layer as the base electrode layer 132, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 132. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 132 is formed of a baked layer.

[0163] Here, the baking layer can be formed using a roller transfer method. When forming the base electrode layer 132 of the first external electrode not only on the fifth surface 112e but also on a portion of the first surface 112a and a portion of the second surface 112b using the roller transfer method, the position of the first maximum thickness point located on the fifth surface 112e can be adjusted by adjusting the pressing pressure and roller speed during roller transfer. Furthermore, by increasing the pressing pressure during roller transfer, it becomes possible to form the base electrode layer 132 on a portion of the first surface 112a and a portion of the second surface 112b. In addition, for the second and third external electrodes, the base electrode layer 132 can be formed on a portion of the third surface 112c and a portion of the fourth surface 112d by adjusting the position and size of the roller grooves for transferring the conductive paste.

[0164] (Conductive resin layer) Furthermore, when the base electrode layer 132 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 112 by itself without forming a baking layer.

[0165] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baked layer or onto the laminate 112, and then heat-treating it at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0166] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 132 with a baked layer, such as a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0167] As described above, the multilayer ceramic capacitor 110 according to the second embodiment is manufactured.

[0168] C. Experimental Examples Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention as described above, multilayer ceramic capacitors were manufactured as experimental samples, and the tilt amount after mounting was measured for each sample.

[0169] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experimental example Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors were fabricated from the samples of the comparative example and Examples 1 to 8. • Structure of multilayer ceramic capacitor: 3 terminals (see Figure 1) • Dimensions (L) of the multilayer ceramic capacitor: 1.22 mm • Dimensions of the multilayer ceramic capacitor (W): 0.92mm • Dimensions (T) of the multilayer ceramic capacitor: 0.48mm • Dielectric thickness of the capacitance-forming area: 0.48 μm • Thickness of the first and second internal electrode layers: 0.40 μm • Number of first internal electrode layers: 220 • Number of layers in the second internal electrode layer: 220 • Thickness of the first and second outer layers: 30 μm L-gap dimension: 50 μm • W-gap dimension: 50 μm • Structure of the internal electrode • Structure of the external electrodes • First external electrode and second external electrode • Underlay electrode layer: A baked layer containing conductive metal (Cu) and glass components. • Plating layer: Two-layer structure consisting of a Ni plating layer and a Sn plating layer. • Third external electrode and fourth external electrode • Underlay electrode layer: A baked layer containing conductive metal (Cu) and glass components. • Plating layer: Two-layer structure consisting of a Ni plating layer and a Sn plating layer.

[0170] Each sample of the comparative example was prepared as a conventional multilayer ceramic capacitor, having a first maximum thickness point and a second maximum thickness point in the center of the folded portion of the first and second external electrodes, and a maximum thickness point in the center of the third external electrode. Each sample in the examples was prepared as a multilayer ceramic capacitor in which the third maximum thickness point of the third external electrode is located on the first or second surface side of the line m connecting the first and second maximum thickness points of the folded portions of the first and second external electrodes, respectively.

[0171] (2) Method for measuring the amount of inclination As an example, after reflow mounting the experimental sample onto a substrate, the cross-section of each substrate was polished to expose the cross-section (WT cross-section) along the stacking direction x and a second direction z, and the tilt amount dev was measured as shown in Figure 19. The tilt amount dev was measured using, for example, a microscope (Keyence VHX-8000).

[0172] (3) Method for measuring the maximum thickness point at each external electrode Using a laser microscope, the first maximum thickness point located at the first folded portion of the first external electrode, the second maximum thickness point located at the second folded portion of the second external electrode, and the third maximum thickness point located at the third external electrode were identified. Then, as shown in Figure 2, the shortest distance d between the line m connecting the first and second maximum thickness points and the third maximum thickness point was measured. A laser microscope (Keyence VK8700) was used to measure this shortest distance d.

[0173] (4) Results Table 1 shows the measurement results of the sample's inclination dev in relation to the change in the shortest distance d between the line m connecting the first and second maximum thickness points and the third maximum thickness point.

[0174] [Table 1]

[0175] According to Table 1, in each of the samples from Examples 1 to 10, the shortest distance d between the line m connecting the first and second maximum thickness points and the third maximum thickness point is 50 μm or more. Therefore, in all examples, a good result was obtained in which the magnitude of the slope dev was 5 μm or less.

[0176] On the other hand, in each of the samples from Comparative Examples 1 to 10, the shortest distance d between the line m connecting the first and second maximum thickness points and the third maximum thickness point was less than 50 μm. Therefore, in all of the comparative examples, the magnitude of the slope dev was 60 μm or more, which was significantly larger than the results of the examples.

[0177] From the above results, it became clear that by setting the shortest distance d between the line m connecting the first and second maximum thickness points and the third maximum thickness point to 50 μm, the maximum thickness points are arranged in a three-point configuration, which in turn reduces the amount of tilt of each sample, especially when vertically mounting through-type multilayer ceramic capacitors.

[0178] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention. [Explanation of Symbols]

[0179] 10, 110 Multilayer ceramic capacitors 12, 112 laminate 12a, 112a First surface 12b, 112b Second face 12c, 112c Third side 12d, 112d Fourth face 12e, 112e Fifth side 12f, 112f, 6th face 14, 114 dielectric layers 16, 116 internal electrode layer 16a, 116a First internal electrode layer 16b, 116b Second internal electrode layer 18, 118 Capacitance forming part 20a, 120a First outer layer 20b, 120b Second outer layer 22a, 22b, 122a, 122b end area 24a, 24b, 124a, 124b lateral regions 25a, 125a First opposing part 25b, 125b Second opposing section 26a, 126a First drawer 26b Second drawer section 28a First extension 28b Second extension 128a Second drawer section 128b Third drawer 30, 130, 230, 330 external electrode 30a, 130a First external electrode 30b, 130b Second external electrode 30c, 130c Third external electrode 30d Fourth external electrode 30a1, 130a1 First covering portion 30b1, 130b1 Second covering portion 30c1, 130c1 Third covering part 30d1 Fourth covering part 30a2, 130a2 First folded section 30b2, 130b2 Second fold 30c2, 130c2 Third folded section 30d2 Fourth fold 30aP1, 30aP2, 130aP: First maximum thickness point 30bP1, 30bP2, 130bP: Second point of maximum thickness 30 cP, 130 cP Third point of maximum thickness 30dP, the fourth point of maximum thickness. 32 Base electrode layer 32a, 132a First base electrode layer 32b, 132b Second base electrode layer 32c, 132c Third underlay electrode layer 32d Fourth underlay electrode layer 34 Plating layer 34a, 134a First plating layer 34b, 134b Second plating layer 34c, 134c Third plating layer 34d Fourth plating layer x stacking direction y First direction z Second direction L is the dimension of the multilayer ceramic capacitor in the first direction. W Dimensions of the second direction of the multilayer ceramic capacitor T Dimensions in the stacking direction of a multilayer ceramic capacitor

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first internal electrode layer is arranged on the plurality of dielectric layers and is drawn out to the third and fourth surfaces, A second internal electrode layer is arranged on the plurality of dielectric layers and is drawn out to the fifth and sixth surfaces, A first external electrode is disposed on the third surface and connected to the first internal electrode layer, A second external electrode is disposed on the fourth surface and connected to the first internal electrode layer, A third external electrode is disposed on the fifth surface and connected to the second internal electrode layer, A fourth external electrode is disposed on the sixth surface and connected to the second internal electrode layer, Equipped with, The first external electrode has a first folded portion that wraps around a part of the fifth surface and a part of the sixth surface, The second external electrode has a second folded portion that wraps around a part of the fifth surface and a part of the sixth surface, It has, The fifth surface or the sixth surface is positioned on the substrate mounting side. It is a multilayer ceramic capacitor, The first external electrode has a first maximum thickness point, which is the region with the greatest thickness in the second direction of the first folded portion located on the fifth surface, The second external electrode has a second maximum thickness point, which is the region with the greatest thickness in the second direction of the second folded portion located on the fifth surface. The third external electrode has a third maximum thickness point, which is the region with the greatest thickness in the second direction of the third external electrode. The shortest distance between the line connecting the first maximum thickness point of the first folded portion and the second maximum thickness point of the second folded portion and the third maximum thickness point of the third external electrode located on the first or second surface side in the stacking direction is 50 μm or more, and / or The first external electrode has a first maximum thickness point, which is the region with the greatest thickness in the second direction of the first folded portion located on the sixth surface, The second external electrode has a second maximum thickness point, which is the region with the greatest thickness in the second direction of the second folded portion located on the sixth surface, The fourth external electrode has a fourth maximum thickness point, which is the region with the greatest thickness in the second direction of the fourth external electrode. A multilayer ceramic capacitor in which the shortest distance between the line connecting the first maximum thickness point of the first folded portion and the second maximum thickness point of the second folded portion and the fourth maximum thickness point of the fourth external electrode located on the first or second surface side in the stacking direction is 50 μm or more.

2. The first point of maximum thickness of the first folded portion is located approximately in the center of the first folded portion. The second point of maximum thickness of the second folded portion is located approximately in the center of the second folded portion. The multilayer ceramic capacitor according to claim 1, wherein the third maximum thickness point of the third external electrode and the fourth maximum thickness point of the fourth external electrode are located on the first surface side or the second surface side of half the height in the stacking direction.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the length in the stacking direction including the laminate and the first to fourth external electrodes is smaller than the length in the second direction including the laminate and the first to fourth external electrodes.

4. The multilayer ceramic capacitor according to claim 3, wherein the maximum thickness of the third external electrode and the fourth external electrode is greater than the maximum thickness of the first folded portion and the second folded portion.

5. The multilayer ceramic capacitor according to claim 4, wherein the average thickness of the third external electrode and the fourth external electrode is greater than the average thickness of the first folded portion and the second folded portion.

6. The length in the first direction including the laminate and the first external electrode to the fourth external electrode is 0.10 mm or more and 3.50 mm or less. The multilayer ceramic capacitor according to claim 5, wherein the length in the stacking direction including the laminate and the first to fourth external electrodes is 0.05 mm or more and 2.80 mm or less.

7. The length in the first direction including the laminate and the first external electrode to the fourth external electrode is 0.40 mm or more and 2.20 mm or less. The multilayer ceramic capacitor according to claim 5, wherein the length in the stacking direction including the laminate and the first to fourth external electrodes is 0.20 mm or more and 1.45 mm or less.

8. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first internal electrode layer is arranged on the plurality of dielectric layers and is drawn out at the central part of the fifth surface in the first direction, A second internal electrode layer is arranged on the plurality of dielectric layers and is drawn out from one end and the other end of the fifth surface in the first direction, Displaced on the fifth surface, connected to the first internal electrode layer, and extending in the stacking direction, At one end of the fifth surface in the first direction, a second external electrode is connected to the second internal electrode layer and extends in the stacking direction, At the other end of the fifth surface in the first direction, a third external electrode is connected to the second internal electrode layer and extends in the stacking direction, A multilayer ceramic capacitor comprising, The first external electrode has a first maximum thickness point, which is the region with the greatest thickness in the second direction of the first external electrode. The second external electrode has a second maximum thickness point, which is the region with the greatest thickness in the second direction of the second external electrode. The third external electrode has a third maximum thickness point, which is the region with the greatest thickness in the second direction of the third external electrode. A multilayer ceramic capacitor in which the shortest distance between the line connecting the second maximum thickness point of the second external electrode and the third maximum thickness point of the third external electrode and the first maximum thickness point of the first external electrode located on the first or second surface in the stacking direction is 50 μm or more.

9. The first maximum thickness point of the first external electrode is located on the first or second surface side of the height of half the height in the stacking direction, The second maximum thickness point of the second external electrode is located approximately in the center of the second external electrode, which is on the fifth surface side. The third point of maximum thickness of the third external electrode is located approximately in the center of the third external electrode, which is located on the fifth surface side. The multilayer ceramic capacitor according to claim 8.

10. The multilayer ceramic capacitor according to claim 8 or 9, wherein the length in the stacking direction including the laminate and the first external electrode to the third external electrode is smaller than the length in the second direction including the laminate and the first external electrode to the third external electrode.

11. The multilayer ceramic capacitor according to claim 10, wherein the maximum thickness of the first external electrode is greater than the maximum thickness of the second external electrode and the third external electrode.

12. The multilayer ceramic capacitor according to claim 11, wherein the average thickness of the first external electrode is greater than the average thickness of the second external electrode and the third external electrode.

13. The length in the first direction including the laminate and the first external electrode to the third external electrode is 0.10 mm or more and 3.50 mm or less. The multilayer ceramic capacitor according to claim 12, wherein the length in the stacking direction including the laminate and the first external electrode to the third external electrode is 0.05 mm or more and 2.80 mm or less.

14. The length in the first direction including the laminate and the first external electrode to the third external electrode is 0.40 mm or more and 2.20 mm or less. The multilayer ceramic capacitor according to claim 12, wherein the length in the stacking direction including the laminate and the first external electrode to the third external electrode is 0.20 mm or more and 1.45 mm or less.

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