Silicon Brain

Abstract

This invention provides a method for reducing the power consumption of information processing systems using neural networks. [Solution] The thread arithmetic unit includes an SB block as a component and returns a thread output to an external input. The external input consists of input elements numbered 0 to (N-1), and comprises a NAND string from the nth column to the (n+m-1)th column, bit lines from the nth column to the (n+m-1)th column, and word lines from the sth row to the (s+N-1)th row. Each NAND string from the nth column to the (n+m-1)th column consists of memory cells from the sth row to the (s+N-1)th row. The data of the jth weight element is stored in the memory cell of the jth row within the NAND string from the nth column to the (n+m-1)th column. The word line of the (s+j)th row is selected, a read voltage is applied, the jth input element is selected, the bit line of the (n+mr)th column is selected, and the input code of the rth is input to the bit line of the (n+mr)th column.

Claims

1. ２０、２３ Includes an SB block whose components are thread processing units, The aforementioned thread arithmetic device returns a thread output to an external input. The aforementioned external input consists of input elements numbered from 0 to (N-1), The above input elements from the 0th to the (N-1)th are each represented in m-elements in binary, The aforementioned thread arithmetic unit consists of a NAND string from the nth column to the (n+m-1)th column, a bit line from the nth column to the (n+m-1)th column, and a word line from the sth row to the (s+N-1)th row, for any integer n. The NAND strings from the nth column to the (n+m-1)th column are each composed of memory cells from the sth row to the (s+N-1)th row, The data of the jth weight element is stored as 0 or 1 in the memory cell of the jth row in the NAND string from the nth column to the (n+m-1)th column. The aforementioned j is an integer between 0 and N-1, From the word lines of the (s+N-1)th row to the aforementioned sth row, select the word line of the (s+j)th row and apply a read voltage. From the above input elements numbered 0 to (N-1), select the jth input element, From the bit lines of the nth to the (n+m-1)th column, select the bit line of the (n+m-r)th column. (r-1) data 0s are attached to the right end of the input element j, and (m-r) data 0s are attached to the left end of the input element j, and these are used as the r-th input code for the input element j. The input code r is input to the bit lines of the (n+m-r) column. A semiconductor device characterized by the following features.

2. １８，２１ The input code for r is represented in 2m binary, The bit lines of the (n+m-r) column input the input code of r digit by digit to one end of the NAND string of the (n+m-r) column. The output from the memory cell in the jth row of the (n+m-r) NAND string is taken as the output code for the rth row. Output codes 0 through (m-1) are output for the bit lines from the nth column to the (n+m-1)th column. Adding up the output codes from the 0th to the (m-1)th, The jth output element is defined as the input element j and the weight element j, A semiconductor device according to claim 1, characterized in that...

3. The word lines from s to the (s+N-1)th word line are selected sequentially, the read voltages are applied sequentially, and the output elements from the 0th to the (N-1)th output are output sequentially. Summing up the output elements from the 0th to the (N-1)th, The output of the aforementioned thread is: The semiconductor device according to claim 2, characterized in that

4. １８，２１ The memory cells in the j-th and (j+1)th rows of the (n+m-r) column NAND string are the j-th and (j+1)th nonvolatile memory cells, The j and (j+1) non-volatile memories each have a first to a third terminal, The third terminal of the non-volatile memory cell j is connected to the word line of row j, The second terminal of the non-volatile memory cell j is connected to the first terminal of the memory cell (j+1), The aforementioned non-volatile memory cell j is capable of storing data 0 or data 1. When the stored data is data 1, if data 0 is input from the bit line of the (n+m-r) column, data 0 is output, and if data 1 is input from the bit line of the (n+m-r) column, data 1 is output. When the stored data is 0, if data 0 is input from the bit line of the (n+m-r) column, data 0 is output, and if data 1 is input from the bit line of the (n+m-r) column, data 0 is output. A semiconductor device according to claim 1, characterized in that...

5. ３０ A well formed on the surface of a semiconductor substrate contains a plurality of small blocks, One of the aforementioned subblocks is the SB block. A semiconductor device according to claim 1, characterized in that...

6. ３５ The word lines from the sth row to the (s+N-1)th row are stacked on the semiconductor surface. The module plane including the SB block is perpendicular to the semiconductor surface, The module plane is arranged so as to be perpendicular to the first axial direction within the semiconductor surface. The module plane is arranged so as to be parallel to the second axis direction which is perpendicular to the first axis direction. The word lines from row s to row (s+N-1) are arranged to be parallel to the second axis direction. The bit lines from the nth column to the (n+m-1)th column are arranged so as to be parallel to the first axis direction. A semiconductor device according to claim 1, characterized in that...

7. The SB block is arranged so as to be perpendicular to a third axis direction perpendicular to the semiconductor surface, The word lines from the sth row to the (s+N-1)th row are arranged parallel to the fourth axis direction within the semiconductor surface, The bit lines from the nth column to the (n+m-1)th column are arranged on the semiconductor surface so as to be perpendicular to the fourth axis direction. A semiconductor device according to claim 1, characterized in that...

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