Improved coded aperture focal plane array using all detectors.

Abstract

The sensing system includes a focal plane array, a detector dual input circuit, a detector selector circuit, and a selection module. The focal plane array includes a plurality of detectors. The detector dual input circuit combines outputs from the detectors received on a first input channel without using outputs received on a second input channel. The detector selector circuit establishes a first signal path between the detectors and the first input channel and a second signal path between the detectors and the second input channel. The detector selector circuit includes a mask that maps the detectors to a first detector group or a second detector group. Based on the mask assignment, the selection module connects one or more of the detectors to the first signal path to establish the first detector group and connects one or more of the detectors to the second signal path to establish the second detector group.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Patent Application No. 18 / 072,932, filed December 1, 2022, which is incorporated herein by reference in its entirety. [Background technology]

[0002] The present disclosure relates to sensors, and more particularly to sensors having coded aperture focal plane arrays.

[0003] As is known in the art, various types of sensors can be used for situational awareness (SA) of vehicles, equipment, aircraft, satellites, ships, etc. Fields of view (FOV), such as hemispherical (2π steradians), spherical (4π steradians), etc., are utilized at relatively high resolution to improve situational awareness (SA) around a target asset (ground vehicle, air vehicle, naval vehicle, infrastructure, etc.), useful for detecting and tracking incoming combat threats as well as for non-combat missions. Summary of the Invention

[0004] According to a non-limiting embodiment, the sensing system includes a focal plane array, a detector dual-input circuit, a detector selector circuit, and a selection module. The focal plane array can be part of a readout integrated circuit package and includes an n x m array of detectors that define an output pixel. The values ​​n and m are array element index values. The detector dual-input circuit is configured to combine outputs from the detectors received on a first input channel without using outputs from the detectors received on a second input channel. The detector selector circuit establishes a first signal path between the detectors and the first input channel and a second signal path between the detectors and the second input channel. The detector selector circuit forms part of the focal plane array within the pixel and includes an electronic mask configured to map the detectors to one or both of a first detector group (Group A) and a second detector group (Group B). The selection module connects one or more of the detectors to the first signal path to define the first detector group and connects one or more of the detectors to the second signal path to define the second detector group. A selection module connects one or more of the detectors to the first and second signal paths based on the mask to establish first and second detector groups.

[0005] According to another non-limiting embodiment, a method for generating image data includes arranging a plurality of detectors in an n x m array to establish a focal plane array and a single output pixel. The focal plane array comprises a portion of a readout integrated circuit package, and the values ​​n and m are array element index values. The method further includes generating an output signal from one or more of the detectors in response to detecting light and combining the output signal received at a first input channel of a detector dual input circuit with an output signal received at a second input channel of the detector dual input circuit. The method further includes establishing, by a detector selector circuit, a first signal path between the detector and the first input channel and establishing, by the detector selector circuit, a second signal path between the detector and the second input channel. The method further includes designating the detectors as a first detector group (Group A) or a second detector group (Group B) using a mask forming part of the focal plane array. The method further includes connecting, by the selection module, one or more of the detectors to a first signal path based on the mask to establish a first detector group, and connecting, by the selection module, one or more of the detectors to a second signal path based on the mask to establish a second detector group.

[0006] According to yet another non-limiting embodiment, the detector selector circuit comprises a focal plane array having an n x m array of detectors that establish output pixels. The values ​​n and m are array element index values. The first signal path is in signal communication with a first input channel of the detector dual-input circuit, and the second signal path is in signal communication with a second input channel of the detector dual-input circuit. The detector selector circuit further comprises a plurality of switch circuits, each configured to selectively connect a respective detector in the array of detectors to either the first signal path or the second signal path.

[0007] Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the present disclosure are described in detail herein and are considered a part of the claimed disclosure. For a better understanding of the present disclosure, together with its advantages and features, reference is made to the description and drawings. [Brief explanation of the drawings]

[0008] For a more complete understanding of the present disclosure, reference should now be made to the following brief description taken in conjunction with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0009] [Figure 1] 1 illustrates a vehicle including a sensor system implementing an improved coded aperture (CA) focal plane array (FPA) according to a non-limiting embodiment. [Figure 2A] FIG. 1 is a schematic diagram illustrating an example implementation of a readout integrated circuit (ROIC) input circuit for a coded aperture focal plane array in accordance with a non-limiting embodiment of the present disclosure. [Figure 2B] FIG. 1 is a block diagram of an example implementation of a coded aperture focal plane array readout pixel with 16 sub-pixel detectors in a 4×4 array, in accordance with a non-limiting embodiment of the present disclosure. [Figure 3] 10 illustrates an example of an aperture mask for a coded aperture focal plane array, according to a non-limiting embodiment of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of an exemplary mounting system having a coded aperture focal plane array, in accordance with a non-limiting embodiment of the present disclosure. [Figure 5] 10 is an example of a mask applied to multiple pixels generated by a photodetector array in accordance with a non-limiting embodiment. [Figure 6] 1 is a flow diagram of an exemplary sequence of steps for a coded aperture focal plane array, in accordance with a non-limiting embodiment of the present disclosure. [Figure 7] FIG. 1 is a schematic diagram of an exemplary computer capable of performing at least a portion of the processes described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] Traditional sensor systems might include many overlapping distributed aperture sensors, each with its own large focal plane array (FPA), or scanning or step-stair systems that use a small number of FPAs at the expense of a slower update rate across the field of view. Other systems combine attributes to produce relatively low-resolution distributed aperture sensors, reducing the number of cameras while providing a large instantaneous field of view (IFOV), which can be supplemented with narrow FOV imagers on agile gimbals for surveying or high-resolution imaging. Traditional computational imaging-based systems use signal processing techniques to increase the resolution of systems with smaller pixel counts or to expand the field of view of smaller sensors by introducing additional optical elements, such as coded apertures (CAs), optical multiplexers, or spatial light modulators (SLMs). To increase resolution, other known systems use pixel dithering to improve the spatial resolution of non-diffraction-limited systems.

[0011] Sensor systems including focal plane arrays for coded aperture (CA) sensing have been developed to improve resolution by using computational imaging techniques (e.g., performed by an image controller) in combination with a readout array for compressed sensing, which electronically applies apertures, or more commonly, coded electronic masks, to the focal plane array instead of using traditional independently movable optical elements or spatial light modulators. The readout array can connect a single readout pixel to an n × m array of smaller detectors (e.g., photodiodes) and provide a mechanism for dynamic selection of columns of the encoded mask in real time at video rates. The aperture mask pattern can then be programmed into a readout integrated circuit (ROIC) and applied to multiple region-of-interest windows where increased resolution is desired, while reading out the remainder of the array at the ROIC pixel resolution.

[0012] However, known sensor systems that perform image reconstruction based on CA sensing suffer from an n × n frame delay. Furthermore, coded CA sensing performed in known sensor systems involves turning off half of the detectors (e.g., shunting the detectors to ground (0 V)) or optically blocking incident radiation from half of the detectors in each pixel pattern and then ignoring the off or blocked detectors when performing image reconstruction. For example, the outputs of a subset of detectors are shunted to ground or the incident illumination is blocked, discarding their optical signals. As a result, half of the optical signal incident on each ROIC pixel is lost. For background-limited sensing devices, sensitivity is proportional to the square root of the optical signal, so losing half the signal reduces sensitivity by √2. As a result, half of the optical signal in each pixel pattern is ignored and wasted, limiting the sensitivity of the reconstructed image.

[0013] Various embodiments described herein provide improved CA focal plane arrays that utilize the optical signals of all individual detectors (i.e., pixels) in each pixel pattern when performing image reconstruction, thereby improving sensitivity by approximately 40% (√2).

[0014] Referring to FIG. 1 , a vehicle 100 including a sensor system 102 mounted thereon implementing a coded aperture focal plane array (FPA) is shown in accordance with a non-limiting embodiment of the present disclosure. While the vehicle 100 is shown as a naval vehicle (e.g., a ship), embodiments of the sensor system 102 described herein may also be implemented in other types of vehicles or structures, including, but not limited to, ground vehicles, aircraft, buildings, structures, unmanned aerial vehicles, geographic regions, etc. Furthermore, coded aperture FPAs can provide any practical FOV that meets the needs of a particular application. In some embodiments, a portion of the FOV can be the focus of the sensor system, facilitating improved resolution compared to known FPAs.

[0015] The sensor system 102 has a field of view (FOV) that can provide some degree of situational awareness (SA) for the vehicle 100. In a non-limiting embodiment, the sensor system 102 provides hemispherical (e.g., 2π steradians) SA with improved resolution (compared to known coded aperture FPAs) to detect and track multiple potential threats as well as provide assistance in a variety of non-combat missions. Other embodiments are provided for full spherical (e.g., 4π steradians) coverage for airborne or spaceborne systems.

[0016] 2A and 2B, a portion of a readout integrated circuit (ROIC) 200 is shown according to a non-limiting embodiment. The readout integrated circuit (ROIC) 200 may be implemented as an integrated circuit (IC) for image reading sensing elements or detectors, such as infrared and ultraviolet light sensors or photodiodes. The ROIC operates by accumulating photocurrent from each pixel and transferring the resulting signal to an output tap for readout. U.S. Pat. No. 10,097,774, assigned to Raytheon Company and incorporated herein by reference, discloses an exemplary ROIC.

[0017] It will be appreciated that any practical n x m array format or size of detector can be used to meet the needs of a particular application. In some embodiments, n does not equal m. While diode-based detectors are used in the illustrated embodiment, it will be appreciated that any suitable type of detector can be used, such as dual-color or multi-color detector diodes, or avalanche photodiodes. The detectors may be sensitive to light at wavelengths ranging from ultraviolet to long-wave infrared or any sub-wavelength band within this range.

[0018] The ROIC 200 implements a detector selector circuit 202 configured to selectively connect individual detectors (e.g., photodiodes) 203 (d1-d16) included in or hybridized to an ROIC pixel 204 (see FIG. 2B ) to one of two input channels 209a or 209b. According to a non-limiting embodiment, each detector 203 is coupled to a switch circuit 205. Each switch circuit 205 selectively connects the detector 203 to a first signal path or a second signal path and selectively connects or disconnects the detector 203 to or from a coded aperture selection module 214. Thus, the switch circuit 205 selectively connects the detector 203 to a first signal path (e.g., signal path 216 associated with a first detector group 216 (Group A)) or a second signal path (e.g., signal path 217 associated with a second detector group 217 (Group B)) in response to control by the coded aperture selection module 214.

[0019] The ROIC 200 outputs a single ROIC pixel 204 per frame via a detector dual input circuit 208. Note that while the illustrated detector dual input circuit 208 is a direct injection (DI) type circuit, other classes of detector input circuits can alternatively be used, including, but not limited to, charge transimpedance amplifiers (CTIAs), per-detector source followers (SFDs), gate modulation, and the like, such as those disclosed in U.S. Patent Nos. 4,445,117 and 5,083,016, which are incorporated herein by reference. Furthermore, the illustrated DI circuit and other circuits may also include other noise reduction circuits, such as in-pixel sample / hold circuits and correlated double sampling. The illustrated DI circuit can also be a dual-polarity circuit capable of using two-color detectors with selectable bias. Examples of DI circuits are disclosed in U.S. Patent Nos. 5,043,820, 5,128,534, and 7,586,074, which are incorporated herein by reference.

[0020] 2A and 2B, the detector dual-input circuit 208 includes a first input channel 209a and a second input channel 209b. The first input channel 209a includes a first direct injection input buffer 210a, a first row select switch 212a, and a first voltage preset switch 213a. The input of the first input channel 209a is connected to first inputs of the detectors 203 (d1-d16) via a first signal path, defining a first detector group (group A) 216. The output of the first input channel 209a is selectively connected to a first column bus line (bus line A) 207 via a first row select switch 212a. Therefore, the first direct injection input buffer 210a and the first row selection switch 212a can be controlled to output a first portion (e.g., a first half) of the ROIC pixel 204 to the first column bus line 207 based on the voltage applied to the detectors 203 included in the first detector group 216 (Group A).

[0021] Similarly, the second input channel 209b includes a second direct injection input buffer 210b, a second row select switch 212b, and a second voltage preset switch 213b. The input of the second input channel 209b is connected to the second inputs of the detectors 203 (d1-d16) via a second signal path, defining a second detector group (Group B) 217. The output of the second input channel 209b is connected to a second column bus line (Bus Line B) 206 via a second row select switch 212b. Therefore, the second direct injection input buffer 210b and the second row select switch 212b can be controlled to output a second portion (e.g., the remaining second half) of the ROIC pixel 204 to the second column bus line 206 based on the voltage applied to the detectors 203 included in the second detector group 217 (Group B).

[0022] First input channel 209a and second input channel 209b can be controlled to read data from detectors 203 (d1-d16) and route the data to first column bus line 207 and second column bus line 206, respectively. While circuit diagrams 209a and 209b provide analog outputs, the circuitry can be modified to perform analog-to-digital conversion within the pixel array and provide a pair of digital outputs from ROIC pixel 204.

[0023] In embodiments where the ROIC pixel outputs on column bus lines 206 and 207 are analog, the analog outputs are converted to the digital domain by analog-to-digital converters located at the end of the pixel array for each column or group of columns. The digital values ​​corresponding to the pixels in Group A and Group B are subtracted from each other (AB). By cycling through various pixel combinations, as shown in FIG. 3, high-resolution spatial information is encoded in the time domain across multiple frames of low-resolution pixel outputs. Furthermore, the digital values ​​corresponding to the pixels in Group A and Group B can be added (A+B) to generate a low-resolution output using all detectors.

[0024] According to non-limiting embodiments, image data can be generated based on a combination of outputs from detectors included in a first detector group (Group A) and outputs from detectors included in a second detector group (Group B). Thus, signal readout to a readout integrated circuit (ROIC) can be achieved by performing a sum or subtraction of the combined outputs from the detectors included in the first detector group (Group A) and the detectors included in the second detector group (Group B). In one example, signal readout to a readout integrated circuit (ROIC) can be achieved by performing an analog-to-digital conversion of each of the outputs from the detectors included in the first detector group (Group A) and the detectors included in the second detector group (Group B) in separate digital registers of the ROIC.

[0025] In another embodiment, the subtraction operation may involve calculating in the analog domain the difference between the outputs from the detectors in the first detector group (Group A) and the outputs of the detectors in the second detector group (Group B). The subtraction may be easily performed using a differential amplifier or by integrating in opposite directions across capacitors.

[0026] In an embodiment, each detector 203 (d1-d16) can be connected to either input channel A (209a) or input channel B (209B) at a given time by coded aperture selection module 214. Thus, the combination of group A and group B forms a pattern to generate an output that can be processed, for example, according to a computational imaging technique performed by an image controller (not shown). Selection module 214 can be located within the ROIC pixel area or on the periphery of ROIC 200 (e.g., outside the pixel area).

[0027] Thus, one or more non-limiting embodiments of the present disclosure overcome limitations of known coded aperture focal plane arrays by duplicating input circuit 209a to enable signals from detector outputs of group B to be integrated and combined with the outputs of group A (e.g., using detector dual input circuit 208), thereby improving sensitivity.

[0028] FIG. 3 shows an example of 16 coded aperture masks 220.1-220.16 used to perform image reconstruction. Each coded mask 220.1-220.16 uses 16 detectors 203, some of which are mapped to a first group 203.1, e.g., Group A (shown in green), and some of which are mapped to a second group 203.2, e.g., Group B (shown in blue). While 16 aperture masks 220.1-220.16 are shown, it is understood that any practical number and type of masks can be used to meet the needs of a particular application. Furthermore, the number of detectors 203 in Group A or Group B of aperture masks 220.1-220.16 within a column can be varied. In the illustrated aperture masks 220.1 to 220.16, except for the first mask 220.1 (shown in the upper left corner), all detectors 203 in group A 203.1 are connected such that half of the detectors 203 are connected to group A 203.1 and the other half of the detectors 203 are connected to group B 203.2.

[0029] According to non-limiting embodiments, ROIC 200 can sequence through or cycle through aperture masks 220.1-220.16 according to a timing scheme or frame rate set by selection logic. The selection logic can be implemented in a peripheral controller section that drives detector selector circuits within the pixel and / or pixel array. In some embodiments, the selection logic, which can be programmable and stored in coded aperture selection module 214, enables the selection module to select and cycle through aperture masks 220.1-220.16. In other embodiments, the selection logic is hard-coded. In other embodiments, different patterns of aperture masks 220.1-220.16 can be programmed into ROIC 200 or hard-coded into the array.

[0030] By sequentially processing aperture masks 220.1-220.16 to map which detectors 203 are connected to Group A or Group B, information from each individual detector 203 can be obtained, as well as aggregate detector information, such as a single output pixel selected for all detectors 203. The array output from each aperture mask 220.1-220.16 can be processed using computational imaging techniques implemented by the image controller, for example, to enhance the array's resolution. For example, 4x4 coded aperture pixels can be used to create a 24kx24k FPA while reading only 6kx6k pixels in any given frame. It is understood that other computational imaging techniques can be applied to utilize mask patterns for other applications, including, but not limited to, event detection, moving target display, and passive depth imaging. In an embodiment, the patterns of aperture masks 220.1-220.16 are changed at the frame rate. Additionally, coded aperture resolution enhancement can be applied to several small regions of interest within the FOV to reduce computational bandwidth.

[0031] 4 shows an exemplary optical imaging system 400 having a coded aperture focal plane array, in accordance with an exemplary embodiment of the present disclosure. An entrance pupil 402 has a diameter Ds and provides a path to an imager 404, which may include one or more lenses. The imager 404 focuses the light onto a focal plane array 406. In an embodiment, a mask 408, such as a Hadamard mask, is provided as part of the focal plane array 406, as described above.

[0032] In an embodiment, the FPA 406 is disposed within an enclosure 410 that is cooled to a selected temperature to reduce or eliminate stray light impinging on the FPA 406 and reducing the accuracy of the sensor. The enclosure 410 may include a cold stop 412 around the temperature controlled region.

[0033] Known optical systems require the formation of an intermediate image between the imager and the reimager, which focuses the light onto the FPA 406. A mask must be placed at the intermediate image. The intermediate image plane of such an optical system must have excellent wavefront error (WFE) quality to achieve diffraction-limited performance. The optical system must be designed to minimize WFE at both the intermediate image plane and the actual image plane where the FPA 406 is placed. Furthermore, these masks require separate optical elements that are distinct from the actual detector or focal plane array (FPA) 406.

[0034] The optical system 400 with the coded aperture FPA 406 described above eliminates the need for a reimager or intermediate image. Furthermore, exemplary embodiments of the present disclosure eliminate the need for a separate movable or electrically switchable optical element, such as a spatial light modulator (SLM). The advantages of the above-described optical system embodiments over conventional systems will be readily apparent to those skilled in the art. Furthermore, standard SLM-based optical systems use a single FPA at the image plane, which again results in a signal loss of nearly half the number of FPA pixels per frame. Alternatively, a dual-FPA system can be constructed in which the SLM is a digital microelectromechanical (MEM) array with mirrored surfaces that have bistatic states (e.g., "on" and "off" positions). In the "on" position, the SLM sends half the light (half the pixels) to one FPA, while elements in the "off" position are sent to the other FPA. The combined dual-FPA system restores both pixel groups for image reconstruction. However, this system is more complex and requires another FPA and associated electronics and cooling.

[0035] 5 shows an example of a pixel mask 408 for performing high-resolution image reconstruction. The pixel mask 408 is defined by a number of measurement codes arranged in a number of columns and rows to define a grid. The measurement codes include positive value codes 500 (e.g., 1) and negative value codes 502 (e.g., -1). Each column represents a pixel (P1-P16) and each row represents a frame (F1-F16).

[0036] The pixel mask 408 is generated according to a Hadamard matrix. A Hadamard matrix is ​​a square matrix whose elements are either positive (+) or negative (-) and whose rows are orthogonal to each other. In other words, each pair of rows in a Hadamard matrix represents two orthogonal vectors, but combinatorially speaking, this means that each pair of rows has matching elements in exactly half of its columns and non-matching elements in the remaining columns. The n-dimensional parallelepiped spanned by the rows of an n x n Hadamard matrix has the largest n-dimensional volume among parallelepipeds spanned by vectors whose elements have absolute values ​​limited to one.

[0037] Different Hadamard orders can be used to increase the amount of compression as the latency changes: a Hadamard matrix of 2 results in a compression ratio of 4 and a latency of 4 frames.

[0038] The Hadamard matrix defines a pixel mask 408 that the image controller can utilize to generate an encoded or compressed image stream. For example, for each frame F1-F16, the Hadamard matrix effectively maps the positive voltage (+) detector 203.1 of group A to a positive value code 500 and the negative voltage (-) detector 203.2 of group B to a negative value code 502. An inverse Hadamard transform (also known as an inverse Hadamard matrix) can then be applied to the encoded frame to decode or perform high-resolution image reconstruction. The measurement matrix used by the image controller can be generated by the image controller and applied to the image. The image controller can generate the appropriate mask through various mechanisms. For example, the image controller can retrieve the pixel mask 408 defined by the Hadamard matrix from memory as needed.

[0039] It is understood that any suitable type of mask pattern sequence can be used to reconstruct an image with an FPA. While exemplary embodiments of the present disclosure are described in connection with a Hadamard mask sequence, it is understood that any practical type of mask pattern and any useful computational imaging technique can be used to meet the needs of a particular application. Examples of computational processing techniques are shown and described in U.S. Patent No. 7,532,772, U.S. Patent Publication No. 2006 / 0038705, U.S. Patent No. 9,445,115, and U.S. Patent No. 9,983,063, all of which are incorporated herein by reference.

[0040] Referring to FIG. 6, a flow diagram illustrates a method for generating image data according to a non-limiting embodiment. The method begins at operation 600, where a plurality of detectors are arranged in an n×m array and a focal plane array and output pixels are established at operation 602. The focal plane array comprises a portion of a readout integrated circuit package. At operation 604, output signals are generated from one or more detectors in response to detecting light, and at operation 606, an output signal received at a first input channel of a detector dual-input circuit is combined with an output signal received at a second input channel of the detector dual-input circuit. At operation 608, a detector selector circuit establishes a first signal path between the detector and the first input channel and a second signal path between the detector and the second input channel. At operation 610, the detectors are mapped to a first detector group (Group A) or a second detector group (Group B) using a mask that forms part of the focal plane array. At operation 612, a selection module connects one or more detectors to a first signal path based on the mask to establish a first detector group, and further connects one or more detectors to a second signal path based on the mask to establish a second detector group. At operation 614, a readout integrated circuit (ROIC) reads out outputs from the detectors mapped to the first detector group (Group A) and the detectors mapped to the second detector group (Group B) to generate an image, and the method ends at operation 616.

[0041] It is understood that any suitable type of mask pattern sequence can be used for encoding, followed by image reconstruction with an FPA. While exemplary embodiments of the present disclosure are described in connection with a Hadamard mask sequence, it is understood that any practical type of mask pattern and any useful computational imaging technique can be used to meet the needs of a particular application. Examples of computational processing techniques are shown and described in U.S. Patent No. 7,532,772, U.S. Patent Application Publication No. 2006 / 0038705, U.S. Patent No. 9,445,115, and U.S. Patent No. 9,983,063, all of which are incorporated herein by reference.

[0042] Referring to FIG. 7 , an exemplary computer 600 capable of performing at least a portion of the processes described herein is shown according to a non-limiting embodiment. The computer 600 may execute processes to implement a mask controller, such as the selection module 214 of FIG. 2A , similar to the operations illustrated in FIG. 6 , for example. The computer 600 includes a processor 602, volatile memory 604, non-volatile memory 606 (e.g., a hard disk), an output device 607, and a graphical user interface (GUI) 608 (e.g., a mouse, keyboard, display, etc.). The non-volatile memory 606 stores computer instructions 612, an operating system 616, and data 618. In one example, the computer instructions 612 are executed by the processor 602 from the volatile memory 604. In a non-limiting embodiment, an article 620 includes non-transitory computer-readable instructions.

[0043] The processing may be implemented in hardware, software, or a combination of the two. The processing may be implemented in a computer program running on a programmable computer / machine, each of which includes a processor, a processor-readable storage medium or other article of manufacture (including volatile and non-volatile memory and / or storage elements), at least one input device, and one or more output devices. The program code may be applied to data entered using the input device to perform processing and generate output information.

[0044] The system may execute processes, at least in part, via a computer program product (e.g., in a machine-readable storage device) for execution by or to control the operation of a data processing device (e.g., a programmable processor, computer, or multiple computers). Each such program may be implemented in a high-level procedural or object-oriented programming language for communicating with a computer system. However, the program may also be implemented in assembly or machine language. The language may be a compiled or interpreted language, and may be deployed in any form, including as a stand-alone program or module, a component, a subroutine, or other unit suitable for use in a computing environment. The computer program may be executed on one computer or may be deployed to run on multiple computers at one site or distributed across multiple sites and interconnected by a communications network. The computer program may be stored on a general-purpose or special-purpose programmable computer-readable storage medium or device (e.g., RAM / ROM, CD-ROM, hard disk, or magnetic diskette) to configure and operate the computer when the storage medium or device is read by the computer.

[0045] The process may also be implemented as a machine-readable storage medium configured with a computer program that, when executed, causes a computer to operate according to instructions in the computer program.

[0046] Processing may be performed by one or more programmable processors executing one or more computer programs to perform the functions of the system. All or part of the system may be implemented as special purpose logic circuitry (e.g., an FPGA (field programmable gate array), a general purpose graphical processing unit (GPGPU), and / or an ASIC (application-specific integrated circuit)).

[0047] Corresponding structure, materials, acts, and equivalents of all means-plus-function elements in the following claims are intended to include any structure, material, or acts for performing the function as specifically claimed in combination with other claimed elements. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the form set forth. Many changes and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present disclosure. The embodiments have been selected and described to best explain the principles and practical applications of the present disclosure and to enable others skilled in the art to understand various embodiments, with various modifications suitable for the particular use intended.

[0048] While preferred embodiments have been described, it is to be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the following claims, which should be construed to maintain appropriate protection for the disclosure as originally described.

Claims

1. 1. A sensing system comprising: a focal plane array having an n x m array of detectors and a single output pixel, where n and m are array element index values, the focal plane array comprising part of a readout integrated circuit package; a detector dual input circuit configured to combine the output from the detector received on a first input channel without using the output from the detector received on a second input channel; a detector selector circuit that establishes a first signal path between the detector and the first input channel and a second signal path between the detector and the second input channel, the detector selector circuit including an electronic mask that forms part of the focal plane array within the pixel and that is configured to map the detector to one or both of a first detector group (Group A) and a second detector group (Group B); a selection module configured to control the electronic mask to connect one or more of the detectors to the first signal path to establish the first detector group and to connect one or more of the detectors to the second signal path to establish the second detector group, the selection module connecting the one or more of the detectors to the first and second signal paths to establish the first and second detector groups based on the electronic mask; A sensing system including:

2. 2. The sensing system of claim 1, wherein a combination of outputs from the detectors in the first detector group (Group A) and the detectors in the second detector group (Group B) produces image data at reduced resolution, the difference of which encodes full resolution information for each detector pixel in the time domain.

3. The detector dual input circuit includes: a first row select switch included in the first input channel and configured to selectively connect the first signal path to a first column bus line; a second row select switch included in the second input channel and configured to selectively connect the second signal path to a second column bus line; The sensing system of claim 2 further comprising:

4. The sensing system of claim 2 further comprising an imager that focuses light onto the focal plane array.

5. The sensing system of claim 2 , wherein the focal plane array comprises part of a readout integrated circuit package.

6. The sensing system of claim 2 , wherein the electronic mask is configured to provide a Hadamard mask pattern.

7. The sensing system of claim 2 , wherein the electronic mask is configured to establish a plurality of different electronic mask patterns, and the selection module operates according to switch logic to cycle the electronic mask through the plurality of different mask patterns.

8. The sensing system of claim 7 , wherein the plurality of different mask patterns are applied to a region of interest within a field of view of the sensing system.

9. The sensing system of claim 2 , wherein the system provides a hemispherical field of view.

10. 1. A method for generating image data, comprising: arranging a plurality of detectors in an n x m array, where n and m are array element index values, to establish a focal plane array and a single output pixel, said focal plane array comprising a portion of a readout integrated circuit package; generating an output signal from one or more of the detectors in response to detecting light; combining an output signal received at a first input channel of a detector dual-input circuit with an output signal received at a second input channel of said detector dual-input circuit; establishing, via a detector selector circuit, a first signal path between the detector and the first input channel, and establishing, via the detector selector circuit, a second signal path between the detector and the second input channel; mapping the detectors to one or both of a first detector group (Group A) or a second detector group (Group B) using an electronic mask forming part of the focal plane array; connecting, by a selection module, one or more of the detectors to the first signal path based on the electronic mask to establish the first detector group, and connecting, by the selection module, one or more of the detectors to the second signal path based on the electronic mask to establish the second detector group; A method comprising:

11. 11. The method of claim 10, further comprising generating the image data based on a combination of outputs from the detectors included in the first detector group (Group A) and outputs from the detectors included in the second detector group (Group B).

12. 12. The method of claim 11, further comprising performing a signal readout to a readout integrated circuit (ROIC) by performing either an addition or subtraction of the combination of outputs from the detectors in the first detector group (Group A) and outputs of the detectors in the second detector group (Group B).

13. 13. The method of claim 12, wherein performing the subtraction comprises calculating a difference in the analog domain between outputs from the detectors in the first detector group (Group A) and outputs of the detectors in the second detector group (Group B).

14. 12. The method of claim 11, further comprising: performing signal readout into a readout integrated circuit (ROIC) by performing analog-to-digital conversion of outputs from the detectors in the first detector group (Group A) and outputs of the detectors in the second detector group (Group B) into separate digital registers in the ROIC.

15. selectively connecting the first signal path to a first column bus line via a first row select switch; selectively connecting the second signal path to a second column bus line via a second row select switch; The method of claim 11 further comprising:

16. establishing a plurality of different Hadamard mask patterns using the mask; cycling the electronic mask through the plurality of different mask patterns; modifying the detectors in the first and second groups based on the plurality of different mask patterns to generate a plurality of different output signals provided to the first and second input channels of the detector dual-input circuit; The method of claim 11 further comprising:

17. a focal plane array having an n x m array of detectors and a single output pixel, where n and m are array element index values, said focal plane array comprising a portion of a readout integrated circuit package; a first signal path in signal communication with a first input channel of the detector dual-input circuit; a second signal path in signal communication with a second input channel of the detector dual-input circuit; a plurality of switch circuits, each switch circuit configured to selectively connect a respective detector in the array of detectors to the first signal path or the second signal path; a detector selector circuit including:

18. 20. The detector selector circuit of claim 17, wherein the switch circuits are in signal communication with a coded aperture selection module, the coded aperture selection module controlling each switch circuit to connect the detector to either the first signal path or the second signal path.

19. 20. The detector selector circuit of claim 18, wherein the detectors connected to the first signal path establish a first detector group configured to provide a first output signal to the first input channel, and the detectors connected to the second signal path establish a second detector group configured to provide a second output signal to the second input channel.

20. 20. The detector selector circuit of claim 19, wherein the first output signal and the second output signal are combined by the detector dual input circuit to generate image data.

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