Edge ring for semiconductor manufacturing equipment and method for manufacturing the same

Abstract

An edge ring for semiconductor manufacturing equipment and a method for manufacturing the same are disclosed. The edge ring for semiconductor manufacturing equipment includes an upper layer having high hardness and a lower layer located below the upper layer and having lower hardness than the upper layer, the lower layer being positioned to contact internal components of a plasma etching apparatus.

Description

[Technical Field]

[0001] The present invention relates to an edge ring for semiconductor manufacturing equipment and a method for manufacturing the same. [Background technology]

[0002] To ensure uniformity of the plasma irradiated onto the wafer for the manufacture of wafer edge chips, it is necessary to ensure uniformity of the temperature of the wafer and the edge ring (or focus ring). Therefore, a smooth supply of He gas for cooling the edge ring and wafer is required.

[0003] CVD SiC materials, which have high corrosion resistance for fine line widths and multi-stage etching, also have excellent plasma resistance. However, they have higher hardness than silicon, resulting in poor adhesion to other components and the occurrence of He leakage for cooling, which can make them difficult to apply to products.

[0004] One hybrid method involves attaching silicon to CVD SiC, where the parts that come into contact with other components are manufactured from silicon and bonded to the upper part of the CVD SiC. However, because adhesives are used, there is a high possibility of particle generation during the process, and the manufacturing process is complex, which may lead to high costs due to increased production costs. In addition, the strength of the adhesive decreases at high temperatures, causing the CVD SiC and silicon parts to shift, which can cause the upper CVD SiC part to warp or delaminate during the process. [Overview of the project] [Problems that the invention aims to solve]

[0005] The present invention aims to provide semiconductor manufacturing equipment components that, in order to solve the aforementioned problems, have improved adhesion to other components and improved plasma resistance by applying high-hardness and low-hardness materials. For example, it aims to provide an edge ring that improves the He leakage development that occurs when using conventional CVD SiC edge rings, and when mounted on semiconductor manufacturing equipment, has improved adhesion to other components and improved plasma resistance.

[0006] The present invention provides a method for manufacturing semiconductor manufacturing equipment components, which allows for the production of semiconductor manufacturing equipment components by a simple method such as a continuous vapor deposition (e.g., CVD) process or bonding, using a method for adjusting the ratio of Si and C in the raw materials supplied during the manufacturing process.

[0007] However, the problems that this invention aims to solve are not limited to those mentioned above, and further problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] An edge ring according to one embodiment includes an upper layer having high hardness; and a lower layer located below the upper layer and having lower hardness than the upper layer, the lower layer may be positioned to contact internal components of a plasma etching apparatus.

[0009] The upper layer according to one embodiment can be formed of SiC or B4C.

[0010] In one embodiment, the thickness of the upper layer is 1 mm or more.

[0011] In one embodiment, the lower layer is made of C / SiC or C / B4C.

[0012] In one embodiment, the lower layer is made of a C / SiC material, and the atomic ratio of Si:C may be 1:1.4 to 1:1.6.

[0013] The lower layer according to one embodiment is a C / B4C material, and the atomic ratio of B:C is more than 0: less than 1-4:1.

[0014] The Vickers hardness of the lower layer according to one embodiment is 1000 kg f / mm 2 ~2000 kg f / mm 2 is.

[0015] The thickness of the lower layer according to one embodiment is 0.2 mm or more.

[0016] The lower layer according to one embodiment can be formed by being deposited on the upper layer.

[0017] The edge ring according to one embodiment is deposited by the CVD method. If the lower layer is C / SiC, it can be deposited by continuously changing the raw material ratio of Si and C. If the lower layer is C / B4C, it can be deposited by continuously changing the raw material ratio of B and C.

[0018] The method for manufacturing an edge ring of the present invention according to one embodiment can form a high-hardness upper layer, form a lower layer with a lower hardness than the upper layer, and be processed in a component form.

[0019] According to one embodiment, when forming the upper layer, the upper layer can be formed by CVD, reaction sintering, or sintering.

[0020] According to one embodiment, when forming the lower layer, the lower layer can be deposited on the upper layer.

[0021] According to one embodiment, when forming the lower layer, the lower layer can be deposited by continuously changing the raw material ratio of B:C or Si:C.

[0022] According to one embodiment, when forming the lower layer, the upper layer and the lower layer can be joined.

[0023] In one embodiment, the upper layer and lower layer can be joined by at least one or a combination thereof, of adhesive, heat, and pressure.

[0024] A method for regenerating a composite material component for semiconductor manufacturing equipment according to one embodiment is a method for regenerating an edge ring, which may include the steps of: forming a lower layer on the lower surface of the upper layer of a focus ring; and processing the shape of the focus ring to include the lower layer.

[0025] In one embodiment, the upper layer may include SiC or B4C, and the lower layer may include C / SiC or C / B4C.

[0026] In one embodiment, the step of forming the lower layer involves forming the lower layer on at least one of the lower surface, upper surface, and side surface of the focus ring, wherein the upper surface is the plasma exposure surface.

[0027] In one embodiment, the step of shaping the focus ring can be performed so that the C / SiC coating layer becomes the lower surface of the focus ring.

[0028] The step of shaping the focus ring according to one embodiment can be performed on a focus ring having an upper surface and a lower surface which are plasma exposed surfaces and which have a region designed for wafer mounting.

[0029] In one embodiment, the step of forming a lower surface on at least one surface of the focus ring includes the step of attaching a coating jig to at least one surface of the focus ring; the step of attaching the coating jig includes the step of attaching the coating jig to the upper surface of the focus ring and depositing the lower surface on at least one surface of the focus ring to which the jig is attached; and the step of depositing the lower layer includes depositing the lower layer on at least one surface excluding the surface on which the coating jig is formed, and removing the coating jig after the step of depositing the lower layer.

[0030] One embodiment may include the step of shaping the lower surface and / or the upper surface of the focus ring. [Effects of the Invention]

[0031] One embodiment of the present invention provides a component for semiconductor manufacturing equipment (e.g., an edge ring) and a method for manufacturing the same, which can prevent damage with excellent resistance in harsh environments in semiconductor manufacturing processes (e.g., environments using plasma, high temperature, high pressure, gas, etching, etc.), have excellent adhesion to other components (e.g., ceramic components) and semiconductor substrates (e.g., wafer substrates) within the semiconductor manufacturing equipment, and achieve process stability. One embodiment of the present invention provides an edge ring for semiconductor manufacturing equipment, in which, for example, the portion to which He gas for cooling is injected and moved in a semiconductor plasma processing process is made of a material having hardness similar to or lower than silicon (e.g., a C-rich material) (e.g., C / SiC or C / B4C) to increase adhesion to other ceramic components, and the portion exposed to the plasma is made of a high-hardness material (e.g., SiC or B4C) to solve the problems of plasma resistance and He gas leakage. [Brief explanation of the drawing]

[0032] [Figure 1a]One embodiment of the present invention shows the configuration of an edge ring in which an upper layer (e.g., a SiC layer or B4C) and a lower layer (e.g., C / SiC or C / B4C) are laminated according to the present invention.

[0033] [Figure 1b] An embodiment of the present invention shows the configuration of an edge ring in which an upper layer (e.g., a SiC layer or B4C), an adhesive layer, and a lower layer (e.g., C / SiC or C / B4C) are laminated according to the present invention.

[0034] [Figure 2] One embodiment of the present invention shows the change in Vickers hardness of a C / SiC material depending on the Si:C raw material ratio.

[0035] [Figure 3a] One embodiment of the present invention shows the crystal properties (XRD) of a SiC material layer (Si:C raw material ratio = 1:1 to 1.1) manufactured according to an embodiment of the present invention.

[0036] [Figure 3b] The crystal properties (XRD) of a C / SiC material (Si:C raw material ratio = 1:1.2~1.4) manufactured according to one embodiment of the present invention are shown.

[0037] [Figure 3c] The crystal properties (XRD) of a C / SiC material (Si:C raw material ratio = 1:1.5~1.6) manufactured according to one embodiment of the present invention are shown.

[0038] [Figure 4a] An embodiment of the present invention shows an SEM image of the surface of a C / SiC material with a Si:C raw material ratio (Si:C raw material ratio = 1:1.1).

[0039] [Figure 4b] An embodiment of the present invention shows an SEM image of the surface of a C / SiC material with a Si:C raw material ratio (Si:C raw material ratio = 1:1.2).

[0040] [Figure 4c] An embodiment of the present invention shows an SEM image of the surface of a C / SiC material with a Si:C raw material ratio (Si:C raw material ratio = 1:1.3).

[0041] [Figure 4d] An embodiment of the present invention shows an SEM image of the surface of a C / SiC material with a Si:C raw material ratio (Si:C raw material ratio = 1:1.4).

[0042] [Figure 4e] An embodiment of the present invention shows an SEM image of the surface of a C / SiC material with a Si:C raw material ratio (Si:C raw material ratio = 1:1.5).

[0043] [Figure 4f] An embodiment of the present invention shows an SEM image of the surface of a C / SiC material with a Si:C raw material ratio (Si:C raw material ratio = 1:1.6).

[0044] [Figure 5a] The crystalline properties (XRD) of a B4C (B / C=4) material manufactured according to one embodiment of the present invention are shown.

[0045] [Figure 5b] One embodiment of the present invention shows the crystalline properties (XRD) of a C / B4C (B / C=1.2) material manufactured according to the embodiment.

[0046] [Figure 5c] One embodiment shows the crystalline properties (XRD) of a C / B4C (B / C=0.6) composite material manufactured according to the embodiment.

[0047] [Figure 6] One embodiment of the present invention shows the change in Vickers hardness of a C / B4C composite material depending on the B / C ratio.

[0048] [Figure 7]One embodiment of the present invention illustrates the steps of a method for regenerating a composite material component for semiconductor manufacturing equipment according to the present invention (for example, a method for regenerating a focus ring).

[0049] [Figure 8] Another embodiment of the present invention illustrates the steps of a method for regenerating composite material components for semiconductor manufacturing equipment according to the present invention (for example, a method for regenerating a focus ring). [Modes for carrying out the invention]

[0050] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In the description of the present invention, if a specific description of a relevant known function or configuration is deemed to unnecessarily obscure the gist of the invention, such detailed description will be omitted. Furthermore, the terms used herein are those used to appropriately express preferred embodiments of the present invention, and these may vary depending on the intent of the user, operator, or the conventions of the art to which the present invention belongs. Therefore, the definitions of these terms should be based on the overall content of this specification. The same reference numerals shown in each drawing indicate the same component.

[0051] Throughout the specification, when a component is described as being located "on" another component, this includes not only cases where the component is in contact with another component, but also cases where there is an additional component between the two components.

[0052] When a part of the specification is described as "including" a certain component, this does not mean that it excludes other components, but rather that it may further include other components.

[0053] The edge ring for semiconductor manufacturing equipment and the manufacturing method thereof according to the present invention will be described in detail below with reference to embodiments and drawings. However, the present invention is not limited to these embodiments and drawings.

[0054] An edge ring according to one embodiment of the present invention includes an upper layer 110 having high hardness; and a lower layer 120 located below the upper layer and having lower hardness than the upper layer 110.

[0055] In one embodiment, the upper layer 110 includes SiC or B4C, and the lower layer 120 includes a C-rich material, which may include, for example, C / SiC or C / B4C. That is, the C-rich material (e.g., C / SiC or C / B4C) has high processability and lower hardness than the upper layer 110, thus solving the problem of He leakage development caused by the high hardness of the upper layer 110. In one embodiment of the present invention, the edge ring has a lower layer 120 in which amorphous carbon is uniformly distributed within SiC (e.g., CVD SiC) or B4C (e.g., CVD B4C), and a plasma-resistant CVD SiC or CVD B4C is formed in the plasma exposure region, thereby improving adhesion to other parts and preventing He leakage development. In other words, while CVD SiC or CVD B4C tend to reduce adhesion to other ceramic parts due to their high hardness, adhesion to other parts can be improved by using C / SiC or C / B4C materials containing amorphous carbon, which has a hardness similar to silicon.

[0056] In one embodiment, the upper layer 110 has a plasma-exposed surface, and the thickness of the upper layer 110 may be at least 1 mm; 1.5 mm; 1 mm to 10 mm; or 1 mm to 5 mm. The maximum or minimum thickness value may be selected from the values ​​mentioned. If it falls within the said thickness range, it can have plasma resistance and maintain adhesion when fixed to other ceramic components. In one embodiment, the upper layer 110 includes a portion A on which a semiconductor wafer substrate is placed, for example, the thickness a of portion A may be at least 1 mm; 1.5 mm; or 1 mm to 5 mm.

[0057] In one embodiment, the lower layer 120 is positioned to contact an internal component (e.g., quartz) of the plasma etching apparatus and includes fastening portions B for fixing and adhering to the internal component. The thickness of the lower layer 120 may be at least 0.2 mm; 0.3 mm; 0.5 mm; 0.2 mm to 10 mm; or 0.2 mm to 2 mm. The mentioned values ​​represent the maximum or minimum thickness. If the thickness falls within the aforementioned range, it can maintain adhesion when fixed to other ceramic components while having plasma resistance.

[0058] In one embodiment, the lower layer 120 is a lower surface having a contact surface with other parts (e.g., quartz), and includes fastening portions B for fixing and adhering to other parts, for example, the thickness b of the portion may be at least 0.2 mm; 0.3 mm; or 0.2 mm to 2 mm.

[0059] In one embodiment, the lower layer 120 includes a C / SiC material, and its properties can be adjusted by changing the ratio of raw materials during C / SiC deposition. For example, during deposition of the C / SiC composite layer 110, the Si:C raw material ratio may be 1:1.4~1:1.6; 1:1.4~1:1.6 (less than); 1:1.41~1:1.59; 1:1.44~1:1.57; 1:1.49~1:1.57; or 1:1.5~1:1.55. By controlling the raw material ratio, it is possible to prevent damage to semiconductor components due to collisions or impacts in semiconductor processes such as plasma environments, and to ensure appropriate Vickers hardness so that the edge ring adheres to other components.

[0060] In one embodiment, the lower layer 120 contains a C / B4C material, and the physical properties can be adjusted by the ratio of the raw materials during C / B4C deposition. The atomic ratio of B and C in the C / B4C material may be greater than 0, 1 to less than 4, 1; 0.1:1 to less than 4, 1; 0.2:1 to 3:1; 0.3:1 to 2:1; or 0.5:1 to 1.5:1. By controlling the atomic ratio, it is possible to prevent damage to semiconductor components due to collisions or impacts in semiconductor processes such as plasma environments, and to ensure appropriate Vickers hardness so that the edge ring adheres well to other components.

[0061] The Vickers hardness of the lower layer 120 (C / SiC or C / B4C) according to one embodiment is 1000 kg f / mm 2 ~2000 kg f / mm 2 and preferably may be similar to or have a low Vickers hardness like silicon.

[0062] When the Vickers hardness of the lower layer is less than 1000 kg f / mm 2 handling becomes difficult due to chipping caused by impacts or shocks with low hardness, and when the hardness of the lower layer exceeds 2000 kg f / mm 2 the high hardness reduces the adhesion to other components, and a He gas leakage problem may occur.

[0063] The lower layer 120 and the upper layer 110 according to one embodiment are formed by vapor deposition, and there may be a bonding layer-free (free, no adhesive layer) (Fig. 1a) between the lower layer 120 and the upper layer 110. This is because during the formation of the upper layer 110 (for example, CVD SiC or CVD B4C), the carbon source is increased from a certain thickness or more, and a dense C / SiC composite layer or C / B4C with improved adhesion to other ceramic components can be formed by a continuous CVD vapor deposition method.

[0064] The edge ring according to one embodiment is vapor-deposited by the CVD method. If the lower layer 120 is C / SiC, it can be vapor-deposited by continuously changing the raw material ratio of Si and C, and if the lower layer 120 is C / B4C, it can be vapor-deposited by continuously changing the raw material ratio of B and C.

[0065] When forming the upper layer 110 according to one embodiment, the upper layer 110 can be formed by CVD, reaction sintering, or sintering. When forming the lower layer 120 according to one embodiment, the lower layer 120 can be vapor-deposited on the upper layer 110.

[0066] In one embodiment, an upper layer 110 is formed on a substrate, the substrate may be graphite or the like, but is not limited thereto. The upper layer 110 according to one embodiment is formed by CVD, reaction sintering, or sintering, for example, at a temperature of 1100°C to 1700°C; or at a temperature of 1200°C to 1450°C to adjust the growth rate and raw material ratio. The conditions mentioned are process conditions applicable to CVD, reaction sintering, or sintering. For example, it may be carried out at a temperature of 1100°C to 1700°C; or at a temperature of 1200°C to 1450°C and a pressure of 700 torr to 760 torr to adjust the growth rate and raw material ratio. The conditions mentioned are process conditions applicable to CVD, reaction sintering, or sintering. In one embodiment, the Si:C raw material ratio or B:C raw material ratio applied during the deposition of each layer by the temperature, the pressure, or both can be selected within the range of the Si:C raw material ratio or B:C raw material ratio mentioned above to ensure the physical properties of the edge ring, which is a component for semiconductor manufacturing equipment of the present invention. When forming the lower layer 120 according to one embodiment, the lower layer 120 can be deposited by continuously changing the raw material ratio of B:C or Si:C.

[0067] In one embodiment, the lower layer 120 and the upper layer 110 may be joined to each other. For example, they may be joined using at least one of heat, pressure, and adhesive. When forming the lower layer 120 according to one embodiment, the upper layer 110 and the lower layer 120 may be joined. The joining of the upper layer 110 and the lower layer 120 according to one embodiment may be done through at least one or a combination of adhesive, heat, and pressure. As shown in Figure 1b according to one embodiment, an edge ring including an adhesive layer 130 can be formed between the upper layer 110 and the lower layer 120. For example, the upper layer 110 and the lower layer 120 may be formed on a substrate, and then bonded after applying an adhesive to the upper layer 110, the lower layer 120, or their surfaces. Heat, pressure, or both may be applied during bonding. The adhesive can be applied without limitation as long as it is applicable to ceramic bonding.

[0068] In one embodiment, the upper layer 110 and the lower layer 120 are formed on a substrate, and after being positioned so that they are in contact with each other, they can be joined by applying heat, pressure, or both.

[0069] In one embodiment, after forming the upper layer 110 and the lower layer 120, the material can be processed into a component shape (edge ​​ring). For example, the edge ring can be processed so that the lower end layer 120 (C / B4C layer or C / SiC layer), which is the part that comes into close contact with other components, is located there, and the upper end layer 110 (SiC layer or B4C layer), which is exposed to plasma and into contact with the semiconductor wafer, is located there. The specific form of the edge ring can be any form or processing method that is well known in the art of the present invention, and can be appropriately selected as long as it does not exceed the object and scope of the present invention, and is not specifically mentioned herein.

[0070] Embodiment 1

[0071] C / SiC materials were manufactured using the CVD method with the Si / C ratios shown in Table 2. XRD and Vickers hardness characteristics of the C / SiC materials were measured. The results are shown in Table 1 and Figure 2.

[0072] The Vickers hardness of the C / SiC material produced in Embodiment 1 was measured for the Si:C raw material ratio and process temperature, and is shown in Table 1 and Figure 2.

[0073] [Table 1]

[0074] Figures 3a to 3c show the XRD measurements of the CSiC material produced in Embodiment 1, depending on the Si:C raw material ratio and process temperature, and the XRD peak values ​​are shown in Tables 2 and 3.

[0075] Referring to Table 1, Figure 2, and Figures 3a-3c, it can be seen that when the Si:C raw material ratio is 1:1.5 or higher, crystalline SiC and crystalline carbon are formed, resulting in low hardness. The region where the Si:C raw material ratio is 1:1.44-1.49 is similar to the Vickers hardness of silicon and quartz, and can provide excellent adhesion to silicon and quartz materials. In other words, as shown in Table 1 and Figure 2, the hardness of the C / SiC material can be seen to change depending on the Si:C ratio, and the Vickers hardness of silicon is 2080 kg. f / mm 2 Therefore, it is advantageous to ensure adhesion with other parts when the Si:C raw material ratio is 1:1.44 to 1.48 at process temperatures of 1300°C to 1400°C, and 1:1.49 to 1.57, preferably 1:1.5 to 1.55, at 1200°C to 1300°C. This corresponds to a C / SiC material that can achieve hardness applicable to edge rings.

[0076] Table 2 shows the SiC(111) peak intensity values ​​obtained by measuring the XRD of the CSiC material produced in Embodiment 1, depending on the Si:C raw material ratio and process temperature.

[0077] [Table 2]

[0078] Table 3 shows the peak intensity values ​​of carbon obtained by measuring the XRD of the CSiC material produced in Embodiment 1, depending on the Si:C raw material ratio and process temperature.

[0079] [Table 3]

[0080] Tables 2 and 3 show the diffraction intensity of SiC(111) in the C / SiC material and the diffraction intensity of the carbon peak in the CSiC material, respectively, under each process condition. It can be confirmed that the diffraction intensity of SiC(111) decreases when the Si:C raw material ratio is 1:1.5 or higher and the process temperature is 1300°C or higher, and that the diffraction intensity of carbon increases with the increase in crystalline carbon.

[0081] Figure 3a shows the XRD pattern of CSiC material with a Si:C raw material ratio of 1:1 to 1.1 (deposition temperature: 1300°C), Figure 3b shows the XRD pattern of CSiC material with a Si:C raw material ratio of 1:1.2 to 1.4 (deposition temperature: 1300°C), and Figure 3c shows the XRD pattern of CSiC material with a Si:C raw material ratio of 1:1.5 to 1.6 (deposition temperature: 1300°C). In Figure 3c, it can be seen that the peak of crystalline carbon grew with increasing carbon raw material ratio.

[0082] Figures 4a, 4b, 4c, 4d, 4e, and 4f show SEM images of the C / SiC material layer of the composite material manufactured in Embodiment 1, depending on the Si:C raw material ratio. Figure 4a shows a Si:C raw material ratio of 1:1.1, Figure 4b shows a Si:C raw material ratio of 1:1.2, Figure 4c shows a Si:C raw material ratio of 1:1.3, Figure 4d shows a Si:C raw material ratio of 1:1.4, Figure 4e shows a Si:C raw material ratio of 1:1.5, and Figure 4f shows a Si:C raw material ratio of 1:1.6. In Figures 4a, 4b, 4c, 4d, 4e, and 4f, it can be seen that the microstructure of the surface of the C / SiC material changes as the Si:C raw material increases, and pores are formed.

[0083] Embodiment 2

[0084] B4C and SiC materials were manufactured using the CVD method. The plasma etching rates for each material were evaluated and are shown in Table 4.

[0085] [Table 4]

[0086] In Table 4, the etching improvement rate is a value related to CVD-B4C.

[0087] As shown in Table 4, it has been confirmed that the CVD B4C material has approximately 35% better plasma corrosion resistance than CVD SiC, and the present invention can provide an edge ring using the CVD B4C material which has excellent plasma corrosion resistance.

[0088] Embodiment 3

[0089] C / B4C materials were manufactured using the CVD method with the B / C ratios shown in Table 2. XRD and Vickers hardness characteristics of the C / B4C materials were measured. The results are shown in Table 5 and Figure 5.

[0090] [Table 5]

[0091] As shown in Figures 5a-5c, carbon and B4C peaks can be observed in the XRD pattern of CVD B4C material. It can be seen that the intensity of the carbon peak increases as the B / C ratio decreases.

[0092] As shown in Figure 6 and Table 5, the hardness of CVD B4C material tends to decrease with decreasing B / C ratio. Here, the Vickers hardness of silicon is approximately 2080 kg. f / mm 2 Therefore, if the B / C ratio is 1.2 or less, it has a lower hardness than silicon, which ensures good adhesion with other parts.

[0093] Vickers hardness of 500 kg f / mm 2 Below 1000kg, the material may become difficult to handle due to chipping caused by impact or collision, so the limit is 1000kg. f / mm 2 The above can be achieved with a B / C ratio of 1 to 1.2 for CB4C.

[0094] This invention involves joining B4C, which has a B / C ratio of 4, with silicon or a C-rich boron carbide (CBC) material with a B / C ratio of 1 to 1.2, by a physical or chemical joining method. Such a joined material can be used as an edge ring material. Specifically, in the edge ring, the silicon or C-rich boron carbide portion may be configured as the part that comes into contact with other ceramic parts, while the B4C portion may be configured as the part exposed to plasma. Edge rings having such a configuration can have improved plasma durability and adhesion to other parts.

[0095] The present invention can provide an edge ring in which a C / B4C or C / SiC material with a high C component and hardness similar to silicon is formed in the part where adhesion to other ceramic parts is required. This ensures plasma resistance with CVD SiC while solving the low adhesion and gas leakage of He that are already present due to the high hardness of CVD SiC.

[0096] A method for regenerating a composite material component for semiconductor manufacturing equipment according to one embodiment is a method for regenerating an edge ring, comprising the steps of: forming a lower layer on the lower surface of the upper layer of a focus ring; and processing the shape of the focus ring to include the lower layer.

[0097] Figure 7 illustrates the steps of a method for regenerating a composite material component for semiconductor manufacturing equipment (for example, a method for regenerating a focus ring) according to one embodiment of the present invention.

[0098] Figure 8 illustrates, according to another embodiment of the present invention, the steps of a method for regenerating composite material components for semiconductor manufacturing equipment according to the present invention (for example, a method for regenerating a focus ring).

[0099] Referring to Figures 7 and 8, Figures 7 and 8 illustrate the steps of the regeneration method depending on the configuration of the focus ring 100 used. In Figure 7, the steps include: attaching a coating jig 200 to the top surface S110; depositing a C / SiC coating layer 300 around the bottom and side surfaces S120; removing the jig 200 S130; processing the C / SiC coating layer 300 S210; and processing the top surface S220. The C / SiC coating layer 300 can be processed in step S130 when the jig 200 is removed.

[0100] In Figure 8, the process includes steps S110 of attaching a coating jig 200 to the upper surface, S120 of depositing a C / SiC coating layer 300 so as to surround the lower and side surfaces, S130 of removing the jig 200, and S220 of processing the upper surface.

[0101] Step S220, which processes the upper surface, removes the silicon or SiC layer damaged by etching or other means from the used focus ring.

[0102] In one embodiment, the upper layer comprises SiC or B4C, and the lower layer comprises C / SiC or C / B4C.

[0103] In one embodiment, the step of forming the lower layer involves forming the lower layer on at least one of the lower surface, upper surface, and side surface of the focus ring, wherein the upper surface is the plasma exposure surface.

[0104] In one embodiment, the step of shaping the focus ring can be performed so that the C / SiC coating layer becomes the lower surface of the focus ring.

[0105] The step of shaping the focus ring according to one embodiment can be performed on a focus ring having an upper surface and a lower surface which are plasma exposed surfaces and which have a region designed for wafer mounting.

[0106] In one embodiment, the step of forming a lower surface on at least one surface of the focus ring includes the step of attaching a coating jig to at least one surface of the focus ring; the step of attaching the coating jig includes the step of attaching the coating jig to the upper surface of the focus ring and depositing the lower surface on at least one surface of the focus ring to which the jig is attached; and the step of depositing the lower layer includes depositing the lower layer on at least one surface excluding the surface on which the coating jig is formed, and removing the coating jig after the step of depositing the lower layer.

[0107] The step of shaping the lower surface and / or upper surface of the focus ring according to one embodiment may be included.

[0108] As described above, although the embodiments have been illustrated with limited embodiments and figures, a person with ordinary skill in the art can make various modifications and variations from the aforementioned base material. For example, the described techniques may be performed in a different order than described, and / or the described components may be combined or combined in a different manner than described, or substituted or replaced with other components or equivalents, and still achieve the desired results. Therefore, the scope of the present invention is not limited to the disclosed embodiments, but is defined by the claims and equivalents thereof.

Claims

1. An upper layer having high hardness, It includes a lower layer located below the upper layer and having a lower hardness than the upper layer, The lower layer is positioned to contact the internal components of the plasma etching apparatus, thereby forming an edge ring.

2. The upper layer is made of SiC or B ４ The edge ring according to claim 1, formed of C.

3. The edge ring according to claim 1, wherein the thickness of the upper layer is 1 mm or more.

4. The lower layer is C / SiC or C / B ４ The edge ring according to claim 1, comprising C.

5. The lower layer is made of C / SiC material. The edge ring according to claim 4, wherein the Si:C atomic ratio is 1:1.4 to 1:1.

6.

6. The aforementioned lower layer is C / B ４ It is made of C material, The edge ring according to claim 4, wherein the atomic ratio of B:C is greater than 0:1 to less than 4:

1.

7. The Vickers hardness of the lower layer is 1000 kgf / mm² to 2000 kgf / mm². ２ The edge ring according to claim 1.

8. The edge ring according to claim 1, wherein the thickness of the lower layer is 0.2 mm or more.

9. The edge ring according to claim 1, wherein the lower layer is formed by vapor deposition on the upper layer.

10. The aforementioned edge ring is deposited by CVD. If the lower layer is C / SiC, the raw material ratio of Si and C is continuously changed during deposition. The lower layer is C / B ４ If C is present, the edge ring according to claim 9, wherein the raw material ratio of B and C is continuously changed and vapor deposition is performed.

11. Forms a high-hardness upper layer, It forms a lower layer with lower hardness compared to the upper layer. A method for manufacturing edge rings by processing them in component form.

12. When forming the upper layer, The edge ring manufacturing method according to claim 11, wherein the upper layer is formed by CVD, reaction sintering, or sintering.

13. When forming the lower layer, The method for manufacturing an edge ring according to claim 11, wherein the lower layer is deposited on the upper layer.

14. When forming the lower layer, The edge ring manufacturing method according to claim 13, wherein the lower layer is deposited by continuously changing the raw material ratio of B:C or Si:C.

15. A method for restoring edge rings according to claim 1, The steps include forming a lower layer on the lower surface of the upper layer of the focus ring, The steps include: shaping the focus ring to include the lower layer, A method for recycling composite material components for semiconductor manufacturing equipment, including [the specified component].

16. The upper layer is made of SiC or B ４ Including C, The lower layer is C / SiC or C / B ４ A method for regenerating a composite material component for semiconductor manufacturing equipment according to claim 15, including C.

17. The step of forming the lower layer is, The lower layer is formed on at least one of the lower surface, upper surface, and side surface of the focus ring. The method for regenerating a composite material component for semiconductor manufacturing equipment according to claim 15, wherein the upper surface is a plasma-exposed surface.

18. The step of processing the shape of the focus ring is: A method for regenerating a SiC composite material component for semiconductor manufacturing equipment according to claim 15, wherein the C / SiC coating layer is shaped so that it becomes the lower surface of the focus ring.

19. The step of processing the shape of the focus ring is: It has an area designed for wafer placement, with an upper surface which is the plasma exposure surface, A method for regenerating a composite material component for semiconductor manufacturing equipment according to claim 15, wherein the shape is processed using a focus ring that includes the lower surface.

20. The step of forming a lower surface on at least one surface of the focus ring is: The step includes attaching a coating jig to at least one surface of the focus ring, The step of attaching the coating jig is, A coating jig is attached to the upper surface of the focus ring, The steps include: depositing the lower surface onto at least one surface of the focus ring to which the jig is attached; Includes, The step of depositing the lower layer is, The lower layer is deposited on at least one surface excluding the surface on which the coating jig is formed. A method for regenerating a composite material component for semiconductor manufacturing equipment according to claim 15, further comprising the step of removing a coating jig after the step of depositing the lower layer.

21. A method for regenerating a composite material component for semiconductor manufacturing equipment according to claim 15, comprising the step of shaping the lower surface and / or upper surface of the focus ring.

Images