Smart IC board, smart IC module, and IC card containing the same

Abstract

The smart IC substrate according to the embodiment includes a substrate having a first surface and a second surface opposite to the first surface, a bonding layer disposed on the first surface, a buffer layer disposed on the bonding layer, a metal layer disposed on the buffer layer, and a plating layer disposed on the other surface of the metal layer, wherein the metal layer comprises an alloy containing nickel (Ni), iron (Fe), and chromium (Cr), the buffer layer comprises a first buffer layer and a second buffer layer, the first buffer layer is disposed between the second buffer layer and the metal layer, the second buffer layer comprises a 2-1 buffer layer and a 2-2 buffer layer, the 2-1 buffer layer is disposed between the first buffer layer and the 2-2 buffer layer, and the surface roughness of the 2-2 buffer layer is greater than the surface roughness of the 2-1 buffer layer.

Claims

1. A substrate having a first surface and a second surface opposite to the first surface, A bonding layer disposed on the first surface, A buffer layer disposed on the bonding layer, A metal layer disposed on the buffer layer, The metal layer includes a plating layer disposed on the other surface of the metal layer, The aforementioned metal layer comprises an alloy containing nickel (Ni), iron (Fe), and chromium (Cr). The buffer layer includes the first buffer layer and the second buffer layer, The first buffer layer is disposed between the second buffer layer and the metal layer. The aforementioned second buffer layer includes a second-first buffer layer and a second-second buffer layer, The 2-1 buffer layer is positioned between the 1 buffer layer and the 2-2 buffer layer. A smart IC substrate in which the surface roughness of the 2-2 buffer layer is greater than that of the 2-1 buffer layer.

2. The first buffer layer and the second-first buffer layer contain metal, The smart IC substrate according to claim 1, wherein the 2-2 buffer layer contains a metal oxide.

3. The plating layer includes a first plating layer disposed below the metal layer and a second plating layer below the first plating layer. The smart IC substrate according to claim 1, wherein the first buffer layer and the first plating layer contain the same metal.

4. The smart IC substrate according to claim 3, wherein the thickness of the first plating layer is greater than the thickness of the first buffer layer.

5. Multiple holes are formed that penetrate the substrate and the bonding layer. The metal layer includes a first region that does not overlap with the hole and a second region that overlaps with the hole. The buffer layer is arranged on the first region, The buffer layer is not placed on the second region. The smart IC substrate according to claim 1, wherein the plating layer is in contact with the metal layer.

6. Multiple holes are formed that penetrate the substrate and the bonding layer. The metal layer includes a first region that does not overlap with the hole and a second region that overlaps with the hole. A first buffer layer and a second buffer layer are arranged on the first region. The first buffer layer and the second-first buffer layer are arranged on the second region. The smart IC substrate according to claim 1, wherein the plating layer is in contact with the second-first buffer layer.

7. The smart IC substrate according to claim 6, wherein the thickness of the second-first buffer layer in the second region is greater than the thickness of the second-first buffer layer in the first region.

8. The aforementioned plating layer includes a second plating layer disposed beneath the metal layer, The second plating layer comprises at least one of gold, silver, and palladium. The smart IC substrate according to claim 1, wherein the thickness of the first buffer layer is greater than the thickness of the second buffer layer and the second plating layer.

9. Multiple holes are formed that penetrate the substrate and the bonding layer. The metal layer includes a first region that does not overlap with the hole and a second region that overlaps with the hole. A first buffer layer and a second buffer layer are arranged on the first region. The first buffer layer is placed on the second region. The smart IC substrate according to claim 8, wherein the second plating layer is in contact with the first buffer layer.

10. Multiple holes are formed that penetrate the substrate and the bonding layer. The metal layer includes a first region that does not overlap with the hole and a second region that overlaps with the hole. A first buffer layer and a second buffer layer are arranged on the first region. The first buffer layer is placed on the second region. The smart IC substrate according to claim 1, wherein the plating layer includes a first plating layer in contact with the first buffer layer and a second plating layer below the first plating layer.

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