Method for manufacturing embedded element package substrate, package substrate and semiconductor

Abstract

To provide a method for manufacturing an embedded device package substrate, a package substrate, and a semiconductor, capable of improving bonding force of material and reducing risk of stratification due to subsequent heating.SOLUTION: A method for manufacturing an embedded device package substrate comprises the steps of: forming a first circuit layer; laminating a first photosensitive layer onto the first circuit layer; disposing an embedded device on the first photosensitive layer, where a pin surface of the embedded device is disposed opposite to the first photosensitive layer; disposing a second photosensitive layer, where the second photosensitive layer covers the embedded device; partially removing the first dielectric layer such that minimum thickness of the first dielectric layer covering a side surface of the embedded device is greater than or equal to a preset threshold; disposing a second dielectric layer, where the second dielectric layer covers the first dielectric layer; and forming a second circuit layer on the second dielectric layer, where the second circuit layer is electrically connected to the first circuit layer and the embedded device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to the technical field of semiconductor fabrication, and in particular to a method for fabricating an embedded device package substrate, a package substrate, and a semiconductor. [Background technology]

[0002] In the past, when manufacturing a substrate that requires embedded elements, the method of embedding the element in a frame was generally used. In the conventional embedded element method, when the CCL method is adopted, it is difficult to control the thickness of the frame, and it is limited by the thickness of the CCL material. In addition, the efficiency of the mechanical gong and laser method is poor, which is disadvantageous for mass production. When the coreless process is adopted, the process flow is complicated, the finished product is expensive, and the main material is organic material, so the overall mechanical strength is relatively small, which is not suitable for products that require high strength. In the frameless design, the materials at the bottom and sides of the embedded element are generally different types of materials, and the two materials have the risk of failure in the subsequent high heat environment due to the difference in CTE, and the bonding interface between the two has the problem of poor bonding strength, which causes the risk of layering. Therefore, a new method for manufacturing embedded element package substrates is urgently needed. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present disclosure is to solve, at least to some extent, one of the technical problems existing in the prior art.

[0004] Therefore, one object of an embodiment of the present disclosure is to provide a method for fabricating an embedded element package substrate, a package substrate, and a semiconductor, which can improve the bonding strength of materials and reduce the risk of layering due to subsequent heating. [Means for solving the problem]

[0005] In order to achieve the above technical objective, the technical solution adopted in the embodiment of the present disclosure includes a method for fabricating an embedded element package substrate, the method for fabricating the embedded element package substrate includes the steps of: fabricating a first circuit layer; pressing a first photosensitive layer on the first circuit layer; placing an embedded element on the first photosensitive layer, where the pin surface of the embedded element is placed opposite the first photosensitive layer; placing a second photosensitive layer, where the second photosensitive layer covers the embedded element, and the first photosensitive layer and the second photosensitive layer are made of the same material, and the first photosensitive layer and the second photosensitive layer form a first dielectric layer; partially removing the first dielectric layer so that the minimum thickness of the first dielectric layer covering the side surface of the embedded element is equal to or greater than a preset threshold; placing a second dielectric layer, where the second dielectric layer covers the first dielectric layer; and fabricating a second circuit layer on the second dielectric layer, which is conductive with the first circuit layer and the embedded element.

[0006] In addition, the method for fabricating an embedded device package substrate according to the above embodiment of the present disclosure may further have the following additional technical features. Furthermore, in an embodiment of the present disclosure, the step of fabricating a second circuit layer on the second dielectric layer that is conductive with the first circuit layer and the embedded element specifically includes a step of fabricating a first conductive copper pillar and a second conductive copper pillar, where the first conductive copper pillar is used to connect the first circuit layer and the second circuit layer, and the second conductive copper pillar is used to connect the second circuit layer and the embedded element, and a step of fabricating a second circuit layer that is conductive with the first circuit layer and the embedded element by the first conductive copper pillar and the second conductive copper pillar.

[0007] Furthermore, in an embodiment of the present disclosure, the step of preparing a second circuit layer that is conductive to the first circuit layer and the embedded element by the first conductive copper pillar and the second conductive copper pillar specifically includes the steps of preparing a metal seed layer connected to the first conductive copper pillar and the second conductive copper pillar, and performing a photosensitive film attachment, exposure development and pattern plating process on the metal seed layer to obtain a second circuit layer connected to the first conductive copper pillar and the second conductive copper pillar.

[0008] Furthermore, in an embodiment of the present disclosure, the step of preparing a first conductive copper pillar and a second conductive copper pillar specifically includes a step of exposing the first circuit layer and exposing the pin surface of the embedded element by a laser drilling process to form a first conductive hole and a second conductive hole, and a step of forming the first conductive copper pillar and the second conductive copper pillar in the first conductive hole and the second conductive hole, respectively, by a hole-filling plating process.

[0009] Further, in an embodiment of the present disclosure, the materials of the first photosensitive layer and the second photosensitive layer both comprise a viscous photosensitive material.

[0010] Furthermore, in an embodiment of the present disclosure, the second dielectric layer comprises a resin-based dielectric material.

[0011] Furthermore, in an embodiment of the present disclosure, the preset threshold is 3 um.

[0012] Meanwhile, an embodiment of the present disclosure further provides an embedded element package substrate, wherein the embedded element package substrate includes a first circuit layer, an embedded element, a second circuit layer, a first dielectric layer, and a second dielectric layer, wherein the first dielectric layer includes a first photosensitive layer and a second photosensitive layer, the first dielectric layer covers the embedded element, the second dielectric layer covers the first dielectric layer, the second dielectric layer is disposed between the first circuit layer and the second circuit layer, the first circuit layer is connected to the second circuit layer, and the second circuit layer is connected to the embedded element.

[0013] Furthermore, in an embodiment of the present disclosure, the wiring board further includes a first conductive copper pillar and a second conductive copper pillar, the first conductive copper pillar being used to electrically connect the first circuit layer and the second circuit layer, and the second conductive copper pillar being used to electrically connect the second circuit layer and the embedded element.

[0014] The present disclosure further provides a semiconductor, the semiconductor including the package substrate according to any one of the above embodiments. Effect of the Invention

[0015] The advantages and beneficial effects of the present disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. The present disclosure uses a photosensitive layer to bond the embedded element, and then uses a photosensitive layer of the same material to package the embedded element, embed the embedded element to a certain thickness threshold by exposure and development, and then embed the photosensitive layer and the dielectric layer by a second dielectric layer to prepare a second circuit layer, and finally obtain an embedded element package substrate. The photosensitive layer at the bottom of the embedded element and the material at the side of the embedded element are the same material, and are consistent as a whole, which can improve the bonding strength of the material and reduce the risk of layering caused by subsequent heating. The present disclosure embeds the embedded element to a certain thickness threshold before pressing the second dielectric layer, and can protect the embedded element, and the present disclosure subsequently uses the covered second dielectric layer to improve the strength of the finished product and reduce the risk of plate cracking. [Brief description of the drawings]

[0016] [Figure 1] 4 is a flow chart of a method for fabricating an embedded device package substrate according to an exemplary embodiment of the present disclosure. [Diagram 2] 1 is a schematic diagram showing a structure of a package substrate according to a specific embodiment of the present disclosure. [Diagram 3] 1A to 1C are schematic diagrams illustrating changes in substrate structure in a method for fabricating an embedded device package substrate according to a specific embodiment of the present disclosure. [Figure 4]10A to 10C are schematic diagrams illustrating changes in the substrate structure in a method for fabricating another embedded device package substrate according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings, and the manufacturing method of the embedded device package substrate, the structure of the package substrate, and the principles and processes of the semiconductor including the package substrate in the embodiments of the present disclosure will be described below.

[0018] Referring to FIG. 1, the method for fabricating an embedded device package substrate of the present disclosure includes the following steps. Step S1: A first circuit layer is prepared. In this step, a first circuit layer can be fabricated on the semi-finished substrate, the mounting plate, or the temporary mounting plate. The first circuit layer can be designed according to specific needs, and the first circuit layer can be fabricated by a conventional process such as fabricating a metal seed layer, attaching a photosensitive film to the seed layer, exposing and developing, and etching, or can be obtained by a plating process. The specific fabrication method of the first circuit layer is not limited here. In the present disclosure, the number of layers of the first circuit layer is not limited to one, and the first circuit layer can be composed of multiple circuit layers that are conductive with each other.

[0019] Step S2: A first photosensitive layer is pressed onto the first circuit layer. In this step, after the preparation of the first circuit layer is completed, a first photosensitive layer can be pressed onto the first circuit layer. During pressing, the first photosensitive layer may completely cover the entire first circuit layer, or may partially cover the first circuit layer. When the first photosensitive layer completely covers the first circuit layer, the first photosensitive layer and the first circuit layer completely overlap when projected in a direction perpendicular to the circuit layer, and when the first photosensitive layer partially covers the first circuit layer, the area of ​​the first photosensitive layer is smaller than the area of ​​the first circuit layer when projected in a direction perpendicular to the circuit layer.

[0020] Step S3: A buried element is disposed on the first photosensitive layer, and the pin surface of the buried element is disposed opposite to the first photosensitive layer. In this step, an embedded element may be placed on the first photosensitive layer, and the pin surface of the embedded element needs to be placed facing the first photosensitive layer during installation; specifically, when the embedded element is bonded from top to bottom during installation, the back surface of the embedded element, i.e., the non-pin surface, can be bonded to the first photosensitive layer, and the pin surface of the embedded element faces upward.

[0021] Step S4: providing a second photosensitive layer, the second photosensitive layer covering the embedded element, the material of the first photosensitive layer and the second photosensitive layer being the same, and the first photosensitive layer and the second photosensitive layer forming a first dielectric layer. In this step, a second photosensitive layer may be installed on the first photosensitive layer and the embedded element, so that the second photosensitive layer can completely cover the first photosensitive layer and the embedded element, and the installation may be performed by mechanical pressing or coating. The material of the second photosensitive layer may be the same as that of the first photosensitive layer, and the photosensitive layer made of the same material can improve the bonding strength of the material of the photosensitive layer and reduce the risk of layering due to subsequent heating. After the second photosensitive layer is installed, the first photosensitive layer and the second photosensitive layer can form a first dielectric layer, which can completely cover the first circuit layer and encapsulate the embedded element.

[0022] Step S5: The first dielectric layer is partially removed so that the minimum thickness of the first dielectric layer covering the side surfaces of the embedded element becomes equal to or greater than a preset threshold value. In this step, the first dielectric layer can be partially removed by a conventional process such as photolithography and etching. The first circuit layer can be exposed during removal, or the first circuit layer can be left unexposed, but the minimum thickness of the first dielectric layer on the side of the embedded element must be equal to or greater than a certain preset threshold during removal. At the certain preset threshold thickness, the photosensitive layer on the side can protect the embedded element from being damaged in the subsequent bonding process and affecting its performance.

[0023] Step S6: A second dielectric layer is provided, and the second dielectric layer covers the first dielectric layer. In this step, after the first dielectric layer is partially removed, a second dielectric layer may be installed on the first dielectric layer, or on the first dielectric layer and the first circuit layer, and the second dielectric layer may completely cover the first dielectric layer, or completely cover the first dielectric layer and the first circuit layer, or may be installed by mechanical physical compression during installation.

[0024] Step S7: A second circuit layer that is electrically connected to the first circuit layer and the embedded element is formed on the second dielectric layer. In this step, after the second dielectric layer is pressed, a second circuit layer connected to the first circuit layer must be fabricated on the second dielectric layer. The first circuit layer and the second circuit layer, and the second circuit layer and the embedded element can be connected by conductive copper columns. In the present disclosure, the number of layers of the second circuit layer is not limited to one, and the second circuit layer may be composed of multiple circuit layers that are conductive to each other.

[0025] Furthermore, the step of fabricating a second circuit layer on the second dielectric layer, which is conductive with the first circuit layer and the embedded element, may specifically include the following steps: Step S21: preparing a first conductive copper pillar and a second conductive copper pillar, the first conductive copper pillar being used to connect the first circuit layer and the second circuit layer, and the second conductive copper pillar being used to connect the second circuit layer and the embedded element. Step S22: A second circuit layer is formed by the first conductive copper pillar and the second conductive copper pillar, the second circuit layer being electrically connected to the first circuit layer and the embedded element.

[0026] In this embodiment, the first conductive copper pillar and the second conductive copper pillar may be prepared first. The first conductive copper pillar may be used to conduct the first circuit layer and the second circuit layer. When the first dielectric layer and the second dielectric layer exist between the first circuit layer and the second circuit layer, the first conductive copper pillar needs to penetrate the first dielectric layer and the second dielectric layer. When only the second dielectric layer exists between the first circuit layer and the second circuit layer, the first conductive copper pillar needs to penetrate the second dielectric layer, and the second conductive copper pillar needs to penetrate the first dielectric layer and the second dielectric layer. After preparing the first conductive copper pillar and the second conductive copper pillar, the second circuit layer may be directly prepared by a plating process, or the second circuit layer may be prepared by first preparing a metal seed layer, and then covering the metal seed layer with a photosensitive film, and carrying out conventional processes such as exposure, development and etching to prepare the second circuit layer.

[0027] Furthermore, the step of fabricating a second circuit layer that is conductive to the first circuit layer and the embedded element by the first conductive copper pillar and the second conductive copper pillar may specifically include the following steps. Step S31: preparing a metal seed layer connected to the first conductive copper pillar and the second conductive copper pillar. Step S32: A photosensitive film is attached to the metal seed layer, and a process of exposure, development and pattern plating is carried out to obtain a second circuit layer connected to the first conductive copper pillar and the second conductive copper pillar.

[0028] In this embodiment, a metal seed layer is first prepared, a photosensitive film is attached to the metal seed layer, and the photosensitive film is subjected to conventional processes such as an exposure and development process and pattern plating, thereby finally obtaining a second circuit layer connected to the first conductive copper pillar and the second conductive copper pillar.

[0029] Furthermore, the step of fabricating the first conductive copper pillar and the second conductive copper pillar may specifically include the following steps. Step S41: Expose the first circuit layer and expose the pin surface of the embedded element through a laser drilling process to form a first through hole and a second through hole. Step S42: Form the first conductive copper pillar and the second conductive copper pillar in the first conductive hole and the second conductive hole, respectively, by a hole filling plating process. In this embodiment, the dielectric layer may be drilled by laser drilling or other drilling process to form a first conductive hole and a second conductive hole, to expose the first circuit layer and to expose the pin surface of the embedded element. Then, a hole-filling plating process is used to form a first conductive copper pillar and a second conductive copper pillar penetrating the dielectric layer in the first conductive hole and the second conductive hole. The first conductive copper pillar can connect the first circuit layer and the second circuit layer, and the second conductive copper pillar can connect the embedded element and the second circuit layer.

[0030] Furthermore, in some embodiments of the present disclosure, the first photosensitive layer and the second photosensitive layer may both be a viscous photosensitive material, which can increase the adhesion between the embedded element and the first photosensitive layer and stabilize the embedded element, and the viscous photosensitive material can also increase the adhesion between the second photosensitive layer and the second dielectric layer, increase the bonding strength between the two, and reduce the risk of layering.

[0031] Furthermore, in some embodiments of the present disclosure, the second dielectric layer may include a resin-based dielectric material. The second dielectric layer material may use other materials with higher structural strength than the viscous photosensitive material, such as glass fiber-reinforced PP material, composite materials made by synthesizing resin-based materials with other materials, etc. Materials with higher structural strength can further reduce the risk of layering, and can also reduce the risk of cracking of the substrate during subsequent process fabrication and specific use.

[0032] Further, in some embodiments of the present disclosure, the preset threshold may be 3 um, which can protect the embedded elements from being damaged by conditions such as compression, high temperature, etc. in subsequent processes, and can further ensure the functionality of the elements and the finished product.

[0033] It should be noted that, corresponding to the method of Fig. 1, an embodiment of the present disclosure further provides a package substrate. Referring to Fig. 2, the package substrate may include a first circuit layer 201, an embedded element 202, a second circuit layer 203, a first dielectric layer 204, and a second dielectric layer 205. Here, the first dielectric layer 204 may include a first photosensitive layer and a second photosensitive layer, the first dielectric layer 204 may cover the embedded element 202, the second dielectric layer 205 may cover the first dielectric layer 204, the second dielectric layer 205 may be disposed between the first circuit layer 201 and the second circuit layer 203, the first circuit layer 201 may be connected to the second circuit layer 203, and the second circuit layer 203 is connected to the embedded element 202.

[0034] 2 , in some embodiments of the present disclosure, the package substrate may further include a first conductive copper pillar 206 and a second conductive copper pillar 207. The first conductive copper pillar 206 is used to electrically connect the first circuit layer 201 and the second circuit layer 203, and the second conductive copper pillar 207 is used to electrically connect the second circuit layer 203 and the embedded element 202.

[0035] The contents of the above method embodiments all apply to the embodiments of this package substrate, the functions specifically realized by the embodiments of this package substrate are the same as those of the above method embodiments, and the beneficial effects achieved are the same as those achieved by the above method embodiments.

[0036] In addition, corresponding to the package substrate of the above-described embodiments, an embodiment of the present disclosure further provides a semiconductor, and the semiconductor may include the package substrate according to any one of the above-described embodiments.

[0037] The contents of the above package substrate embodiments are all applicable to the present semiconductor embodiment, the functions specifically realized by the present semiconductor embodiment are the same as those of the above package substrate embodiment, and the beneficial effects achieved by the present semiconductor embodiment are the same as those achieved by the above package substrate embodiment.

[0038] Hereinafter, a method for fabricating an embedded device package substrate according to the present disclosure will be described with reference to the drawings.

[0039] (Embodiment 1) In this embodiment, the first photosensitive layer and the second photosensitive layer are made of a viscous photosensitive material, and the preset threshold value is set to 3 um.

[0040] Referring to a-f in FIG. 3, a first circuit layer 302 is prepared on a mounting plate 301 by a conventional process, a first viscous photosensitive layer 303 is pressed onto the first circuit layer 302, and then an embedded element 304 is placed on the first viscous photosensitive layer 303, and the pins of the embedded element 304 are facing up when placed on the first viscous photosensitive layer 303, and the back surface of the embedded element 304 is bonded to the first viscous photosensitive layer 303. Then, the first viscous photosensitive layer 303 and the embedded element 304 are covered with a second viscous photosensitive layer 305, and the first viscous photosensitive layer 303 and the second viscous photosensitive layer 305 form a first dielectric layer 306. Then, the first dielectric layer 306 may be partially removed to set the minimum thickness of the first dielectric layer 306 covering the side surface of the embedded element 304 to 3 um or more and expose the first circuit layer 302; then, the second dielectric layer 307 may be pressure-bonded to the first dielectric layer 306 and the first circuit layer 302, where the second dielectric layer 307 covers the first dielectric layer 306 and the first circuit layer 302, and the first dielectric layer 306 covers the embedded element 304; finally, a second circuit layer 308 that is electrically connected to the first circuit layer 302 and the embedded element 304 is formed on the second dielectric layer 307.

[0041] (Embodiment 2) In this embodiment, the first photosensitive layer and the second photosensitive layer are made of a viscous photosensitive material, and the preset threshold value is set to 3 um.

[0042] Referring to a to f in FIG. 4, a first circuit layer 402 is prepared on a support plate 401 by a conventional process, and then a first viscous photosensitive layer 403 is pressed onto the first circuit layer 402. Then, an embedded element 404 is placed on the first viscous photosensitive layer 403, and when placed, the pins of the embedded element 404 face up, and the back surface of the embedded element 404 is bonded to the first viscous photosensitive layer 403. Then, the first viscous photosensitive layer 403 and the embedded element 404 are covered with a second viscous photosensitive layer 405, and the first viscous photosensitive layer 403 and the second viscous photosensitive layer 405 are bonded to the first viscous photosensitive layer 405. A dielectric layer 406 can be formed, then the first dielectric layer 406 is partially removed, and the minimum thickness of the first dielectric layer 406 covering the side of the embedded element 404 is 3 um or more, and then the second dielectric layer 407 can be pressed onto the first dielectric layer 406, where the second dielectric layer 407 covers the first dielectric layer 406, and the first dielectric layer 406 covers the embedded element 404 and the first circuit layer 402, and finally, a second circuit layer 408 that is conductive with the first circuit layer 402 and the embedded element 404 is formed on the second dielectric layer 407.

[0043] In some alternative embodiments, the functions / operations noted in the block diagrams may not occur in the order noted in the operational diagrams. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functions / operations involved. It should be noted that the embodiments shown and described in the flowcharts of the present disclosure are provided in an exemplary manner to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are executed independently.

[0044] In the above description of the present specification, the term "one embodiment / example," "another embodiment / example," or "some embodiments / examples" means that the specific features, structures, materials, or characteristics described in connection with an embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. And, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0045] Although embodiments of the present disclosure have been shown and described, as will be understood by those skilled in the art, various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present disclosure, and the scope of the present disclosure is limited only by the claims and their equivalents.

[0046] Although the above describes a preferred embodiment of the present disclosure in detail, the present disclosure is not limited to the above-described embodiment. A person skilled in the art may make various equivalent modifications or replacements without departing from the spirit of the present disclosure, and all of these equivalent modifications or replacements are included in the scope limited by the claims of the present disclosure.

Claims

1. 1. A method of making an embedded device package substrate, comprising: creating a first circuit layer; pressing a first photosensitive layer onto the first circuit layer; placing a buried element on the first photosensitive layer, a pin surface of the buried element facing the first photosensitive layer; providing a second photosensitive layer, the second photosensitive layer covering the embedded elements, the material of the first photosensitive layer and the second photosensitive layer being the same, and the first photosensitive layer and the second photosensitive layer forming a first dielectric layer; a step of partially removing the first dielectric layer so that a minimum thickness of the first dielectric layer covering a side surface of the embedded element becomes equal to or greater than a preset threshold; providing a second dielectric layer, the second dielectric layer covering the first dielectric layer and surrounding sides of the first dielectric layer; and forming a second circuit layer on the second dielectric layer, the second circuit layer being electrically connected to the first circuit layer and the embedded device.

2. The step of forming a second circuit layer on the second dielectric layer, the second circuit layer being conductive with the first circuit layer and the embedded element, specifically includes: Fabricating a first conductive copper pillar and a second conductive copper pillar, the first conductive copper pillar being used to connect the first circuit layer and the second circuit layer, and the second conductive copper pillar being used to connect the second circuit layer and the embedded element; 2. The method for manufacturing an embedded element package substrate according to claim 1, further comprising the step of: forming a second circuit layer that is conductive with the first circuit layer and the embedded element by the first conductive copper pillar and the second conductive copper pillar.

3. The step of forming a second circuit layer electrically connected to the first circuit layer and the embedded element by the first conductive copper pillar and the second conductive copper pillar specifically includes: preparing a metal seed layer connected to the first conductive copper pillar and the second conductive copper pillar; 3. The method for manufacturing an embedded device package substrate according to claim 2, further comprising the steps of: attaching a photosensitive film to the metal seed layer, exposing and developing the photosensitive film, and pattern plating the metal seed layer to obtain the second circuit layer connected to the first conductive copper pillar and the second conductive copper pillar.

4. The step of preparing the first conductive copper pillar and the second conductive copper pillar specifically includes: exposing the first circuit layer and exposing the pin surface of the embedded element by a laser drilling process to form a first through hole and a second through hole; 3. The method for manufacturing an embedded device package substrate as claimed in claim 2, further comprising: forming the first conductive copper pillar and the second conductive copper pillar in the first conductive hole and the second conductive hole, respectively, by a hole-filling plating process.

5. 2. The method for preparing an embedded device package substrate as claimed in claim 1, wherein the materials of the first photosensitive layer and the second photosensitive layer both comprise viscous photosensitive material.

6. 2. The method of claim 1, wherein the second dielectric layer comprises a resin-based dielectric material.

7. 2. The method of claim 1, wherein the preset threshold is 3 um.

8. A package substrate, a first circuit layer, an embedded element, a second circuit layer, a first dielectric layer, and a second dielectric layer; the first dielectric layer includes a first photosensitive layer and a second photosensitive layer, the first photosensitive layer is pressed onto the first circuit layer, the embedded element is installed on the first photosensitive layer such that a pin surface faces the first photosensitive layer, the second photosensitive layer covers the embedded element, the first photosensitive layer and the second photosensitive layer are made of the same material, and the minimum thickness of the first dielectric layer covering the side surface of the embedded element is equal to or greater than a preset threshold; the second dielectric layer covers the first dielectric layer and surrounds a side surface of the first dielectric layer; the second circuit layer is disposed on the second dielectric layer; the first circuit layer is connected to the second circuit layer; The second circuit layer is connected to the embedded element.

9. 9. The package substrate according to claim 8, further comprising a first conductive copper pillar and a second conductive copper pillar, the first conductive copper pillar being used for electrically connecting the first circuit layer and the second circuit layer, and the second conductive copper pillar being used for electrically connecting the second circuit layer and the embedded element.

10. A semiconductor comprising the package substrate according to claim 8.

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