Multilayer Capacitors

Abstract

A multilayer capacitor is provided with a laminate having a first side surface and a second side surface, a first side surface covering part covering the first side surface, and a second side surface covering part covering the second side surface. The laminate is obtained by laminating, in the z-direction, a plurality of first conductor layers, a plurality of second conductor layers, a plurality of dielectric layers, and a plurality of insulation layers. Each of the plurality of first conductor layers is linked to the first side surface covering part and set away from the second side surface covering part. Each of the plurality of second conductor layers is linked to the second side surface covering part and set away from the first side surface covering part. The plurality of insulation layers has a lower dielectric strength than each of the plurality of dielectric layers. Each of the plurality of dielectric layers is sandwiched by a first conductor layer and a second conductor layer 3. The plurality of insulation layers include an insulation layer sandwiched by two first conductor layers 2 and an insulation layer sandwiched by two second conductor layers 3.

Description

[Technical Field]

[0001] The present disclosure relates to a stacked capacitor. [Background technology]

[0002] Conventionally, electronic circuits for power conversion devices (such as inverters) incorporated in vehicles, industrial machinery, and the like have been known. Capacitors are used in such electronic circuits, for example, to smooth voltage. Patent Document 1 discloses a conventional multilayer capacitor. The multilayer capacitor described in Patent Document 1 includes a plurality of first internal electrodes, a plurality of second internal electrodes, a plurality of dielectric films, a plurality of insulating materials, and a pair of external electrodes. Each of the first internal electrodes and each of the second internal electrodes is a metal film. The plurality of first internal electrodes are connected to one of the pair of external electrodes, and the plurality of second internal electrodes are connected to the other of the pair of external electrodes. The plurality of first internal electrodes and the plurality of second internal electrodes have opposite polarities when current is applied to the multilayer capacitor. Each insulating film is a plastic polymer film such as trifluorochloroethylene resin. In this multilayer capacitor, the insulating films, the first internal electrodes, the dielectric films, and the second internal electrodes are stacked in this order, and a plurality of such laminates are stacked. Therefore, each insulating film is sandwiched between each first internal electrode and each second internal electrode to insulate them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 08-97078 Summary of the Invention [Problem to be solved by the invention]

[0004] In the multilayer capacitor described in Patent Document 1, when a potential difference occurs between the first internal electrode and the second internal electrode, a voltage is applied not only to the dielectric layers but also to the insulating film. Therefore, the dielectric strength of this multilayer capacitor is limited to the lower of the dielectric strength of the dielectric layers or the insulating film. In particular, when the dielectric strength of the insulating film is lower than the dielectric strength of the dielectric layers, the dielectric strength of the multilayer capacitor is reduced.

[0005] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a multilayer capacitor capable of suppressing a decrease in dielectric strength. [Means for solving the problem]

[0006] The multilayer capacitor provided by the present disclosure includes a laminate having a main surface and a back surface facing opposite each other in a first direction and a first side surface and a second side surface facing opposite each other in a second direction perpendicular to the first direction, a first side electrode covering the first side surface, and a second side electrode covering the second side surface. The laminate includes a plurality of conductor layers, a plurality of dielectric layers, and a plurality of insulating layers stacked in the first direction. The plurality of conductor layers includes a plurality of first conductor layers and a plurality of second conductor layers spaced apart from each other in the first direction, and each of the plurality of first conductor layers is connected to the first side surface electrode and spaced apart from the second side surface electrode. Each of the plurality of second conductor layers is connected to the second side surface electrode and spaced apart from the first side surface electrode. Each of the plurality of insulating layers has a lower dielectric strength than each of the plurality of dielectric layers. Each of the plurality of dielectric layers is sandwiched between each of the plurality of first conductor layers and each of the plurality of second conductor layers. The plurality of insulating layers include those sandwiched between two of the first conductor layers between two of the dielectric layers adjacent in the first direction, and those sandwiched between two of the second conductor layers between two of the dielectric layers adjacent in the first direction.

[0007] Preferably, each of the plurality of dielectric layers is in contact with both the first side electrode and the second side electrode.

[0008] Preferably, each of the plurality of dielectric layers is continuous from one edge of the laminate to the other edge thereof in a third direction orthogonal to the first direction and the second direction.

[0009] Preferably, an insulator made of the same material as the insulating layers is disposed between each of the first conductive layers and the second side electrode in the second direction.

[0010] Preferably, an insulator made of the same material as the insulating layers is disposed between each of the second conductive layers and the first side electrode in the second direction. [Effects of the Invention]

[0011] The multilayer capacitor of the present disclosure can suppress a decrease in dielectric strength. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view showing a multilayer capacitor according to a first embodiment. [Figure 2] FIG. 1 is a plan view showing a multilayer capacitor according to a first embodiment. [Figure 3] FIG. 2 is a bottom view showing the multilayer capacitor according to the first embodiment. [Figure 4] FIG. 1 is a front view showing a multilayer capacitor according to a first embodiment. [Figure 5] FIG. 2 is a rear view showing the multilayer capacitor in accordance with the first embodiment. [Figure 6] FIG. 1 is a left side view showing a multilayer capacitor according to a first embodiment. [Figure 7] FIG. 1 is a right side view showing a multilayer capacitor in accordance with a first embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. [Figure 9] FIG. 2 is a plan view showing a first conductor layer according to the first embodiment. [Figure 10]FIG. 2 is a plan view showing a dielectric layer according to the first embodiment. [Figure 11] FIG. 3 is a plan view showing a second conductor layer according to the first embodiment. [Figure 12] FIG. 2 is a plan view showing an insulating layer according to the first embodiment. [Figure 13] FIG. 10 is a perspective view showing a multilayer capacitor according to a second embodiment. [Figure 14] FIG. 4 is a plan view showing a multilayer capacitor according to a second embodiment. [Figure 15] FIG. 4 is a bottom view showing the multilayer capacitor according to the second embodiment. [Figure 16] FIG. 4 is a front view showing a multilayer capacitor according to a second embodiment. [Figure 17] FIG. 10 is a rear view showing the multilayer capacitor according to the second embodiment. [Figure 18] FIG. 4 is a left side view showing a multilayer capacitor according to a second embodiment. [Figure 19] FIG. 4 is a right side view showing the multilayer capacitor according to the second embodiment. [Figure 20] FIG. 15 is a cross-sectional view taken along the line XX-XX in FIG. [Figure 21] FIG. 10 is a plan view showing a first conductor layer according to a second embodiment. [Figure 22] FIG. 10 is a plan view showing a dielectric layer according to a second embodiment. [Figure 23] FIG. 10 is a plan view showing a second conductor layer according to a second embodiment. [Figure 24] FIG. 10 is a plan view showing an insulating layer according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Preferred embodiments of the multilayer capacitor of the present disclosure will be described below with reference to the drawings. In the following description, identical or similar components are designated by the same reference numerals, and redundant description will be omitted.

[0014] First Embodiment 1 to 12 show a multilayer capacitor A1 according to a first embodiment. The multilayer capacitor A1 includes a multilayer body 1 and a pair of external electrodes 61, 62. The multilayer body 1 includes a plurality of first conductor layers 2, a plurality of second conductor layers 3, a plurality of dielectric layers 4, and a plurality of insulating layers 5.

[0015] FIG. 1 is a perspective view of the multilayer capacitor A1. FIG. 2 is a plan view of the multilayer capacitor A1. FIG. 3 is a bottom view of the multilayer capacitor A1. FIG. 4 is a front view of the multilayer capacitor A1. FIG. 5 is a rear view of the multilayer capacitor A1. FIG. 6 is a left side view of the multilayer capacitor A1. FIG. 7 is a right side view of the multilayer capacitor A1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a plan view of each first conductor layer 2. FIG. 10 is a plan view of each dielectric layer 4. FIG. 11 is a plan view of each second conductor layer 3. FIG. 12 is a plan view of each insulating layer 5.

[0016] For convenience of explanation, three mutually orthogonal directions are referred to as the x-direction, y-direction, and z-direction. The z-direction is the thickness direction of the multilayer capacitor A1. The x-direction is the left-right direction in the plan view of the multilayer capacitor A1 (see FIG. 2). The y-direction is the up-down direction in the plan view of the multilayer capacitor A1 (see FIG. 2). One of the x-directions is referred to as the x1-direction, and the other of the x-directions is referred to as the x2-direction. Similarly, one of the y-directions is referred to as the y1-direction, the other of the y-directions is referred to as the y2-direction, one of the z-directions is referred to as the z1-direction, and the other of the z-directions is referred to as the z2-direction. In the following explanation, "plan view" refers to the view from the z-direction. The z-direction is an example of the "first direction," the x-direction is an example of the "second direction," and the y-direction is an example of the "third direction."

[0017] The laminate 1 is, for example, a substantially rectangular parallelepiped. As shown in Fig. 2, the laminate 1 has a rectangular shape with the x direction as the short side direction and the y direction as the long side direction in a plan view. The laminate 1 has a main surface 101, a back surface 102, and a plurality of side surfaces 103 to 106.

[0018] As shown in FIGS. 4 to 8, the main surface 101 and the back surface 102 are spaced apart in the z direction. The main surface 101 faces the z2 direction, and the back surface 102 faces the z1 direction. As shown in FIGS. 4 to 8, the multiple side surfaces 103 to 106 are located between the main surface 101 and the back surface 102 in the z direction, and are connected to the main surface 101 and the back surface 102, respectively. The side surfaces 103 and 104 are spaced apart in the x direction, as shown in FIGS. 2 and 3. The side surface 103 faces the x2 direction, and the side surface 104 faces the x1 direction. The side surfaces 105 and 106 are spaced apart in the y direction, as shown in FIGS. 2 and 3. The side surface 105 faces the y2 direction, and the side surface 106 faces the y1 direction. The side surface 103 is an example of a "first side surface," and the side surface 104 is an example of a "second side surface."

[0019] As described above, the laminate 1 includes a plurality of first conductor layers 2, a plurality of second conductor layers 3, a plurality of dielectric layers 4, and a plurality of insulating layers 5. In this embodiment, as shown in FIG. 8, the laminate 1 includes three first conductor layers 2a to 2c, three second conductor layers 3a to 3c, three dielectric layers 4a to 4c, and four insulating layers 5a to 5d. The plurality of first conductor layers 2, the plurality of second conductor layers 3, the plurality of dielectric layers 4, and the plurality of insulating layers 5 are stacked in the z direction in a configuration that will be described in detail later. The combination of the plurality of first conductor layers 2 and the plurality of second conductor layers 3 is an example of "plurality of conductor layers."

[0020] Each of the multiple first conductor layers 2 is made of, for example, Cu. The thickness of each first conductor layer 2 is, for example, 30 μm or more and 70 μm or less. As shown in FIG. 8, the edge of each first conductor layer 2 on the x2 direction side is exposed from the side surface 103. The multiple first conductor layers 2 overlap each other in a planar view. As shown in FIG. 9, each first conductor layer 2 extends from the edge of the x2 direction side of the laminate 1 toward the x1 direction in a planar view. As shown in FIG. 9, the edge of each first conductor layer 2 on the x2 direction side is exposed from the side surface 103, and the edge of the x1 direction side is not exposed from the side surface 104. Therefore, in a planar view, the edge of each first conductor layer 2 on the x1 direction side is located more inward of the laminate 1 than the side surface 104. Furthermore, as shown in FIG. 9, each first conductor layer 2 is not exposed from either the side surface 105 or the side surface 106 in a planar view. Therefore, in a plan view, the edge of each first conductor layer 2 on the y1 direction side is located inside the laminate 1 relative to the side surface 106, and the edge on the y2 direction side is located inside the laminate 1 relative to the side surface 105.

[0021] 9, in plan view, an insulator 29 is formed around each first conductor layer 2 (excluding the edge on the x2 direction side). Specifically, the insulator 29 is located between each first conductor layer 2 and the side surface 104, between each first conductor layer 2 and the side surface 105, and between each first conductor layer 2 and the side surface 106. The insulator 29 is made of the same material as the insulating layer 5, which will be described later.

[0022] Each of the multiple second conductor layers 3 is made of, for example, Cu. The thickness of each second conductor layer 3 is, for example, 30 μm or more and 70 μm or less. As shown in FIG. 8, the edge of each second conductor layer 3 on the x1 direction side is exposed from the side surface 104. The multiple second conductor layers 3 overlap each other in a planar view. As shown in FIG. 11, each second conductor layer 3 extends from the edge of the x1 direction side of the laminate 1 toward the x2 direction in a planar view. As shown in FIG. 11, the edge of each second conductor layer 3 on the x1 direction side is exposed from the side surface 104, and the edge of the x2 direction side is not exposed from the side surface 103. Therefore, in a planar view, the edge of each second conductor layer 3 on the x2 direction side is located more inward of the laminate 1 than the side surface 103. Furthermore, as shown in FIG. 11, each second conductor layer 3 is not exposed from either the side surface 105 or the side surface 106 in a planar view. Therefore, in a planar view, the edge of each second conductor layer 3 on the y1 direction side is located inside the laminate 1 relative to the side surface 106, and the edge on the y2 direction side is located inside the laminate 1 relative to the side surface 105.

[0023] 11, in plan view, an insulator 39 is formed around each second conductor layer 3 (excluding the edge on the x1 direction side). Specifically, the insulator 39 is located between each second conductor layer 3 and the side surface 103, between each second conductor layer 3 and the side surface 105, and between each second conductor layer 3 and the side surface 106. The insulator 39 is made of the same material as the insulator 29. In other words, the insulator 39 is made of the same material as the insulating layer 5, which will be described later.

[0024] The first conductor layers 2 and the second conductor layers 3 partially overlap each other in plan view. Furthermore, the first conductor layers 2 and the second conductor layers 3 have opposite polarities when the multilayer capacitor A1 is energized.

[0025] Each dielectric layer 4 is sandwiched between a corresponding first conductor layer 2 and a corresponding second conductor layer 3. In the example shown in FIG. 8, the dielectric layer 4a is sandwiched between the first conductor layer 2a and the second conductor layer 3a. The dielectric layer 4b is sandwiched between the second conductor layer 3b and the first conductor layer 2b. The dielectric layer 4c is sandwiched between the first conductor layer 2c and the second conductor layer 3c. As shown in FIG. 10, each dielectric layer 4 is connected in plan view from the edge of the laminate 1 in the x1 direction to the edge of the laminate 1 in the x2 direction, and from the edge of the laminate 1 in the y1 direction to the edge of the laminate 1 in the y2 direction. Each dielectric layer 4 is made of a film-like resin material, such as a polymer film. The material of each dielectric layer 4 is not limited to a film-like resin material and may be any material having a relative dielectric constant greater than 1. Examples of such materials include ceramics containing a metal oxide perovskite compound as a main component. The thickness of each dielectric layer 4 is, for example, not less than 8 μm and not more than 25 μm.

[0026] Each of the multiple insulating layers 5 is made of, for example, prepreg. Each insulating layer 5 insulates the two first conductor layers 2 and the two second conductor layers 3 that contact each of the two opposite sides in the z direction. Each insulating layer 5 has a lower dielectric strength than each dielectric layer 4. Each insulating layer 5 also functions as an adhesive layer for the two first conductor layers 2 and the two second conductor layers 3 that contact each of the two opposite sides in the z direction. The thickness of each insulating layer 5 is, for example, 40 μm or more and 100 μm or less.

[0027] 8, the multiple insulating layers 5 include one sandwiched between two first conductor layers 2 between two dielectric layers 4 adjacent in the z direction, and one sandwiched between two second conductor layers 3 between two dielectric layers 4 adjacent in the z direction. Furthermore, the multiple insulating layers 5 further include one sandwiched between the first conductor layer 2 and a pair of external electrodes 61, 62 (main surface covering portions 612, 622 described below) formed on the main surface 101 of the laminate 1, and one sandwiched between the second conductor layer 3 and a pair of external electrodes 61, 62 (rear surface covering portions 613, 623 described below) formed on the rear surface 102 of the laminate 1. In the example shown in FIG. 8, the insulating layer 5a is a surface layer on the z2 direction side of the laminate 1, and is sandwiched between the main surface covering portions 612, 622 described below and the first conductor layer 2a. The insulating layer 5b is sandwiched between the second conductor layer 3a and the second conductor layer 3b between the two dielectric layers 4a and 4b. The insulating layer 5c is sandwiched between the first conductor layer 2b and the first conductor layer 2c between the two dielectric layers 4b and 4c. The insulating layer 5d is a surface layer on the z1 direction side of the laminate 1, and is sandwiched between back surface covering portions 613 and 623 (described later) and the second conductor layer 3c.

[0028] The laminate 1 includes first units, each of which is formed by stacking a first conductor layer 2, a dielectric layer 4, and a second conductor layer 3 in this order in the z direction, and second units, each of which is formed by stacking a second conductor layer 3, a dielectric layer 4, and a first conductor layer 2 in this order from the z2 direction to the z1 direction, stacked alternately with an insulating layer 5 sandwiched between them. The number of first units and second units is not particularly limited, and the number of first units and second units does not have to be the same. In the example shown in FIG. 8 , the layers are stacked in the following order: insulating layer 5, first unit, insulating layer 5, second unit, insulating layer 5, first unit, insulating layer 5. That is, in the example shown in FIG. 8 , two first units and one second unit are stacked alternately with an insulating layer 5 sandwiched between them. The laminate structure of the laminate 1 is not limited to the above example, and may be configured such that each surface layer on both sides in the z direction is a dielectric layer 4.

[0029] In the laminate 1, the x-direction dimensions, y-direction dimensions, and z-direction dimensions (thickness) of each layer (each first conductor layer 2, each second conductor layer 3, dielectric layer 4, and insulating layer 5), the constituent material of each layer, the number of layers stacked, etc. are not particularly limited and can be changed appropriately based on the specifications of the multilayer capacitor A1 (e.g., capacitance, size, etc.). The capacitance C of the multilayer capacitor A1 is expressed as C=ε0·ε r ·(S / d)·N[F]. In this formula, ε0 is the dielectric constant of a vacuum, ε r where σ is the relative permittivity of the dielectric (each dielectric layer 4), S is the area of ​​the internal electrode (the region where each first conductor layer 2 and each second conductor layer 3 overlap in a planar view), d is the distance between the electrodes (between each first conductor layer 2 and each second conductor layer 3), and N is the number of dielectric layers 4 stacked. For example, from the above formula, the greater the separation distance in the z direction between each first conductor layer 2 and each second conductor layer 3 (the thickness of the dielectric layer 4), the smaller the capacitance. Also, the greater the relative permittivity of the dielectric layer 4, the greater the capacitance. Also, the greater the area of ​​each first conductor layer 2 and each second conductor layer 3 in a planar view, the greater the capacitance. Also, the greater the number of stacked layers of each layer (the number of the above units), the greater the capacitance.

[0030] The pair of external electrodes 61, 62 are formed so as to cover a part of the main surface 101, a part of the back surface 102, and each of the side surfaces 103, 104 of the laminate 1. The pair of external electrodes 61, 62 are terminals of the multilayer capacitor A1. The pair of external electrodes 61, 62 are spaced apart and insulated from each other. The pair of external electrodes 61, 62 are made of, for example, but not limited to, Cu. The pair of external electrodes 61, 62 are formed by, for example, but not limited to, plating.

[0031] The external electrode 61 is one terminal of the multilayer capacitor A1. The external electrode 61 includes a side surface covering portion 611, a main surface covering portion 612, and a back surface covering portion 613. The side surface covering portion 611 covers the side surface 103 as shown in FIGS. 1 to 5, 7, and 8. The main surface covering portion 612 covers a portion of the main surface 101 as shown in FIGS. 1, 2, 4, 5, and 8. The main surface covering portion 612 is formed on the portion of the main surface 101 on the x2 direction side as shown in FIG. 2. The main surface covering portion 612 is connected to the side surface covering portion 611. The back surface covering portion 613 covers a portion of the back surface 102 as shown in FIGS. 3 to 5, and 8. The back surface covering portion 613 is formed on the portion of the back surface 102 on the x2 direction side as shown in FIG. 3. The back surface covering portion 613 is connected to the side surface covering portion 611. 8 , the main surface covering portion 612 and the back surface covering portion 613 do not overlap the second conductor layers 3 in a plan view. The external electrode 61 may further include a portion that is connected to the side surface covering portion 611, the main surface covering portion 612, and the back surface covering portion 613 and covers part of the two side surfaces 105, 106. The external electrode 61 may not include the main surface covering portion 612 or the back surface covering portion 613.

[0032] As described above, since the insulator 39 is disposed between the side surface 103 and each second conductor layer 3, as shown in FIG. 11 , each insulator 39 is disposed between the side surface covering portion 611 and each second conductor layer 3 in the x direction. Therefore, each insulator 39 insulates the side surface covering portion 611 from each second conductor layer 3. Furthermore, as shown in FIGS. 8 and 9 , the side surface covering portion 611 is in contact with the edge of each first conductor layer 2 on the x2 direction side, and therefore the side surface covering portion 611 electrically connects multiple first conductor layers 2 that are disposed at a distance in the z direction. Therefore, the multiple first conductor layers 2 are at the same potential via the side surface covering portion 611. The side surface covering portion 611 is an example of a "first side surface electrode."

[0033] The external electrode 62 is the other terminal of the multilayer capacitor A1. The external electrode 62 includes a side surface covering portion 621, a main surface covering portion 622, and a back surface covering portion 623. The side surface covering portion 621 covers the side surface 104, as shown in FIGS. 2 to 6 and 8. The main surface covering portion 622 covers a portion of the main surface 101, as shown in FIGS. 2, 4, 5 and 8. The main surface covering portion 622 is formed on a portion of the main surface 101 on the x1 direction side, as shown in FIG. 2, and is separated from the main surface covering portion 612 (external electrode 61). The main surface covering portion 622 is connected to the side surface covering portion 621. The back surface covering portion 623 covers a portion of the back surface 102, as shown in FIGS. 3 to 5 and 8. The back surface covering portion 623 is formed on a portion of the back surface 102 on the x1 direction side, and is separated from the back surface covering portion 613 (external electrode 61). 8, the main surface covering portion 622 and the back surface covering portion 623 do not overlap the first conductor layers 2 in plan view. The external electrode 62 may further include a portion that is connected to the side surface covering portion 621, the main surface covering portion 622, and the back surface covering portion 623 and covers part of the two side surfaces 105, 106. The external electrode 62 does not have to include the main surface covering portion 622 or the back surface covering portion 623.

[0034] As described above, since the insulator 29 is disposed between the side surface 104 and each first conductor layer 2, as shown in FIG. 9, each insulator 29 is disposed between the side surface covering portion 621 and each first conductor layer 2 in the x direction. Therefore, each insulator 29 insulates the side surface covering portion 621 from each first conductor layer 2. Furthermore, as shown in FIGS. 8 and 11, the side surface covering portion 621 is in contact with the edge of each second conductor layer 3 on the x1 direction side, and therefore the side surface covering portion 621 electrically connects multiple second conductor layers 3 that are disposed at a distance in the z direction. Therefore, the multiple second conductor layers 3 are at the same potential via the side surface covering portion 621. The side surface covering portion 621 is an example of a "second side surface electrode."

[0035] The multilayer capacitor A1 has the following functions and effects.

[0036] In the multilayer capacitor A1, each of the multiple dielectric layers 4 is sandwiched between a respective first conductor layer 2 and a respective second conductor layer 3 in the z direction. The multiple insulating layers 5 include those sandwiched between two first conductor layers 2 (e.g., first conductor layers 2b and 2c) between two adjacent dielectric layers 4 (e.g., dielectric layers 4b and 4c) in the z direction, and those sandwiched between two second conductor layers 3 (e.g., second conductor layers 3a and 3b) between two adjacent dielectric layers 4 (e.g., dielectric layers 4a and 4b) in the z direction. Each insulating layer 5 has a lower dielectric strength than each of the dielectric layers 4. With this configuration, the dielectric layer 4 is sandwiched between two conductor layers (the first conductor layer 2 and the second conductor layer 3) with different potentials, and the insulating layer 5 is sandwiched between two conductor layers (the two first conductor layers 2 or the two second conductor layers 3) with the same potential. Therefore, when a potential difference occurs between the plurality of first conductor layers 2 and the plurality of second conductor layers 3 while the multilayer capacitor A1 is energized, a voltage is applied in the thickness direction (z direction) of the dielectric layer 4, but no voltage is applied in the thickness direction (z direction) of the insulating layer 5. This means that it is not necessary to ensure the withstand voltage (dielectric strength) of the insulating layer 5. In other words, the multilayer capacitor A1 can suppress a decrease in dielectric strength.

[0037] In the multilayer capacitor A1, for example, the dielectric layer 4 is made of a resin material and the insulating layer 5 is made of a prepreg. Conventional multilayer capacitors include ceramic capacitors in which the dielectric layer 4 is made of ceramic. Due to its physical properties, ceramic is prone to cracking due to stress such as thermal stress. Therefore, in ceramic capacitors, heat generated when current is applied can cause damage such as cracking in the dielectric layer 4. This damage reduces the dielectric strength of the dielectric layer 4. In contrast, in the multilayer capacitor A1 of the present disclosure, the dielectric layer 4 is not made of ceramic, so the occurrence of cracks and other damage due to thermal stress can be suppressed. Therefore, the multilayer capacitor A1 can suppress a decrease in dielectric strength.

[0038] In the multilayer capacitor A1, the edges of each first conductor layer 2 on the y1-direction side and the y2-direction side are covered with insulators 29. Furthermore, the edges of each second conductor layer 3 on the y1-direction side and the y2-direction side are covered with insulators 39. With this configuration, the first conductor layers 2 and the second conductor layers 3 are not exposed at the side surfaces 105, 106 of the laminate 1. Therefore, it is possible to prevent unintended short circuits between the first conductor layers 2 and the second conductor layers 3 at the side surfaces 105, 106.

[0039] Second Embodiment 13 to 24 show a multilayer capacitor A2 according to the second embodiment.

[0040] FIG. 13 is a perspective view of the multilayer capacitor A2. FIG. 14 is a plan view of the multilayer capacitor A2. FIG. 15 is a bottom view of the multilayer capacitor A2. FIG. 16 is a front view of the multilayer capacitor A2. FIG. 17 is a rear view of the multilayer capacitor A2. FIG. 18 is a left side view of the multilayer capacitor A2. FIG. 19 is a right side view of the multilayer capacitor A2. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 14. FIG. 21 is a plan view of each first conductor layer 2 according to the second embodiment. FIG. 22 is a plan view of each dielectric layer 4 according to the second embodiment. FIG. 23 is a plan view of each second conductor layer 3 according to the second embodiment. FIG. 24 is a plan view of each insulating layer 5 according to the second embodiment.

[0041] As shown in Fig. 13, the multilayer capacitor A2 is a substantially rectangular parallelepiped, similar to the multilayer capacitor A1. However, as shown in Figs. 13 to 24, unlike the multilayer capacitor A1, the multilayer capacitor A2 is rectangular in shape with its longitudinal direction in the x direction and its lateral direction in the y direction in a plan view. Except for this, the components of the multilayer capacitor A2, that is, the laminate 1 (plurality of first conductor layers 2, pluralities of second conductor layers 3, pluralities of dielectric layers 4, and pluralities of insulating layers 5) and the pair of external electrodes 61, 62, are configured similarly to the multilayer capacitor A1.

[0042] In the multilayer capacitor A2, similar to the multilayer capacitor A1, each of the multiple dielectric layers 4 is sandwiched between a respective first conductor layer 2 and a respective second conductor layer in the z-direction. The multiple insulating layers 5 include those sandwiched between two first conductor layers 2 (e.g., first conductor layers 2b and 2c) and those sandwiched between two second conductor layers 3 (e.g., second conductor layers 3a and 3b). Therefore, when a potential difference occurs between the multiple first conductor layers 2 and the multiple second conductor layers 3, a voltage is applied in the thickness direction (z-direction) of the dielectric layers 4, but no voltage is applied in the thickness direction (z-direction) of the insulating layers 5. Therefore, the withstand voltage (dielectric strength) of the insulating layers 5 does not need to be guaranteed. In other words, the multilayer capacitor A2 can suppress a decrease in dielectric strength. Additionally, the multilayer capacitor A2 can achieve the same effects as the above-described multilayer capacitor A1.

[0043] The multilayer capacitor according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the multilayer capacitor according to the present disclosure can be freely designed in various ways. [Explanation of symbols]

[0044] A1, A2: Multilayer capacitors 1: Laminate 101: Main surface 102: Back side 103, 104, 105, 106: Side 2, 2a, 2b, 2c: first conductor layer 3,3a,3b,3c: 2nd conductor layer 29, 39: Insulator 4, 4a, 4b, 4c: dielectric layers 5,5a,5b,5c,5d: Insulating layer 61,62:External electrode 611, 621: Side covering part 612,622: Main surface covering part 613, 623: Back surface coating

Claims

1. A laminate having a main surface and a back surface facing in opposite directions in a first direction, and a first side surface and a second side surface facing in opposite directions in a second direction perpendicular to the first direction; a first side electrode covering the first side; a second side electrode covering the second side; Equipped with The laminate includes a plurality of conductor layers, a plurality of dielectric layers, and a plurality of insulating layers stacked in the first direction, the plurality of conductor layers include a plurality of first conductor layers and a plurality of second conductor layers spaced apart from each other in the first direction, each of the plurality of first conductor layers is connected to the first side electrode and is spaced apart from the second side electrode; each of the plurality of second conductor layers is connected to the second side electrode and is spaced apart from the first side electrode; Each of the plurality of insulating layers has a lower dielectric strength than each of the plurality of dielectric layers; Each of the plurality of dielectric layers is sandwiched between each of the plurality of first conductor layers and each of the plurality of second conductor layers, the plurality of insulating layers include at least one first insulating layer sandwiched between two of the first conductor layers between two of the dielectric layers adjacent to each other in the first direction, and at least one second insulating layer sandwiched between two of the second conductor layers between two of the dielectric layers adjacent to each other in the first direction; In the plurality of insulating layers, the at least one first insulating layer and the at least one second insulating layer are alternately arranged one by one in the first direction, each of the plurality of dielectric layers is in contact with both the first side electrode and the second side electrode; A stacked capacitor, wherein the constituent material of each of the plurality of insulating layers is different from the constituent material of each of the plurality of dielectric layers.

2. 2. The multilayer capacitor according to claim 1, wherein each of the plurality of dielectric layers is connected from an edge on one side of the laminate to an edge on the other side thereof in a third direction perpendicular to the first direction and the second direction.

3. 3. The multilayer capacitor according to claim 1, wherein an insulator made of the same material as that of the insulating layers is disposed between each of the first conductor layers and the second side electrode in the second direction.

4. 4. The multilayer capacitor according to claim 1, wherein an insulator made of the same material as that of the insulating layers is disposed between each of the second conductor layers and the first side electrode in the second direction.

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