Semiconductor Package

Abstract

To provide a semiconductor package with a chip stack, in which the manufacturing cost is reduced by effectively reducing the difficulty in a process.SOLUTION: A semiconductor package 100 includes a substrate 110, a plurality of first bumps 120, a first chip 130, a plurality of metal columns 140, a plurality of second bumps 150, and a second chip 160. The substrate includes a plurality of first conductive pads 113 on an upper surface 111, and a plurality of second conductive pads 114. One end of each first bump is connected to each first conductive pad. The first chip is connected to the other end of the first bump. One end of each metal column is connected to each second conductive pad 114. One end of each second bump is connected to the other end of each metal column. The cross-sectional area of each metal column is larger than that of each second bump. The second chip is connected to the other end of the second bump and exists over the first chip.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to semiconductor packages, and more particularly to semiconductor packages having chip stacks. [Background technology]

[0002] With the mass use of wearable devices, the industry has a higher requirement for the size of integrated circuits, and currently integrated circuits are developing toward miniaturization. At the same time, it is necessary to increase the computing speed while reducing the size, but it is difficult to increase the number of transistors that can be placed on a single chip, so chip stack packaging has become one of the main technologies to increase the computing speed of integrated circuits. Summary of the Invention [Problem to be solved by the invention]

[0003] Chip stacking uses a bump structure to stack two or more chips three-dimensionally on a single semiconductor package, and by stacking multiple chips within a limited size, it is possible to increase the overall computing speed. To stack the chips vertically, it is necessary to space the two chips using tall bumps to prevent problems such as warping of the stacked chips and difficulty in dissipating heat, but manufacturing tall bumps makes the process more difficult and significantly increases costs.

[0004] Therefore, the inventors believed that the above-mentioned drawbacks could be improved, and as a result of extensive research, they came to propose the present invention, which rationally and effectively improves the problems.

[0005] As a result of extensive research, the present inventors have found that the above object can be achieved by a technique in which the second chip is raised by a metal pillar and the first chip and the second chip are stacked on top of each other.

[0006] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor package, which is a package having a chip stack, and can effectively reduce the process difficulty and reduce the manufacturing cost. [Means for solving the problem]

[0007] In order to solve the above problems, the present invention employs the following means. A semiconductor package according to one aspect of the present invention includes a substrate, a plurality of first bumps, a first chip, a plurality of metal posts, a plurality of second bumps, and a second chip. A sealing layer and an electromagnetic wave shielding layer, The substrate has a top surface, a plurality of first conductive pads, and a plurality of second conductive pads, the first conductive pads and the second conductive pads being located on the top surface. One end of each of the first bumps is connected to a respective one of the first conductive pads, the first chip is connected to the other end of the first bumps, one end of each of the metal pillars is connected to a respective one of the second conductive pads, and one end of each of the second bumps is connected to the other end of each of the metal pillars. A cross-sectional area of ​​each of the metal pillars is larger than a cross-sectional area of ​​each of the second bumps, the second chip is connected to the other end of the second bumps, and the second chip is located above the first chip. The sealing layer is disposed on the upper surface of the substrate and covers the first bump, the first chip, the metal pillar, the second bump, and the second chip. The electromagnetic wave shielding layer covers the sealing layer and the substrate. A side surface of any one of the metal pillars is electrically connected to the electromagnetic wave shielding layer. Effect of the Invention

[0008] The present invention is configured as described above and therefore provides the effects described below. According to the present invention, a semiconductor package having a chip stack is achieved by lifting the second chip with two-tiered metal posts and second bumps and positioning the first chip below the second chip. Also, by supporting the second chip with a two-tiered structure, the process complexity is reduced and the process yield is increased.

[0009] Other features of the present invention will become apparent from the following detailed description of the present invention and the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment of the present invention. [Diagram 2] 4 is a cross-sectional view showing a connection portion between a metal post and a second bump of the semiconductor package according to the first embodiment of the present invention. FIG. [Diagram 3] 1 is a partially enlarged view showing a semiconductor package according to a first embodiment of the present invention. [Figure 4] FIG. 11 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention. [Diagram 5] FIG. 11 is a cross-sectional view showing a semiconductor package according to a third embodiment of the present invention. [Figure 6] FIG. 11 is a cross-sectional view showing a semiconductor package according to a fourth embodiment of the present invention. [Figure 7] FIG. 13 is a plan view showing a semiconductor package according to a fourth embodiment of the present invention. [Figure 8] FIG. 13 is a cross-sectional view showing a semiconductor package according to a fifth embodiment of the present invention. [Figure 9] FIG. 13 is a plan view showing a semiconductor package according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Below, an embodiment of the semiconductor package of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiment, and the components, materials, etc. described below can be modified in various ways within the scope of the spirit of the present invention.

[0012] (First embodiment) 1 is a cross-sectional view showing a semiconductor package 100 according to a first embodiment of the present invention. The semiconductor package 100 includes a substrate 110, a plurality of first bumps 120, a first chip 130, a plurality of metal posts 140, a plurality of second bumps 150, a second chip 160, and a sealing layer 170.

[0013] In this embodiment, the substrate 110 is a redistribution layer and has an upper surface 111, a lower surface 112, a plurality of first conductive pads 113, a plurality of second conductive pads 114, and a plurality of third conductive pads 115. The first conductive pad 113 and the second conductive pad 114 are located on the upper surface 111, and the third conductive pad 115 is located on the lower surface 112. In this embodiment, the substrate 110 is composed of a dielectric material and multiple metal layers.

[0014] The first circuit layers 116 and the second circuit layers 117 are formed of multiple metal layers of the substrate 110. Each of the first circuit layers 116 is electrically connected to each of the first conductive pads 113 and any one of the third conductive pads 115, and electrically connects each of the first conductive pads 113 and any one of the third conductive pads 115. The second circuit layer 117 is electrically connected to each of the second conductive pads 114 and any one of the third conductive pads 115, and electrically connects each of the second conductive pads 114 and any one of the third conductive pads 115. Each of the third conductive pads 115 is connected to a solder ball 190, and the semiconductor package 100 is connected to another circuit board (not shown) via the solder ball 190. In this embodiment, the positions of the first conductive pad 113 and the second conductive pad 114 are modified by the third conductive pad 115, the first circuit layer 116, and the second circuit layer 117 to accommodate the circuit layout of different circuit boards. In other embodiments, the substrate 110 can be other IC circuit boards, and the type of the substrate 110 is not limited to the types described in the embodiments of the present invention.

[0015] 1, one end of each of the first bumps 120 is connected to a respective one of the first conductive pads 113, and the other end of each of the first bumps 120 is connected to a respective one of the first chips 130. The first bumps 120 are formed on the first chips 130 through a bump patterning process, and the first chips 130 and the first bumps 120 are mounted on the first conductive pads 113 of the substrate 110 in a flip-chip manner. The first bumps 120 are made of copper, a copper alloy, or a combination of other metals such as nickel, gold, etc.

[0016] One end of each of the metal pillars 140 is connected to the second conductive pads 114. Preferably, the metal pillars 140 are prefabricated and then placed on the second conductive pads 114, or the metal pillars 140 are formed on the second conductive pads 114 through exposure, development, and electroplating processes. One end of each of the second bumps 150 is connected to the other end of each of the metal pillars 140, and the other end of the second bumps 150 is connected to the second chip 160. The second bumps 150 are formed on the second chip 160 through a patterning process, and the second chip 160 and the second bumps 150 are placed on the metal pillars 140 by a flip-chip method. The second bumps 150 are made of copper, copper alloy, or a combination of other metals such as nickel and gold.

[0017] In this embodiment, the second chip 160 is elevated by the two-stage metal pillars 140 and the second bumps 150 to position the second chip 160 above the first chip 130, thereby greatly reducing the process complexity. In addition, the metal pillars 140 are prefabricated, which omits the processes of exposure, development, and electroplating, further reducing the overall process complexity.

[0018] 2 is a cross-sectional view showing connection points between the metal pillars 140 and the second bumps 150 of the semiconductor package according to the present invention. With reference to both Fig. 1 and Fig. 2, preferably, the cross-sectional area of ​​each of the metal pillars 140 is larger than the cross-sectional area of ​​each of the second bumps 150, so that the second chip 160 and the second bumps 150 can be easily opposed to each other during the flip-chip process, thereby improving the process yield. In this embodiment, the ratio of the cross-sectional area of ​​each of the second bumps 150 to the cross-sectional area of ​​each of the metal pillars 140 is in the range of 1:1 to 1:3.

[0019] 3, the height H2 of each of the metal pillars 140 is preferably higher than the height H1 of each of the first bumps 120, so that the second chip 160 can be more easily installed above the first chip 130. In this embodiment, the ratio of the height H1 of each of the first bumps 120 to the height H2 of each of the metal pillars 140 is in the range of 1:1 to 1:5.

[0020] As shown in FIG. 1, the encapsulation layer 170 is disposed on the upper surface 111 of the substrate 110, and the encapsulation layer 170 covers the first bump 120, the first chip 130, the metal post 140, the second bump 150, and the second chip 160, and has insulating and waterproof properties to protect the components. The encapsulation layer 170 is an epoxy molding compound (EMC). In addition, in order to prevent the components from being affected by electromagnetic waves from the surrounding chips, or the electromagnetic waves generated by the components from affecting the surrounding chips, in this embodiment, the encapsulation layer 170 and the substrate 110 are covered with an electromagnetic shield layer 180 as an electromagnetic shield, and the electromagnetic shield layer 180 is made of metal and has a large area, so that the electromagnetic shield layer 180 also serves as a ground layer for the semiconductor device. Preferably, any one of the second circuit layers 117 is electrically connected to the electromagnetic shielding layer 180, and the second conductive pad 114 and the third conductive pad 115 are electrically connected to the electromagnetic shielding layer 180 via the second circuit layer 117 and are grounded.

[0021] (Second Example) The configuration of the second embodiment of the present invention is shown in Fig. 4. The difference between this embodiment and the first embodiment is that the sealing layer 170 of this embodiment has a through hole 171, and the side of the metal pillar 140 is exposed to the outside of the sealing layer 170 by the through hole 171 and is connected to the electromagnetic wave shielding layer 180. Since the height of the metal pillar 140 is greater than the thickness of the first circuit layer 116, the area over which the side of the metal pillar 140 is connected to the electromagnetic wave shielding layer 180 is increased, thereby achieving a higher grounding effect.

[0022] In addition, in this embodiment, since the metal pillar 140 has a large area, it provides a large supporting force to the second chip 160 and the second bumps 150, thereby preventing the problem of warping of the second chip 160 during the flip chip process.

[0023] (Third Example) The configuration of the third embodiment of the present invention is shown in Fig. 5. The difference between the second embodiment and the third embodiment is that the semiconductor package 100 of the present embodiment includes a plurality of first chips 130, each of which is connected to the other end of the first bump 120, and all of the first chips 130 are located below the second chip 160. The metal pillar 140 of the present embodiment is connected to the electromagnetic shield layer 180 via the through hole 171 and has a large area, so that it can provide a large supporting force to the second chip 160 and the second bump 150. The second chip 160 has a large width and has a space below it to accommodate two first chips 130, thereby increasing the processing speed of the single semiconductor package 100.

[0024] (Fourth Example) The configuration of the fourth embodiment of the present invention is shown in Figures 6 and 7. The difference between this embodiment and the first embodiment is that the semiconductor package 100 of this embodiment includes a plurality of second chips 160, each of which is connected to the other end of the second bump 150, and all of the second chips 160 are located above the first chip 130. There is a gap D between two adjacent second chips 160, and the back surface of the first chip 130 is exposed from the gap D. In this embodiment, the packaging density of the semiconductor package 100 is further increased by providing a plurality of second chips 160, thereby further improving the overall efficiency.

[0025] (Fifth Example) The configuration of the fifth embodiment of the present invention is shown in Figures 8 and 9. The difference between the fourth embodiment and the fifth embodiment is that the semiconductor package 100 of the present embodiment includes a plurality of first chips 130, each of which is connected to the other end of the first bump 120, and each of the first chips 130 is located below each of the second chips 160. A first gap D1 is provided between two adjacent first chips 130, and a second gap D2 is provided between two adjacent second chips 160, and the second gap D2 is located above the first gap D1. In the present embodiment, the packaging density of the semiconductor package 100 is further increased by providing a plurality of first chips 130 and second chips 160, thereby further improving the overall efficiency.

[0026] In the present invention, the second chip 160 is raised by two-tiered metal pillars 140 and second bumps 150, and the first chip 130 is positioned below the second chip 160, thereby achieving a semiconductor package 100 having a chip stack. In addition, the second chip 160 is supported by a two-tiered structure, which reduces process complexity and improves process yield.

[0027] As described above, the present invention is not limited to the above-described embodiment, and can be embodied in various forms without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0028] 100 Semiconductor Packages 110 Substrate 111 Top surface 112 Bottom surface 113 First conductive pad 114 Second conductive pad 115 3rd conductive pad 116 1st circuit layer 117 2nd circuit layer 120 First Bump 130 First Chip 140 metal pillar 150 2nd Bump 160 2nd Chip 170 Sealing layer 171 Through hole 180 Electromagnetic Shielding Layer 190 Solder balls H1 Height of first bump H2 Height of metal pole H3 Second bump height D Gap D1 First Gap D2 Second Gap

Claims

1. a substrate (110) having a top surface (111), a plurality of first conductive pads (113), and a plurality of second conductive pads (114), the first conductive pads and the second conductive pads being located on the top surface; a plurality of first bumps, each of which has one end connected to a respective one of the first conductive pads; a first chip (130) connected to the other end of the first bump; a plurality of metal pillars (140), each of which has one end connected to a respective one of the second conductive pads; a plurality of second bumps (150), each of which has one end connected to the other end of a corresponding one of the metal posts, the cross-sectional area of ​​each of the metal posts being greater than the cross-sectional area of ​​each of the second bumps; a second chip (160) connected to the other end of the second bump and located above the first chip; an encapsulation layer (170) disposed on the upper surface of the substrate and covering the first bumps, the first chip, the metal pillars, the second bumps, and the second chip; an electromagnetic wave shielding layer (180) covering the sealing layer and the substrate; A semiconductor package, characterized in that a side surface of any one of the metal posts is electrically connected to the electromagnetic wave shielding layer.

2. The semiconductor package according to claim 1, characterized in that the sealing layer has a through hole (171), and any one of the metal pillars is exposed to the outside of the sealing layer through the through hole and is connected to the electromagnetic wave shielding layer.

3. 3. The semiconductor package of claim 2, wherein the substrate is a redistribution layer, the substrate has a plurality of first circuit layers (116) and a plurality of second circuit layers (117), each of the first circuit layers being electrically connected to a respective one of the first conductive pads, each of the second circuit layers being electrically connected to a respective one of the second conductive pads, and any one of the second circuit layers being electrically connected to the electromagnetic wave shielding layer.

4. 2. The semiconductor package according to claim 1, further comprising a plurality of the first chips, each of the first chips being connected to the other end of the first bump, and all of the first chips being located below the second chip.

5. If the cross-sectional area of ​​each of the second bumps is 1, 2. The semiconductor package of claim 1, wherein a ratio of a cross-sectional area of ​​each of the second bumps to a cross-sectional area of ​​each of the metal posts is in a range between 1:1 and 1:

3.

6. 2 . The semiconductor package according to claim 1 , wherein the height of each of the metal posts is greater than the height of each of the first bumps.

7. If the height of each of the first bumps is 1, 7. The semiconductor package of claim 6, wherein a ratio of the height of each of the first bumps to the height of each of the metal pillars ranges between 1:1 and 1:

5.

8. 2. The semiconductor package according to claim 1, further comprising a plurality of said second chips, each of said second chips being connected to the other end of said second bump, and all of said second chips being located above said first chip.

9. 9. The semiconductor package according to claim 8, wherein there is a gap (D) between two adjacent second chips, the gap exposing the back surface of the first chip.

10. 9. The semiconductor package according to claim 8, further comprising a plurality of the first chips, each of the first chips being connected to the other end of the first bump, and each of the first chips being located below each of the second chips.

11. 11. The semiconductor package of claim 10, wherein a first gap (D1) is formed between two adjacent first chips, and a second gap (D2) is formed between two adjacent second chips, the second gap being located above the first gap.

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