Chip structure and manufacturing method thereof

Abstract

To provide a chip structure and a method for manufacturing the same.SOLUTION: A method for manufacturing a chip structure first sticks a back surface 112 of a wafer 100 to a first carrier 200, cuts the wafer 100 into a plurality of separated dies 110, and forms groove portions 130 between the dies 110. After sticking an active surface 111 of the wafer 100 to a second carrier 300, the first carrier 200 is removed to expose the back surface 112 and side surface 113 of each die 110 and the groove portions 130. Next, a heat dissipation cover 140 is formed on the back surface 112 and side surface 113 of each die 110, thereby configuring a plurality of chip structures A having the heat dissipation cover 140. This increases the heat dissipation efficiency of the die 110, prevents the formation of metal fragments that contaminate the die 110, and also prevents a situation where the heat dissipation cover 140 comes off the die 110.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a chip structure and a method for manufacturing the same, and more particularly to a chip structure and a method for manufacturing the same that can improve the heat dissipation efficiency of the chip, prevent the formation of metal debris, and prevent the situation where the heat dissipation cover is detached from the die. [Background technology]

[0002] As the computing speed of integrated circuits increases, the chips become hotter, and the chips become smaller in volume, making it difficult to dissipate heat from the chips. When the chips become overheated, the computing speed decreases and even the chips are damaged. Summary of the Invention [Problem to be solved by the invention]

[0003] As shown in Fig. 8, before the sawing process, the active surface 11 of the wafer 10 is attached to the carrier 20 and the back surface 12 of the wafer 10 is exposed, and a heat dissipation layer 30 is formed on the back surface 12 to enhance the heat dissipation effect. As shown in Fig. 9, the sawing process is then carried out, and the heat dissipation layer 30 and the wafer 10 are simultaneously sawed by a sawing tool (not shown), the wafer 10 is sawed into a plurality of separate dies 10a, and the heat dissipation layer 30 is sawn into a plurality of heat sinks 30a, each of which is located on the back surface 12a of each die 10a. Since each heat sink 30a is formed at the same time as the wafer 10 is sawed, the heat dissipation area of ​​each heat sink 30a is the same as the area of ​​the back surface 12a of each die 10a, and the heat dissipation effect of each die 10a is limited.

[0004] 8 and 9 , before the cutting process, the heat dissipation layer 30 is formed on the back surface 12 of the wafer 10, so that when the cutting tool cuts the heat dissipation layer 30 and the wafer 10 simultaneously, the heat dissipation layer 30 forms multiple metal fragments P, and the metal fragments P adhere to the exposed surfaces of the carrier 20 and the die 10a, respectively.

[0005] 9, when each die 10a is picked and placed, metal fragments P remaining on the carrier 20 and the die 10a contaminated the active surface 11a of the die 10a. In addition, stress generated when cutting the heat dissipation layer 30 with a cutting tool caused the heat sink 30a to detach from the die 10a, affecting the quality and yield of the die 10a.

[0006] Therefore, the present inventors believed that the above-mentioned drawbacks could be improved, and as a result of extensive research, they came to propose the present invention, which effectively improves the above-mentioned problems through rational design.

[0007] The present invention has been made in consideration of the above, and its object is to provide a chip structure and a manufacturing method thereof in which a heat dissipation cover is formed on the back and side of a die after cutting a wafer, thereby increasing the heat dissipation area of ​​the heat dissipation cover, improving the heat dissipation efficiency, preventing the formation of metal fragments, increasing the mechanical strength of the heat dissipation cover, and preventing the heat dissipation cover from detaching from the die. [Means for solving the problem]

[0008] In order to solve the above problems, a method for manufacturing a chip structure according to one aspect of the present invention includes the steps of attaching a wafer (100) to a first carrier (200), the wafer having a plurality of unseparated dies (110), the wafer being attached to the first carrier by the backsides (112) of each of the dies and exposing the active surfaces (111) of each of the dies; cutting the wafer along dicing lanes (120) between the active surfaces of each of the dies to separate the dies, forming grooves (130) between the dies, and forming a front end of the ... The method includes the steps of exposing the side surfaces (113) of each of the dies from the grooves, attaching the wafer to a second carrier (300), the wafer being attached to the second carrier by the active surfaces of each of the dies already separated, removing the first carrier to expose the grooves and the back surfaces and the side surfaces of each of the dies, and forming a heat dissipation cover (140) for each of the dies to form a plurality of chip structures (A), the heat dissipation cover being directly formed to cover the back surfaces and the side surfaces. The heat dissipation cover has a first portion (141), a second portion (142) and a connection portion (143), the connection portion being located between the first portion and the second portion and connected to the first portion and the second portion, the first portion being formed on the back surface, the second portion being formed on the side surfaces by the grooves, and the connection portion being formed at an outer corner of the back surface. A first gap (S1) is provided between the connection portions of the adjacent chip structures, and a second gap (S2) is provided between the second portions of the adjacent chip structures, the first gap being smaller than the second gap, and the first gap and the second gap being gradually reduced by the second carrier toward the opening (131) of the groove. A first exposed surface (141a) of the first portion is connected to a third exposed surface (143a) of the connection portion, and a second exposed surface (142a) of the second portion is connected to a fourth exposed surface (143b) of the connection portion. Along a direction perpendicular to the back surface, the first portion has a first thickness (D1), and along a direction parallel to the back surface, the second portion has a second thickness (D2), and the first thickness is thicker than the second thickness.The second thickness is gradually reduced by the connecting portion toward the active surface, and the second exposed surface of the second portion is inclined toward the second carrier.

[0009] Also, a chip structure according to another aspect of the present invention is manufactured by the above-mentioned method. The chip structure includes a die (110) and a heat dissipation cover (140), and the heat dissipation cover is directly formed to cover the back surface (112) and side surface (113) of the die. The heat dissipation cover has a first part (141), a second part (142), and a connection part (143), and the connection part is located between the first part and the second part and connected to the first part and the second part, the first part is located on the back surface, the second part is located on the side surface, and the connection part is located at an outer corner of the back surface. A first exposed surface (141a) of the first part is connected to a third exposed surface (143a) of the connection part, and a second exposed surface (142a) of the second part is connected to a fourth exposed surface (143b) of the connection part. Along a direction perpendicular to the back surface, the first portion has a first thickness (D1), along a direction parallel to the back surface, the second portion has a second thickness (D2), the first thickness being greater than the second thickness, the second thickness being gradually reduced by the connection portion toward the active surface (111) of the die, and an acute angle is formed between the second exposed surface and the side surface.

[0010] In the present invention, after cutting the wafer, a heat dissipation cover is formed on the back and side of each die. This prevents the formation of metal fragments when the heat dissipation cover is cut, and also prevents the heat dissipation cover from detaching from the die due to the stress generated when cutting the heat dissipation cover. The second part and the connection part of the heat dissipation cover increase the heat dissipation area of ​​the heat dissipation cover and increase the mechanical strength, thereby preventing the heat dissipation cover from detaching from the die. [Brief description of the drawings]

[0011] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a chip structure according to an embodiment of the present invention. [Diagram 2]1A to 1C are cross-sectional views illustrating a method for manufacturing a chip structure according to an embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a chip structure according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a chip structure according to an embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a chip structure according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view illustrating a chip structure according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view illustrating a chip structure according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a conventional method for manufacturing a chip structure. [Figure 9] 1A to 1C are cross-sectional views illustrating a conventional method for manufacturing a chip structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The following describes a chip structure and a method for manufacturing the same according to an embodiment of the present invention with reference to the drawings. However, the present invention is not limited to this, and various modifications are possible within the scope of the description. The technical scope of the present invention also includes embodiments obtained by appropriately combining the technical means disclosed in the different embodiments.

[0013] First, a method for manufacturing a chip structure according to the present invention will be described with reference to FIGS.

[0014] The manufacturing method of the chip structure according to the present invention is used to manufacture a chip structure A having a heat dissipation cover. In the example of Fig. 1, first, a wafer 100 is attached to a first carrier 200. The wafer 100 has a plurality of dies 110, and the first carrier 200 is selected from adhesive tapes. The wafer 100 is attached to the first carrier 200 by the back surface 112 of each of the dies 110, and the active surface 111 of each of the dies 110 is exposed. The active surface 111 has a plurality of conductive pads 111a, and a redistribution circuit layer and / or bumps (not shown) are formed on the active surface 111, which are electrically connected to the conductive pads 111a.

[0015] 1 and 2 , a sawing process is then performed. A sawing tool (not shown) saws the wafer 100 along the dicing lanes 120 between the active surfaces 111 of the dies 110 toward the back surface 112, separating the dies 110 and forming grooves 130 between the dies 110. The grooves 130 expose the side surfaces 113 of the dies 110 and the first carrier 200.

[0016] Next, the wafer 100 is attached to the second carrier 300. The second carrier 300 is selected from an adhesive tape, and the wafer 100 is attached to the second carrier 300 by the active surface 111 of each of the separated dies 110, and the active surface 111 and the groove portion 130 are covered by the second carrier 300 (see FIG. 3). Next, the first carrier 200 is removed to expose the back surface 112, the side surface 113, and the groove portion 130 located between the dies 110 (see FIG. 4). In this embodiment, the wafer 100, the first carrier 200, and the second carrier 300 are inverted and attached together to be integrated, and then the first carrier 200 is removed, but the present invention is not limited thereto.

[0017] 5 and 6, next, a heat dissipation cover 140 is formed on the back surface 112 and the side surface 113 of each die 110, to form a plurality of chip structures A having the heat dissipation cover 140. The heat dissipation cover 140 is formed by physical vapor deposition (PVD), sputtering, or deposition, and the heat dissipation cover 140 is directly formed to cover the back surface 112 and the side surface 113. The heat dissipation cover 140 has a first part 141, a second part 142, and a connecting part 143, and the connecting part 143 is located between the first part 141 and the second part 142 and is connected to the first part 141 and the second part 142. The first part 141 is formed on the back surface 112, the second part 142 is formed on the side surface 113 by the groove part 130, and the connecting part 143 is formed at the outer corner of the back surface 112. Preferably, the width W of the groove 130 between the dies 110 is equal to or greater than 10 μm and does not exceed 2000 μm, which contributes to forming the second portion 142 covering the side surface 113. In this embodiment, the first virtual line L1 extending along the back surface 112 is located between the second portion 142 and the connection portion 143, and the second virtual line L2 extending along the side surface 113 is located between the first portion 141 and the second portion 142.

[0018] Next, in this embodiment, the heat dissipation cover 140 completely covers the back surface 112 and the side surface 113, and the second part 142 of the heat dissipation cover 140 completely covers the side surface 113 (see Figs. 5 and 6). The first exposed surface 141a of the first part 141 corresponds to the back surface 112, and the area of ​​the first exposed surface 141a is substantially the same as the area of ​​the back surface 112, and the second exposed surface 142a of the second part 142 corresponds to the side surface 113, and the area of ​​the second exposed surface 142a is larger than the area of ​​the side surface 113. The first exposed surface 141a is connected to the third exposed surface 143a of the connection part 143, and the second exposed surface 142a is connected to the fourth exposed surface 143b of the connection part 143. The first virtual line L1 is located between the second exposed surface 142a and the fourth exposed surface 143b, and the second virtual line L2 is located between the first exposed surface 141a and the third exposed surface 143a. 7, in another embodiment, the heat dissipation cover 140 completely covers the back surface 112 and partially covers the side surface 113. The second portion 142 of the heat dissipation cover 140 covers the first region 113a of the side surface 113 and exposes the second region 113b of the side surface 113. The first region 113a is adjacent to the back surface 112, the second region 113b is adjacent to the active surface 111, and the area of ​​the second exposed surface 142a of the second portion 142 is larger than the area of ​​the first region 113a.

[0019] As shown in Fig. 5, a first gap S1 is present between the connection parts 143 of adjacent chip structures A, and a second gap S2 is present between the second parts 142 of adjacent chip structures A, the first gap S1 being smaller than the second gap S2, and the first gap S1 and the second gap S2 are gradually reduced toward the opening 131 of the groove part 130 by the second carrier 300. Along a direction perpendicular to the back surface 112 (the direction of the axis Y as shown in Fig. 5), the first part 141 has a first thickness D1, and along a direction parallel to the back surface 112, the second part 142 has a second thickness D2, and the first thickness D1 is thicker than the second thickness D2. The first thickness D1 is 0.5 µm or more, which improves the uniformity of the first part 141 and the second part 142. The second thickness D2 is gradually reduced by the connection portion 143 toward the active surface 111, and the second exposed surface 142a of the second portion 142 is inclined toward the second carrier 300. Next, as shown in FIG. 6, an acute angle B is formed between the second exposed surface 142a and the side surface 113, and the area of ​​the second exposed surface 142a is larger than the area of ​​the side surface 113. Along a direction parallel to the back surface 112, the connection portion 143 has a third thickness D3, and the third thickness D3 is thicker than the second thickness D2. The third thickness D3 is gradually reduced by the connection portion 143 toward the second portion 142, and the area of ​​the fourth exposed surface 143b of the connection portion 143 is increased by inclining the fourth exposed surface 143b toward the second carrier 300. In addition, the connection portion 143 increases the mechanical strength of the heat dissipation cover 140, thereby preventing the second portion 142 from detaching from the side surface 113.

[0020] 5 and 6, the first connection surface 143c of the connection portion 143 is located on the first virtual line L1, and the second connection surface 143d of the connection portion 143 is located on the second virtual line L2. Since the third thickness D3 of the connection portion 143 gradually decreases toward the second portion 142, the area of ​​the second connection surface 143d is larger than the area of ​​the first connection surface 143c, thereby increasing the areas of the third exposed surface 143a and the fourth exposed surface 143b of the connection portion 143.

[0021] 5 to 7, after a pick and place process, the chip structure A is detached from the second carrier 300. The chip structure A includes a die 110 and a heat dissipation cover 140 formed directly on the back surface 112 and the side surface 113.

[0022] In this way, the present invention increases the heat dissipation area of ​​the heat dissipation cover 140 by the second exposed surface 142a of the second part 142, and the third exposed surface 143a and fourth exposed surface 143b of the connecting part 143. By forming the heat dissipation cover 140 on the back surface 112 and the side surface 113 of the die 110 after the cutting process, it is possible to prevent metal fragments from being formed when cutting the heat dissipation cover 140, and the connecting part 143 enhances the mechanical strength of the heat dissipation cover 140, thereby preventing the heat dissipation cover 140 from being detached from the die 110.

[0023] As described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0024] 10 Wafers 10a die 11 Active Surface 11a Active surface 12 Back side 12a back side 20 Career 30 Heat dissipation layer 30a heat sink P Metal fragments 100 wafers 110 Die 111 Active Surface 111a Conductive Pad 112 Back side 113 Side 113a 1st area 113b 2nd area 120 Dicing Lane 130 Groove 131 Opening 140 Heat sink cover 141 Part 1 141a 1st exposed surface 142 Part 2 142a 2nd exposed surface 143 Connection 143a 3rd exposed surface 143b 4th exposed surface 143c First connection surface 143d Second connection surface 200 1st Career 300 Second Carrier A-Chip structure B Acute angle D1 First thickness D2 Second thickness D3 Third thickness L1 First virtual line L2 Second virtual line S1 First gap S2 Second gap W width Y-Axis

Claims

1. attaching a wafer (100) to a first carrier (200), the wafer having a plurality of unseparated dies (110), the wafer being attached to the first carrier by a backside (112) of each of the dies and exposing an active side (111) of each of the dies; sawing the wafer along dicing lanes (120) between the active surfaces of each of the dies to separate the dies and form grooves (130) between the dies, exposing a side surface (113) of each of the dies through the grooves; attaching the wafer to a second carrier (300), the wafer being attached to the second carrier by the active surface of each of the dies already separated; removing the first carrier to expose the groove and the back and side surfaces of each of the die; A heat dissipation cover (140) is formed on each of the dies to form a plurality of chip structures (A), the heat dissipation cover is directly formed to cover the back surface and the side surface, the heat dissipation cover has a first part (141), a second part (142) and a connection part (143), the connection part is located between the first part and the second part and is connected to the first part and the second part, the first part is formed on the back surface, the second part is formed on the side surface by the groove part, the connection part is formed at an outer corner of the back surface, there is a first gap (S1) between adjacent connection parts, and there is a second gap (S2) between adjacent second parts, the first gap is smaller than the second gap, and the first gap and the front the second gap is reduced by the second carrier toward an opening (131) of the groove portion, a first exposed surface (141a) of the first portion is connected to a third exposed surface (143a) of the connection portion, and a second exposed surface (142a) of the second portion is connected to a fourth exposed surface (143b) of the connection portion, the first portion has a first thickness (D1) along a direction perpendicular to the back surface, and the second portion has a second thickness (D2) along a direction parallel to the back surface, the first thickness being thicker than the second thickness, and the second thickness is reduced by the connection portion toward the active surface, and the second exposed surface of the second portion is inclined toward the second carrier.

2. 2. A method for manufacturing a chip structure as described in claim 1, characterized in that a first virtual line (L1) extending along the back surface is located between the second portion and the connection portion, a second virtual line (L2) extending along the side surface is located between the first portion and the second portion, and an area of ​​the second exposed surface is larger than an area of ​​the side surface.

3. 2. The method for manufacturing a chip structure according to claim 1, wherein a first virtual line (L1) extending along the back surface is located between the second portion and the connection portion, a second virtual line (L2) extending along the side surface is located between the first portion and the second portion, the second portion covers a first region (113a) of the side surface and exposes a second region (113b) of the side surface, the first region is adjacent to the back surface, the second region is adjacent to the active surface, and an area of ​​the second exposed surface is larger than an area of ​​the first region.

4. 2. The method for manufacturing a chip structure according to claim 1, characterized in that the connection portion has a first connection surface (143c) and a second connection surface (143d), the first connection surface being located on a first virtual line (L1) extending along the back surface, the second connection surface being located on a second virtual line (L2) extending along the side surface, and an area of ​​the second connection surface being larger than an area of ​​the first connection surface.

5. A method for manufacturing a chip structure as described in claim 1, characterized in that along the direction parallel to the back surface, the connection portion has a third thickness (D3), the third thickness is thicker than the second thickness, the third thickness is reduced toward the second portion by the connection portion, and the fourth exposed surface of the connection portion is inclined toward the second carrier.

6. 2. The method for manufacturing a chip structure according to claim 1, wherein the width of the groove is 10 [mu]m or more.

7. 2. The method for manufacturing a chip structure according to claim 1, wherein the first thickness is 0.5 [mu]m or more.

8. A die (110); A heat dissipation cover (140) formed directly on the back surface (112) and side surface (113) of the die so as to cover the same, the heat dissipation cover having a first portion (141), a second portion (142), and a connection portion (143), the connection portion being located between the first portion and the second portion and connected to the first portion and the second portion, the first portion being located on the back surface, the second portion being located on the side surface, the connection portion being located at an outer corner of the back surface, and a first exposed surface (141a) of the first portion being connected to a third exposed surface (143a) of the connection portion. a second exposed surface (142a) of the second portion is connected to a fourth exposed surface (143b) of the connection portion, the first portion has a first thickness (D1) along a direction perpendicular to the back surface, and the second portion has a second thickness (D2) along a direction parallel to the back surface, the first thickness being greater than the second thickness, and the second thickness being reduced by the connection portion toward an active surface (111) of the die, and an acute angle is formed between the second exposed surface and the side surface.

9. The chip structure of claim 8, characterized in that a first virtual line (L1) extending along the back surface is located between the second portion and the connection portion, a second virtual line (L2) extending along the side surface is located between the first portion and the second portion, and an area of ​​the second exposed surface is larger than an area of ​​the side surface.

10. 9. The chip structure of claim 8, wherein a first virtual line (L1) extending along the back surface is located between the second portion and the connection portion, a second virtual line (L2) extending along the side surface is located between the first portion and the second portion, the second portion covers a first region (113a) of the side surface and exposes a second region (113b) of the side surface, the first region is adjacent to the back surface, the second region is adjacent to the active surface, and an area of ​​the second exposed surface is larger than an area of ​​the first region.

11. The chip structure of claim 8, characterized in that the connection portion has a first connection surface (143c) and a second connection surface (143d), the first connection surface is located on a first virtual line (L1) extending along the back surface, the second connection surface is located on a second virtual line (L2) extending along the side surface, and an area of ​​the second connection surface is larger than an area of ​​the first connection surface.

12. The chip structure described in claim 8, characterized in that along the direction parallel to the back surface, the connection portion has a third thickness (D3), the third thickness being thicker than the second thickness, and the third thickness being reduced toward the second portion by the connection portion.

13. The chip structure of claim 8 , wherein the first thickness is 0.5 μm or more.

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