Photoelectric conversion devices and equipment

Abstract

To provide a technique for changing the gain of a photoelectric conversion apparatus while suppressing an increase in chip size.SOLUTION: A photoelectric conversion apparatus includes: a light receiving circuit that converts light into an electrical signal; a readout circuit that reads out an analog signal corresponding to the electrical signal; a ΔΣ AD converter that converts the analog signal into a digital signal; and a control circuit that changes the gain of the photoelectric conversion apparatus according to a change in the drive mode of the photoelectric conversion apparatus. The control circuit changes the gain of the photoelectric conversion apparatus by changing the setting of the ΔΣ AD converter.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. reference and equipment. [Background technology]

[0002] Various techniques have been proposed to widen the range of input signals in photoelectric conversion devices. In Patent Document 1, a sample-and-hold circuit that holds a noise signal and a data signal is configured with multiple capacitive elements, and the gain is changed by changing the number of capacitive elements used for holding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] In a configuration in which the gain is changed by changing the number of capacitive elements in a sample-and-hold circuit as in Patent Document 1, it is necessary to mount many capacitive elements, which increases the chip size. An object of some aspects of the present invention is to provide a technology that makes it possible to change the gain of a photoelectric conversion device while suppressing an increase in chip size. [Means for solving the problem]

[0005] In view of the above problems, there is provided a photoelectric conversion device comprising: a light receiving circuit that converts light into an electric signal; a readout circuit that reads out an analog signal corresponding to the electric signal; a ΔΣ AD converter that converts the analog signal into a digital signal; and a control circuit that changes a gain of the photoelectric conversion device in accordance with a change in a drive mode of the photoelectric conversion device, wherein the analog signal read out by the readout circuit is an analog current signal, and the readout circuit has a variable resistor on a signal path that supplies the analog current signal to the ΔΣ AD converter, a voltage of a data signal is input to one node of the variable resistor, a voltage of a noise signal is input to the other node of the variable resistor, and the analog current signal corresponding to the difference between the data signal and the noise signal is generated by a current flowing through the variable resistor; The control circuit changes the resistance value of the variable resistor to change the gain of the photoelectric conversion device. [Effects of the Invention]

[0006] By using the above means, it becomes possible to change the gain of the photoelectric conversion device while suppressing an increase in chip size. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a photoelectric conversion device 100 according to some embodiments. [Figure 2] FIG. 2 is a diagram illustrating an example of the circuit configuration of a pixel circuit 111 according to some embodiments. [Figure 3] FIG. 2 is a diagram illustrating an example of the circuit configuration of a pixel circuit 111 according to some embodiments. [Figure 4] FIG. 2 is a diagram illustrating an example of the circuit configuration of a read circuit 121 according to some embodiments. [Figure 5] FIG. 1 is a diagram illustrating an example of the circuit configuration of a ΔΣ modulator according to some embodiments. [Figure 6] FIG. 2 is a diagram illustrating an example of a circuit configuration of a current generating circuit according to some embodiments. [Figure 7] FIG. 10 is a diagram illustrating another example circuit configuration of a ΔΣ modulator according to some embodiments. [Figure 8] FIG. 1 is a diagram illustrating an example of the configuration of a device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0009] The following mainly describes an embodiment in which the photoelectric conversion device 100 is used for imaging. In this case, the photoelectric conversion device 100 can be used as an imaging element (image sensor) for generating an image. Other examples of the photoelectric conversion device 100 include a rangefinder (a sensor used for focus detection or distance measurement using TOF (Time Of Flight)), a photometry element (a sensor used for measuring the amount of incident light), a LiDAR (Light Detection and Ranging) sensor, etc. The embodiments described below can be applied to photoelectric conversion devices in general.

[0010] An example configuration of a photoelectric conversion device 100 according to some embodiments will be described with reference to the block diagram of Fig. 1. In the example shown in Fig. 1, the photoelectric conversion device 100 includes a pixel unit 110, a readout unit 120, an AD conversion unit 130, a horizontal scanning circuit 140, a signal processing circuit 150, an output circuit 160, a vertical scanning circuit 170, and a timing control circuit 180.

[0011] The pixel section 110 includes a plurality of pixel circuits 111 arranged in a two-dimensional array, a plurality of drive lines 112 provided for each pixel row, and a plurality of signal lines 113 provided for each pixel column. The pixel rows refer to the plurality of pixel circuits 111 lined up in the horizontal direction in Fig. 1. The pixel columns refer to the plurality of pixel circuits 111 lined up in the vertical direction in Fig. 1.

[0012] The pixel circuits 111 convert incident light into an electric signal. Therefore, the pixel circuits 111 may also be called light receiving circuits. A control signal is supplied to each of the plurality of pixel circuits 111 from the vertical scanning circuit 170 via a drive line 112. An electric signal is read out from the pixel circuit 111 to which an active level control signal has been supplied by the readout unit 120 via a signal line 113.

[0013] The readout unit 120 includes a plurality of readout circuits 121 provided for each signal line 113, and a control circuit 122 that controls the operation of these readout circuits 121. The readout circuits 121 read out analog signals corresponding to the electrical signals generated by the pixel circuits 111, and supply the analog signals to the AD conversion unit 130.

[0014] The AD conversion unit 130 includes a plurality of AD converters 131 provided for each signal line 113, and a control circuit 132 that controls the operation of these AD converters 131. The AD converters 131 convert the analog signals supplied from the readout circuit 121 into digital signals. In the following description, the AD converters 131 are ΔΣ AD converters.

[0015] The horizontal scanning circuit 140 sequentially reads out the digital signals from the plurality of AD converters 131 and supplies them to the signal processing circuit 150. The photoelectric conversion device 100 may have a memory circuit for storing the digital signals between the AD conversion unit 130 and the horizontal scanning circuit 140. The signal processing circuit 150 processes digital signals corresponding to the electrical signals generated by each pixel circuit 111. The signal processing circuit 150 may perform correction processing, interpolation processing, etc. on the digital signals, for example.

[0016] The digital signal processed by the signal processing circuit 150 is output from the output circuit 160 to an external device 190 outside the photoelectric conversion device 100. The external device 190 may be, for example, a control device for a device incorporating the photoelectric conversion device 100. The timing control circuit 180 controls the overall operation of the photoelectric conversion device 100 by supplying control signals to each circuit of the photoelectric conversion device 100. For example, the timing control circuit 180 may change the drive mode of the photoelectric conversion device 100 in response to an instruction from the external device 190. The timing control circuit 180 changes the gain of the photoelectric conversion device 100 in response to the change in the drive mode of the photoelectric conversion device 100. Specific examples of gain change methods will be described later. The change in drive mode may include a change between a still image capture mode and a video capture mode for photography using the photoelectric conversion device 100. The change in drive mode may include a change in sensitivity for photography using the photoelectric conversion device 100. The change in drive mode may include a change in the resolution of AD conversion by the AD converter 131. The change in the driving mode may include a change in the frame rate of video shooting using the photoelectric conversion device 100. The change in the driving mode may include at least one of the above examples.

[0017] A specific example of the circuit configuration of the pixel circuit 111 will be described with reference to the circuit diagram in Fig. 2. The pixel circuit 111 can have any configuration that converts incident light into an electrical signal. Fig. 2 describes one example, but the pixel circuit 111 may have other configurations.

[0018] 2, the pixel circuit 111 includes a photoelectric conversion element 201, a transfer transistor 202, a reset transistor 203, an amplification transistor 204, and a selection transistor 205. In the example of Fig. 2, the pixel unit 110 includes three drive lines 112 for each pixel row, which supply control signals PRES, PTX, and PSEL to the pixel circuit 111, respectively.

[0019] The photoelectric conversion element 201 converts incident light into electric charges and accumulates the electric charges. The photoelectric conversion element 201 may be, for example, a photodiode or a phototransistor. The photoelectric conversion element 201 may be a CMOS (Complementary Metal Oxide Semiconductor) sensor. Alternatively, the photoelectric conversion element 201 may be a SPAD (Single Photon Avalanche Diode) sensor.

[0020] The photoelectric conversion element 201 is connected to a floating diffusion 206 via a transfer transistor 202. A control signal PTX is supplied to the gate of the transfer transistor 202 from the vertical scanning circuit 170. When the control signal PTX becomes active level, the transfer transistor 202 becomes conductive. In response to this, the signal charge accumulated in the photoelectric conversion element 201 is transferred to the floating diffusion 206.

[0021] The floating diffusion 206 is also connected to the gate of the amplification transistor 204. One main electrode of the amplification transistor 204 is connected to the signal line 113 via the selection transistor 205. The other main electrode of the amplification transistor 204 is connected to the power supply potential VDD. A control signal PSEL is supplied to the gate of the selection transistor 205 from the vertical scanning circuit 170. In response to the control signal PSEL becoming active level, the selection transistor 205 becomes conductive. In response to this, one main electrode of the amplification transistor 204 is connected to the current source of the readout circuit 121. As a result, the amplification transistor 204 operates as a source follower, and a signal corresponding to the potential of the floating diffusion 206 is read out to the signal line 113.

[0022] The reset transistor 203 is connected between the floating diffusion 206 and the power supply potential VDD. A control signal PRES is supplied to the gate of the reset transistor 203 from the vertical scanning circuit 170. In response to the control signal PRES becoming active level, the reset transistor 203 becomes conductive. In response to this, the potential of the floating diffusion 206 is reset to the power supply potential VDD.

[0023] A specific example of the circuit configuration of the readout circuit 121 will be described with reference to the circuit diagram of Fig. 3. The readout circuit 121 can have any configuration that reads out the electrical signal generated in the pixel circuit 111. Fig. 3 describes one example, but the readout circuit 121 may have other configurations.

[0024] In the example illustrated in FIG. 3, the readout circuit 121 includes current sources 301 , 308 , and 309 , sample-and-hold circuits 302 and 303 , amplifiers 304 and 306 , transistors 305 and 307 , and a resistor 312 .

[0025] A current source 301 supplies a bias current to the pixel circuit 111 (specifically, its amplification transistor 204). Sample-and-hold circuits 302 and 303 each hold an output voltage from the pixel circuit 111. A timing control circuit 180 controls the pixel circuit 111 to output an electrical signal when the photoelectric conversion element 201 is in a reset state (hereinafter referred to as a noise signal) and an electrical signal corresponding to incident light (hereinafter referred to as a data signal). In accordance with instructions from the timing control circuit 180, the control circuit 122 controls the readout circuit 121 to read out the noise signal and hold it in the sample-and-hold circuit 302. In addition, in accordance with instructions from the timing control circuit 180, the control circuit 122 controls the readout circuit 121 to read out the data signal from the pixel circuit 111 and hold it in the sample-and-hold circuit 303.

[0026] The amplifier 304 and the transistor 305 function as a source follower. The current source 308 supplies a bias current to the source follower. The potential of a node 310 between the current source 308 and the transistor 305 has a value corresponding to the voltage (noise signal) held in the sample-and-hold circuit 302.

[0027] The amplifier 306 and the transistor 307 function as a source follower. The current source 309 supplies a bias current to the source follower. The potential of a node 311 between the current source 309 and the transistor 307 has a value corresponding to the voltage (data signal) held in the sample-and-hold circuit 303.

[0028] Resistor 312 is connected between node 310 and node 311. Therefore, the voltage applied to resistor 312 is the potential difference between node 310 and node 311. Therefore, an analog current signal corresponding to the difference between the data signal and the noise signal is supplied from read circuit 121 to AD converter 131. In this way, read circuit 121 has a function of performing correlated double sampling (CDS).

[0029] In some embodiments, the resistor 312 may be a variable resistor. The resistor 312 is located on a signal path that supplies an analog current signal from the readout circuit 121 to the AD converter 131. Therefore, the control circuit 122 can change the value of the analog current signal sent to the AD converter 131 for the same data signal by changing the resistance value of the resistor 312. Specifically, by decreasing the resistance value of the resistor 312, the value of the analog current signal sent to the AD converter 131 for the same data signal increases, thereby increasing the gain of the photoelectric conversion device 100. Conversely, by increasing the resistance value of the resistor 312, the value of the analog current signal sent to the AD converter 131 for the same data signal decreases, thereby decreasing the gain of the photoelectric conversion device 100. In this way, the control circuit 122 can change the gain of the photoelectric conversion device 100 by changing the resistance value of the resistor 312.

[0030] A specific circuit configuration example of the AD converter 131 will be described with reference to the block diagram of FIG. 4. The AD converter 131 is a ΔΣ AD converter. The AD converter 131 converts an input analog signal into a digital signal. The AD converter 131 in FIG. 4(a) includes a first-order ΔΣ modulator 404 and a decimation filter 405. The AD converter 131 in FIG. 4(b) includes a second-order ΔΣ modulator 407 and a decimation filter 405. Alternatively, the AD converter 131 may include a third-order or higher-order ΔΣ modulator. Using a higher-order ΔΣ modulator improves the noise shaping effect. The ΔΣ modulators 404 and 407 convert the input analog signal into a 1-bit digital signal string. The decimation filter 405 performs decimation (thinning) on ​​this 1-bit digital signal string. For example, the decimation filter 405 generates a digital signal corresponding to the proportion of the time during which the 1-bit digital signal string is 1 within a predetermined time period. The delta-sigma modulator 404 may convert the input analog signal into a digital signal sequence of 2 or more bits.

[0031] 4(a), the first-order ΔΣ modulator 404 has a subtractor 401, an integrator 402, a quantizer 403, and a DA converter (DAC) 406. The subtractor 401 is supplied with an input to the AD converter 131 (i.e., the analog signal from the readout circuit 121). The subtractor 401 is also supplied with an analog signal from the DA converter 406. The subtractor 401 supplies the difference between the analog signal from the readout circuit 121 and the analog signal from the DA converter 406 to the integrator 402.

[0032] The integrator 402 integrates the output from the subtractor 401. The quantizer 403 quantizes the integration result from the integrator 402. For example, the quantizer 403 generates a 1-bit digital signal sequence based on the integration result and supplies it to the decimation filter 405. The output from the quantizer 403 becomes the output from the ΔΣ modulator 404.

[0033] The output from the quantizer 403 is also supplied to the DA converter 406. The DA converter 406 generates a signal according to the output from the quantizer 403 and supplies this to the subtractor 401. The signal supplied from the DA converter 406 to the subtractor 401 is subtracted from the analog signal supplied from the readout circuit 121, as described above.

[0034] 4(b), the second-order ΔΣ modulator 404 has subtractors 401 and 408, integrators 402 and 409, a quantizer 403, and DA converters (DACs) 406 and 410. The configurations of the subtractor 401, the integrator 402, the quantizer 403, and the DA converter (DAC) 406 are the same as those of the first-order ΔΣ modulator 404.

[0035] The output from the integrator 402 is supplied to the subtractor 408. In addition, the analog signal from the DA converter 410 is also supplied to the subtractor 408. The subtractor 408 supplies the difference between the analog signal from the integrator 402 and the analog signal from the DA converter 410 to the integrator 409. The integrator 409 integrates the output from the subtractor 408. The quantizer 403 quantizes the integration result from the integrator 409.

[0036] The output from the quantizer 403 is also supplied to a DA converter 410. The DA converter 410 generates a signal according to the output from the quantizer 403 and supplies this to a subtractor 408. The signal supplied from the DA converter 410 to the subtractor 408 is subtracted from the analog signal supplied from the integrator 402, as described above.

[0037] 5, an example of the circuit configuration of the ΔΣ modulators 404 and 407 when the input to the AD converter 131 is an analog current signal will be described. Fig. 5(a) shows an example of the circuit configuration of the first-order ΔΣ modulator 404, and Fig. 5(b) shows an example of the circuit configuration of the second-order ΔΣ modulator 407.

[0038] First, we will explain an example of the circuit configuration of the first-order ΔΣ modulator 404. The subtractor 401 is composed of a node 501 connected to the readout circuit 121, the DA converter 406, and the integrator 402. The analog current from the DA converter 406 is subtracted from the analog current signal from the readout circuit 121 supplied to the node 501, and the resulting current is supplied to the integrator 402.

[0039] The integrator 402 is composed of a capacitor 502. The capacitor 502 is charged by the output from the subtractor 401 so as to integrate the output. The voltage of the capacitor 502 is supplied to the quantizer 403. The quantizer 403 is composed of a comparator 503. The comparator 503 outputs a high-level or low-level voltage depending on the value of the voltage supplied from the integrator 402.

[0040] The DA converter 406 is composed of a switch element 504 and a current generating circuit 505. The current generating circuit 505 generates an analog current to be supplied to the subtractor 401. The switch element 504 is located on a signal path between the subtractor 401 and the current generating circuit 505. The on / off state of the switch element 504 is switched depending on the output from the quantizer 403. When the output from the quantizer 403 is high, the switch element 504 is turned on, and as a result, a current is supplied from the current generating circuit 505 to the subtractor 401. On the other hand, when the output from the quantizer 403 is low, the switch element 504 is turned off, and as a result, no current is supplied from the current generating circuit 505 to the subtractor 401. In this way, the value of the analog current supplied from the DA converter 406 to the subtractor 401 changes depending on the output from the quantizer 403.

[0041] Next, an example circuit configuration of the second-order ΔΣ modulator 407 will be described. The ΔΣ modulator 407 has subtractors 401 and 408, integrators 402 and 409, a Gm amplifier 506, a quantizer 403, and DA converters 406 and 410. The circuit configurations of the subtractor 401, the integrator 402, the quantizer 403, and the DA converter 406 are the same as those of the first-order ΔΣ modulator 404. The Gm amplifier 506 is an amplifier that converts the analog voltage signal supplied from the integrator 402 into an analog current signal and supplies this to the subtractor 408. The analog voltage signal is supplied from the integrator 402 to the inverting input terminal of the Gm amplifier 506, and a reference voltage Vref is supplied from the control circuit 132 to the non-inverting input terminal of the Gm amplifier 506.

[0042] The subtractor 408 is configured with a node 507 connected to the Gm amplifier 506, the DA converter 410, and the integrator 409. The analog current from the DA converter 410 is subtracted from the analog current signal from the Gm amplifier 506 supplied to the node 507, and the resulting current is supplied to the integrator 409. The integrator 409 is configured with a capacitor 508. The capacitor 508 is charged by the output from the Gm amplifier 506 so as to integrate the output. The voltage of the capacitor 508 is supplied to the quantizer 403.

[0043] The DA converter 410 is composed of a switch element 509 and a current generating circuit 510. The current generating circuit 510 generates an analog current to be supplied to the subtractor 408. The switch element 509 is located on a signal path between the subtractor 408 and the current generating circuit 510. The on / off state of the switch element 509 is switched depending on the output from the quantizer 403. When the output from the quantizer 403 is at a high level, the switch element 509 is turned on, and as a result, a current is supplied from the current generating circuit 510 to the subtractor 408. On the other hand, when the output from the quantizer 403 is at a low level, the switch element 509 is turned off, and as a result, no current is supplied from the current generating circuit 510 to the subtractor 408. In this way, the value of the analog current supplied from the DA converter 416 to the subtractor 408 changes depending on the output from the quantizer 403.

[0044] A specific example of the circuit configuration of the current generating circuit 505 will be described with reference to the circuit diagram in FIG. 6. The current generating circuit 505 can have any configuration that allows the amount of current to be generated to be changed. Although FIG. 6 describes one example, the current generating circuit 505 may have other configurations. The current generating circuit 510 may have the same circuit configuration as the current generating circuit 505.

[0045] The current generating circuit 505 has transistors 601 and 602, switch elements 603 and 604, and a capacitor 605. The transistor 601 is connected between the switch element 504 and ground. The transistors 602 and 603 are connected in series between the switch element 504 and ground. A bias voltage Vbias is supplied to the gates of the transistors 601 and 602 from the control circuit 132 via the switch element 604. The bias voltage Vbias is also supplied to the capacitor 605.

[0046] The switch element 604 and the capacitor 605 form a sample-and-hold circuit. Even when the switch element 604 is turned off, the bias voltage Vbias held in the capacitor 605 is supplied to the gates of the transistors 601 and 602.

[0047] Transistors 601 and 602 each function as a current source that generates a current according to a bias voltage Vbias supplied to the gate. The current generated by transistor 601 is supplied to switch element 504. The current generated by transistor 602 is supplied to switch element 504 when switch element 603 is on. The current generated by transistor 602 is not supplied to switch element 504 when switch element 603 is off. The on / off of switch elements 603 and 604 is controlled by a control signal supplied from control circuit 132.

[0048] In this way, the value of the analog current supplied from current generating circuit 505 to switch element 504 changes depending on whether switch element 603 is on or off. Specifically, a larger current is supplied when switch element 603 is on than when switch element 603 is off. Furthermore, it is also possible to change the current values ​​generated by each of transistors 601 and 602 by changing the value of bias voltage Vbias. By having such a current generating circuit 505, the DA converter 406 can change the value of the analog current supplied from DA converter 406 to subtractor 401 for the same output (high level in the above example) from quantizer 403.

[0049] 7, an example circuit configuration of the first-order ΔΣ modulator 404 when the input to the AD converter 131 is an analog voltage signal will be described. The subtractor 401 is composed of a capacitor 701. One terminal of the capacitor 701 is connected to the readout circuit 121 and the DA converter 406. The other terminal of the capacitor 701 is connected to the integrator 402. The analog voltage from the DA converter 406 is subtracted from the analog voltage signal from the readout circuit 121 that is supplied to the capacitor 701, and the resulting voltage is supplied to the integrator 402.

[0050] The integrator 402 is composed of an operational amplifier 702 and capacitors 703 and 704. The capacitor 703 is connected between the input and output of the operational amplifier 702. The capacitor 704 is connected between the operational amplifier 702 and the subtractor 401. The quantizer 403 is composed of a comparator 705. The comparator 705 outputs a high-level or low-level voltage depending on the value of the voltage supplied from the integrator 402.

[0051] The DA converter 406 is configured by a switch element 706. The control circuit 132 supplies the switch element 706 with voltages VH and VL. The voltage VH is greater than the voltage VL. The switch element 706 supplies one of the voltages VH and VL to the subtractor 401 based on the output from the quantizer 403. In this way, the value of the analog voltage supplied from the DA converter 406 to the subtractor 401 varies depending on the output from the quantizer 403. The control circuit 132 may supply the voltages VH and VL supplied from an external source to the switch element 706, or may generate the voltages VH and VL itself.

[0052] As described above, the timing control circuit 180 changes the gain of the photoelectric conversion device 100 in response to a change in the drive mode of the photoelectric conversion device 100. As described above, the timing control circuit 180 may change the gain of the photoelectric conversion device 100 by changing the resistance value of the resistor 312. Alternatively or in addition to this, the timing control circuit 180 may change the gain of the photoelectric conversion device 100 by changing the setting of the AD converter 131.

[0053] Specifically, when an analog current signal is supplied to the AD converter 131, changing the setting of the AD converter 131 may include changing the value of the analog current supplied from the DA converter 406 to the subtractor 401 for the same output from the quantizer 403. Also, when an analog current signal is supplied to the AD converter 131, changing the setting of the AD converter 131 may include changing the value of the analog current supplied from the DA converter 410 to the subtractor 408 for the same output from the quantizer 403. The former case will be specifically described below. Changing the value of the analog current supplied from the DA converter 406 to the subtractor 401 may include changing the number of transistors connected to the subtractor 401 or 408, among the plurality of transistors 601 and 602, as described above. Alternatively or in addition to this, changing the value of the analog current supplied from the DA converter 406 to the subtractor 401 may include changing the value of the voltage Vbias supplied to the gates of the transistors 601 and 602. By changing the value of the voltage Vbias, the current can be changed more precisely than by changing the number of transistors.

[0054] When an analog current signal is supplied to the AD converter 131, changing the setting of the AD converter 131 may include changing the value of the reference voltage Vref supplied to the Gm amplifier 506. By changing the value of the reference voltage Vref, the output from the Gm amplifier 506 changes for the same output from the integrator 402. This also changes the gain of the AD converter 131.

[0055] When an analog voltage signal is supplied to the AD converter 131, changing the setting of the AD converter 131 may include changing the value of the analog voltage supplied from the DA converter 406 to the subtractor 401 for the same output from the quantizer 403. Furthermore, when an analog voltage signal is supplied to the AD converter 131, changing the setting of the AD converter 131 may include changing the value of the analog voltage supplied from the DA converter 410 to the subtractor 408 for the same output from the quantizer 403. For example, the control circuit 132 may change one or both of the voltage VH and the voltage VL described in FIG. 7. As a result, for the same output from the quantizer 403, the value subtracted from the input analog voltage signal changes, and therefore the gain of the AD converter 131 also changes.

[0056] Changing the settings of the AD converter 131 may include changing the settings of the decimation filter 405. The settings to be changed may be, for example, the constant of the decimation filter 405 or the frequency of the clock signal of the decimation filter 405.

[0057] Any of the above-described methods for changing the gain of the photoelectric conversion device 100 can suppress an increase in chip size compared to changing the number of capacitors. In the above-described embodiment, the photoelectric conversion device 100 has one AD converter 131 for each pixel column. Alternatively, the photoelectric conversion device 100 may have a common AD converter 131 for multiple pixel columns. In the above-described embodiment, correlated double sampling is performed in the readout circuit 121. Alternatively, the readout circuit 121 may supply a noise signal and a data signal to the AD converter 131, respectively, without performing correlated double sampling. The AD converter 131 performs AD conversion on the noise signal and the data signal, respectively. The signal processing circuit 150 may calculate the difference between the noise signal and the data signal after AD conversion.

[0058] With reference to FIG. 8(a), an embodiment of a device 800 including a semiconductor device 803 will be described in detail. The semiconductor device 803 may be the photoelectric conversion device of any of the above-described embodiments. The semiconductor device 803 may include a semiconductor device 801 and a package 802 that houses the semiconductor device 801. The package 802 may include a base to which the semiconductor device 801 is fixed, and a lid such as glass that faces the semiconductor device 801. The package 802 may further include a bonding member such as a bonding wire or bump that connects a terminal provided on the base to a terminal (bonding pad) provided on the semiconductor device 801.

[0059] The device 800 may include at least one of an optical device 804, a control device 805, a processing device 806, a display device 807, a storage device 808, and a mechanical device 809. The optical device 804 is, for example, a lens, a shutter, or a mirror. The optical device 804 corresponds to a photoelectric conversion device. The control device 805 controls the semiconductor device 803. The control device 805 is, for example, a semiconductor device such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0060] The processing device 806 processes the signal output from the semiconductor device 803. The processing device 806 is a semiconductor device such as a CPU (Central Processing Unit) or ASIC for configuring an AFE (Analog Front End) or a DFE (Digital Front End). The display device 807 is an EL (Electro-Luminescence) display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 803. The storage device 808 is a magnetic device or a semiconductor device that stores the information (images) obtained by the semiconductor device 803. The storage device 808 is a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory), or a non-volatile memory such as a flash memory or a hard disk drive.

[0061] The mechanical device 809 has a moving part or a propulsion part such as a motor or an engine. In the device 800, the signal output from the semiconductor device 803 is displayed on the display device 807, or transmitted to the outside by a communication device (not shown) provided in the device 800. For this purpose, the device 800 may further include a storage device 808 and a processing device 806 in addition to the storage circuit and arithmetic circuit provided in the semiconductor device 803. The mechanical device 809 may be controlled based on the signal output from the semiconductor device 803.

[0062] The device 800 is also suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 809 in the camera may drive components of the optical device 804 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 809 in the camera may move the semiconductor device 803 for vibration isolation.

[0063] Furthermore, the device 800 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 809 in the transportation equipment may be used as a moving device. The device 800 as transportation equipment may transport the semiconductor device 803 or may assist and / or automate driving (piloting) using a photographing function. The processing device 806 for assisting and / or automating driving (piloting) may perform processing to operate the mechanical device 809 as a moving device based on information obtained by the semiconductor device 803. Alternatively, the device 800 may be a medical device such as an endoscope, a measuring device such as an analytical distance sensor, an analytical device such as an electron microscope, or office equipment such as a copier.

[0064] An embodiment of an imaging system and a moving object will be described using FIGS. 8(b) and 8(c). FIG. 8(b) shows an example of an imaging system 810 related to an in-vehicle camera. The imaging system 810 includes a photoelectric conversion device 811. The photoelectric conversion device 811 may be any of the photoelectric conversion devices described in the above-described embodiments. The imaging system 810 includes an image processing unit 812, which is a processing device that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 811. The imaging system 810 also includes a parallax acquisition unit 813, which is a processing device that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion device 811. The imaging system 810 also includes a distance acquisition unit 814, which is a processing device that calculates the distance to an object based on the calculated parallax, and a collision determination unit 815, which is a processing device that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 813 and the distance acquisition unit 814 are examples of information acquisition means that acquire information such as distance information to an object. That is, the distance information is information related to parallax, defocus amount, distance to the object, etc. The collision determination unit 815 may determine the possibility of a collision using any of this distance information. The various processing devices described above may be realized by dedicated hardware or by general-purpose hardware that performs calculations based on software modules. Furthermore, the processing devices may be realized by FPGA, ASIC, etc., or a combination of these.

[0065] The imaging system 810 is connected to a vehicle information acquisition device 816 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 810 is also connected to a control ECU 817, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of the collision determination unit 815. In other words, the control ECU 817 is an example of a mobile object control means that controls a mobile object based on distance information. The imaging system 810 is also connected to an alarm device 818 that issues an alarm to the driver based on the determination result of the collision determination unit 815. For example, if the determination result of the collision determination unit 815 indicates a high possibility of a collision, the control ECU 817 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 818 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0066] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 810. Fig. 8(c) shows the imaging system 810 when imaging the area in front of the vehicle (imaging range 819). The vehicle information acquisition device 816 sends an instruction to operate the imaging system 810 to perform imaging.

[0067] In the above explanation, an example of control to prevent collision with other vehicles has been described, but the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as automobiles, but can be applied to moving bodies (transportation equipment) such as ships, aircraft, and industrial robots. The moving devices in moving bodies (transportation equipment) are various means of movement such as engines, motors, wheels, and propellers. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

[0068] The above-described embodiments can be modified as appropriate without departing from the spirit and scope of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," it can be said that the specification discloses "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because a statement that "A is greater than B" presupposes that the case where "A is not greater than B" is taken into consideration. Claims are attached to publicly define the scope of the invention. [Explanation of symbols]

[0069] 100 photoelectric conversion device, 111 pixel circuit, 121 readout circuit, 131 AD converter

Claims

1. A photoelectric conversion device, a light receiving circuit that converts light into an electrical signal; a readout circuit that reads out an analog signal corresponding to the electrical signal; a ΔΣ AD converter that converts the analog signal into a digital signal; a control circuit that changes a gain of the photoelectric conversion device in response to a change in a drive mode of the photoelectric conversion device; the analog signal read by the readout circuit is an analog current signal, the readout circuit has a variable resistor on a signal path that supplies the analog current signal to the ΔΣ AD converter; a voltage of a data signal is input to one node of the variable resistor, a voltage of a noise signal is input to the other node of the variable resistor, and the analog current signal corresponding to the difference between the data signal and the noise signal is generated by a current flowing through the variable resistor; The control circuit changes the resistance value of the variable resistor to change the gain of the photoelectric conversion device.

2. A photoelectric conversion device, a light receiving circuit that converts light into an electrical signal; a readout circuit that reads out a first analog current signal corresponding to the electrical signal; a ΔΣ AD converter that converts the first analog current signal into a digital signal; a control circuit that changes a gain of the photoelectric conversion device in response to a change in a drive mode of the photoelectric conversion device; The ΔΣ AD converter is a first subtractor supplied with the first analog current signal; a first integrator that integrates the output from the first subtractor; a quantizer that quantizes the integration result by the first integrator; a decimation filter that performs decimation processing on the output from the quantizer; a first DA converter that supplies a first analog current corresponding to the output from the quantizer to the first subtractor so that the first analog current signal is subtracted from the first analog current signal; a second subtractor supplied with the second analog current signal from the first integrator; a second integrator that integrates the output from the second subtractor; an amplifier that converts the output from the second integrator into a current; a second DA converter that supplies a second analog current corresponding to the output from the quantizer to the second subtractor so that the second analog current signal is subtracted from the second analog current signal; the readout circuit has a resistive element on a signal path that supplies the first analog current signal to the ΔΣ AD converter; a voltage of a data signal is input to one node of the resistor element, a voltage of a noise signal is input to the other node of the resistor element, and the first analog current signal corresponding to a difference between the data signal and the noise signal is generated by a current flowing through the resistor element; the control circuit changes a gain of the photoelectric conversion device by changing a setting of the ΔΣ AD converter; Changing the setting of the ΔΣ AD converter changing the value of the first analog current supplied from the first DA converter to the first subtractor for the same output from the quantizer; and changing a value of a reference voltage supplied to the amplifier.

3. the first DA converter includes a current generating circuit that generates an analog current to be supplied to the first subtractor; the current generating circuit includes a plurality of current sources; 3. The photoelectric conversion device according to claim 2, wherein changing the setting of the ΔΣ AD converter includes changing the number of current sources connected to the first subtractor from among the plurality of current sources.

4. each of the plurality of current sources includes a transistor; The photoelectric conversion device according to claim 3 , wherein changing the setting of the ΔΣ AD converter includes changing a value of a voltage supplied to a gate of the transistor.

5. 5. The photoelectric conversion device according to claim 2, wherein changing the setting of the ΔΣ AD converter includes changing the setting of the decimation filter.

6. The change of the driving mode is Switching between a still image capture mode and a moving image capture mode using the photoelectric conversion device; Changing the sensitivity of photography using the photoelectric conversion device; Changing the resolution of AD conversion by the ΔΣ AD converter; Changing the frame rate of video shooting using the photoelectric conversion device; The photoelectric conversion device according to claim 1 , comprising at least one of the following:

7. The photoelectric conversion device according to any one of claims 1 to 6, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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