High-performance power integrated circuit semiconductor device

Abstract

To provide a high-voltage, high-current power integrated circuit semiconductor device that can achieve low loss, small chip area, and high reliability by eliminating the snap-back phenomenon characteristic of reverse-conducting semiconductor elements.SOLUTION: An Si power integrated circuit semiconductor device chip 200 consists of an element-integrated substrate 201 in which a semiconductor chip body with dielectric isolation integrated circuit structure is laid out with single-crystal islands containing integrated circuit components in an isolation area 217 and an element support substrate 202 with both support and conductive path functions for the element-integrated substrates laminated on top of each other, and the element-integrated substrate is provided with a main functional part of vertical semiconductor element in a predetermined single-crystal island and a drain 205 or a collector 204 by removing a dielectric insulation isolation film 206 at the bottom of the single-crystal island and laminated with the element support substrate to form the vertical semiconductor element.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit semiconductor device, and more particularly to a high-performance power integrated circuit semiconductor device suitable for increasing power capacity, i.e., for increasing voltage resistance and current, and also suitable for miniaturization and low loss. [Background technology]

[0002] In recent years, Si power integrated circuit semiconductor devices integrating high-voltage, low-to-medium-power output elements have been developed and commercialized for a variety of applications. These output elements are often Si-IGBTs and Si-MOSFETs, which are also used as major semiconductor devices as discrete elements. However, while discrete Si-IGBTs have been supplied with voltages up to 6.5 kV and 100 A, power integrated circuit semiconductor devices are limited to voltages of 0.7 kV and current capacities of 20 A due to various constraints, and higher power capacities are desired. Meanwhile, Si-IGBTs, which are expected to be used as output elements in power integrated circuit semiconductor devices, have shown remarkable progress as discrete elements in recent years, with various innovations aimed at achieving lower on-resistance and faster turn-off speeds in order to achieve higher performance, such as lower loss. Representative examples include Si reverse-conducting IGBTs (Prior Art Example 1 shown in Figure 10 and Prior Art Example 2 shown in Figure 11), which have recently been commercialized as power elements for electric vehicles. These are disclosed in Non-Patent Documents 1 and 2, respectively. A brief explanation will be given below, but for the sake of simplicity, an n-channel element will be taken as an example. In the prior art example 1, a collector short-circuited Si-IGBT (n-channel type), - The drift layer is shorted to the collector electrode by an n+ short circuit part provided in the p+ collector layer, and when turned off, - By removing carriers remaining in the drift layer through this n+ short circuit, the turn-off time is shortened, resulting in a significant reduction in loss.

[0003] Incidentally, in the case of Si reverse-conducting IGBTs, including the disclosed Prior Art Example 1, the output characteristics, i.e., the Ice-Vce characteristic between the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice), suffer from a snapback phenomenon in which the collector-emitter voltage just before turn-on is greater than the collector-emitter voltage just after turn-on, inducing various transient phenomena and impairing reliability. The collector-emitter voltage just before turn-on is hereinafter referred to as the snapback voltage and written as Vsb, and the collector-emitter current at this Vsb is hereinafter referred to as the snapback current and written as Isb. The Si reverse-conducting IGBT (n-channel type) of Prior Art Example 2 is composed of a reverse-conducting Si-IGBT region composed of multiple reverse-conducting Si-IGBT cells and a pilot IGBT region composed of one pilot IGBT cell. By making the collector width of the pilot IGBT cell significantly larger than that of the reverse-conducting IGBT cell, the lateral resistance of the buffer layer between the short circuits is significantly increased, and the pilot IGBT region turns on before the reverse-conducting IGBT region with a small Isb, suppressing the snapback phenomenon that occurs when the pilot IGBT region turns on before the reverse-conducting IGBT region, thereby suppressing malfunctions caused by transient voltages and transient currents and improving reliability. Note that these disclosed IGBTs have no blocking capability against reverse voltages because the n drift layer is shorted to the collector electrode by the n+ short circuit, and are therefore collectively referred to as reverse-conducting IGBTs. Therefore, all of them will be referred to as reverse-conducting IGBTs below.

[0004] Meanwhile, Prior Art Example 3 by the inventors discloses a 650V 25A class dielectrically isolated integrated circuit in which low-voltage control vertical and lateral elements and a high-voltage output vertical IGBT are integrated on the same chip. The control element section integrates drive circuits and protection circuits, suggesting that high-density and high-integration high-performance functions can be achieved, while the output IGBT has a vertical structure, which significantly reduces drift resistance, resulting in low on-resistance and large current capacity, thereby achieving a significant increase in current, low loss, and high performance for the power integrated circuit semiconductor device.

[0005] In recent years, the development of high-voltage, high-power and medium-power semiconductor devices using wide-gap semiconductors such as SiC semiconductors has been progressing, and significant performance improvements have been made in semiconductor devices such as discrete SiC MOSFETs and discrete SiC IGBTs. For example, Prior Art Example 4 discloses a 6.5 kV-class discrete SiC MOSFET. This device incorporates a SiC Schottky diode as a flywheeling diode (hereinafter referred to as FWD), which is essential for applications such as inverters. This diode suppresses the on-voltage degradation characteristic of SiC semiconductor devices, thereby achieving high performance and reliability. However, wide-gap semiconductors such as SiC semiconductors pose many challenges, including the crystal quality and large area of ​​semiconductor chips. Development of basic component circuits is still in its infancy, and there are no examples of the development or practical application of full-scale power integrated circuit semiconductor devices integrating control circuits and high-voltage, high-current output elements. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Hajime AKIYAMA and five others, "Effects of Shorted Collector on Characteristics of IGBTS," Proceedings of the 2nd International Symposium on Power Semiconductor Devices & ICs, April 1990, pp. 131-136. [Non-patent document 2] Litauras Storasta and two others, "A Comparison of Charge Dynamics in the Reverse-Conducting RCIGBT and Bi-mode Insulated Gate Transistor BiGT," Proceedings of the 22nd International Symposium on Power Semiconductor Devices & ICs, June 2010, pp. 391-394. [Non-patent document 3] T. Mizoguchi, T. Shirasawa, M. Mori, and Y. Sugawara, "600V, 25A Dielectrically Isolated Power IC with Vertical IGBT," Proceedings of the 3rd International Symposium on Power Semiconductor Devices & ICs, April 1991, pp. 40-44. [Non-patent document 4] Kotaro Kawahara and nine others, 6.5kV Schottky-Barrier-Diode-Embedded SiC-MOSFET for Compact Full-Unipolar Mode, Proceedings of the 29th International Symposium on Power Semiconductor Devices & ICs, June 2017, pp. 41-44. Summary of the Invention [Problem to be solved by the invention]

[0007] As mentioned above, due to various technical issues, power integrated circuit semiconductor devices currently have a breakdown voltage of 0.7 kV and a current capacity of 25 A or less. Increasing power capacity to meet various new needs is an important challenge. Increasing power capacity requires both higher breakdown voltage and higher current. Furthermore, this must be achieved within a reasonable chip size (e.g., approximately 20 mm x 20 mm or less) for economical reasons. As mentioned above, in recent years, IGBT and MOSFET discrete elements, which are expected to serve as output elements in power integrated circuit semiconductor devices, have been pursuing low on-resistance and fast turn-off speeds in order to achieve high performance, such as low loss. Reverse-conducting IGBTs and reverse-conducting MOSFETs have attracted attention as suitable elements. In this specification, reverse-conducting semiconductor elements are defined in a narrower sense than the general term

[0003] , and are defined as elements in which the high-breakdown-voltage pn main junction within the element functions as a forward drive (FWD), essential for inverters and other devices, when reverse-biased. In this case, since the FWD is inherent in the element, there is no need to introduce or form a separate one, and the chip area occupied by the output element can be reduced by nearly half, which is expected to result in a significant reduction in the area of ​​the integrated circuit semiconductor device chip and lower costs. However, reverse conducting semiconductor elements of this definition have various technical issues, as described below, and there are no examples of them being incorporated into power integrated circuit semiconductor devices and put to practical use.

[0008] In various industrial fields, such as mobile devices such as electric vehicles, there is strong demand for small, lightweight, low-loss, low-cost semiconductor devices with a capacity of 1 kV or more. Currently, this is met with semiconductor modules, but power integrated circuit semiconductor devices are expected to be even smaller, lighter, lower-loss, and lower-cost. Therefore, the first important challenge is to solve the technical problems of the prior art, devise a structure that can accommodate reverse-conducting semiconductor elements such as reverse-conducting IGBTs and reverse-conducting MOSFETs that are suitable for low-loss and high performance (e.g., high reliability), and realize a power integrated circuit semiconductor device with a high breakdown voltage of 1 kV or more and a large current capacity.

[0009] In Prior Art Example 3, the output IGBT of a dielectric integrated circuit semiconductor device is vertically structured, significantly reducing drift resistance and achieving low on-resistance and high current capacity. However, reverse-conducting semiconductor elements are not considered or even mentioned. In the structure of Prior Art Example 3, it is difficult to provide a short circuit on the collector electrode side of the backside of the element, as in Prior Art Examples 1 and 2. Therefore, the loss reduction based on the significant reduction in switching loss due to the shortened turn-off time achieved by incorporating a reverse-conducting semiconductor element is not realized. Furthermore, it is not possible to achieve the FWD function using the p-body junction inherent in the IGBT. Therefore, a reverse-conducting semiconductor element must be incorporated into the chip, significantly increasing the chip area, or must be externally mounted. The second challenge to be solved in power integrated circuit semiconductor devices is to enable the incorporation of a reverse-conducting semiconductor element with a small footprint and low loss.

[0010] However, reverse conducting semiconductor devices such as reverse conducting IGBTs have a short turn-on time, i.e., the time it takes for the device to transition from just before turning on to just after, so when snapback occurs, a steep voltage change (hereafter referred to as dV / dt) and a steep current change (hereafter referred to as dI / dt) occur at turn-on. As a result, a steep jump in current (C·dv / dt) occurs due to the parasitic capacitance present in the circuit, and a steep jump in voltage (L·dI / dt) occurs due to the parasitic reactor, which induces a large transient phenomenon. This can cause large disturbances in circuits that use reverse conducting semiconductor devices such as reverse conducting IGBTs, resulting in malfunctions and, in some cases, damage to elements and circuits, significantly reducing reliability. Therefore, suppressing or eliminating the snapback phenomenon is a third extremely serious problem in power integrated circuit semiconductor devices in which various circuits are integrated in a small chip area.

[0011] Furthermore, in the Si reverse-conducting IGBT of Prior Art Example 2, a pilot IGBT region is located adjacent to a reverse-conducting IGBT region consisting of multiple reverse-conducting IGBT cells. The p+ collector width of the pilot IGBT region is significantly larger than the p+ collector width of the IGBT cells in the reverse-conducting IGBT region, significantly increasing the lateral resistance of the buffer layer above the p+ collector. Therefore, the pilot IGBT region is first turned on with a small Isb. This suppresses snapback in the pilot IGBT region. However, in Prior Art Example 2, the area of ​​the pilot IGBT region relative to the overall IGBT chip area is significantly larger. For example, in Prior Art Example 2, the p+ collector width of a standard Si reverse-conducting IGBT cell designed for 3.3 kV is 180 microns, while the p+ collector width of the pilot IGBT is approximately 3.6 times larger, at 650 microns or more. This reduces Vsb to the built-in voltage of approximately 0.7 V, thereby eliminating snapback. If the p+ collector width of a reverse-conducting IGBT standard cell is significantly reduced and miniaturized, the lateral resistance of the standard cell decreases. Therefore, a larger current is required to achieve the built-in voltage Vbi of the collector junction. Therefore, the p+ collector width of the pilot IGBT must be correspondingly increased. While this eliminates the snapback phenomenon, it also reduces the area occupied by the reverse-conducting IGBT standard cell in a given IGBT chip. This reduces the number of standard cells that can be integrated on a given chip, increasing the on-resistance and hindering the reverse-conducting IGBT's inherent function of removing residual carriers during turn-off. Given the current economical situation where chip sizes are set to approximately 20 mm x 20 mm or less for yield and other reasons, eliminating the snapback phenomenon of reverse-conducting semiconductor elements in a small footprint is a critical issue for power integrated circuit semiconductor devices, and is the fourth challenge to be addressed.

[0012] In Prior Art Example 4, a SiC Schottky diode is embedded in a SiC-MOSFET as a FWD. This successfully suppresses on-state voltage degradation and improves reliability, but it significantly increases the dedicated chip area by approximately two times. Because drift resistance increases significantly at higher temperatures or withstand voltages, further significant increases in the area of ​​the SiC Schottky diode are unavoidable to reduce loss. Furthermore, unlike reverse-conducting IGBTs, the IGBT cannot be activated to lower on-state resistance due to conductivity modulation when an excessive current is introduced or supplied due to an accident, thereby increasing the current withstand capacity. Therefore, to avoid damage to the device, the dedicated chip area of ​​the SiC-MOSFET and SiC-FWD must be further increased to accommodate anticipated overcurrents. Given the current chip area constraints of approximately 20 mm x 20 mm for integrated circuit semiconductor device devices, the increase in the dedicated area due to the FWD is a significant issue and represents the fifth challenge to be resolved.

[0013] The present invention aims to solve the problems of the prior art and provide a power integrated circuit semiconductor device structure capable of incorporating large-power components, i.e., high-voltage and / or large-current components, particularly reverse-conducting semiconductor components, in order to achieve a large power capacity. Another object of the present invention is to provide a power integrated circuit semiconductor device with a structure that allows for the incorporation of large-power components with a small footprint or low loss. Another object of the present invention is to provide a high-performance reverse-conducting power integrated circuit semiconductor device that achieves FWD functionality without integrating a separate FWD, thereby enabling a reduction in chip size. Another object of the present invention is to provide a highly reliable power integrated circuit semiconductor device that suppresses or eliminates the snapback phenomenon in high-performance reverse-conducting power integrated circuit semiconductor devices for output, while also eliminating this phenomenon with a smaller footprint. Another object of the present invention is to provide a highly reliable, high-performance reverse-conducting power integrated circuit semiconductor device that uses a wide-gap semiconductor such as SiC to eliminate or suppress on-voltage degradation. [Means for solving the problem]

[0014] solution

[0015] Before proceeding, some terms will be defined. In an integrated circuit semiconductor device, the semiconductor portion of an integrated circuit semiconductor device chip excluding electrodes, wiring, insulating protective films, etc. is defined as the chip body and is described by this name. In addition, the integrated circuit components are connected to other integrated circuit components by wiring via a surface insulating protective film on the semiconductor chip body, and the wiring portion that crosses over the isolation region between the components exposed on the surface within the semiconductor chip body, the dielectric insulating isolation film, and the inclined channel stopper is defined as a crossover wiring. The chip body is composed of an element integration substrate and an element support substrate underneath. The upper part of the chip body, which is composed of an isolation region where single-crystal islands on which elements are formed are laid out with a dielectric insulating isolation film interposed therebetween, is defined as the element integration substrate, and the lower part of the chip body, which supports this substrate and all or part of which functions as the conduction path and heat dissipation path for the elements, is defined as the element support substrate; these terms will be used hereinafter. Furthermore, among semiconductor elements integrated on a single crystal island, an element in which both the input and output electrodes are formed on one main surface of the chip, i.e., on surface A of the above-mentioned element integration substrate opposite the element support substrate, is defined as a horizontal semiconductor element. Furthermore, an element in which either the input or output electrode is formed on surface A of the element integration substrate and the other electrode is formed on the other main surface of the chip, i.e., on surface B of the above-mentioned element support substrate opposite the element integration substrate, is defined as a vertical semiconductor element. In the following, to avoid complexity and to facilitate understanding, the description will be directed to a power integrated circuit semiconductor device that uses n-channel type IGBTs and n-channel type MOSFETs as components with large power capacities (e.g., output elements).

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of this invention is a dielectrically isolated integrated circuit semiconductor device, in which the semiconductor chip body is configured by single crystal islands laid out in an isolation region via a dielectric insulating isolation film, the side surfaces of the single crystal islands have a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components within the single crystal islands are connected to the integrated circuit components within other single crystal islands by wiring via a surface insulating protective film on the semiconductor chip body, and in this integrated circuit semiconductor device, components with large power capacity have a novel Surface Carrier Density Decrease Electric Field Reduction Region (abbreviated as SCaDFRR, pronounced SCAD FRR) provided on the surface of the inclined channel stopper layer below the jumper wiring.

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of the present invention is characterized in that a component element having a large power capacity has a thick buried insulating protective film provided between the surface carrier concentration reduced electric field relaxation region SCaDFRR on the surface of the gradient channel stopper layer and the surface of the chip body, and the surface insulating protective film is provided on the surface of the chip body in contact with this thick buried insulating protective film.

[0018] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is a dielectrically isolated integrated circuit semiconductor device, in which the semiconductor chip body is configured by single crystal islands laid out in an isolation region via a dielectric insulating isolation film, the side surfaces of the single crystal islands form a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit constituent elements in the single crystal islands are connected to the integrated circuit constituent elements in other single crystal islands by wiring via a surface insulating protective film on the semiconductor chip body, The integrated circuit includes a lateral IGBT in a specific single crystal island as an integrated circuit component, and a buffer layer is provided on at least the bottom surface of the collector of the lateral IGBT in contact with the collector, and a part of the buffer layer is exposed on the surface of the semiconductor chip and connected to the electrode of the collector of the lateral IGBT, thereby short-circuiting the collector.

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention is a dielectrically isolated integrated circuit semiconductor device, in which a semiconductor chip body is configured by single crystal islands being laid out in an isolation region via a dielectric insulating isolation film, the sides of the single crystal islands being at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and integrated circuit components in the single crystal islands are connected to integrated circuit components in other single crystal islands by wiring via a surface insulating protective film on the semiconductor chip body, wherein the semiconductor chip body of the dielectrically isolated integrated circuit semiconductor device is configured by laminating and bonding an element integrated substrate, in which the isolation region is laid out with the single crystal islands including the integrated circuit components, and an element support substrate having both a support function for the element integrated substrate and a conductive path function, and the element integrated substrate is provided with predetermined single crystal islands from which the dielectric insulating isolation film at the bottom of the single crystal islands has been removed in order to integrate vertical semiconductor elements, and a first main electrode and a control electrode on the surface of the predetermined single crystal island are connected The vertical semiconductor element is characterized in that a main functional part of the vertical semiconductor element connected to an electrode is formed between the surface of the predetermined single-crystal island and a buffer layer at the bottom of the island, the drain or collector of the vertical semiconductor element is connected to the buffer layer and formed exposed on the bonding surface of the element integrated substrate and bonded to the element support substrate, and the drain or collector is connected to a second main electrode on the back surface of the element support substrate via the element support substrate to form the vertical semiconductor element. The main functional part is a term that collectively refers to the remaining structural elements within the chip body constituting the element, excluding the drain or collector or short-circuit part.

[0020] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention comprises: In

[0019] , the vertical semiconductor element is a bipolar element, the first main electrode is formed on the surface of the predetermined single crystal island on which the main functional unit is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body, a third main electrode is formed on the surface of the inclined channel stopper of the predetermined single crystal island on which the main functional unit is formed or on the surface of the isolation region adjacent thereto via the dielectric insulating isolation film, and a part of the isolation region is connected to the buffer layer at the bottom of the predetermined single crystal island and the collector, the drift layer of the main functional unit and the isolation region of the element integration substrate have the same polarity, but the element support substrate has the opposite polarity, and the second main electrode is electrically connected to the third main electrode, whereby the element between the first main electrode and the second and third main electrodes constitutes a vertical reverse conducting semiconductor element. In order to solve the above-mentioned problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention comprises:

[0019] In the above, the vertical semiconductor element is a unipolar element, the first main electrode is formed on the surface of the predetermined single crystal island on which the main functional unit is formed, and the second main electrode is formed on the back surface of the device support substrate of the semiconductor chip body; a third main electrode is formed on the surface of the inclined channel stopper of the predetermined single crystal island on which the main functional unit is formed or on the surface of the isolation region adjacent thereto via the dielectric insulating isolation film, and a part of the isolation region is connected to the buffer layer at the bottom of the predetermined single crystal island and the drain; the drift layer of the main functional unit and the device support substrate have the same polarity, but the isolation region of the device integration substrate has an opposite polarity; and the second main electrode is electrically connected to the third main electrode, whereby the element between the first main electrode and the second and third main electrodes constitutes a vertical reverse conducting semiconductor element.

[0021] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of the present invention is characterized in that the reverse conducting semiconductor element has a single buffer layer or a multiple buffer layer consisting of two or more layers.

[0022] To solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device of the present invention is characterized in that the semiconductor chip body has a structure in which the bonding surfaces of an integrated substrate having a bonding surface that is a mixture of polycrystalline and single-crystalline surfaces and an element support substrate having a bonding surface that is solely a single-crystalline surface or a bonding surface that is solely a polycrystalline surface are directly bonded together. Hereinafter, to clarify the difference from the bonding structures in various conventional dielectric isolation type power integrated circuit semiconductor devices and to avoid confusion, when the integrated substrate has a bonding surface that is a mixture of polycrystalline and single-crystalline surfaces and the element support substrate has a bonding surface that is solely a single-crystalline surface, this will be referred to as Single and Poly mixed crystal surface & Single crystal surface Direct Bonding Structure, or SP&S-DBS for short. When the integrated substrate is the same but the element support substrate has a bonding surface that is solely a polycrystalline surface, this will be referred to as Single and Poly mixed crystal surface & Poly crystal surface Direct Bonding Structure, or SP&P-DBS for short.

[0023] In order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the semiconductor device is made of a SiC semiconductor. Also, in order to solve the above-mentioned problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the surface of the single crystal island of the power integrated circuit semiconductor device made of a SiC semiconductor has a single crystal island crystal plane structure formed using a C-plane, i.e., a (000-1) crystal plane, the side surface is formed using a {0-33-8} plane, and the bottom surface of the single crystal island is formed using a Si-plane, i.e., a (0001) plane.

[0024] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention comprises: In a dielectrically insulated integrated circuit semiconductor device, the semiconductor chip body is configured with single crystal islands laid out in an isolation region via a dielectric insulating isolation film, the side of the single crystal island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and integrated circuit components in the single crystal island are connected to integrated circuit components in other single crystal islands by wiring provided on a surface insulating protective film on the surface of the semiconductor chip body, the vertical semiconductor element has the surface carrier concentration reduced field relaxation region (SCaDFRR), and also has a structure (SP&S-DBS or SP&P-DBS) in which the element integrated substrate having an attachment surface with a mixture of polycrystalline and single crystal surfaces is bonded to the element support substrate having an attachment surface with only a single crystal surface or only a polycrystalline surface.

[0025] In order to solve the above-mentioned problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention comprises: An inverter circuit is built in, and the inverter circuit As the arm configuration of each phase, the upper arm is The vertical semiconductor element or the vertical reverse conducting semiconductor element is included. The lower arm is configured to include a lateral semiconductor element or a lateral reverse conducting semiconductor element. It is characterized by the fact that

[0026] The power integrated circuit semiconductor device according to the present invention, in the above-described invention, includes a novel surface field relaxation region (SCaDFRR) on the surface of the graded channel stopper layer under the interconnection for a component element with a large power capacity, thereby achieving a high breakdown voltage. Furthermore, despite the use of a thick element support substrate, a first main electrode is formed on the main surface, and the second and third main electrodes are electrically connected, thereby realizing a vertically structured reverse conducting semiconductor element for output between the first, second, and third main electrodes. This significantly reduces drift resistance compared to a lateral IGBT structure within a dielectric isolation island, achieving low on-resistance and large current capacity. Therefore, these high breakdown voltage and large current capacity enable a high capacity power integrated circuit semiconductor device.

[0027] To achieve high breakdown voltages in power integrated circuit semiconductor devices, it is necessary to install a field-relief region to reduce the surface peak electric field in the semiconductor chip body under the jumper wiring, and to thicken the insulating protective film under the jumper wiring. For high breakdown voltages, the field area becomes too large if only the field-relief region is installed, so the insulating protective film must also be thickened, but this thickness becomes very large. While the thickness varies depending on the field-relief region and the insulating film composition, for example, based on prior art reference 3, which uses a field-relief region called FRR and a silicon oxide film (hereinafter referred to as SiO2 film), a thickness of 12 μm or more is required for a breakdown voltage of 1.2 kV, making it difficult to form. Furthermore, when connecting the wiring on the thin insulating protective film of the element inside the insulating island, a large step occurs, which can lead to wiring breakage at this step. To avoid this, the insulating protective film inside the device is made in a stepped shape, with each step usually being about 1 to 2 μm thick. However, in the case of high voltage resistance, for example, when the insulating protective film is 12 μm or thicker, the number of steps must be increased, which results in the size of most integrated circuit semiconductor device components increasing and the chip becoming bulky. For these reasons, there are no examples of integrated circuit semiconductor devices with high voltage resistance of 650 V or more, which is a major obstacle to commercialization.

[0028] In the present invention, a high-power-capacity component achieves high breakdown voltage by providing a novel surface carrier concentration-reducing field relaxation region (SCaDFRR) on the surface of the graded channel stopper under the jumper. Prior art 3 introduced a field relaxation region (FRR) on the drift region surface under the jumper to increase the carrier concentration on the drift region surface and achieve high breakdown voltage, but this also resulted in a high concentration on the entire surface of the high-concentration graded channel stopper. This resulted in a higher electric field concentration at the drift region-side edge of the graded channel stopper, limiting the breakdown voltage (i.e., the voltage at which the maximum electric field in this field concentration area reaches the breakdown field strength of the semiconductor material) to a low value. In the present invention, a novel SCaDFRR with a lower carrier concentration is provided on the drift region-side surface of the graded channel stopper under the jumper. As a result, the low-concentration SCaDFRR region is depleted due to the potential difference with the jumper, and the position where the surface electric field is maximized shifts near the boundary between the SCaDFRR and the undepleted graded channel stopper surface. As a result, the field is relaxed by the voltage share of the SCaDFRR, thereby increasing the breakdown voltage. Therefore, it is preferable that the SCaDFRR be long as long as the surface of the gradient channel stopper maintains its function as a channel stopper. Since the SCaDFRR region is provided within the gradient channel stopper, it has the advantage of not increasing the device size. Since the SCaDFRR allows for a high breakdown voltage, the thickness of the insulating protective film under the jumper wiring can be reduced if the breakdown voltage is to be maintained. Furthermore, the thickness of the insulating protective film can be reduced while increasing the breakdown voltage within the range of the maximum electric field reduction effect of the SCaDFRR. Furthermore, as long as the FRR is provided adjacent to the gradient channel stopper under the jumper wiring on the drift region side, the FRR can effectively exert its electric field relaxation effect, so it is also preferable to have the FRR and SCaDFRR coexist.

[0029] As described above in

[0027] , to achieve high breakdown voltage in a power integrated circuit semiconductor device, it is necessary to thicken the insulating protective film under the interconnect wiring to reduce the electric field strength on the surface of the semiconductor element and ensure that the maximum electric field strength is below the breakdown field strength of the semiconductor material. When the breakdown voltage is high, the thickness of this insulating protective film becomes very large. To prevent wiring breakage, the insulating protective film is made stepped, with the step height reduced. However, this requires an increased number of steps, which increases the size of most of the integrated circuit semiconductor device components and results in a bulky chip, which is not practical. To solve this problem, the present invention provides a configuration in which a thick buried insulating film is provided under the surface of the chip body, the SCaDFRR is provided directly below it, and a separate insulating protective film is provided on the surface of the chip body above this thick buried insulating film. For example, if the semiconductor material is Si and an FRR is used and an SiO2 film is used as the insulating film, an insulating film thickness of 12 μm or more is required for a breakdown voltage of 1.2 kV. However, if the insulating film thickness reduction effect of the above-mentioned SCaDFRR is expected to be 2 μm and the thickness of the insulating protective film on the surface of the chip body is set to a realistic thickness of about 6 μm, this problem can be solved by making the thickness of the above-mentioned buried insulating film below the main surface at about 4 μm or more.

[0030] In the present invention, a component element having a large power capacity has its main functional part formed in a single crystal island from which the dielectric insulating isolation film at the bottom of the single crystal island has been removed, and this main functional part is connected to the conductive path of the element support substrate via the drain or collector to form a vertical semiconductor element. As a result, compared to the lateral semiconductor element of a conventional dielectrically isolated power integrated circuit semiconductor device, the drain or collector is formed below the main functional part rather than on the surface of the element, which makes it possible to reduce the drift thickness, significantly reduce the drift resistance, and reduce loss, and also to significantly increase the current capacity without increasing the element area, thereby achieving a large power capacity.

[0031] In the present invention, a first main electrode is formed on the surface of the single crystal island on which the main functional part of the component element with a large power capacity is formed, and a second main electrode is formed on the back surface of the semiconductor chip body, and a third main electrode is formed on the surface of the isolation region adjacent to the single crystal island on which the main functional part is formed and sandwiched between a dielectric insulating isolation film, and the second main electrode and the third main electrode are electrically connected, so that the element between the first main electrode and the second and third main electrodes can easily be realized as a vertical structure reverse conducting semiconductor element.

[0032] In the present invention, when the vertical semiconductor element of a power integrated circuit semiconductor device is a bipolar element, the drift layer and the isolation region of the element integration substrate have the same polarity, while the element support substrate has the opposite polarity, making it easy to provide a reverse-conducting vertical bipolar semiconductor element such as a reverse-conducting vertical IGBT. For example, in the case of this bipolar element, the drift layer and the isolation region of the element integration substrate have the same n-type polarity, while the element support substrate has the opposite polarity, p-type. As a result, a vertical IGBT can be formed between the first main electrode and the second main electrode, a short circuit can be formed between the first main electrode and the third main electrode, and the second main electrode and the third main electrode are electrically connected, thereby realizing a vertical reverse-conducting IGBT between the first main electrode and the second main electrode and the third main electrode. As a result, the low on-resistance of the vertical element allows for large current capacity and low loss, and the reduced loss due to the reduced turn-off time of the reverse-conducting IGBT can also be achieved. Furthermore, during reverse bias, the first and third main electrodes can be operated as a FWD consisting of a p-body junction, eliminating the need for a separate FWD and enabling significant chip miniaturization. In the structure of Prior Art Example 3, the connection to the collector electrode (equivalent to the second main electrode) via a thick p-collector layer made it difficult to provide an n+ short circuit. However, in the present invention, by configuring the element support substrate and the element integration substrate with different polarities, it is easy to provide a vertical IGBT and a short circuit independently, thereby enabling the provision of a vertical reverse-conducting IGBT structure. This results in lower loss and a larger current capacity due to the vertical configuration, and further reduced loss due to a significant reduction in switching loss caused by a shorter turn-off time of the reverse-conducting semiconductor element.

[0033] In the present invention, if the vertical semiconductor element of a power integrated circuit semiconductor device is a unipolar element, the drift layer and the element support substrate can be made the same polarity and the isolation region of the element integration substrate can be made the opposite polarity, thereby easily providing a reverse-conducting vertical unipolar semiconductor element. For example, if the vertical semiconductor element is a unipolar element such as a MOSFET, the drift layer and the element support substrate can be made the same n-type polarity and the isolation region of the element integration substrate can be made the opposite p-type polarity. As a result, a vertical MOSFET can be formed between the first and second main electrodes, and an IGBT can be formed between the first and third main electrodes. Since the second and third main electrodes are electrically connected, the first and second main electrodes and the third main electrodes function as a reverse-conducting IGBT under forward bias. Because there is no pn junction in the current path of the vertical MOSFET, it can enjoy large current capacity and low loss due to the low on-resistance of the vertical structure at low applied voltages. Meanwhile, IGBTs can also be operated in parallel at applied voltages above the built-in voltage. As a result, the low loss due to the IGBT's conductivity modulation and the small temperature dependence of its on-resistance are effective, allowing it to handle excessive current, especially at high temperatures. At this time, part of the vertical MOSFET functions as an n+ short circuit, so the IGBT functions as a reverse-conducting IGBT, significantly reducing switching losses by shortening the turn-off time, thereby enjoying low loss. In addition, when reverse biased, the first and second main electrodes can operate as a FWD consisting of a p-body junction, eliminating the need for a separate FWD and allowing for significant chip miniaturization.

[0034] In the present invention, the reverse conducting semiconductor element of a power integrated circuit semiconductor device has a single-layer buffer layer or a multiple buffer layer consisting of two or more layers. In the case of a single-layer structure, the buffer layer thickness and impurity concentration are appropriately reduced to maximize the lateral resistance of the buffer layer above it, even with a given small p-collector layer width. This ensures that Vsb is below the built-in voltage Vbi of the p+ collector junction even with a small Isb, eliminating the snapback phenomenon. As a result, a reverse conducting semiconductor element with a small p+ collector width reduces the chip area of ​​the power integrated circuit semiconductor device, suppresses or eliminates the snapback phenomenon, and achieves high reliability. In the case of a multiple buffer layer consisting of two or more layers, only the final layer remains undepleted at the built-in voltage Vbi of the p+ collector junction, while the other layers are fully depleted. As a result, the resistance of the buffer layer through which Isb flows can be further increased, the p+ collector width can be further reduced, the area of ​​the reverse conducting semiconductor element and, ultimately, the chip area of ​​the power integrated circuit semiconductor device can be further reduced, and the snapback phenomenon can be further suppressed or eliminated, achieving high reliability.

[0035] In the present invention, for an integrated circuit semiconductor device composed only of lateral semiconductor elements, a semiconductor chip formation wafer is constructed by bonding a wafer for an element integrated substrate having a polycrystalline bonding surface and a wafer for an element support substrate having a single crystal bonding surface. The wafer for an element integrated substrate is pre-treated for bonding by, for example, treating it with a 70°C NH4OH and HO2 solution, rinsing it with ultrapure water, and then spin-drying it. Then, a single crystal Si wafer for an element support substrate is set on the wafer for an element integrated substrate and bonded by high-temperature heat treatment in an oxidizing atmosphere. Compared to the conventional method of forming both wafers as a single unit using epitaxial growth, the high-temperature, long-time epitaxial growth process for forming the support substrate and the post-growth grinding and polishing process for flattening large curvatures can be omitted, which has the advantage of greatly simplifying the power integrated circuit semiconductor device manufacturing process and significantly reducing costs. On the other hand, for the formation of integrated circuit semiconductor devices comprising vertical semiconductor elements, a wafer with a new bonding structure for forming semiconductor chips (SP&S-DBS described in

[0022] ) is realized by bonding a wafer for an element integrated substrate having a bonding surface in which the insulating isolation oxide film has been removed and the single crystal surface of the region where the vertical semiconductor elements will be formed and a polycrystalline surface formed on the insulating isolation oxide film are mixed, to a wafer for an element support substrate having a bonding surface consisting only of a single crystal surface. Although the bonding strength of the bonding surface between single crystal surfaces is higher than that of the bonding surface between single crystal surfaces and polycrystalline surfaces, bonding between single crystal surfaces tends to cause voids to form at the bonding boundary, which reduces the bonding strength. This problem is overcome by devising bonding temperature, bonding pressure, bonding atmosphere gas, pretreatment process, and materials. For example, as a pretreatment process, a wafer for a device integrated substrate having a bonding surface that is a mixture of polished single crystal and polycrystalline surfaces and a wafer for a device support substrate having a bonding surface that is solely a single crystal surface are heat-treated in a reducing atmosphere such as hydrogen annealing before bonding, bonding hydrogen atoms to the dangling ring bonds of Si atoms on the bonding surfaces. The bonding process for the two wafers is then carried out in an oxidizing atmosphere, bonding these hydrogen atoms with oxygen to remove them as HO and bonding Si atoms on the bonding surfaces of both wafers. To increase the bonding strength through this bonding, the bonding temperature and bonding pressure applied to the wafers are higher than those for bonding a polycrystalline bonding surface and a single crystal bonding surface described above at the beginning of this paragraph. As a result, compared to the case of only the above-mentioned lateral semiconductor elements, there are bonded portions where single crystal surfaces have a high bonding strength, and the bonding strength of these portions is improved, thereby improving the bonding strength of the entire bonded wafer.This further reduces damage caused by partial peeling in the subsequent element manufacturing process, and is expected to improve the yield of good products.

[0036] The power integrated circuit semiconductor device according to the present invention comprises: The integrated circuit semiconductor device is made of a wide-gap semiconductor such as a SiC semiconductor. As a result, it has become possible to achieve even higher breakdown voltage, lower loss, smaller chip size, and higher heat resistance, which far surpasses that of Si semiconductors. Furthermore, a semiconductor device with high performance can be realized. Compared to pn isolated power integrated circuit semiconductor devices, the leakage current is extremely low even at high temperatures. This makes it suitable for achieving high voltage and heat resistance, and since the width of the isolation region between elements can be significantly narrower than with pn junctions, it is also suitable for achieving smaller chips and lower loss. Therefore, the SiC dielectrically isolated power integrated circuit semiconductor device, which combines both, can be said to be an ideal power semiconductor device. In the case of an integrated circuit semiconductor device having an SP&S-DBS wafer configuration made of a SiC semiconductor, for example, in order to increase the bonding strength, as described in

[0035] , A wafer for an element integrated substrate having a bonding surface in which a single crystal surface and a polycrystalline surface are mixed, which has been polished as a pretreatment process, and a wafer for an element support substrate having a bonding surface in which only a single crystal surface is polished. Before bonding, both wafers are heat-treated in a reducing atmosphere such as hydrogen annealing to bond hydrogen atoms to dangling bonds of Si atoms and carbon atoms (hereinafter referred to as C atoms) on the bonding surface. The subsequent bonding process is carried out in an oxidizing atmosphere to bond these hydrogen atoms with oxygen and remove them as HO, while bonding the Si atoms and C atoms. To increase the bonding strength due to this bonding, the bonding temperature and bonding pressure applied to the wafer are higher than those for Si described in

[0035] . For the final polishing of both wafers prior to this pre-processing, it is effective to apply a catalyst surface reference etching method (commonly known as the CARE method) which has ultra-high precision polishing accuracy at the atomic level. The heat treatment in a reducing atmosphere before the bonding may be a nitriding treatment in an NO or NO atmosphere, and the subsequent bonding step may be similarly performed in an oxidizing atmosphere, whereby nitrogen atoms in the dangling bonds are bonded with oxygen and removed, and Si atoms and C atoms on the bonding surfaces of both wafers are bonded to each other, thereby completing the bonding.

[0037] To realize this SiC semiconductor dielectrically isolated integrated circuit device, the present invention uses a novel single-crystal island crystal plane structure in which each face of the single-crystal island is composed of a crystal plane with a crystal orientation unique to the present invention. Specifically, n-type single-crystal islands are formed using 4HSIC. The surface of the single-crystal island is composed of a C-plane, i.e., the (000-1) crystal plane, the side is composed of a {0-33-8} plane equivalent to the (0-33-8) plane, and the bottom of the single-crystal island is composed of a Si-plane, i.e., the (0001) crystal plane. This novel single-crystal island crystal plane structure offers the following advantages: (1) The Si-plane can be flattened at the atomic level by using the catalytic surface-referenced etching (CARE) method, an excellent planarization technique, compared to the C-plane. Therefore, using a Si-plane as the bottom of the single-crystal island provides a better bonding surface and stronger adhesive strength during bonding, making it extremely suitable for vertical devices formed by bonding single-crystal portions as described in the present invention. (2) The side faces are constructed with the {0-33-8} plane, equivalent to the (0-33-8) plane, resulting in an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) relative to the C-plane surface. This crystal plane is suitable for its fast oxidation rate and the ease of forming thick insulating isolation oxide films for high-voltage applications. Furthermore, this plane can almost completely block micro-defects such as micropipes in the drift region, which can cause breakdown voltage problems and increased leakage current, during formation using CVD methods such as epitaxial growth. This makes it an extremely suitable crystal plane for forming high-quality, thin channel stoppers. (3) The C-plane provides the best MOS interface, enabling the fabrication of MOSFETs with high channel mobility. Furthermore, the C-plane has the fastest oxidation rate, making it ideal for high-voltage integrated circuit semiconductor devices that require thick, high-quality insulating protective films under interconnects. Furthermore, SiC semiconductors have dielectric breakdown strength approximately one order of magnitude higher than Si semiconductors, allowing for thinner insulating protective films under interconnects, even for high-voltage applications, as explained in

[0027] and

[0029] . As a result, it is easier to form an insulating protective film, and the number of steps required to avoid wiring breaks can be reduced, preventing the device area from becoming larger and allowing for chip miniaturization.On the other hand, in the case of SiC semiconductors, bipolar devices such as IGBTs and FWDs that are configured with p-body junctions have a problem of a specific on-voltage degradation phenomenon that significantly reduces reliability.However, the reverse conduction structure of the present invention described above allows only majority carriers to flow when the device is started up or in operation, and the MaCH-TEDREC method (an operating method invented by the present inventor and disclosed in Patent No. 6232687) can be applied, which raises the junction temperature above the temperature at which on-state voltage degradation is suppressed or eliminated, thereby eliminating or significantly suppressing on-state voltage degradation and achieving high reliability.

[0038] When the power integrated circuit semiconductor device according to the present invention incorporates an inverter circuit, the upper arm of the inverter is configured to include the vertical semiconductor element. As a result, for example, in an inverter having arms of one or more phases, the upper arm of each phase has the collector or drain of the reverse conducting semiconductor element of each phase connected in parallel to the high-potential wiring of the power supply. Therefore, the element structure of the present invention is suitable, in which multiple reverse conducting semiconductor elements can be connected in parallel to the second main electrode (collector electrode or drain electrode) via an element support substrate. On the other hand, the lower arm of each phase has the first main electrode (emitter electrode or source electrode) connected in parallel to the low-potential wiring of the power supply. However, since the potential of the second main electrode (collector electrode or drain electrode) changes during inverter operation, the reverse conducting semiconductor element is suitable, in which the second main electrode (collector electrode or drain electrode) is independent from the other phases. For this reason, the structures of embodiments 7 to 9 are set as suitable arm structures for one phase. [Effects of the Invention]

[0039] As described above, the present invention enables the vertical structure of the output reverse-conducting element in a dielectrically isolated power integrated circuit semiconductor device, significantly increasing current capacity and reducing loss, thereby increasing the capacity and reducing loss of the power integrated circuit semiconductor device. Furthermore, by optimizing and multiplexing the buffer layer, snapback can be eliminated with a small footprint, improving reliability. Furthermore, wafers for dielectrically isolated integrated circuit semiconductor devices using the novel wafer bonding structure SP&S-DBS can significantly reduce costs and improve wafer bonding strength, thereby streamlining subsequent device fabrication. Furthermore, by using SiC semiconductors and applying a novel SiC single-crystal island crystal face structure in addition to SCaDFRR and SP&S-DBS, significant increases in capacity and loss can be achieved, while on-state voltage degradation can be eliminated, improving reliability. As a result, the application of the power integrated circuit semiconductor device of the present invention can significantly contribute to the miniaturization, weight reduction, reduction in loss, high reliability, and cost savings of various power conversion circuit-equipped devices for home appliances, office equipment, vehicles, industrial applications, etc. [Brief explanation of the drawings]

[0040] [Figure 1] Schematic cross-sectional view of a Si lateral reverse conducting IGBT according to the first embodiment. [Figure 2] Schematic cross-sectional view of a Si reverse conducting IGBT according to a second embodiment. [Figure 3] Manufacturing process flow of Si reverse conducting IGBT according to the second embodiment [Figure 4] Schematic cross-sectional view of a SiC reverse conducting MOSFET according to a third embodiment. [Figure 5] Schematic cross-sectional view of a SiC reverse conducting MOSFET according to a fourth embodiment. [Figure 6] 10 is a schematic cross-sectional view of a SiC reverse conducting IGBT according to a fifth embodiment. [Figure 7] 1. Output element configuration for one phase of a Si single-phase inverter integrated circuit semiconductor device according to a seventh embodiment [Figure 8] Output element configuration for one phase of SiC three-phase inverter integrated circuit semiconductor device according to the eighth embodiment [Figure 9]10 is a schematic cross-sectional view of a SiC reverse conducting MOSFET according to a sixth embodiment. [Figure 10] Schematic cross-sectional view of a high-voltage Si reverse conducting IGBT according to prior art example 1 [Figure 11] Schematic cross-sectional view of a high-voltage Si reverse conducting IGBT according to prior art example 2 [Figure 12] Schematic cross-sectional view of a high-voltage SiIGBT according to Prior Art Example 3 DETAILED DESCRIPTION OF THE INVENTION

[0041] Preferred embodiments of a dielectrically isolated power integrated circuit semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions designated by n or p semiconductor polarity indicate that electrons or holes, respectively, are the majority carriers. In the drawings, the numbers and arrows indicating layers and regions generally represent only one representative layer or region, and the others are omitted. Each figure is a schematic cross-sectional view intended to avoid clutter and better explain the invention. There is no correlation between the structural factors within or between the figures, such as magnitude or proportionality. However, the numerical values ​​of each structural factor are described as specifically as possible in the explanatory text, so please refer to them for understanding. To avoid cluttering the figures, only three or four output element cells are depicted, and only one multi-stage surface protection film is depicted. Furthermore, peripheral circuit components other than the output element are depicted only schematically, with approximately two or so. In a power integrated circuit semiconductor device, elements constituting a gate drive circuit for a known output element, various detection circuits for voltage, current, temperature, etc., and various protection circuits are formed on each insulating isolation island as a single element, multiple elements, or circuit unit according to the specifications of the power integrated circuit semiconductor device. In this specification, circuits and elements other than these output elements are collectively defined as peripheral circuits and peripheral circuit elements and will be described by these names. In the following embodiments, the focus will be particularly on the output elements of a dielectrically isolated power integrated circuit semiconductor device chip, which is essential for understanding the present invention, and descriptions of the peripheral circuits and package will be omitted.

[0042] (Embodiment 1) FIG. 1 shows a main part of a power integrated circuit semiconductor device chip 100 according to a first embodiment. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, focusing on an output element. The device chip 100 is made of a silicon semiconductor, and is designed to withstand a voltage of, for example, 1.2 kV / 3 A. This is a dielectrically isolated power integrated circuit semiconductor device chip, and in Figure 1, the periphery of the output element is also slightly The output element is a reverse conducting IGBT with a trench gate structure, and is a striped cell type. The stripe-shaped single crystal island has 25 stripe-shaped cells, but it is complicated. To avoid clutter, only three cells are shown in the figure. The output element single crystal island width is approximately 520 μm. The length of the single crystal island is 5 mm. Compared to the pn isolation type, the dielectric isolation type has extremely low leakage current even at high temperatures and has good insulation between elements. The edge isolation region is significantly smaller, making it easier to achieve high breakdown voltage and reduce chip size. It is very suitable for power integrated circuit semiconductor devices. The chip body of the first embodiment is composed of an element integrated substrate 101 and an element support substrate 102. The two substrates are bonded together using wafer bonding technology. The pasting technology was developed by the inventors and is called "NEW DIELECTRIC ISOLATION FOR HIGH VOLTAGE ICS BY SINGLE SILICON POLY SILICON DIRECT BOND ING (SPSDB) TECHNIQUE" in Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, May 1992, p.316- 321". The bonding structure using this wafer bonding technology is named

[0022] . If we follow this method, we can call it a P&S-DBS structure, which can be formed by using the pasting method and pre-processing described in the top 1 to 10 lines of

[0035] . By applying this structure, Thick device support substrates in conventional dielectrically isolated power product circuit semiconductor device fabrication processes. This eliminates the need for a long epitaxial growth process at temperatures of 1200°C or higher. The power integrated circuit semiconductor device manufacturing process can be greatly simplified and the manufacturing equipment can be This has the advantage of greatly simplifying the system and simplifying maintenance, and significantly reducing costs. Most of the various bonding structures of dielectric isolation type power integrated circuit semiconductor devices including SOI that have been disclosed so far are P&S-DBS.

[0043] First, the configuration and features of the first embodiment of Fig. 1 will be described. Briefly, the configuration of a conventional dielectrically isolated integrated circuit semiconductor device is as follows: The Si semiconductor chip body is configured with single-crystal islands laid out in isolation region 117 via dielectric insulating isolation film 106. The sides of the single-crystal islands are inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body. Therefore, channel stoppers 125 extending along dielectric insulating isolation film 106 are inclined with respect to the front and back surfaces, and are hereinafter referred to as inclined channel stoppers. Furthermore, integrated circuit components within a single-crystal island are connected to integrated circuit components within other single-crystal islands by wiring via a surface insulating protective film provided on the semiconductor chip body. As described in paragraph

[0015] , wiring portion 116 that crosses over the isolation region, dielectric insulating isolation film, and inclined channel stopper exposed on the surface of the semiconductor chip body is defined as a crossover wiring. In this embodiment, the surface of the Si semiconductor chip body is composed of the (001) plane, the side surface is composed of the {111} plane, and the predetermined angle determined by the crystal orientation relative to the surface is approximately 54.7 degrees or (180 degrees - 54.7 degrees).

[0044] The p-type collector 104 of a reverse-conducting IGBT in a single-crystal island within the device integration substrate 101 is surrounded by an n-type buffer layer 107 and connected to a second main electrode (collector electrode) 103 via a short-circuit 105 located away from the n-type emitter 110, forming a reverse-conducting structure. The n-type buffer layer 107 has a double-buffer layer configuration and has a higher lateral resistance than a single-buffer layer configuration. Therefore, even with a short p-type collector width, a built-in voltage Vbi of approximately 0.7 V can be achieved with a small Isb, enabling the IGBT to turn on. This significantly suppresses snapback. In other words, snapback can be significantly suppressed with a small footprint. The basic concept of the double-buffer layer is disclosed in Japanese Patent No. 6383971 by the present inventor. Furthermore, the p-type body 109 connected to the first main electrode (emitter electrode) 120 and the drift layer 108 form a FWD, which is connected to the second main electrode (collector electrode) 103 via the n-type short-circuit 105. As a result, there is no need to separately integrate FWDs within the single crystal island, allowing for a significant reduction in the device area.

[0045] The dielectrically isolated power integrated circuit semiconductor device chip of this embodiment, which aims to achieve a significantly higher breakdown voltage, differs in configuration from conventional dielectrically isolated integrated circuit semiconductor device chips in the following two respects. The first difference is that in addition to conventional high-voltage field-mitigation technologies such as field plates 123 for mitigating the electric field at the junction edge and surface field reduction layers FRR for mitigating the electric field in the inclined channel stopper portion, a novel surface carrier density decrease field reduction region (SCaDFRR) is provided on the surface of the inclined channel stopper 125 under the jumper. In the 600V chip of Prior Art 3, the surface insulating protective film 118 under the jumper is an insulating film made of SiO2 with a thickness of approximately 5.4 μm. In the present embodiment, a breakdown voltage of 1.2 kV or more is required, so the surface insulating protective film 118 made of SiO2 needs to be approximately 12 μm or thick, which makes it difficult to form. Therefore, in this embodiment, an SCaDFRR 121 is newly provided on the surface of the inclined channel stopper 125 to improve the breakdown voltage and reduce the thickness of the insulating film. The principle is described in

[0028] , but by providing the SCaDFRR, a film thickness reduction of approximately 2 μm or more is expected, although this differs depending on the length, the film quality of the insulating film, the degree of coexistence with the FRR, etc. When applied to the above-mentioned prior art 3, the film thickness can be reduced to approximately 10 μm.

[0046] The second difference is the use of a buried insulating film 140 in the chip body beneath the interconnects. When a voltage corresponding to the breakdown voltage is applied, the surface electric field concentration beneath the interconnects 116 can cause dielectric breakdown on the silicon surface. Therefore, a surface insulating protective film thickness is required to mitigate this surface electric field concentration and prevent dielectric breakdown. For high breakdown voltages, this thickness becomes very large. For example, for a breakdown voltage of 1.2 kV, an insulating film thickness of 12 μm or more is required, as mentioned above, making its formation difficult. Furthermore, a large step occurs between the wiring 119 on the thin insulating film leading to the device connection within the insulating isolation island, causing wiring breakage at the step. To avoid this, the insulating film beneath the wiring inside the device is stepped, with each step typically about 1–2 μm. However, for high breakdown voltages, the number of steps must be increased, resulting in larger step sections between the steps. This results in larger device sizes and larger chips. For this reason, there are no examples of integrated circuit semiconductor devices capable of withstanding voltages of 650 V or more, which poses a major obstacle to commercialization.

[0047] In this embodiment, a thick buried insulating film 140 is provided by burying a portion of the thick surface insulating protective film 118 under the interconnections, which was previously formed on the surface of the chip body, beneath the surface of the chip body. The SCaDFRR 121 is provided below that, and another surface insulating protective film 118 is provided on the surface of the chip body with a thickness that subtracts the buried insulating film thickness. For example, since the insulating film thickness reduction effect of the above-mentioned SCaDFRR is expected to be about 2 μm, the thickness of the buried insulating film below the main surface is set to about 4 μm in order to make the thickness of the surface insulating protective film on the surface of the chip body a realistic thickness of about 6 μm. This reduces the number of steps in the insulating protective film on the surface of the chip body of the power integrated circuit semiconductor device, thereby achieving a reduction in chip area.

[0048] The main structural specifications are, for example, the drift layer has an impurity concentration of 1x10 14 cm -3 The thickness may be 140 μm. The n+ emitter region has an impurity concentration and thickness of 5×10 19 cm -3 1.5μm, p-body region is 3x10 17 cm-3 The thickness from the surface is 4 μm, and the n-buffer layer is 2 x 10 16 cm -3 4μm, p+ collector area is 1x10 19 cm -3 The thickness of the gate oxide may be 1300 Å, the thickness of the SiO2 dielectric isolation film may be 5 μm, and the chip body thickness may be approximately 300 μm.

[0049] Next, the characteristics of the power integrated circuit semiconductor device of the first embodiment will be described. This power integrated circuit semiconductor element chip 100 was mounted in a high-voltage package for characteristic measurement and subjected to an operation test. When a forward voltage was applied between the emitter electrode 120 and the collector electrode 103 with no gate voltage applied, a leakage current flowed, but good forward blocking characteristics were exhibited, and the breakdown voltage at room temperature, i.e., the voltage at which avalanche breakdown occurred, was approximately 1.42 kV, and the leakage current before avalanche breakdown was 1×10 at room temperature. -6 A / cm 2 Below, even at high temperatures of 250°C, it is 8x10 -6 A / cm 2 The following is good:

[0050] In addition, when a gate voltage is applied in the forward direction and increased, the reverse conducting IGBT turns on. Although a snapback phenomenon is observed, Vsb is low at about 1.6V, which is a level that does not pose a problem in practical use. 2 The on-state voltage at room temperature when a current density of 100 A / cm is applied is low at approximately 2.5 V. 2 The turn-off time when current is applied is approximately 1.2 μs, which is approximately half that of a Si-IGBT of the same voltage class. As a result of the reverse conducting IGBT function, the turn-off time can be reduced and made faster, resulting in a significant reduction in switching loss. Furthermore, the 100 A / cm of FWD 2 When a current is applied at a current density of 1.5 V at room temperature, the on-state voltage is low and favorable.

[0051] As described above, according to this embodiment, a high-voltage reverse-conducting IGBT can be integrated as an output element of a Si power integrated circuit semiconductor device chip using SCaDFRR and a buried insulating film, and high voltage resistance, a reduced chip footprint, and low loss can be achieved, thereby achieving a large capacity power integrated circuit semiconductor device. Furthermore, the snapback phenomenon can be significantly suppressed to a practically negligible level, achieving high reliability. Furthermore, during inverter reflux, the built-in diode consisting of the p-body and n-drift layer can be used as a FWD diode, eliminating the need for a separate diode. This allows for a significant reduction in the semiconductor chip size of the power integrated circuit semiconductor device, thereby reducing costs.

[0052] (Embodiment 2) Fig. 2 is a cross-sectional view schematically showing an output element, which is a main part of a Si power integrated circuit semiconductor device chip 200 according to embodiment 2. The semiconductor device chip 200 according to embodiment 2 shown in Fig. 2 is a dielectrically isolated power integrated circuit semiconductor device chip manufactured using a Si semiconductor and having a designed breakdown voltage of, for example, 1.2 kV / 60 A, and is configured such that an element integrated substrate 201 and an element support substrate 202 are bonded together using a novel bonding structure (SP&S-DBS) according to the present invention. This configuration can be formed using the pasting method and its pre-treatment described in lines 19 to 26 at the top of

[0035] , for example. The output element is a vertical reverse-conducting IGBT with a trench gate structure, employing a novel reverse-conducting IGBT structure according to the present invention, and is integrated within a dielectrically isolated single-crystal island and adjacent isolation region 217 of an element integration substrate 201. The output element is stripe-shaped, with the stripe-shaped single-crystal island having a width of approximately 6.5 mm and a length of 5 mm. Five hundred stripe-shaped cells are formed in the stripe-shaped single-crystal island, but to avoid complication, only four cells are shown in the figure. As mentioned above, compared to the pn isolation type, the dielectric isolation type has extremely low leakage current even at high temperatures and requires a significantly smaller isolation region, making it easy to achieve high voltage resistance and reduce chip size, and is therefore suitable for high-voltage power integrated circuit semiconductor devices.

[0053] First, the configuration and features of the first embodiment shown in Figure 2 will be described in detail. In the second embodiment, most of the main functional components of reverse conducting IGBT 200, an output device, are formed within a dielectric isolation island. However, insulating film 206 at the bottom of this dielectric isolation island is removed, so that the device is connected to p+ element support substrate 202 via p+ collector 204, which is connected to collector electrode 203, the second main electrode. Therefore, the device portion between emitter electrode 220, the first main electrode, and collector electrode 203, the second main electrode, can function as a vertical Si-IGBT. Meanwhile, the device portion between first main electrode 220 and third main electrode 215 is connected to n+ region (n+ short-circuit portion and MOSFET drain) 205 via the portion of the dielectric isolation island where the insulating film has been removed, and further connected to third main electrode 215 via n isolation region 217. Therefore, the device between first main electrode 220 and third main electrode 215 can function as a Si-MOSFET. Furthermore, the third main electrode 215 is electrically connected by wire bonding to the metal portion of the package to which the second main electrode 203 is die-bonded, outside the chip, so the second main electrode 203 and the third main electrode 215 are electrically connected. Therefore, the elements between the first main electrode 220 and the second and third main electrodes 203 and 215 function as a reverse-conducting IGBT as a whole. Furthermore, by adjusting the width of the n+ region 205 and the width of the p+ region 204, it is possible to make the MOSFET operation the main operation when the n+ region 205 width is large, and the IGBT operation the main operation when the p+ region 205 width is large. In this embodiment, to make the IGBT operation the main operation, the ratio of the width of the p+ region 204 to the width of the n+ region 205 may be set to approximately 90:10, thereby making the p+ region 204 considerably large. On the other hand, the n+ region 205 functions as a short-circuit part for the p+ collector 204, allowing for the rapid discharge of residual carriers in the drift layer 208 during turn-off. As a result, the turn-off time is shortened and turn-off loss is reduced, resulting in low loss in the power integrated circuit semiconductor device chip. Furthermore, since the width of the p+ collector 204 is large, multiple n+ regions 205 are provided within the p+ collector 204 for each specified number of cells to efficiently and quickly discharge residual carriers. Only one n+ region 205 is shown in Figure 2 for illustrative purposes.The spacing between the n+ regions 205 is determined by the conditions for suppressing the snapback phenomenon. The n+ regions 205 provided within the p+ collector 204 divide the p+ collector 204 at a predetermined location deep within the plane of the drawing, connecting the n+ regions 205 on the left and right of the p+ collector 204 and the internal n+ regions to each other, thereby reducing resistance and quickly discharging remaining carriers.

[0054] Furthermore, when a voltage corresponding to the breakdown voltage is applied between the first and second main electrodes, electric field concentration occurs at the high-voltage junction inside the device. This is suppressed by known termination technology, such as the field plate 223 shown in the figure, and channels generated on the chip surface are blocked by inclined channel stopper technology. Furthermore, to prevent gate breakdown due to electric field concentration at the bottom of the trench gate, known techniques are used, such as thickening the oxide film 212 at the bottom of the gate and installing a p-well for gate bottom cover (not shown). When these techniques are used for appropriate design, the primary factor determining the breakdown voltage is the electric field concentration occurring under the wiring. In this device structure, this is the surface electric field concentration in the inclined channel portion 225 under the jumper 216. This surface electric field concentration causes breakdown on the Si surface at a voltage lower than the breakdown voltage. To prevent this breakdown, the surface electric field concentration must be reduced and a thick insulating protective film must also be used. For example, a dielectric breakdown voltage of 1.2 kV requires a dielectric protective film thickness of 12 μm or more, which makes it difficult to form. Furthermore, a large step occurs between the emitter 210 inside the insulating isolation island and the wiring 219 on the thin insulating protective film leading to the connection, causing the wiring to break at the step. To avoid this, the insulating protective film below the wiring inside the device is made stepped, with each step typically about 1 to 2 μm. However, for high voltages, the number of steps must be increased, resulting in a larger step between the steps, which results in the size of most integrated circuit semiconductor device components increasing and the chip becoming bulky. For these reasons, there are no examples of integrated circuit semiconductor devices with high voltages of 650 V or more, which is a major obstacle to commercialization.

[0055] In this embodiment, a significant portion of the thick insulating protective film 218 under the interconnects, which was previously formed on the chip surface, is formed as a buried insulating film 240 below the surface of the chip body. This reduces the thickness of the surface insulating protective film 218 formed on the chip surface and reduces the number of steps. Furthermore, the novel electric field relaxation region SCaDFRR 221 described in the first embodiment is formed below the buried insulating film 240, thereby reducing the insulating film thickness by approximately 2 μm or more. As a result, for example, the surface oxide film 218, which requires 12 μm or more to achieve a breakdown voltage of 1.2 kV, can be reduced to approximately 6 μm, and the buried insulating film 240 below the surface can be reduced to approximately 4 μm. This achieves both a higher breakdown voltage for the power integrated circuit semiconductor device chip and a reduced chip area due to the reduced number of steps. Furthermore, when this chip is used in an inverter or the like, the pn junction diode formed by the p-body 209 and n-drift layer 208 can be used as a FWD diode during the inverter's return current. In other words, the return current flows through the route of the first electrode 220 → p-body 209 → n-drift 208 → n+ short circuit portion 205 → isolation region 217 → third electrode 215, and functions as an FWD. As a result, there is no need to provide a separate diode as an FWD. Because an FWD requires a current capacity roughly equivalent to that of an IGBT, the semiconductor chip size of a power integrated circuit semiconductor device can be reduced to nearly half, enabling the miniaturization and cost reduction of power integrated circuit semiconductor devices.

[0056] Furthermore, with regard to the snapback phenomenon associated with reverse-conducting IGBTs, the single-crystal island width for reverse-conducting IGBTs is sufficiently wide, as described in

[0052] , so even a single buffer layer can increase the lateral resistance, and a small snapback current Isb can reduce the snapback voltage Vsb to below the built-in voltage Vbi of silicon, thereby eliminating the snapback phenomenon. However, the extended buffer layer increases the p+ collector 204, which increases the short-circuit spacing, potentially impairing the discharge rate of residual carriers during turn-off. In this case, a double buffer layer is preferable. The double buffer layer increases the lateral resistance of the undepleted current path for the snapback current Isb in the buffer layer adjacent to the drift 208, thereby reducing the p+ collector width required to eliminate the snapback phenomenon. In other words, the smaller short-circuit spacing increases the discharge rate of residual carriers during turn-off, effectively improving the inherent switching speed of reverse-conducting IGBTs and reducing losses. Eliminating the snapback phenomenon also fully achieves high reliability.

[0057] Next, we will briefly explain the fabrication process flow of the second embodiment using Figure 3. Please note that [5] and [6] in Figure 3 are slightly expanded on the right side compared to [4] and the preceding figures for ease of illustration. First, a mask for forming an isolation groove is formed on the n-type single-crystal main substrate 230, and the n-type single-crystal main substrate 230 is selectively etched using high-temperature molten KOH until the isolation groove reaches a predetermined depth. During this etching, the mask width for the third main electrode 215 formation area is set wider than the mask width for the other isolation V-groove formation areas. The isolation groove depth may be 160 μm. If the etching is stopped when the etching depth of the V-groove reaches 160 μm, the wider third main electrode 215 formation area is automatically formed along with the other V-groove formation areas. Next, an n-type gradient channel stopper 225 is formed by diffusion, and then a double buffer layer 207 is formed by selective double diffusion of, for example, phosphorus and antimony (see [1] in Figure 3). After that, a SiO2 insulating film 206 for dielectric isolation is formed over the entire surface. The thickness may be approximately 4 μm. Next, the SiO2 insulating film 206 in the portion where the p+ collector 204 is to be formed is removed by selective etching, and a p+ single-crystal layer for the p+ collector 204 is formed by epitaxial growth. For example, the thickness of the p+ epitaxial layer may be 18 μm. The p+ epitaxial layer is then selectively etched to form the p+ collector 204. After that, the p+ collector 204 in the portion where the n short-circuit layer 205 is to be formed is removed by selective etching, and the SiO2 dielectric insulating isolation film 206 in the portion where the third main electrode 215 is to be formed is also selectively etched (see [2] in Figure 2). This exposes the single crystal in the portion where the n short-circuit layer 205 is to be formed and the portion where the third main electrode 215 is to be formed. Next, n+ epitaxial growth is performed on the entire surface until it reaches a thickness that completely fills all of the isolation trenches, including the portion where the third main electrode 215 is to be formed. At this time, n single crystal grows on the portion where the n+ short circuit layer 205 is formed, the portion where the third main electrode 215 is formed, and on the p+ collector 204, and n polycrystal grows on the insulating isolation oxide film 206, resulting in a mixture of both crystals in the isolation region 217. After that, grinding and mirror polishing are performed until the p+ collector 204 is exposed, completing the device integrated substrate 201 (see [3] in Figure 3).

[0058] Subsequently, a wafer with a novel bonded structure (SP&S-DBS) is completed by bonding this wafer with a separately prepared n+ single crystal wafer having only a single crystal surface bonding surface and serving as the device support substrate 202, and a device integrated substrate 201 having a novel polycrystalline and single crystal mixed bonding surface (see [4] in Figure 3). This bonded wafer with a novel bonded structure has less curvature than wafers with conventional epitaxial growth substrates, and also has less curvature and stronger bonding strength than wafers with a bonded structure (P&S-DBS) of a single crystal surface and a polycrystalline surface disclosed in Embodiment 1 or previously. The reason for the small curvature is that polycrystals shrink more severely than single crystals when cooled after epitaxial growth, resulting in a large curvature of the wafer. However, in the new structure, the presence of a mixed single crystal region suppresses shrinkage. The strong bond strength is due to the fact that, while conventional bonding sections consist solely of single-crystal and polycrystalline bonded sections, the new structure also includes a single-crystal to single-crystal bonded section, which has strong bonding strength. However, bonding sections of single crystals tend to have voids at the bonding boundary, reducing bonding strength. Voids are therefore eliminated by devising bonding temperature, pressure, bonding atmosphere gas, and pretreatment materials. The resulting bonded wafer, with its small curvature and strong bonding strength, is then polished to expose the dielectrically isolated crystal islands from the top surface of the bonded wafer, completing the device-integrated substrate 201 and completing the wafer for power integrated circuit semiconductor device chips (see [5] in Figure 3). The thickness of the finished wafer may be approximately 300 μm. Thereafter, 4 μm of Si is removed by selective etching from the portion where the buried insulating film 240 is to be formed, followed by selective ion implantation of phosphorus or aluminum in the portion where the SCaDFRR 221 is to be formed, followed by forming SiO2 of a thickness of 4 μm or more over the entire surface by CVD, followed by mirror polishing to complete the formation of the buried insulating film 240. Thereafter, although this is a well-known and general method and therefore will not be described further, electrodes and wiring such as trench gate structure output elements, planar gate structure drive and control circuit elements, detection and protection circuit elements, third electrode 215, etc. are formed in each single crystal island using a predetermined element fabrication technology to complete the power integrated circuit semiconductor device of this second embodiment (see [6] in FIG. 3).

[0059] In this embodiment, by using the above-mentioned new bonding structure (SP&S-DBS), it is possible to reduce the curvature of the bonded wafer and improve the bonding strength of the entire bonded wafer. As a result, the manufacturing process in the subsequent predetermined element manufacturing process can be simplified, damage during element manufacturing can be reduced, and the yield of good products can be improved. Above all, the new bonding structure (SP&S-DBS) makes it possible to omit the conventional high-temperature and long-time epitaxial growth process at about 1200°C, thereby achieving a significant simplification of the power integrated circuit semiconductor device manufacturing process and simplifying the manufacturing equipment. The significant benefits are that it simplifies the process and maintenance, resulting in significant cost reductions.

[0060] Other than the above, the main structural specifications, such as the drift layer, p-body region, n+ emitter region, n-buffer layer, gradient channel stopper, and gate oxide film, are the same as those in the first embodiment. On the other hand, the p+ collector region is 1×10 19 cm -3 18 μm, and the impurity concentration of the p+ isolation region is 1x10 19 cm -3 The distance from the p-body region to the SiO2 dielectric insulating isolation film may be 170 μm, the thickness of the SiO2 dielectric insulating isolation film may be 4 μm, and the p+ element support substrate may have a carrier concentration of 1×10 19 cm -3 The thickness may be 150 μm. In this case, the thickness of the device integrated substrate 201, that is, the thickness of the region between the p+ device support substrate 202 and the surface of the chip body, is 155 μm.

[0061] Next, the characteristics of the power integrated circuit semiconductor device manufactured by the above process flow will be described. This power integrated circuit semiconductor element chip 200 was mounted in a package created for characteristic measurement and subjected to an operation test. Naturally, the third main electrode 215 is wire-bonded to the metal terminal surface of the package to which the second main electrode 203 is die-bonded, and the two are electrically connected. The element exhibits good forward blocking characteristics, with a breakdown voltage at room temperature, i.e., the voltage at which avalanche breakdown occurs, of approximately 1.36 kV, and the leakage current before avalanche breakdown is 5 x 10 at room temperature. -6 A / cm 2 Below, even at a high temperature of 250°C, it is 6x10 -5 A / cm 2 The results are good, at less than 1.9μs. Furthermore, when a gate voltage is applied in the forward direction and increased, the reverse conducting IGBT turns on, but no snapback phenomenon was observed when it turns on. When a current density of 100A / cm2 is applied in the on state, the on-voltage at room temperature is low and good, at about 1.9V. Furthermore, the turn-off time when a current density of 50A is applied is about 0.7μs, which is shorter than that of Si-IGBTs of the same voltage class. As a result of being able to reduce the turn-off time and increase the speed, switching losses can be significantly reduced and low-loss can be achieved. Furthermore, the 100A / cm2 current density of the FWD 2 When a current is applied at a current density of 1.5 V at room temperature, the on-state voltage is low and favorable.

[0062] As described above, this embodiment enables the integration of vertical reverse-conducting IGBTs with high breakdown voltage and large current capacity as output elements on power integrated circuit semiconductor devices by using SCaDFRR and buried insulating film. This enables higher breakdown voltage, reduced chip footprint, and reduced loss, resulting in significantly increased capacity for power integrated circuit semiconductor devices. Furthermore, the application of a novel polycrystalline and single-crystal mixed bonding structure (SP&S-DBS) enables the realization of low-cost dielectrically isolated integrated circuit wafers with high-quality bonding surfaces with strong adhesive strength and minimal curvature. Furthermore, the snapback phenomenon can be eliminated, achieving high reliability. Furthermore, the built-in diode consisting of a p-body and n-drift layer can be used as a forward-drive diode during inverter return current, eliminating the need for a separate diode. This significantly reduces the semiconductor chip size of power integrated circuit semiconductor devices, further reducing costs.

[0063] (Embodiment 3) Generally, SiC semiconductor elements have the following characteristics compared to Si semiconductor elements: high voltage resistance, small size and low loss, high heat resistance, It has significantly superior performance in terms of high heat dissipation and high power tolerance, making it suitable for power elements. In particular, since the dielectric breakdown field strength of SiC is high, the width of the field region of the element is set to about one digit of that of Si. Therefore, the device area can be significantly reduced for the same breakdown voltage. - Integrated circuit semiconductor devices have a higher leakage current than pn isolated power integrated circuit semiconductor devices. It is suitable for achieving high voltage and heat resistance because it is extremely small even at high temperatures, and the width of the element isolation region is Since it can be made significantly narrower, it is suitable for small, low-loss, high-voltage integrated circuit semiconductor devices. The inventors have noticed the above features and have developed the following in the first and second embodiments in order to better achieve the object of the present invention. The new polycrystalline and single crystal mixed bonded structure SP&S-DBS of the present invention and the new In addition to the SCaDFRR structure, a new SiC dielectric isolation type power integrated circuit semiconductor device is also suitable. A new single crystal island crystal plane structure was devised and applied to construct the third embodiment. FIG. 4 shows a SiC dielectric isolation type power supply manufactured using the SiC semiconductor according to the third embodiment. 1 is a schematic cross-sectional view showing an output element, which is a main part of an integrated circuit semiconductor device chip 300. The integrated circuit semiconductor device chip 300 is made up of an element integrated substrate 301, an element support substrate 302, and These are bonded together using the novel SP&S-DBS bonding structure of the present invention. However, current SiC bulk crystals have inferior crystal quality compared to Si bulk crystals. Therefore, for example, in [1] (described in

[0057] ) of the process flow of Figure 3 (which is an IGBT process flow and should be used with an understanding of the differences from MOSFETs), before forming a mask for forming an isolation groove on the starting n-type single crystal main substrate 230, an n-type single crystal layer thicker than the V-type isolation groove of a predetermined depth is epitaxially grown on the SiC single crystal main substrate (corresponding to 230 in Figure 3), so that all of the completed single crystal islands are embedded in this epitaxial layer. As a result, the SiC epitaxial single crystal layer has much better crystal quality than SiC bulk crystals, and each integrated circuit component formed on the epitaxial single crystal island can have significantly better characteristics than if it were formed in SiC bulk crystal. Naturally, the SiC single crystal main substrate is completely removed in the polishing step in process flow [5] of Figure 3, leaving only the epitaxial single crystal in each single crystal island of the device integrated substrate. The same applies to the device integrated substrates of embodiment 4 and onwards. The novel SiC bonding structure SP&S-DBS can be formed using the bonding method and its pretreatment described in the top lines 11 to 18 of

[0036] , for example. The same applies to the SiC chips of the SiC dielectric isolation type power integrated circuit semiconductor devices of the following embodiments 4, 5, and 8.

[0064] The output element is a SiC reverse-conducting MOSFET with a design breakdown voltage of 1.2 kV and a current capacity of 100 A. It is integrated within a dielectrically insulated isolation island on the device integration substrate 301. It is a vertical reverse-conducting MOSFET with a trench gate structure and a stripe configuration. The single-crystal island on which this output element is integrated is approximately 2.5 mm wide and 5 mm long. Numerous cells are integrated and connected in parallel within the single-crystal island, but for clarity, only four cells are shown in the figure. In the dielectrically isolated integrated circuit semiconductor device, the semiconductor chip body is composed of single-crystal islands densely packed in the isolation region 317 via a dielectrically insulated isolation film 306. The side surfaces of the single-crystal islands are inclined at a predetermined angle determined by the crystal orientation relative to the surface of the semiconductor chip body. To achieve an ideal combination of the above-described dielectrically isolated integrated circuit semiconductor device and a SiC semiconductor, this embodiment uses a novel single-crystal island crystal plane structure in which each face of the single-crystal island is configured with a plane of a crystal orientation unique to this invention. Specifically, n single-crystal islands are formed using 4HSIC. The surface of the single-crystal island is constructed using the C-plane, i.e., the (000-1) crystal plane, the side is constructed using the {0-33-8} plane, and the bottom of the single-crystal island is constructed using the Si-plane, i.e., the (0001) plane. This results in the following advantages: (1) In the fabrication of conventional SiC individual devices, extremely high flatness at the atomic level is achieved on the Si surface using the catalytic surface-referenced etching (CARE) method, an excellent planarization technique. It has been reported that this method achieves better flatness than the C-plane. Therefore, by using the Si plane as the bottom of the single-crystal island, a better quality and stronger bonding surface can be obtained between the single-crystal surfaces in the SP&P-DBS structure, which combines polycrystalline and single-crystal surfaces. This is extremely suitable for the vertical device constructed by bonding single-crystal portions together, as in this embodiment. (2) The {0-33-8} plane on the side has an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) with respect to the C-plane on the surface, which allows for extremely fast oxidation and is suitable for forming a thick insulating isolation oxide film for high voltage applications. By forming a thick insulating isolation oxide film, the MOS effect caused by the potential difference between the isolation region and the single-crystal island can be suppressed, and depletion and accumulation on the side of the single-crystal island through the dielectric insulating isolation film can be suppressed, thereby suppressing interference with the characteristics of high-voltage elements within the single-crystal island, such as an increase in leakage current.Furthermore, this plane is extremely suitable as a crystal plane for forming a high-quality graded channel stopper layer for high-voltage devices because even if there are micro-defects such as micropipes in the drift region that cause voltage-defective defects, they can be almost completely blocked during the formation of the growth layer using CVD methods such as epitaxial growth. (3) The C-plane provides the best MOS interface, making it ideal for fabricating MOSFETs with high channel mobility. Furthermore, the C-plane has the highest oxidation rate, making it extremely suitable for high-voltage integrated circuit semiconductor devices that require a thick, high-quality insulating protective film under the interconnects.

[0065] Compared with the Si semiconductor device of the second embodiment, the SiC semiconductor device can have a significantly thinner drift region for the same breakdown voltage. This allows for a significantly shallower V-groove for forming the single-crystal islands, thereby significantly reducing the thickness of the device integration substrate. This results in the following advantages: (1) In the epitaxial growth process for filling the V-grooves in the device integration substrate, a thinner polycrystalline layer can be formed, reducing the curvature caused by shrinkage of the polycrystalline Si during the cooling process at the end of epitaxial growth. This simplifies subsequent processes such as polishing and bonding in the planarization process for bonding, allowing for the use of larger wafer diameters, which is advantageous for reducing costs. (2) To achieve a predetermined strength with minimal damage during the series of manufacturing processes for forming devices on the single-crystal islands, the wafer thickness is typically set to, for example, approximately 300 to 400 μm. For example, if the thickness is set to 300 μm, a 1.2 kV Si element is restricted by a thick drift region of about 150 μm, so the thickness of the element support substrate wafer must be half that, at about 150 μm, but with SiC elements, the drift region can be made significantly thinner, so it can be made thicker at about 250 μm. As a result, the element support substrate wafer can be made thicker, making it less likely to bend, and in the series of manufacturing processes for forming elements on single crystal islands, there are fewer adverse effects such as wafer bending due to oxidation and high-temperature heat treatment, and damage to elements due to these variations.

[0066] The remaining configuration and features of embodiment 3 shown in Fig. 4 will be specifically described below. In embodiment 3, the output element is a stripe-shaped trench-gate SiC reverse-conducting MOSFET 300, and its main functional section is mostly formed within a dielectric isolation island. However, the insulating film at the bottom of this dielectric isolation island is removed, allowing connection via n-drain 305 to n+ element support substrate 302, which is connected to second main electrode 303. Therefore, the element between first main electrode 320 and second main electrode 303 can function as a vertical reverse-conducting SiC MOSFET, and drift resistance can be reduced compared to the lateral structure of embodiment 1. The resulting reduction in on-resistance, combined with the reduction in on-resistance due to the physical properties of SiC, allows for significant loss reduction.

[0067] In this embodiment, similarly to the second embodiment, a significant portion of the thick insulating film 318 below the interconnector 316, which was previously formed on the chip surface, is formed as a buried insulating film 340 below the surface of the chip body, and a SCaDFRR 321 is provided directly below it, thereby achieving a high breakdown voltage, and further reducing the thickness of the insulating protective film 318 on the surface of the chip body, thereby reducing the step and the number of steps. Since the diffusion rate of impurities in SiC is extremely slow compared to Si, a high-concentration n-type gradient channel stopper must be formed by deposition techniques such as CVD. As a result, the gradient channel stopper on the main surface of the chip below the wiring has a nearly uniform high-concentration carrier concentration (for example, 8×10) compared to when it is formed by diffusion. 18 cm -3 ) and the carrier concentration (for example, 8×10 15 cm -3 The difference between the surface electric field strength and the surface electric field strength is extremely large, and the extension of the channel under the wiring is suddenly stopped at this portion, causing a sudden increase in the surface electric field strength, resulting in dielectric breakdown and damage to the SiC surface portion, SiO2 film, etc. In this embodiment, in addition to the FRR, a new SCaDFRR321 is provided to alleviate the surface electric field strength. This SCaDFRR321 ion-implants p-type dopants into the n-type gradient channel stopper on the main surface of the chip to offset the carrier concentration, for example, 1x10 16 ~5x10 17 cm-3 The surface electric field strength is moderated within this range. In the case of 1.2 kV SiC devices, the width of the field region is approximately 15 μm, which is approximately one order of magnitude smaller than that of Si devices. Therefore, the high-voltage effect of the SCaDFRR321 formed on the surface of the approximately 5 μm-thick gradient channel stopper is significantly greater than that of Si devices. Furthermore, if part of the high-voltage effect of the SCaDFRR321 is used to reduce the thickness of the insulating protective film 318, a greater thickness reduction effect can be achieved than with Si devices. As a result, for example, a surface insulating protective oxide film of 12 μm or more is required to achieve a 1.2 kV breakdown voltage. However, by reducing the thickness of the buried insulating film 340 below the surface to approximately 4 μm and adding the insulating film thickness reduction effect associated with the high-voltage effect of the SCaDFRR321, the surface insulating protective oxide film can be reduced to 6 μm or less, thereby reducing the number of steps on the chip and thereby reducing the chip area. Furthermore, by allocating part of the reduced chip area to an increased number of cells, loss reduction can be achieved.

[0068] Furthermore, this device's high-voltage main junction functions as a flywheeling diode (FWD), essential for inverters and other devices, when reverse biased. It is a reverse-conducting SiC MOSFET according to the definition of

[0007] . This eliminates the need for a separate FWD, significantly reducing chip area and potentially reducing costs. Because the FWD requires a current capacity roughly equivalent to that of a MOSFET, the semiconductor chip size of power integrated circuit devices can be reduced by approximately half, resulting in smaller and more cost-effective power integrated circuit devices. While the FWD is comprised of an internal SiC pn diode, such SiC bipolar semiconductor devices suffer from an on-voltage degradation phenomenon, where the on-voltage, a characteristic of SiC, increases over time due to stacking faults inherent in the device. This degradation can increase losses over time during power application, degrade the efficiency of inverters and other devices, and, if excessive, damage the device itself or disrupt the current distribution balance between devices within the module, resulting in damage to some devices and potentially damaging the device itself. To resolve or suppress this problem, the inventors developed the MaCH-TEDREC method and disclosed it in Patent No. 5835679. This method prevents the expansion of stacking faults inherent in the device, which are the cause of degradation, by conducting only majority carriers during device startup and operation, thereby raising the device temperature above the degradation suppression temperature (for example, 150°C to 200°C or higher in the case of elimination). In the case of a reverse-conducting MOSFET using an intrinsic pn diode as a FWD, only the forward conduction current caused by majority carriers can be independently conducted during forward bias, making it possible to apply the MaCH-TEDREC method to eliminate on-state voltage degradation. In this way, this embodiment can resolve the on-state voltage degradation over time that is unique to SiC bipolar devices and achieve high reliability in power integrated circuit semiconductor devices.

[0069] The main structural specifications of this embodiment are as follows: For example, the drift layer 308 has an impurity concentration of 8×10 15 cm -3 The thickness may be 13 μm. The n+ source region 310 has an impurity concentration and a thickness of 3×10 19 cm -30.3μm, p-body region 309 is 1x10 18 cm -3 The thickness from the main surface is 0.7 μm, and the n-gradient channel stopper layer is 8 × 10 18 cm -3 Thickness 4 μm, n+ drain region 304 is 5x10 19 cm -3 The thickness may be 13 μm, the distance from the p-body region to the SiO2 dielectric insulating isolation film may be 25 μm, and the thickness of the SiO2 dielectric insulating isolation film 306 may be 5 μm. 19 cm -3 The thickness may be 260 μm. In this case, the thickness of the element integrated substrate 301, i.e., the region between the n+ element support substrate 302 and the surface of the chip body, is approximately 40 μm. The thickness of the gate oxide film 311 may be 1000 angstroms.

[0070] Next, the characteristics of the power integrated circuit semiconductor device according to this embodiment will be described. This power integrated circuit semiconductor element chip 300 was mounted in a package created for characteristic measurement and subjected to an operation test. When a forward voltage was applied between the source electrode 320 and the drain electrode 303 with no gate voltage applied, a leakage current flows, but the device exhibits good forward blocking characteristics, and the breakdown voltage at room temperature, i.e., the voltage at which avalanche breakdown occurs, is approximately 1.42 kV. The leakage current before avalanche breakdown is 5×10 at room temperature. -6 A / cm 2 Below 1x10 even at high temperatures of 250°C -6 A / cm 2 In addition, when the gate voltage is applied in the forward direction and increased, the reverse conducting MOSFET turns on. 2 The on-state voltage at room temperature when a current density of 100 Ω / cm is applied is a low, favorable 0.35 V, and the on-state voltage at 200°C is also a low, favorable 0.51 V. The specific on-state resistance RonS is 3.5 mΩ / cm at room temperature. 2 The gate voltage Vg is set to 20V and the current is 300A / cm 2 When a current density of 50A / cm is applied, the on-state voltage is approximately 1.5V, which allows for significant loss reduction. 2When measured under the condition of a current density of 100A / cm, the turn-on time was 1.5ns and the turn-off time was approximately 35ns. As a result of reducing the switching time and increasing the speed, the switching loss can be significantly reduced. 2 A 2000-hour current test was conducted at a current density of Even after the test, the MaCH-TEDREC method was effective, and no on-state voltage degradation was observed.

[0071] As described above, according to this embodiment, by applying SCaDFRR and a buried insulating film to the SiC reverse-conducting MOSFET, which is the output element of the SiC power integrated circuit semiconductor device chip, a high breakdown voltage is achieved. Furthermore, by reducing the thickness of the insulating film on the surface of the chip body, the step height and number of steps are reduced, resulting in a reduced chip area and low loss. Furthermore, by applying a novel single-crystal island crystal plane structure and a novel polycrystalline / single-crystal mixed bonding structure, SP&S-DBS, a thick oxide film can be easily formed under the jumper wiring, facilitating high breakdown voltage. This also enables the realization of a low-cost, dielectrically isolated integrated circuit semiconductor device with a high-quality bonding surface with strong adhesive strength and minimal curvature. Furthermore, during inverter return current, the diode comprised of the p-body and n-drift layer within the element can be used as a FWD diode, eliminating the need for a separate diode. This significantly reduces the semiconductor chip size of the power integrated circuit semiconductor device, further reducing costs. Furthermore, by eliminating on-voltage degradation, high reliability is achieved.

[0072] Fourth Embodiment Figure 5 is a schematic cross-sectional view of a SiC dielectrically isolated power integrated circuit semiconductor device chip according to a fourth embodiment, focusing on the output element, which is a major component of the chip. The chip is fabricated using a SiC semiconductor and has a design breakdown voltage of 1.2 kV and a current capacity of 80 A. This is a vertical reverse-conducting output MOSFET designed to respond to situations such as an accident when a power conversion facility incorporating the chip must suddenly supply a large current exceeding that generated during normal operation. The differences in the device structure compared to the third embodiment are that a third main electrode 415 is provided in an adjacent isolation region 417 and is externally connected to the second electrode 403 by wire bonding; the isolation region 417 is made of p-type SiC, which has the opposite polarity to the n-type device support substrate 402; and p-collectors 404 of the reverse-conducting IGBT are provided on both sides of the n-drain 405. Functionally, during normal operation, the vertical reverse-conducting MOSFET between the first main electrode 420 and the second main electrode 403 operates, and when a large current is supplied during an accident or other such event, the reverse-conducting IGBT between the first main electrode 420 and the second main electrode 403 and the third main electrode 415 also operates, and the current flowing through the IGBT is added to the current flowing through the vertical reverse-conducting MOSFET for a predetermined, relatively short time until the protection device is activated, thereby responding to the accident. When the reverse-conducting IGBT operates, the n-drain 405 of the vertical reverse-conducting MOSFET and the element support substrate 402 function as a short-circuit part, which speeds up the discharge of residual carriers at turn-off and reduces loss.

[0073] 5, embodiment 4 includes all of the new features of the present invention described in embodiments 2 and 3. That is, it includes the new SCaDFRR and buried insulating film, the new single-crystal island crystal surface structure, the new SP&S-DBS mixed polycrystalline and single-crystal surface bonded structure, and the new reverse conducting IGBT structure with a third main electrode, all of which achieve the same effects. Also, apart from the element structure within the single-crystal island and the above-mentioned differences, it is almost the same as embodiment 3, including its specifications.

[0074] The element area of ​​the single-crystal island remains the same, but is increased by the third main electrode. Furthermore, because p-type collectors are provided on both sides, the width of the n-type drain is approximately 80%, reducing the rated current during operation by approximately 20%. However, reverse-conducting IGBT current can still flow during an accident. For example, at an applied voltage of 7 V, the element temperature rises due to self-heating, increasing the on-resistance of the MOSFET, and the conduction current does not flow proportionally to the applied voltage. However, the on-resistance of the reverse-conducting IGBT remains almost constant even with changes in element temperature due to the contribution of the conductivity modulation effect. As a result, during an accident, although for a short period limited by the thermal resistance of the package, a conduction current of approximately 190 A, nearly double that of the reverse-conducting MOSFET in embodiment 3, can be expected. Furthermore, high reliability is achieved by eliminating the snapback phenomenon and the on-voltage degradation of the IGBT and FWD. Furthermore, although the conduction current of the FWD decreases slightly, it is at a level that is not a problem in practical use. This eliminates the need for a separate diode, significantly reducing the SiC chip size and reducing costs.

[0075] In this embodiment, the ratio between the low on-resistance MOSFET function and the current-withstanding function can be set to some extent arbitrarily depending on the application by changing the ratio between the width of n-drain 405 and the width of p-collector 404. In some cases, it is also possible to obtain only the MOSFET function between the first and second main electrodes without connecting the third main electrode to the second main electrode.

[0076] As described above, in the event of an accident, this embodiment is expected to provide a larger current flow than the reverse-conducting MOSFET of embodiment 3, although only for a short time limited by the thermal resistance of the package, etc. Furthermore, as in embodiment 3, the application of SCaDFRR and buried insulating film not only achieves a high breakdown voltage, but also reduces the thickness of the insulating film on the surface of the chip body, thereby reducing the number of steps and the chip area, thereby achieving low loss. Furthermore, high reliability can be achieved by eliminating the snapback phenomenon and on-voltage degradation. Furthermore, during inverter reflux, the diode comprised of the p-body and n-drift layer within the element can be used as a FWD diode, eliminating the need for a separate diode. This significantly reduces the semiconductor chip size of the power integrated circuit semiconductor device, thereby reducing costs.

[0077] Fifth Embodiment FIG. 6 is a cross-sectional view illustrating a SiC dielectrically isolated power integrated circuit semiconductor device chip according to a fifth embodiment, focusing on an output element, which is a major component of the chip. The chip is fabricated using a SiC semiconductor and has a design breakdown voltage of 1.2 kV and a current capacity of 60 A. Because the temperature dependence of the on-resistance of a SiC-IGBT is significantly smaller than that of a SiC-MOSFET, this is a vertical reverse-conducting output IGBT intended for use in high-temperature regions. The differences in the device structure compared to the fourth embodiment are that isolation region 517 is made of n-type SiC, which has the opposite polarity to p-type device support substrate 402; n-type short-circuiting portions 505 of the reverse-conducting MOSFET are provided on both sides of p-type collector 504; and device support substrate 502 is made of polycrystalline SiC. When the reverse-conducting IGBT operates, residual carriers are quickly discharged via short-circuiting portions 505 and third main electrode 515 externally connected to second main electrode 503, thereby reducing loss. In this fifth embodiment, polycrystalline SiC is used as the element support substrate 502 in the novel SP&P-DBS, a polycrystalline and single-crystal mixed bonding structure of the present invention, but by increasing the bonding temperature, it is possible to achieve a bonding strength that is comparable to that when a single-crystal support substrate is used, and curvature is also at an acceptable level, so there are no practical problems. The advantage of being able to significantly reduce costs compared to single-crystal element support substrates is extremely great.

[0078] Sixth Embodiment FIG. 9 is a schematic cross-sectional view of a SiC dielectrically isolated power integrated circuit semiconductor device chip 600 fabricated using a SiC semiconductor according to a sixth embodiment, focusing on the output element, which is a major component of the chip. The output element is a SiC reverse-conducting MOSFET with a design breakdown voltage of 1.2 kV and a current capacity of 100 A. It is a vertical reverse-conducting MOSFET with a trench gate structure and a stripe configuration. The single-crystal island on which the output element is integrated is approximately 2.5 mm wide and 5 mm long. This sixth embodiment differs from the third embodiment in that the side surfaces of the single-crystal island are constructed using {11-22} crystal planes and that the epitaxially grown layer is thickened when forming the isolation region of the device integrated substrate 701 without using a bonding substrate, allowing the device integrated substrate 701 to also serve as a device support substrate. However, the structural specifications and fabrication process flow of the integrated circuit semiconductor device chip 600 and the SiC reverse-conducting MOSFET output element are identical, and the characteristics of the fabricated output element are also almost identical. In the sixth embodiment, the side surface of the single-crystal island, which is formed by the {11-22} crystal plane, has a larger inclination angle with respect to the C-plane on the front surface of the single-crystal island and the Si-plane on the back surface of the single-crystal island than the {0-33-8} plane. This allows for an increased bottom area of ​​the single-crystal island, thereby reducing the on-resistance of the output device. Furthermore, the single-crystal island volume can be increased, thereby increasing the heat storage capacity and power handling capability. This effect is enhanced as the device's withstand voltage increases, resulting in a thicker drift layer and thus a thicker single-crystal island. Naturally, similar effects can be achieved by using crystal planes other than the {11-22} plane, such as the {10-12} plane or the {10-11} plane, which have a larger inclination angle with respect to the surface of the single-crystal island than the {0-33-8} plane. Furthermore, while the sixth embodiment does not offer the various advantages of using a bonded substrate as in the first to fifth embodiments, it does have the advantage of reducing the number of manufacturing steps, since the thick device-integrated substrate of the present embodiment can be formed simply by extending the epitaxial growth time for forming the isolation regions of the device-integrated substrate.

[0079] (Seventh Embodiment) Figure 7 shows the output element configuration for one phase of a semiconductor device according to a seventh embodiment, a Si dielectrically isolated single-phase inverter integrated circuit semiconductor device, constructed using Si semiconductor elements with a breakdown voltage of 1.2 kV and a current capacity of 30 A. All output elements are reverse-conducting Si-IGBTs with a trench gate structure. The upper arm is a vertical reverse-conducting Si-IGBT, and the lower arm is a lateral reverse-conducting Si-IGBT. Figure 7 shows a simplified device structure, omitting the numbers and arrows for each structural element. However, the lateral reverse-conducting Si-IGBT has almost the same device configuration as the IGBT of the first embodiment shown in Figure 1, except for the element size and the fact that it is formed on a p-type single-crystal element support substrate. The vertical reverse-conducting Si-IGBT also has almost the same device configuration as the IGBT of the second embodiment shown in Figure 2, except for the element size. The fabrication process flow for the element structure shown in Figure 7 is almost the same as the process flow shown in Figure 3. That is, although not shown, a single crystal island for a lateral reverse conducting Si-IGBT that is larger than the vertical reverse conducting Si-IGBT is created in the same manner as the small single crystal island 260 for the control circuit element in Figure 3, and a wafer for fabricating chips for integrated circuit semiconductor devices is completed as shown in Figure 3(5). After that, a lateral reverse conducting Si-IGBT is also formed within the single crystal island using a process flow similar to that for the element portion of the vertical reverse conducting Si-IGBT formed within the single crystal island.

[0080] In the upper arm of each phase of a single-phase inverter, the collectors of the reverse-conducting Si-IGBTs in each layer are connected in parallel to the high-potential wiring of the power supply, so an element structure in which collector 204 can be connected in parallel to second main electrode (collector electrode) 203 in Figure 2 via an element support substrate is preferable. On the other hand, the lower arm of each phase is connected in parallel to the low- and high-potential wiring of the power supply, but the collector potential changes during inverter operation, so a lateral-structure reverse-conducting Si-IGBT in which second main electrode (collector electrode) 203 is independent from the other phases is preferable. For this reason, the structure shown in Figure 7 is set as the preferable arm structure for one phase. Compared to vertical-structure reverse-conducting Si-IGBTs, lateral-structure reverse-conducting Si-IGBTs have larger drift resistance. Therefore, to make the current capacity of the upper and lower arm 1.2 kV elements approximately the same, the element area must be approximately three times larger, which allows for approximately equal on-resistance. Trial calculations show that a one-chip single-phase inverter with 600V, 5kW, and a PWM frequency of 20kHz can be realized with a chip size of 20mm x 20mm. As a result, it is expected to make a significant contribution to reducing the size, weight, and loss of various motor-equipped devices for home appliances, offices, vehicles, industrial applications, etc.

[0081] (Embodiment 8) The semiconductor device according to embodiment 8 in FIG. 8 shows the output element configuration for one phase of a SiC dielectrically isolated three-phase inverter integrated circuit semiconductor device configured using SiC semiconductor elements with a breakdown voltage of 1.2 kV and a current capacity of 80 A. All output elements have a trench gate structure, with the upper arm being a reverse-conducting SiC-MOSFET with a vertical structure and the lower arm being a reverse-conducting SiC-MOSFET with a lateral structure. Although a simplified structure is shown in FIG. 8, the vertical reverse-conducting SiC-MOSFET has almost the same element configuration as the SiC-MOSFET of embodiment 3 in FIG. 4, except for the element size. Furthermore, the lateral reverse-conducting SiC-MOSFET is configured with SiC semiconductor instead of Si, and the values ​​of each component correspond to those of the SiC element, and except for the element size, it is the same as the IGBT of embodiment 1 in FIG. 1 and the single-crystal island type. The device configuration is almost the same. The fabrication process flow for the device structure in Figure 8 is almost the same as the process flow in Figure 3. That is, although not shown, a single-crystal island for a lateral-structure reverse-conducting SiC-MOSFET, which is larger than the vertical-structure reverse-conducting SiC-MOSFET, is created in the same way as the single-crystal island 260 for the small control circuit device, and the wafer of chips for the integrated circuit semiconductor device in Figure 3(5) is completed. Thereafter, a lateral-structure reverse-conducting SiC-MOSFET is also fabricated within the single-crystal island using almost the same process flow as the device portion of the vertical-structure reverse-conducting SiC-MOSFET formed within the single-crystal island.

[0082] In the upper arm of each phase of the three-phase inverter, the collectors of the reverse-conducting SiC MOSFETs in each layer are connected in parallel to the high-potential wiring of the power supply, so an element structure in which the drains 204 can be connected in parallel to the second main electrode (drain electrode) 203 in Figure 2 via an element support substrate is preferable. On the other hand, the lower arm of each phase is connected in parallel to the low- and high-potential wiring of the power supply, but the collector potential changes during inverter operation, so a reverse-conducting SiC MOSFET with a lateral structure in which the second main electrode (drain electrode) 203 is independent from the other phases is preferable. For this reason, the structure shown in Figure 8 is set as the most suitable structure. Compared to vertical reverse-conducting SiC MOSFETs, lateral reverse-conducting SiC MOSFETs have a higher drift resistance. Therefore, to make the current capacity of the upper and lower arm 1.2 kV devices approximately the same, the single-crystal island size of the lateral reverse-conducting SiC MOSFET needs to be approximately 1.9 times larger, so that the on-resistance is approximately the same. According to the results of the trial calculations, a single-chip three-phase inverter with 600V, 30kW, and a PWM frequency of 20kHz can be realized with a chip size of 20mm x 20mm, despite having a three-phase configuration. As a result, this will make a significant contribution to reducing the size and weight, reducing loss, and increasing the reliability of various motor-equipped devices for home appliances, office use, vehicles, industrial use, etc.

[0083] (Ninth Embodiment) The semiconductor device according to the ninth embodiment is a SiC dielectrically isolated three-phase inverter integrated circuit semiconductor device configured using SiC semiconductor elements with a breakdown voltage of 1.2 kV and a current capacity of 60 A (not shown). All of the output elements constituting one phase are reverse-conducting SiC-IGBTs with a trench gate structure, with the upper arm being a reverse-conducting SiC-IGBT with a vertical structure and the lower arm being a reverse-conducting SiC-IGBT with a lateral structure. The element support substrate is configured as a p+ polycrystalline substrate. The vertical reverse-conducting SiC-IGBT has almost the same element configuration as the IGBT of the fifth embodiment shown in Figure 6. The lateral reverse-conducting SiC-IGBT is the same as the first embodiment shown in Figure 1 except for the element size, the structure factor corresponding to the SiC semiconductor, and the fact that it is formed on a p-type single-crystal element support substrate. Other than that, there are few differences from the sixth embodiment, so a detailed explanation will be omitted, but despite the large current capacity of 60A and the three-phase configuration, the effect of reducing the on-resistance due to the IGBT conductivity modulation contributes significantly, and it is expected that a single-chip three-phase inverter of 600V, 20kW, and PWM frequency of 20kHz class suitable for high-temperature applications can be realized with a chip size of 20mm x 20mm. As a result, this can greatly contribute to the miniaturization, weight reduction, low loss, and high reliability of various motor-equipped devices for home appliances, office use, vehicles, industrial use, etc.

[0084] While the present invention has been described above based on the first through ninth embodiments, it will be obvious to those skilled in the art that the present invention is not limited to these embodiments and can be easily modified and applied in various ways. For example, by changing the numerical values ​​of the structural specifications and modifying the cell structure, it is naturally possible to apply the present invention to power integrated circuit semiconductor devices using reverse-conducting semiconductor elements with higher breakdown voltages of 2 kV or more or, conversely, lower breakdown voltages of 1 kV or less as output elements. While n-type reverse-conducting SiC-IGBTs have been mentioned, it is also self-evident that the present invention can be similarly applied to p-type reverse-conducting SiC-IGBTs with different polarities. It is also naturally possible to modify and apply the cell shape to various mesh shapes, including honeycomb shapes, in addition to the stripe shape mentioned above. It is also naturally possible to apply the present invention to semiconductor elements with various gates, such as planar gate types, in addition to the trench-gate IGBTs and MOSFETs mentioned above. Furthermore, while reverse-conducting SiC-IGBTs and reverse-conducting SiC-MOSFETs have been mentioned as reverse-conducting semiconductor elements, it is also naturally possible to apply the present invention to other transistors, such as static induction transistors and junction gate transistors, as well as reverse-conducting semiconductor elements using other wide-gap semiconductors, such as GaN and diamond. Furthermore, while a dielectrically isolated integrated circuit semiconductor device known as EPIC has been mentioned, the crystal plane configuration of the single crystal island is not limited to the configuration mentioned in this invention, and it will be readily apparent to those skilled in the art that the side surface can be configured with other crystal planes that have a specific, fixed crystal plane angle relative to the front or back surface of the single crystal island. Furthermore, while 4H-SiC has been mentioned, it will be readily apparent to those skilled in the art that the present invention can be applied to other polytypes of SiC crystals. Furthermore, it will be readily apparent to those skilled in the art that the present invention can be applied to SOI and other dielectrically isolated integrated circuit semiconductor devices other than EPIC, and further modified and applied to pn junction isolated integrated circuit semiconductor devices. [Industrial Applicability]

[0085] The present invention can be used in various inverters for EVs, HEVs, electric railway vehicles, etc., and can improve efficiency and extend driving distances by significantly reducing size and weight and reducing loss. It can also improve efficiency by reducing size and weight and reducing loss in power conditioners for solar power generation and wind power generation. Furthermore, it can be applied to power supplies and inverters for home appliances and office equipment, reducing size and weight and reducing loss. As such, the industrial applicability is extremely great. [Explanation of symbols]

[0086] [1] 101, 201, 301, 401, 501, 601: Element integration substrate. [2] 102, 202, 302, 402, 502, 602: Element support substrate. [3] 103, 203, 303, 403, 503, 603: First main electrode. [4] 104, 204, 304, 404, 504, 604: P+ collector layer. [5] 105, 205, 305, 405, 505, 605: N+ short circuit or N+ drain. [6] 106, 206, 306, 406, 506, 606: Insulating isolation oxide film. [7] 107, 207, 307, 407, 507, 607: N buffer layer. [8]. 108, 208, 308, 408, 508, 608: n-type drift layer. [9]. 109, 209, 309, 409, 509, 609: p-type body region.

[10] . 110, 210, 310, 410, 510, 610: n-type emitter region.

[11] . 111, 211, 311, 411, 511, 611: gate oxide.

[12] . 112, 212, 312, 412, 512, 612: polycrystalline silicon electrode.

[13] . 113, 213, 313, 413, 513, 613: gate electrode.

[14] . 114, 214, 314, 414, 514, 614: interlayer insulating film.

[15] . 115, 215, 315, 415, 515, 615: Third main electrode.

[16] . 116, 216, 316, 416, 516, 616: Transition wiring.

[17] . 117, 217, 317, 417, 517, 617: Isolation region.

[18] . 118, 218, 318, 418, 518, 618: Insulation film under transition wiring.

[19] . 119, 219, 319, 419, 519, 619: Internal wiring.

[20] . 120, 220, 320, 420, 520, 620: First main electrode.

[21] . 121, 221, 321, 421, 521, 621: Surface Carrier Concentration Reduced Field Relaxation Region (SCaDFRR).

[22] . 122, 222, 322, 422, 522, 622: Electrodes for control circuit elements.

[23] . 123, 223, 323, 423, 523, 623: Field plates.

[24] . 124, 224, 324, 424, 524, 624: Surface Field Relaxation Layer (abbreviated as FRR).

[25] . 125, 225, 325, 425, 525, 625: Graded Channel Stopper.

[26] . 140, 240, 340, 440, 540, 640: Buried Insulator.

[27] .230: Single crystal main substrate.

Claims

1. A power integrated circuit semiconductor device, wherein the semiconductor chip body of the power integrated circuit semiconductor device is configured with single crystal islands laid out in an isolation region via a dielectric insulating isolation film, the sides of the single crystal islands are inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single crystal islands are connected to the integrated circuit components in other single crystal islands by wiring provided on a surface insulating protective film on the surface of the semiconductor chip body, the semiconductor chip body of the power integrated circuit semiconductor device is configured by laminating and bonding an element integrated substrate, which is configured by spreading the single crystal islands including the integrated circuit components in the isolation region, and an element support substrate having both a support function for the element integrated substrate and a conductive path function, The device integration substrate is provided with predetermined single crystal islands from which the dielectric insulating separation film at the bottom of the single crystal island has been removed in order to integrate vertical semiconductor devices, and a main functional part of the vertical semiconductor device connected to a first main electrode and a control electrode on the surface of the predetermined single crystal island is formed between the island surface of the predetermined single crystal island and a buffer layer at the island bottom, and an inclined channel stopper is formed along the inclined side surface of the single crystal island within the single crystal island, the vertical semiconductor element is a bipolar element, a collector of the bipolar element is connected to the buffer layer and formed exposed on the bonding surface of the element integrated substrate, and the element is bonded to the element support substrate, the collector is connected to a second main electrode formed on the back surface of the element support substrate via the element support substrate, and a third main electrode is formed on a surface of the inclined channel stopper of the predetermined single crystal island in which the main functional unit is formed or on a surface of the isolation region adjacent to the predetermined single crystal island via the dielectric insulating isolation film, a drift layer of the main function section and an isolation region of the element integration substrate having the same polarity, but an element support substrate having an opposite polarity, and the second main electrode and the third main electrode are electrically connected to each other, so that elements between the first main electrode and the second main electrode and between the first main electrode and the third main electrode constitute vertical reverse conducting semiconductor elements.

2. A power integrated circuit semiconductor device, wherein the semiconductor chip body of the power integrated circuit semiconductor device is configured with single crystal islands laid out in an isolation region via a dielectric insulating isolation film, the sides of the single crystal islands are inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single crystal islands are connected to the integrated circuit components in other single crystal islands by wiring provided on a surface insulating protective film on the surface of the semiconductor chip body, the semiconductor chip body of the power integrated circuit semiconductor device is configured by laminating and bonding an element integrated substrate, which is configured by spreading the single crystal islands including the integrated circuit components in the isolation region, and an element support substrate having both a support function for the element integrated substrate and a conductive path function, The device integration substrate is provided with predetermined single crystal islands from which the dielectric insulating separation film at the bottom of the single crystal island has been removed in order to integrate vertical semiconductor devices, and a main functional part of the vertical semiconductor device connected to a first main electrode and a control electrode on the surface of the predetermined single crystal island is formed between the island surface of the predetermined single crystal island and a buffer layer at the island bottom, and an inclined channel stopper is formed along the inclined side surface of the single crystal island within the single crystal island, the vertical semiconductor element is a unipolar element, a drain of the unipolar element is connected to the buffer layer and formed exposed on the bonding surface of the element integrated substrate, and is bonded to the element support substrate, the drain is connected to a second main electrode formed on the back surface of the element support substrate via the element support substrate, and a third main electrode is formed on a surface of the inclined channel stopper of the predetermined single crystal island in which the main functional unit is formed or on a surface of the isolation region adjacent to the predetermined single crystal island via the dielectric insulating isolation film, a drift layer of the main function section and an isolation region of the element integrated substrate having the same polarity, but an element support substrate having an opposite polarity, and the second main electrode and the third main electrode are electrically connected to each other, so that elements between the first main electrode and the second main electrode and between the first main electrode and the third main electrode constitute vertical reverse conducting semiconductor elements.

3. A power integrated circuit semiconductor device according to

1. to

2. , characterized in that the vertical reverse conducting semiconductor element has a single buffer layer or a multiple buffer layer consisting of two or more layers.

4. In claim 1 or claim 2, the semiconductor chip body is a structure in which the element integrated substrate having a bonding surface with a mixture of polycrystalline and single-crystalline surfaces is bonded to the element support substrate having a bonding surface with only a single-crystalline surface (SP&S-DBS); Alternatively, a power integrated circuit semiconductor device characterized by having either a structure (SP&P-DBS) in which the element integrated substrate having a bonding surface with a mixture of polycrystalline and single-crystalline surfaces is bonded to the element support substrate having a bonding surface with only a polycrystalline surface.

5. 4. A power integrated circuit semiconductor device according to claim 1, wherein the semiconductor chip body is made of a SiC semiconductor.

6. A power integrated circuit semiconductor device according to claim 5, characterized in that the specified single crystal island has a single crystal island crystal plane structure in which the surface is constructed using a C-plane, i.e., a (000-1) plane crystal plane, the side is constructed using a {0-33-8} plane, and the bottom surface of the single crystal island is constructed using a Si-plane, i.e., a (0001) plane.

7. In

2. to

6. , the power integrated circuit semiconductor device includes the vertical reverse conducting semiconductor element which is a unipolar element, and in a small current output region, only the element between the second main electrode and the first main electrode of the vertical reverse conducting semiconductor element is operated, and in a large current output region, the element between the third main electrode and the first main electrode is also operated.

8. In any of claims 1 to 6, The power integrated circuit semiconductor device has a built-in inverter circuit, and an upper arm of each phase of the inverter circuit is configured to include the vertical reverse conducting semiconductor element according to any one of claims 1 to 6, and a lower arm is configured to include a lateral reverse conducting semiconductor element.

Images