Method, system, and computer program product for protecting against out-of-bounds references (dedicated boundary information register file for protecting against out-of-bounds memory references)

Abstract

To provide a method, a system, and a device for protection against out-of-bounds references.SOLUTION: A method, a system, and a device include storing an address of a buffer in a general-purpose register, storing boundary information (BI) for the buffer in a boundary information register, and using a content of the boundary information register to determine whether the loading or storage is out of bounds when a content of the general-purpose register is used as an address in a loading or storage operation.SELECTED DRAWING: Figure 10B

Description

[Technical Field]

[0001] The present invention relates to embodiments of methods, apparatus, and systems for a bounds information register file, and more particularly, but not exclusively, to methods, apparatus, and systems for using a dedicated bounds information register file to protect against out-of-bounds memory references. [Background technology]

[0002] Memory safety vulnerabilities (e.g., buffer overflows, null pointers, heap corruption, use after free, or double free) occur when software accidentally or maliciously accesses system memory in a way that exceeds its allocated size and memory address. Summary of the Invention [Problem to be solved by the invention]

[0003] Programs such as C and C++, which have been widely used in certain operating systems and other programs, can be prone to multiple memory security errors that attackers can exploit, with dangerous and disruptive consequences such as remote code execution or privilege escalation flaws. For example, by reading memory beyond its boundaries, an attacker may be able to bypass memory protections and obtain secret values.

[0004] Therefore, there is a need to have techniques that can efficiently reduce or eliminate memory security vulnerabilities. [Means for solving the problem]

[0005] In view of the foregoing and other problems, drawbacks, and shortcomings of the aforementioned background art, exemplary aspects of the disclosed invention provide methods, apparatus, and systems for a dedicated bounds information register file to protect against out-of-bounds memory references.

[0006] An embodiment of the present invention, a method for protecting against out-of-bounds references, includes storing the address of a buffer in a general purpose register and storing bounds information (BI) for the buffer in a bounds information register, and using the contents of the bounds information register to determine whether the load or store is out-of-bounds when the contents of the general purpose register are used as an address in a load or store operation.

[0007] An embodiment of the present invention, a system for protecting against out-of-bounds references, includes storing the address of a buffer in a general purpose register and storing bounds information (BI) for the buffer in a bounds information register, and using the contents of the bounds information register to determine whether the load or store is out-of-bounds when the contents of the general purpose register are used as an address in a load or store operation.

[0008] Another embodiment of the present invention, a computer program product, comprises a computer-readable storage medium having program instructions embodied thereon, the program instructions being readable and executable by a computer to cause the computer to perform a method for protecting against out-of-bounds references, the method including storing an address of a buffer in a general purpose register and storing boundary information (BI) for the buffer in a boundary information register, and using the contents of the boundary information register to determine whether the load or store is out-of-bounds when the contents of the general purpose register are used as an address in a load or store operation.

[0009] There have thus been outlined, rather broadly, certain embodiments of the invention in order that the detailed description thereof herein may be better understood, and in order that the present contribution to the art may be better appreciated. There are, of course, additional embodiments of the invention that will be described below and that will form the subject matter of the claims appended hereto.

[0010] It is understood that the invention is not limited in its application to the details of construction and to the arrangement of components set forth in the following description or illustrated in the drawings. The invention can be embodied and can be practiced and carried out in various ways in addition to those described. Also, it is understood that the phraseology and terminology employed in the specification and abstract is for the purpose of description and should not be regarded as limiting.

[0011] As such, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.

[0012] Exemplary aspects of the present invention will be better understood from the following detailed description of exemplary embodiments of the invention, taken in conjunction with the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of a system according to an embodiment of the present invention. [Figure 2] FIG. 10 is a diagram illustrating a boundary information table. [Figure 3] FIG. 10 illustrates a method for a boundary information table. [Figure 4] FIG. 10 illustrates a method for choosing between two boundary information tables, an index table and a value / key table, in an embodiment of the present invention. [Figure 5] FIG. 10 is a diagram illustrating an example of a BI creation command according to an embodiment of the present invention. [Figure 6] FIG. 10 is a diagram illustrating an example of a load instruction according to an embodiment of the present invention. [Figure 7A] FIG. 1 illustrates how an application can be modified to include protection from out-of-bounds memory references, according to an embodiment of the present invention. [Figure 7B]FIG. 1 illustrates how an application can be modified to include protection from out-of-bounds memory references using INTEL® MPX. [Figure 8] FIG. 10 is a diagram illustrating an example of a store instruction according to an embodiment of the present invention. [Figure 9] FIG. 10 illustrates an alternative implementation of mapping. [Figure 10A] FIG. 1 illustrates a method of an embodiment of the present invention. [Figure 10B] FIG. 1 illustrates a method of an embodiment of the present invention. [Figure 11] FIG. 1 illustrates an exemplary hardware / information handling system for incorporating example embodiments of the present invention. [Figure 12] 1 illustrates a signal-bearing storage medium for storing machine-readable instructions for a program that performs a method according to an example embodiment of the present invention. [Figure 13] FIG. 1 depicts a cloud computing node according to an example embodiment of the present invention. [Figure 14] FIG. 1 is a diagram depicting a cloud computing environment, according to an example embodiment of the present invention. [Figure 15] FIG. 2 depicts abstraction model layers according to an example embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention is now described with reference to the drawing figures, wherein like reference numerals refer to like parts throughout. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. Conversely, dimensions of the various shapes may be arbitrarily increased or decreased for clarity. Example embodiments are provided below for illustration and not to limit the scope of the claims. Furthermore, it should be noted that any of the steps may be performed in different orders, or in combination, or simultaneously. Additionally, any of the illustrated structures and embodiments may be modified or combined.

[0015] Out-of-bounds memory references can pose serious security issues. It is important to check whether each memory reference, load, or store is within the memory boundaries of the memory reference. One existing solution is the INTEL® Memory Protection (MPX) system. MPX introduced a new instruction set architecture (ISA) and hardware support for precise bounds checking. In memory, the bounds information (BI) of each buffer is stored and retrieved with a pointer value as a key. In the core, the pointer and its BI are stored in registers, and a mapping is maintained with additional instructions added by the compiler. The original computation and the bounds protection operation share the same hardware resources. Other methods exist that attempt to eliminate or reduce memory security vulnerabilities. However, all of these other solutions have one major problem: they require multiple additional instructions, making their implementations more expensive. This can result in a four-fold or greater increase in the number of instructions, and even if bounds checking is disabled, execution time can increase by more than two-fold.

[0016] Embodiments of the present invention solve the above-mentioned problems with memory safety vulnerabilities and eliminate the problem of increasing the number of instructions associated with previous solutions. Generally, embodiments of the present invention introduce a dedicated register file to hold bounds information for the active pointer, which resides in a general-purpose register. The present technique also maintains a mapping from the general-purpose register to the bounds register so that bounds-checking-related operations can be performed in the original instruction. The number of instructions that would be added for bounds checking is significantly reduced. Also, special hardware is added to perform bounds-checking-related operations for instructions. Additionally, with the bounds information register, the latency of most instructions does not increase when bounds-checking operations are added to the instruction.

[0017] Embodiments of the present invention provide strict protection, where they protect every buffer, down to the byte. The system is applicable to C / C++ applications and other programs that may have memory issues where arbitrary pointer arithmetic is present, and the number of buffers to be protected in a single application may range from thousands to millions.

[0018] FIG. 1 illustrates an example system for an embodiment of the present invention. The system 100 includes a CPU (central processing unit) core 10 and a memory 20. The CPU core 10 includes an instruction fetch and decode 12, an ALU (arithmetic logic unit) 14, a general-purpose register file 16, a bounds register file 18, and a bounds processing unit 21. The general-purpose register file 16 communicates with a data cache 22, while the bounds register file 18 is connected to a bounds information (BI) cache 24. BI information can be cached within the hardware organization 100 in a dedicated cache (BI cache 24). The BI cache 24 limits the speed degradation from accessing a bounds information (BI) table 26 in the memory 20.

[0019] The memory 20 includes a boundary information table 26 that includes an index table 28 and a value / key table 30. Thus, the boundary information table 26 is within the memory 20.

[0020] The CPU core 10 communicates with the index table 28 and the value / key table 30. The CPU core 10 provides data to the value / key table 30 via the value of a pointer (path 25), and provides data to the index table 28 via the index in the pointer (path 23).

[0021] The boundary information (BI) includes the starting address and length of each buffer. The index table 28 includes access by index. The value / key table 30 includes access by pointer value as a key. Instruction execution in the CPU core 10 includes a BI register 18 for holding boundary information. The system 100 maintains a mapping between general-purpose registers in the general-purpose register file 16 and boundary information registers in the boundary register file 18. The boundary information of the pointers in the register file 18 can be located from the original instruction. The boundary processing unit 21 performs operations for boundary protection.

[0022] Boundary register file 18 is further detailed as follows: Registers (e.g., 128 bits) in boundary register file 18 store boundary information, including the starting address and length of a buffer. System 100 ensures that the BI of a pointer in register 18 can be found via a mapping, e.g., FB below. FB(R n )=B m : General-purpose register R n The BI of the pointer in the Boundary Register B m It means it's inside.

[0023] Such a mapping allows the boundary information to be accessed through a pointer register. System 100 does not use separate instructions to operate on the boundary information, as is the case in MPX. Additional register addresses can be added to previous instructions.

[0024] One proposed implementation of MapFB: Shadow of general-purpose registers FB(R n )=B n The number of bounds registers 18 may be the same as the number of general purpose registers 16, or may be reduced if the compiler only uses a subset of the general purpose registers 16 for pointers. The system 100 propagates BIs (e.g., Ri , R j , R k ), while the compiler marks which operands are pointers (R k is a pointer). BI is a pointer to k From B i (to)

[0025] The boundary information table 26 is further detailed as follows. The boundary information table 26 contains at least two sub-tables, including an index table 28 and a value / key table 30 .

[0026] FIG. 2 shows the boundary information table 26. In the index table 28, each entry contains a starting address 40 and a buffer length 42. Each entry in the value / key table 30 contains a pointer value (key) 50, a starting address 52, and a buffer length 54. The value / key table 30 can be augmented when necessary and is searched by pointer value. The pointer value (key) 50 can be obtained from the pointer value 64 of the pointer 60. The index 62 of the pointer 60 can be used to obtain an entry in the index table.

[0027] The index table 28 may be organized as a linear table containing multiple BI entries 29, each of which includes a base address field 40 and an object size or length field 42. Each BI entry 29 in the index table 28 may be associated with a heap object. Accessing a particular BI entry 29 in the index table 28 corresponding to a given object may involve a single table lookup. The single table lookup may involve using an index 62, which may be embedded in a pointer 60 during object allocation.

[0028] The member functions or microinstructions are as follows: Void initialize(long long int bit_mask): Sets up index bit mapping from bit_mask and allocates space for the index table and value / key table. unsigned long long int get_index_bits(void *addr): Returns an unsigned value representing the index bits in a pointer address. Void *set_index_bits(void *addr, unsigned int v): Returns the address with the index bits set in the value v. Constant INDEX_NA: all ones 11...1 / / No index is available for this pointer. The functions get_index_bits and set_index_bits should be directly supported by the hardware.

[0029] FIG. 3 shows the method for the boundary information table.

[0030] The system 100 may set up 202 the index bits mapping from the bit mask and allocate space for the index table 28 and the value / key table 30 in step 204. Steps 202 and 204 may be implemented with the instruction "Void initialize(long long int bit_mask)" described above.

[0031] The system 100 then returns 206 the unsigned value represented by index bits 62 in the pointer address. The system 100 then returns the address with index bits 62 set to the value v in step 208. Constant INDEX_NA: all ones 11...1, where in step 210, no index is available for this pointer. The functions in step 206 ("get_index_bits") and step 208 ("set_index_bits") should be supported directly by hardware.

[0032] FIG. 4 illustrates how an embodiment of the present invention chooses between two boundary information tables 26: an index table 28 and a value / key table 30.

[0033] The choice or selection between the two boundary information tables 26, the index table 28 and the value / key table 30, can be determined at run time (step 232) based on resource availability (index bits) 62. The binary code is the same.

[0034] The system 100 provides the compiler / user with control by allowing either bounds information table 26 (index table 28 or value / key table 30) to be used when possible and to reserve entries in the index table 28 for future buffer allocations.

[0035] The system 100 determines in step 234 whether the caller (compiler / user) makes a decision. If the determination in step 234 is "yes," the system 100 determines in step 240 whether an index table 28 is selected by the compiler / user (caller). If the determination in step 240 is "no," the system 100 uses the value / key table 30 for the buffer. If the determination in step 240 is "yes," the system 100 uses the index table 28 for the buffer (238).

[0036] If the determination in step 234 is "no," system 100 determines (236) whether index table 28 is selected by runtime heuristics. If the determination in step 236 is "no," system 100 uses value / key table 30 for the buffer (242). If the determination in step 236 is "yes," system 100 uses index table 28 for the buffer (238).

[0037] As with the choices shown above, there can be simple or complex methods used. A simple strategy is to use the index table 28 first. The system 100 can use the index table 28 for buffers where the buffer pointer itself involves many loads / stores. The system 100 can enforce the use of the index table 28 for pointers that result in a matching type conversion.

[0038] FIG. 5 shows an example of a BI creation instruction 370 according to an embodiment of the present invention.

[0039] 6 shows an example of a load instruction 402 according to an embodiment of the present invention. Note that the boundary protection operations 400 (not in bold 404) are designed to be able to be enabled or disabled at runtime.

[0040] 7A shows how an application can be modified to include protection from out-of-bounds memory references in accordance with an embodiment of the present invention. It requires far fewer instructions than other methods, such as MPX, and the same code is used regardless of which bounds information table 26 is used. The modifications also include "createBI p, p, @a+79, 0" (406) to create the bounds information table 26. Also, the "load*" in 408 indicates a pointer load.

[0041] 7B shows how an application can be modified to include protection from out-of-bounds memory references using INTEL® MPX. As can be seen by the bold underlined line for instruction 409, the number of instructions increases dramatically when MPX is used instead of the present invention.

[0042] 8 shows an example of a store instruction 412 according to an embodiment of the present invention. Note that the boundary guard operations (not shown in bold in instruction 414) are designed to be able to be enabled or disabled at runtime.

[0043] FIG. 9 shows an alternative implementation of the mapping.

[0044] System 100 can add an additional N bits to each general purpose register in general purpose register file 16. The additional N bits can be 2 N The boundary registers N may be used to index N boundary registers, where N is an integer (step 302).

[0045] FB(R i )=B j ,j is R i is the extra N-bit value added to

[0046] The mapping is maintained as follows: at pointer initialization time, choose a free B(BI) register and record the index of this B(BI) register in the N bit of the general register for the pointer (304). For all other registers, the N bit should indicate the B(BI) register with which these other registers are associated (306).

[0047] Propagate through pointer arithmetic by selecting a non-zero value for the additional bit from the operand (308). One of the main issues becomes how to free or spill the BI registers in the BI register file 18.

[0048] System 100 releases BI registers in BI register file 18 with instructions inserted by the compiler as follows: Instructions for releasing registers: System 100 uses a mapped register file and requires a release instruction to release a BI register from BI register file 18. If one-to-one mapping is used, no release instruction is required and hardware can maintain BI register file 18. System 100 uses points-to analysis to identify a set of pointers: (B1:{R2,R4}) for each BI register (step 310).

[0049] When it is determined (by data flow analysis) that pointer register 60 becomes dead (312), system 100 removes pointer register 60 from the register set (314).

[0050] If it is determined (316) that the register set is about to become empty, the system frees (step 318) the corresponding BI register 18. Another method is to identify which BI registers are still in use by scanning all live pointers (at the start or end of a function) and free the others in step 318.

[0051] When a determination is made that there are not enough, the system 100 spills 320 the BI registers 18. Assuming KS is the set of registers to be preserved (the minimum of the two BI registers for the next instruction), then: If FB(Rx)!=FB(Ry), spill Rx for all Ry in KS. For restore purposes, remember all Rz's where FB(Rz) = FB(Rx). The system then makes a selection as to which registers to spill using the method used for register spilling combined with the point-to analysis results (322).

[0052] FIG. 10A illustrates a method according to an embodiment of the present invention.

[0053] The system 100 stores boundary information (BI) in registers in the boundary register file 18 (step 502). The boundary information is mapped to the general-purpose register file 16. The boundary information includes a starting address and a length for each buffer.

[0054] Next, the system 100 generates an index table 28 from the boundary information from the boundary register file 18 to the memory 20 (step 504). The index table 28 is accessed by an index. Each entry in the index table 28 includes a starting address 40 and a buffer length 42.

[0055] The system 100 also generates a value / key table 30 in memory 20 from the bounds information (step 506). The value / key table 30 is accessed with a pointer value 64 as a key 50. Each entry in the value / key table 30 includes a key 50 of a pointer value 62, a starting address 52, and a buffer length 54. The bounds information for the pointer can be located from the original instruction.

[0056] System 100 protects against out-of-bounds references (step 508) using index table 28 and value / key table 30. Processor or CPU core 10 includes boundary processing unit 21 that performs the operations for protecting against out-of-bounds references.

[0057] Therefore, embodiments of the present invention introduce a dedicated register file to hold bounds information for the active pointer, and the active pointer resides in a general-purpose register. Embodiments of the present invention maintain a mapping from the general-purpose registers in general-purpose register file 16 to the bounds registers in bounds register file 18 so that bounds-checking related operations can be performed in the original instruction. The number of instructions that would be added for bounds checking is greatly reduced by the present invention. Also, special hardware is introduced to perform bounds-checking related operations for instructions. Also, with the bounds information registers in bounds information register file 18, the latency of most instructions does not increase when bounds-checking operations are added to the instructions.

[0058] Thus, embodiments of the present invention can provide strict protection, where system 100 protects every buffer, down to the byte. Embodiments of the present invention are applicable to legacy programs, such as C / C++ applications, which contain arbitrary pointer arithmetic and where the number of buffers to be protected within a single application can range from thousands to millions.

[0059] FIG. 10B illustrates a method according to an embodiment of the present invention.

[0060] Another stated method for protecting out-of-bounds references includes the following: When a buffer is allocated, system 100 stores the address of the buffer in a general-purpose register from general-purpose register file 16 and stores the buffer's boundary information (BI) in a boundary information register from boundary register file 18 (step 510). When the contents of a general-purpose register from general-purpose register file 16 are used as an address during a load or store operation, system 100 uses the contents of the boundary information register in boundary register file 18 to determine whether the load or store is out-of-bounds (step 512).

[0061] The various features shown in the various figures of Figures 1 through 10 may be combined, changed, or switched between the various examples. The system 100 shown in Figures 1 through 10 may further be implemented in hardware and software as shown in Figures 11 through 15.

[0062] FIG. 11 shows another hardware configuration of a system in which an information handling / computer system 1100 according to the present invention is present, preferably having at least one processor or central processing unit (CPU) 1110 capable of executing the techniques of the present invention in the form of a software program for software intelligence as a service.

[0063] The CPU 1110 is interconnected via a system bus 1112 to random access memory (RAM) 1114, read-only memory (ROM) 1116, input / output (I / O) adapter 1118 (for connecting peripheral devices such as a disk unit 1121 and a tape drive 1140 to the bus 1112), a user interface adapter 1122 (for connecting a keyboard 1124, a mouse 1126, speakers 1128, a microphone 1132, or other user interface devices, or a combination thereof, to the bus 1112), a communications adapter 1134 (for connecting the information handling system to a data processing network, the Internet, an intranet, a personal area network (PAN), etc.), and a display adapter 1136 (for connecting the bus 1112 to a display device 1138 and / or a printer 1139 (e.g., a digital printer, etc.)).

[0064] In addition to the hardware / software environments described above, another aspect of the present invention includes a computer-implemented method for carrying out the above-described method. By way of example, this method may be executed in the specific environment described above.

[0065] Such methods may be performed by operating, for example, a computer, such as embodied by a digital data processing apparatus, to execute a series of machine-readable instructions, which may reside in various types of signal-bearing media.

[0066] Thus, this aspect of the invention is directed to a programmed product including a signal-bearing storage medium tangibly embodying a program of machine-readable instructions executable by a digital data processor incorporating CPU 1110 and the above-described hardware to perform the methods of the invention.

[0067] This signal-bearing storage medium may include, for example, RAM housed in the CPU 1110, such as represented by fast-access storage.

[0068] Alternatively, the instructions may reside on another signal-bearing storage medium 1200, such as flash memory 1210 or optical storage diskette 1220 (FIG. 12), that is directly or indirectly accessible by CPU 1110.

[0069] The instructions may be stored on a variety of machine-readable data storage media, whether contained in flash memory 1210, optical disk 1220, computer / CPU 1110, or elsewhere.

[0070] Thus, the present invention may be a system, a method, and / or a computer program product, which may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0071] A computer-readable storage medium can be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as punch cards or ridge-in-groove structures with instructions recorded on them), and any suitable combination of the foregoing. Computer-readable storage media as used herein should not be construed as signals that are ephemeral in nature, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted through wires.

[0072] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within the respective computing / processing device.

[0073] Computer-readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk®, C++, and traditional procedural programming languages ​​such as the “C” programming language or similar programming languages). The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, an electronic circuit device (including, for example, a programmable logic device, a field programmable gate array (FPGA), or a programmable logic array (PLA)) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to individualize the electronic circuit device to implement aspects of the present invention.

[0074] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0075] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, the instructions of which execute via the processor of the computer or other programmable data processing apparatus to produce means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0076] These computer-readable program instructions may also be stored on a computer-readable storage medium such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture including instructions for performing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, and may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0077] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, executing on the computer, other programmable apparatus, or other device, cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-executed process to implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0078] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions (including one or more executable instructions for performing specified logical functions). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be realized by a dedicated hardware-based system (that performs the specified functions or acts or executes a combination of dedicated hardware and computer instructions).

[0079] Referring now to FIG. 13, a schematic of an example cloud computing node 1400 is shown. Cloud computing node 1400 is merely one example of a suitable cloud computing node and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the invention described herein. Nevertheless, cloud computing node 1400 may perform and / or implement any of the functions described above. As previously noted, system 100 of FIG. 1 may be implemented in a cloud infrastructure such as FIG. 13 (and similarly FIGS. 14 and 15). Cloud computing node 1400 includes computer system / server 1412, which is operational with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system / server 1412 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments (which include any of the above systems or devices).

[0080] Computer system / server 1412 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. Computer system / server 1412 may also be practiced in distributed cloud computing environments where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0081] 13, computer system / server 1412 in cloud computing node 1400 is depicted in the form of a general-purpose computing device. Components of computer system / server 1412 may include, but are not limited to, one or more processors or processing units 1416, a system memory 1428, and a bus 1418 (which couples various system components, including system memory 1428, to processor 1416).

[0082] Bus 1418 represents any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus (using any of a variety of bus architectures). By way of example, and without limitation, such architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0083] Computer system / server 1412 typically includes a variety of computer system-readable media, which can be any available media that can be accessed by computer system / server 1412 and includes both volatile and nonvolatile media, removable and non-removable media.

[0084] System memory 1428 may include computer-system-readable media in the form of volatile memory, such as random access memory (RAM) 1430 and / or cache memory 1432. Computer system / server 1412 may also include other removable / non-removable, volatile / non-volatile computer-system storage media. By way of example only, storage system 1434 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown, but typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and an optical disk drive may be provided for reading from and writing to removable, non-volatile optical disks (such as CD-ROMs, DVD-ROMs, or other optical media). In such cases, each may be connected to bus 1418 by one or more data media interfaces. As further depicted and explained below, memory 1428 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present invention.

[0085] A program / utility 1440 having a set (at least one) of program modules 1442 may be stored in memory 1428, as well as, by way of example and not limitation, an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include an implementation of a networking environment. The program modules 1442 generally perform the functions and / or methods of embodiments of the present invention as described herein.

[0086] The computer system / server 1412 may also communicate with one or more external devices 1414 (such as a keyboard, pointing device, or display 1424), one or more devices that allow a user to interact with the computer system / server 1412, or any device (e.g., a network card, modem, etc.) that allows the computer system / server 1412 to communicate with one or more other computing devices, or a combination thereof. Such communication may occur via an input / output (I / O) interface 1422. Furthermore, the computer system / server 1412 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via a network adapter 1420. As shown, the network adapter 1420 communicates with the other components of the computer system / server 1412 via a bus 1418. Although not shown, it is understood that other hardware and / or software components may be used in conjunction with computer system / server 1412. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0087] Referring now to FIG. 14 , an illustrative cloud computing environment 1550 is depicted. As shown, the cloud computing environment 1550 includes one or more cloud computing nodes 1400, with which local computing devices used by cloud users, such as, for example, a personal digital assistant (PDA) or cellular phone 1554A, a desktop computer 1554B, a laptop computer 1554C, or an automobile computer system 1554N, or combinations thereof, may communicate. The nodes 1400 may also communicate with each other. The nodes 1400 may be physically or virtually grouped in one or more networks, such as private, community, public, or hybrid clouds, or combinations thereof, as described above (not shown). This enables the cloud computing environment 1550 to provide infrastructure, platform, and / or software as a service without requiring cloud users to maintain resources on their local computing devices. The types of computing devices 1554A-1554N shown in FIG. 16 are intended to be illustrative only, and it is understood that computing node 1400 and cloud computing environment 1550 can communicate with any type of computerized device over any type of network and / or network-addressable connection (e.g., using a web browser).

[0088] Referring now to Figure 15, a set of functional abstraction layers provided by cloud computing environment 1550 (Figure 14) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 15 are for illustrative purposes only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0089] The hardware and software layer 1600 includes hardware and software components. Examples of hardware components include mainframes (one example is an IBM® zSeries® system), RISC (reduced instruction set computer) architecture-based servers (one example is an IBM® pSeries® system), IBM® xSeries® systems, IBM® BladeCenter® systems, storage devices, and networks and networking components. Examples of software components include network application server software (one example is IBM® WebSphere® application server software) and database software (one example is IBM® DB2® database software). (IBM®, zSeries, pSeries, xSeries, BladeCenter, WebSphere, and DB2 are trademarks of International Business Machines Corporation, registered in many jurisdictions worldwide.)

[0090] The virtualization layer 1620 provides an abstraction layer at which instances of virtual entities such as virtual servers, virtual storage, virtual networks (including virtual private networks), virtual applications and operating systems, and virtual clients may be provided.

[0091] In one example, the management layer 1630 may provide the functions described below: Resource provisioning dynamically procures computing and other resources utilized to perform tasks within the cloud computing environment. Metering and pricing tracks costs as resources are utilized within the cloud computing environment and bills or invoices for the usage of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection of data and other resources. A user portal provides consumers and system administrators with access to the cloud computing environment. Service level management allocates and manages cloud computing resources to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment pre-provisions and procures cloud computing resources in anticipation of future requirements according to SLAs.

[0092] Workload tier 1640 provides examples of functionality for which a cloud computing environment may be utilized. Examples of workloads and functionality that may be provided from this tier include mapping and navigation, software development and lifecycle management, virtual classroom instruction delivery, data analytics processing, transaction processing, and, more particularly with respect to the present invention, functionality such as APIs and runtime system components that generate search autocomplete suggestions based on contextual input.

[0093] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a related application to co-pending U.S. patent application Ser. No. 17 / 137,708, IBM Docket No. P202003117US01, filed December 30, 2020, and U.S. patent application Ser. No. 17 / 071,257, IBM Docket No. P202000217US01, filed October 15, 2020, the entire contents of which are incorporated herein by reference.

[0094] The many features and advantages of the present invention are apparent from this detailed specification, and it is, therefore, intended by the appended claims to cover all such features and advantages of the present invention that fall within the true spirit and scope of the invention. Further, because so many modifications and variations will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation illustrated and described, and therefore, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

[0095] It is understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of embodiments other than those described and of being practiced and carried out in various ways. Also, it is understood that the phraseology and terminology employed in the specification and abstract is for the purpose of description and should not be regarded as limiting.

[0096] As such, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention. [Explanation of symbols]

[0097] 10 CPU cores 12 Instruction Fetch and Decode 14 ALU (Arithmetic Logic Unit) 16 General Purpose Register File 18 Boundary Register File 20 memory 21 Boundary Processing Unit 22 Data Cache 23 Through the index in the pointer 24 Boundary Information (BI) Cache 25 via the value of the pointer 26 Boundary Information Table 28 Index Table 29 BI entries 30 values / key table 40 Starting Address, Address, Base Address Fields 42 Buffer Length, Length, Object Size or Length Field 50 pointer value, key 52 Starting Address, Address 54 Buffer length, length 60 Pointer 62 index, index bit 64 pointer values 100 systems 370 BI Creation Order 400 Boundary Protection Operations 402 Load Instruction 404 Bold 412 store instructions 1100 Information Handling / Computer Systems 1110 Processor, Central Processing Unit (CPU), Computer 1112 System Bus, Bus 1114 Random Access Memory (RAM) 1116 Read-Only Memory (ROM) 1118 Input / Output (I / O) Adapter 1121 Disk Unit 1122 User Interface Adapter 1124 keyboard 1126 Mouse 1128 Speaker 1132 Microphone 1134 Communication Adapter 1136 Display Adapter 1138 Display devices, displays 1139 Printer 1140 Tape Drive 1141 Reader / Scanner 1200 Signal-bearing storage media 1210 Flash Memory 1220 Optical storage diskettes, optical disks 1400 Overview, Cloud Computing Node, Node, Computing Node 1412 Computer Systems / Servers 1414 External Devices 1416 Processor, Processing Unit 1418 Bus 1420 Network Adapter 1422 Input / Output (I / O) Interface 1424 display 1428 System Memory 1430 Random Access Memory (RAM) 1432 Cache memory, cache 1434 Storage Systems 1440 Programs / Utilities 1442 program modules 1550 Cloud Computing Environment 1554A Personal Digital Assistant (PDA) or Cellular Phone 1554B Desktop Computer 1554C Laptop Computer 1554N Automotive Computer System 1600 Hardware and Software Layers, Hardware and Software 1620 Virtualization Layer, Virtualization 1630 Management layer, management 1640 Workload Tier, Workload

Claims

1. 1. A method for protecting against cross-boundary references, comprising: The computer storing a buffer address in a general purpose register and a boundary information (BI) of said buffer in a boundary information register; using the contents of the boundary information register to determine whether a load or store operation is out of bounds when the contents of the general purpose register are used as an address in the load or store operation; storing said boundary information in said boundary information register in a boundary information register file; generating an index table in memory from the boundary information; generating a value and key table in said memory from said boundary information; using said index table and said value and key table to protect against references across said boundary; A method comprising:

2. which of the index table or value and key table is accessed is based on a heuristic; the index table is accessed by an index; each entry in the index table includes a starting address and a length of a buffer; the boundary information is mapped to the general-purpose registers; The method of claim 1.

3. said value and key table is accessed with a pointer value as a key; 2. The method of claim 1, wherein each entry in the value and key table includes a key for a pointer value, a starting address, and a length of a buffer.

4. the boundary information includes a starting address and a length of each buffer; the bounds information of the pointer can be located from the original instruction; the processor includes a boundary processing unit that performs the operations to protect against cross-boundary references; The method of claim 1.

5. 2. The method of claim 1, further comprising: when an address in the general purpose register is assigned to a second general purpose register, the boundary information of a first register is used as the boundary information of a second register.

6. 1. A system for cross-boundary reference protection, comprising: a memory for storing computer instructions; 1. A processor, comprising: storing a buffer address in a general purpose register and a boundary information (BI) of said buffer in a boundary information register; using the contents of the boundary information register to determine whether a load or store operation is out of bounds when the contents of the general purpose register are used as an address in the load or store operation; storing said boundary information in said boundary information register in a boundary information register file; generating an index table in said memory from said boundary information; generating a value and key table in said memory from said boundary information; using said index table and said value and key table to protect against cross-boundary references; the processor configured to execute the computer instructions to A system comprising:

7. which of the index table or value and key table is accessed is based on a heuristic; the index table is accessed by an index; each entry in the index table includes a starting address and a length of a buffer; the boundary information is mapped to the general-purpose registers; The system of claim 6.

8. said value and key table is accessed with a pointer value as a key; 7. The system of claim 6, wherein each entry in the value and key table includes a key for a pointer value, a starting address, and a length of a buffer.

9. the processor includes a boundary processing unit that performs the operations to protect against cross-boundary references; the boundary information includes a starting address and a length of each buffer; The bounds information of the pointer can be located from the original instruction. The system of claim 6.

10. 7. The system of claim 6, wherein when an address in the general purpose register is assigned to a second general purpose register, the boundary information of a first register is used as the boundary information of a second register.

11. A computer program for protecting against cross-boundary references, comprising: The program instructions are storing a buffer address in a general purpose register and a boundary information (BI) of said buffer in a boundary information register; using the contents of the boundary information register to determine whether a load or store operation is out of bounds when the contents of the general purpose register are used as an address in the load or store operation; storing said boundary information in said boundary information register in a boundary information register file; generating an index table in memory from the boundary information; generating a value and key table in said memory from said boundary information; using said index table and said value and key table to protect against cross-boundary references; A computer program readable and executable by a computer to cause the computer to carry out a method comprising:

12. which of the index table or value and key table is accessed is based on a heuristic; the index table is accessed by an index; each entry in the index table includes a starting address and a length of a buffer; the boundary information is mapped to the general-purpose registers; 12. The computer program of claim 11.

13. the processor includes a boundary processing unit that performs the operations to protect against cross-boundary references; said value and key table is accessed with a pointer value as a key; each entry in said value and key table includes a key for a pointer value, a starting address, and a length of a buffer; 12. The computer program of claim 11.

14. the boundary information includes a start in address and a length of each buffer; The bounds information of the pointer can be located from the original instruction.

12. The computer program of claim 11.

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