Semiconductor device

Abstract

This semiconductor device comprises a first lead having a die pad portion, a first semiconductor element mounted on the die pad portion, and a plurality of second leads. The plurality of second leads are arrayed, on one side in a first direction orthogonal to the thickness direction of the die pad portion, along a second direction orthogonal to the thickness direction and the first direction. The die pad portion comprises a die pad main surface facing one side in the thickness direction. The center of the first semiconductor element when viewed in the thickness direction is displaced from the center in the second direction of the die pad main surface. Each of the plurality of second leads comprises a second pad portion extending toward the first semiconductor element when viewed in the thickness direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a QFN (Quad Flat Non-leaded Package) type semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, a first lead, multiple second leads, multiple bonding wires, and a sealing resin. The semiconductor element is mounted at the center of the main surface of the mounting portion of the first lead, and each electrode pad is connected to each second lead by a bonding wire. All of the bonding portions of the second leads to which the bonding wires are bonded extend toward the center of the main surface of the mounting portion of the first lead when viewed in the thickness direction. Therefore, each bonding wire can be formed so as not to overlap other second leads adjacent to the second lead to which the bonding wire is bonded when viewed in the thickness direction. This prevents the bonding wire from contacting the other adjacent second leads.

[0003] Japanese Patent Application Laid-Open No. 2021-2587

[0004] However, if the semiconductor element is mounted at a position offset from the center of the main surface of the mounting portion, the bonding wire may overlap, in the thickness direction, with another second lead adjacent to the second lead to which the bonding wire is joined.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can prevent a wire from overlapping, in the thickness direction, with another lead adjacent to the lead to which the wire is bonded.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a first lead having a die pad portion, a first semiconductor element mounted on the die pad portion, and a plurality of second leads arranged on a first side in a first direction orthogonal to a thickness direction of the die pad portion, along a second direction orthogonal to the thickness direction and the first direction. The die pad portion has a die pad main surface facing the first side in the thickness direction. An element center, which is the center of the first semiconductor element as viewed in the thickness direction, is positioned offset from the center of the die pad main surface in the second direction. Each of the plurality of second leads has a second pad portion extending toward the first semiconductor element as viewed in the thickness direction.

[0007] According to the above configuration, in the semiconductor device, it is possible to prevent the wire from overlapping, in the thickness direction, with another lead adjacent to the lead to which the wire is bonded.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view showing the semiconductor device of FIG. 1, seen through a sealing resin. FIG. 3 is a bottom view showing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partially enlarged view of FIG. 2. FIG. 8 is a partially enlarged view of FIG. 2. FIG. 9 is a plan view showing a die pad portion. FIG. 10 is a plan view showing a die pad portion of a semiconductor device according to a first modification of the first embodiment. FIG. 11 is a plan view showing a die pad portion of a semiconductor device according to a second modification of the first embodiment. FIG. 12 is a plan view showing a die pad portion of a semiconductor device according to a third modification of the first embodiment. FIG. 13 is a plan view showing a die pad portion of a semiconductor device according to a fourth modification of the first embodiment. FIG. 14 is a plan view showing a die pad portion of a semiconductor device according to a fifth modification of the first embodiment. FIG. 15 is a plan view showing a die pad portion of a semiconductor device according to a sixth modified example of the first embodiment. FIG. 16 is a plan view showing a die pad portion of a semiconductor device according to a seventh modified example of the first embodiment. FIG. 17 is a plan view showing a die pad portion of a semiconductor device according to an eighth modified example of the first embodiment. FIG. 18 is a plan view showing a die pad portion of a semiconductor device according to a ninth modified example of the first embodiment. FIG. 19 is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 20 is a plan view showing a semiconductor device according to a third embodiment, seen through the sealing resin. FIG. 21 is a plan view showing a semiconductor device according to a first modified example of the third embodiment, seen through the sealing resin. FIG. 22 is a plan view showing a semiconductor device according to a fourth embodiment, seen through the sealing resin. FIG. 23 is a plan view showing a semiconductor device according to a fifth embodiment, seen through the sealing resin.

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed from a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0012] First Embodiment: FIGS. 1 to 9 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a lead 1, a lead 2, a plurality of leads 3, semiconductor elements 61 and 62, a plurality of wires 7, and a sealing resin 8. The semiconductor device A10 is used, for example, in a gate driver circuit of an inverter device of an electric vehicle or a hybrid vehicle. The semiconductor device A10 amplifies a control signal input from the outside and outputs it to a switching element (not shown). Note that the use and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is a QFN type. However, the package format of the semiconductor device A10 is not limited to the QFN type.

[0013] FIG. 1 is a perspective view showing a semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. FIG. 3 is a bottom view showing the semiconductor device A10. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partially enlarged view of FIG. 2. FIG. 8 is a partially enlarged view of FIG. 2. FIG. 9 is a plan view showing a die pad portion 11 (described later) of a lead 1.

[0014] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For convenience of explanation, the thickness direction of the semiconductor device A10 is referred to as the thickness direction z, the direction along one side of the semiconductor device A10 perpendicular to the thickness direction z (the left-right direction in FIGS. 2 and 3) is referred to as the first direction x, and the direction perpendicular to the thickness direction z and the first direction x (the up-down direction in FIGS. 2 and 3) is referred to as the second direction y. Note that the shape and dimensions of the semiconductor device A10 are not limited.

[0015] Lead 1, lead 2, and multiple leads 3 (hereinafter, collectively referred to as "leads 1 to 3") are components that form a conductive path between the semiconductor elements 61 and 62 and the wiring board on which the semiconductor device A10 is mounted. Note that some of the multiple leads 3 are not electrically connected to the semiconductor elements 61 and 62. Leads 1 to 3 are formed, for example, by etching or punching a metal plate. Leads 1 to 3 are made of metal, preferably either Cu or Ni, or an alloy thereof or 42 alloy. In this embodiment, a case where leads 1 to 3 are made of Cu will be described as an example. The thickness of leads 1 to 3 is, for example, 0.08 to 0.3 mm, and in this embodiment, it is approximately 0.2 mm.

[0016] 2, lead 1 is disposed toward a first side x1 in the first direction x of the semiconductor device A10 and extends over the entire semiconductor device A10 in the second direction y. Lead 2 is spaced apart from lead 1 and disposed toward a second side x2 in the first direction x of the semiconductor device A10. Each lead 3 is spaced apart from leads 1 and 2 and also spaced apart from each other, and disposed at either both ends of the semiconductor device A10 in the first direction x or both ends of the semiconductor device A10 in the second direction y. In terms of dimensions in the thickness direction z, lead 1 is larger than lead 2, and each lead 3 is larger than lead 2.

[0017] The lead 1 supports the semiconductor elements 61 and 62 and includes a die pad portion 11 and a plurality of terminal portions 12 .

[0018] The die pad portion 11 mounts the semiconductor elements 61 and 62. The die pad portion 11 is located toward the first side x1 in the first direction x and at the center in the second direction y of the semiconductor device A10, and has a rectangular (or approximately rectangular) shape when viewed in the thickness direction z. The die pad portion 11 has a main surface 111, a back surface 112, and a back surface recess 113. The main surface 111 and the back surface 112 face opposite each other in the thickness direction z. The main surface 111 faces the first side z1 in the thickness direction z. The main surface 111 is the surface on which the semiconductor elements 61 and 62 are mounted. As shown in FIG. 9 , the main surface 111 has an edge 111a. The edge 111a is an edge extending in the second direction y on the first side x1 of the main surface 111 in the first direction x. The back surface 112 faces the second side z2 in the thickness direction z. The back surface 112 is exposed from the sealing resin 8 and serves as a back surface terminal.

[0019] The back surface recess 113 is a portion of the die pad portion 11 recessed from the back surface 112 toward the first side z1 in the thickness direction z. The thickness (dimension in the thickness direction z) of the portion of the die pad portion 11 where the back surface recess 113 is located is approximately half the thickness of the portion where the back surface 112 is located. The back surface recess 113 is formed, for example, by half-etching from the second side z2 in the thickness direction z. As shown in FIG. 3 , the back surface recess 113 is disposed around the back surface 112. The back surface recess 113 is not exposed from the sealing resin 8 and is covered by the sealing resin 8. This prevents the lead 1 from peeling off from the sealing resin 8 toward the second side z2 in the thickness direction z. The shape of the die pad portion 11 is not limited. For example, the die pad portion 11 does not need to have the back surface recess 113.

[0020] The die pad portion 11 has an opening 4. Note that in FIGS. 2, 8, and 9, the opening 4 is hatched relatively finely for ease of understanding. The opening 4 is an opening having an open end in the main surface 111, and in this embodiment, is a recess recessed from the main surface 111 to the second side z2 in the thickness direction z. The depth of the opening 4 (dimension in the thickness direction z) is approximately half the thickness of the die pad portion 11 (the distance between the main surface 111 and the back surface 112 in the thickness direction z). The opening 4 is formed, for example, by half-etching from the first side z1 in the thickness direction z. As shown in FIG. 9, the opening 4 includes openings 41 to 45.

[0021] The opening 41 is located between the semiconductor element 62, shown by an imaginary line (two-dot chain line) in FIG. 9 , and the edge 111 a in the first direction x, and extends in the second direction y. In this embodiment, both ends of the opening 41 in the second direction y are located inside the outer edge of the main surface 111 when viewed in the thickness direction z. The opening 42 is connected to an end of the opening 41 on a first side y1 in the second direction y and extends to the first side x1 in the first direction x. In other words, the opening 42 is located on the first side x1 in the first direction x of the opening 41. In this embodiment, both ends of the opening 42 in the first direction x are located inside the outer edge of the main surface 111 when viewed in the thickness direction z. The semiconductor element 61, shown by an imaginary line (two-dot chain line) in FIG. 9 , is located on the first side y1 of the opening 42 in the second direction y. A portion of the opening 4 formed by the openings 41 and 42 is L-shaped when viewed in the thickness direction z.

[0022] The opening 43 is located between the semiconductor element 62 and the opening 41 in the first direction x and extends in the second direction y. In the present embodiment, both ends of the opening 43 in the second direction y are located inside the outer edge of the main surface 111 as viewed in the thickness direction z. The opening 44 is connected to an end of the opening 43 on the first side y1 in the second direction y and extends to the first side x1 in the first direction x. In other words, the opening 44 is located on the first side x1 in the first direction x of the opening 43. The opening 44 is also located between the semiconductor element 61 and the opening 42 in the second direction y. In the present embodiment, both ends of the opening 44 in the first direction x are located inside the outer edge of the main surface 111 as viewed in the thickness direction z. The opening 45 is connected to an end of the opening 43 on the first side y1 in the second direction y and extends to the first side y1 in the second direction y. In other words, the opening 45 is located on the first side y1 in the second direction y of the opening 43. In this embodiment, as viewed in the thickness direction z, both ends of the opening 45 in the second direction y are located inside the outer edge of the main surface 111. A portion of the opening 4 that is composed of the openings 43, 44, and 45 has a T-shape as viewed in the thickness direction z.

[0023] As shown in FIG. 9 , the main surface 111 of the die pad portion 11 includes a first region 51, a second region 52, and a third region 53. In FIG. 9 , the first region 51, the second region 52, and the third region 53 are indicated by imaginary lines (two-dot chain lines) and relatively coarsely hatched. The first region 51 is a region sandwiched between the openings 41 and 42 and the openings 43 and 44. The first region 51 is located on a first side x1 in the first direction x of the semiconductor element 62 and is a region to which the wire 7 (wire 73 described later) is bonded, as shown in FIG. 2 . The first region 51 may be plated. A plating layer formed by this plating process is made of a metal containing, for example, Ag. The plating layer enhances the bonding strength of the wire 73 while protecting the lead 1 from impact during wire bonding of the wire 73. The second region 52 is a region on a second side x2 in the first direction x of the openings 43 and 45. 2, the second region 52 is a region where a semiconductor element 62 is mounted. The third region 53 is a region on a first side x1 in the first direction x of the opening 45 and on a first side y1 in the second direction y of the opening 44. The third region 53 is located on the first side x1 of the center of the main surface 111 of the die pad portion 11 in the first direction x, and on the first side y1 of the center in the second direction y. The third region 53 is a region where a semiconductor element 61 is mounted, as shown in FIG.

[0024] In other words, the first region 51, the second region 52, and the third region 53 are regions partitioned by the openings 4. The openings 43 partition the first region 51 and the second region 52. The openings 44 partition the first region 51 and the third region 53. The openings 45 partition the second region 52 and the third region 53. Note that the shape and arrangement of the openings 4 are not limited to those described above, and the shapes and arrangement of the first region 51, the second region 52, and the third region 53 are not limited to those described above.

[0025] The multiple terminals 12 are bonded to the wiring board when the semiconductor device A10 is mounted on the wiring board. Each terminal 12 is connected to the die pad 11 and has a rectangular (or approximately rectangular) shape when viewed in the thickness direction z. The multiple terminals 12 include six terminals 12a, two terminals 12b, eight terminals 12c, and terminals 12d and 12e. The six terminals 12a are connected to a first side x1 of the die pad 11 in the first direction x and are arranged along the second direction y, closer to a second side y2 in the second direction y. The six terminals 12a overlap the opening 4 (opening 41) when viewed in the first direction x. The two terminals 12b are connected to a first side y1 of the die pad 11 in the second direction y and are arranged along the second direction y, closer to a second side x2 in the first direction x. The eight terminals 12c are connected to a second side y2 in the second direction y of the die pad portion 11 and are arranged along the first direction x. The terminal 12d is connected to a corner of the die pad portion 11 on the first side x1 in the first direction x and on the first side y1 in the second direction y. The terminal 12e is connected to a corner of the die pad portion 11 on the first side x1 in the first direction x and on the second side y2 in the second direction y.

[0026] Each terminal portion 12 has a main surface 121, a back surface 122, and an end surface 123. The main surface 121 and the back surface 122 face opposite each other in the thickness direction z. The main surface 121 faces a first side z1 in the thickness direction z. The main surface 121 and the main surface 111 of the die pad portion 11 are flush with each other. The back surface 122 faces a second side z2 in the thickness direction z. The back surface 122 and the back surface 112 of the die pad portion 11 are spaced apart as shown in FIG. 3 and are located at the same position in the thickness direction z. The end surface 123 is perpendicular to the main surface 121 and the back surface 122 and is connected to the main surface 121 and the back surface 122. The terminal portion 12d and the terminal portion 12e each have two end surfaces 123. The end surfaces 123 are formed by singulation during a cutting process in the manufacturing process. The end surface 123 and the back surface 122 are exposed from the sealing resin 8 and connected to form terminals (see FIG. 5). The shape, arrangement position and number of the terminal portions 12 are not limited.

[0027] The lead 2 is arranged spaced apart from the lead 1 on the second side x2 in the first direction x. The die pad portion 11 of the lead 1 and the lead 2 are arranged side by side in the first direction x. The lead 2 is electrically connected to the semiconductor element 62 by a plurality of wires 7 (a plurality of wires 74 described later). The lead 2 includes a pad portion 21 and a plurality of terminal portions 22.

[0028] The pad portion 21 has a plurality of wires 74 bonded thereto. The pad portion 21 has a main surface 211, a back surface 212, and through holes 213. The main surface 211 and the back surface 212 face opposite each other in the thickness direction z. The main surface 211 faces a first side z1 in the thickness direction z. The main surface 211 is the surface to which the plurality of wires 74 are bonded. As shown in FIG. 7 , the main surface 211 includes a bonded region 211a and a non-bonded region 211b. In FIG. 7 , the bonded region 211a and the non-bonded region 211b are indicated by imaginary lines (two-dot chain lines). The bonded region 211a is the region to which the plurality of wires 74 are bonded, and is located on the main surface 211 closer to the second side y2 in the second direction y. The non-bonded region 211b is the region to which the plurality of wires 74 are not bonded, and is located on the first side y1 in the second direction y relative to the bonded region 211a. The dimension L1 of the bonding region 211a in the second direction y is 40% to 60% of the dimension L2 of the lead 2 in the second direction y. The bonding region 211a may be plated. The plating layer formed by the plating is made of a metal containing, for example, Ag. The plating layer enhances the bonding strength of the wire 74 while protecting the lead 2 from impact during wire bonding of the wire 74. The back surface 212 faces the second side z2 in the thickness direction z. The back surface 212 is covered with the sealing resin 8. The thickness (dimension in the thickness direction z) of the pad portion 21 is approximately half the thickness of the die pad portion 11 and is approximately the same as the thickness of the portion of the die pad portion 11 where the back surface recess 113 is located. The pad portion 21 is formed, for example, by half-etching from the second side z2 in the thickness direction z.

[0029] The through holes 213 are holes that penetrate the pad portion 21 in the thickness direction z. The through holes 213 make it easier for the material of the sealing resin 8 to fill the back surface 212 side of the pad portion 21 in the sealing resin 8 formation process in the manufacturing process of the semiconductor device A10. In this embodiment, the pad portion 21 has four rectangular (or approximately rectangular) through holes 213 that are elongated in the second direction y and arranged in the second direction y. The shape, number, and arrangement of the through holes 213 are not limited. Furthermore, the pad portion 21 does not have to have the through holes 213.

[0030] The terminals 22 are bonded to the wiring board when the semiconductor device A10 is mounted on the wiring board. Each terminal 22 is connected to the second side x2 of the pad 21 in the first direction x and has a rectangular (or approximately rectangular) shape when viewed in the thickness direction z. In this embodiment, twelve terminals 22 are arranged at equal intervals along the second direction y.

[0031] Each terminal portion 22 has a main surface 221, a back surface 222, and an end surface 223. The main surface 221 and the back surface 222 face opposite each other in the thickness direction z. The main surface 221 faces a first side z1 in the thickness direction z. The main surface 221 and the main surface 211 of the pad portion 21 are flush with each other. The back surface 222 faces a second side z2 in the thickness direction z. In this embodiment, as shown in FIG. 3 , the distance L3 between the back surface 222 of the terminal portion 22 of the lead 2 and the back surface 112 of the die pad portion 11 is sufficiently large, for example, 30% to 40% of the dimension L4 of the semiconductor device A10 in the first direction x. Note that the distance between the back surface 222 and the back surface 112 is not limited to this. The end surface 223 is a surface that is perpendicular to the main surface 221 and the back surface 222 and connects to the main surface 221 and the back surface 222. The end surface 223 is formed by singulation during a cutting process in the manufacturing process. The end surface 223 and the back surface 222 are exposed from the sealing resin 8 and connected to form terminals (see FIGS. 4 and 5). The shape, arrangement position, and number of the terminal portions 22 are not limited.

[0032] The leads 3 form conductive paths between the semiconductor elements 61, 62 and a wiring board on which the semiconductor device A10 is mounted. The leads 3 also include so-called dummy leads that are not conductive to the semiconductor elements 61, 62. Each lead 3 has a pad portion 31 and a terminal portion 32.

[0033] The pad portion 31 is a portion to which the wire 7 (a wire 71 described later) is bonded. The pad portion 31 may or may not have the wire 71 bonded thereto. The pad portion 31 has a main surface 311 and a back surface 312. The main surface 311 and the back surface 312 face opposite each other in the thickness direction z. The main surface 311 faces a first side z1 in the thickness direction z. The main surface 311 is the surface to which the wire 71 is bonded. The main surface 311 may be plated. A plating layer formed by the plating process is made of a metal containing Ag, for example. The plating layer increases the bonding strength of the wire 71 while protecting the leads 3 from impact during wire bonding of the wire 71. The plating layer may be formed only on the leads 3 to which the wire 71 is bonded. The back surface 312 faces a second side z2 in the thickness direction z. The back surface 312 is covered with a sealing resin 8. The thickness of the pad portion 31 (dimension in the thickness direction z) is approximately half the thickness of the die pad portion 11, and is approximately the same as the thickness of a portion of the die pad portion 11 where the rear surface side recess 113 is located. The pad portion 31 is formed, for example, by half-etching processing from the second side z2 in the thickness direction z.

[0034] The terminal portion 32 is bonded to the wiring board when the semiconductor device A10 is mounted on the wiring board. The terminal portion 32 is connected to the pad portion 31 and has a rectangular (or approximately rectangular) shape when viewed in the thickness direction z. The terminal portion 32 has a main surface 321, a back surface 322, and an end surface 323. The main surface 321 and the back surface 322 face opposite each other in the thickness direction z. The main surface 321 faces a first side z1 in the thickness direction z. The main surface 321 and the main surface 311 of the pad portion 31 are flush with each other. The wire 71 may be bonded to the main surface 321 of the terminal portion 32. The back surface 322 faces a second side z2 in the thickness direction z. The end surface 323 is perpendicular to the main surface 321 and the back surface 322 and is connected to the main surface 321 and the back surface 322. The end surface 323 is formed by singulation during a cutting process in the manufacturing process. The end surface 323 and the back surface 322 are exposed from the sealing resin 8 and connected to form a terminal (see FIG. 4). The shape of the terminal portion 32 is not limited.

[0035] As shown in FIG. 2, the leads 3 include a plurality of leads 3a, a plurality of leads 3b, a lead 3c, a lead 3e, a pair of leads 3f, and a pair of leads 3g.

[0036] In this embodiment, the multiple leads 3 include seven leads 3a. Note that the number of leads 3a is not limited. The multiple leads 3a are arranged closer to the first side y1 in the second direction y at an end of the semiconductor device A10 on the first side x1 in the first direction x. The multiple leads 3a are arranged on the first side x1 in the first direction x of the die pad portion 11, along the second direction y, between the terminal portions 12a and 12d in the second direction y. In addition, in this embodiment, the multiple leads 3 include seven leads 3b. Note that the number of leads 3b is not limited. The multiple leads 3b are arranged closer to the first side x1 in the first direction x at an end of the semiconductor device A10 on the first side y1 in the second direction y. The multiple leads 3b are arranged on the first side y1 in the second direction y of the die pad portion 11, along the first direction x, between the terminal portions 12b and 12d in the first direction x. The multiple leads 3a and the multiple leads 3b are arranged so as to be electrically connected to the semiconductor element 61 via wires 71. In this embodiment, most of the multiple leads 3a and multiple leads 3b are electrically connected to the semiconductor element 61, but some are not electrically connected to the semiconductor element 61. It should be noted that there are no limitations on which of the multiple leads 3a and multiple leads 3b are electrically connected to the semiconductor element 61, or which electrode 611 (described later) of the semiconductor element 61 they are electrically connected to. As shown in Fig. 8 , each pad portion 31 of the multiple leads 3a and multiple leads 3b extends toward an element center 61c, which is the center of the semiconductor element 61, when viewed in the thickness direction z.

[0037] In this embodiment, the multiple leads 3 include one lead 3c and one lead 3e. The numbers of leads 3c and 3e are not limited. Lead 3c is arranged on a first side x1 in the first direction x of the die pad portion 11, between terminal portion 12a and terminal portion 12e in the second direction y. Lead 3e is arranged on a second side y2 in the second direction y of the die pad portion 11, between terminal portion 12c and terminal portion 12e in the first direction x. Leads 3c and 3e are so-called dummy leads.

[0038] In this embodiment, the multiple leads 3 include a pair of leads 3f and a pair of leads 3g. The pair of leads 3g are arranged one on each of the first side y1 and the second side y2 of the lead 2 in the second direction y. One lead 3g is arranged at a corner on the first side y1 in the second direction y on the second side x2 in the first direction x of the semiconductor device A10, and the other lead 3g is arranged at a corner on the second side x2 in the first direction x on the second side y2 in the second direction y on the second side x2 in the first direction x of the semiconductor device A10. The multiple leads 3 do not necessarily have to include the lead 3g. The pair of leads 3f are arranged one on each of the first side y1 and the second side y2 in the second direction y of the lead 2. Each lead 3f is arranged between the lead 2 and each lead 3g in the second direction y. The number of leads 3f is not limited. The leads 3f and 3g are so-called dummy leads.

[0039] A plating layer containing, for example, Sn may be disposed on the surfaces of the leads 1 to 3 that are exposed from the sealing resin 8. The material of the plating layer is not limited. When the semiconductor device A10 is surface-mounted on a wiring board by soldering, the plating layer improves the adhesion of solder to the exposed surfaces while preventing erosion of the exposed portions due to soldering. The shape and arrangement of the leads 1 to 3 are not limited to those described above.

[0040] The semiconductor element 61 and the semiconductor element 62 are elements that perform the electrical functions of the semiconductor device A10. The semiconductor element 62 is a switching element. In this embodiment, the semiconductor element 62 is a high electron mobility transistor (HEMT) using gallium nitride (GaN). Note that nitride semiconductors other than GaN may be used for the semiconductor element 62. The semiconductor element 62 may also be an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a bipolar transistor, or the like. The semiconductor element 62 includes a primary surface 62a, a rear surface 62b, a plurality of first electrodes 621, a second electrode 622, and a plurality of third electrodes 623.

[0041] The element principal surface 62a and the element back surface 62b face opposite each other in the thickness direction z. The element principal surface 62a faces a first side z1 in the thickness direction z, and the element back surface 62b faces a second side z2 in the thickness direction z. A plurality of first electrodes 621, a second electrode 622, and a plurality of third electrodes 623 are arranged on the element principal surface 62a. The plurality of first electrodes 621 are source electrodes and are arranged side by side along the second direction y on the element principal surface 62a closer to the first side x1 in the first direction x. The second electrode 622 is a gate electrode and is arranged side by side along the second direction y on the element principal surface 62a closer to the first side y1 in the second direction y. The plurality of third electrodes 623 are drain electrodes and are arranged side by side along the second direction y on the element principal surface 62a closer to the second side x2 in the first direction x. Other electrodes are also arranged on the element principal surface 62a. Furthermore, the layout of the electrodes 621 to 623 is not limited.

[0042] As shown in FIGS. 4 to 6 , the semiconductor element 62 has an element back surface 62b bonded to the main surface 111 of the die pad portion 11 via a bonding member 65. In this embodiment, the bonding member 65 is, for example, Ag paste. The bonding member 65 may be a conductive bonding material such as solder or a sintered silver bonding material, or may be an insulating bonding material. As shown in FIGS. 2 and 9 , the semiconductor element 62 is disposed in the second region 52 of the main surface 111, i.e., on the second side x2 of the openings 43 and 44 in the first direction x.

[0043] The semiconductor element 61 is a driving element that drives the semiconductor element 62. The semiconductor element 61 generates a driving signal based on a control signal input from the outside and outputs it to the semiconductor element 62. The semiconductor element 61 also controls the driving signal based on a source sense signal input from the semiconductor element 62. The semiconductor element 61 has a main surface 61a, a back surface 61b, and a plurality of electrodes 611.

[0044] The element principal surface 61a and the element back surface 61b face opposite each other in the thickness direction z. The element principal surface 61a faces a first side z1 in the thickness direction z, and the element back surface 61b faces a second side z2 in the thickness direction z. A plurality of electrodes 611 are arranged on the element principal surface 61a. Note that the function and arrangement of each electrode 611 are not limited.

[0045] As shown in FIG. 4 , the semiconductor element 61 has an element back surface 61b bonded to the main surface 111 of the die pad portion 11 via a bonding member 65. As shown in FIGS. 2 and 9 , the semiconductor element 61 is disposed in the third region 53 of the main surface 111, i.e., on the first side x1 of the opening 45 in the first direction x and on the first side y1 of the opening 44 in the second direction y. The semiconductor element 61 is disposed on the first side x1 relative to the semiconductor element 62 in the first direction x and on the first side y1 relative to the semiconductor element 62 in the second direction y. An element center 61c, which is the center of the semiconductor element 61 as viewed in the thickness direction z, is located on the first side y1 of the center of the main surface 111 of the die pad portion 11 in the second direction y and is located on the first side x1 of the center of the main surface 111 in the first direction x.

[0046] 2, the plurality of wires 7, together with the leads 1 to 3, form a conductive path for the semiconductor elements 61 and 62 to perform predetermined functions. The constituent material of each wire 7 is, for example, but not limited to, Cu, Au, Ag, Al, or an alloy containing any of these. The plurality of wires 7 each include a plurality of wires 71, 72, 73, and 74.

[0047] 2 and 8 , the plurality of wires 71 form conductive paths between the semiconductor element 61 and the plurality of leads 3. Each wire 71 is conductively joined to one of the electrodes 611 of the semiconductor element 61 and the main surface 311 of the pad portion 31 of one of the plurality of leads 3 a or the plurality of leads 3 b. This allows the semiconductor element 61 to receive signals from the outside and output signals to the outside via the plurality of leads 3 and the wires 71. Because the pad portions 31 of both the plurality of leads 3 a and the plurality of leads 3 b extend toward the element center 61 c of the semiconductor element 61 as viewed in the thickness direction z, each wire 71 can be formed so as not to overlap, as viewed in the thickness direction z, with other leads 3 adjacent to the lead 3 to which the wire 71 is joined.

[0048] 2 and 8 , the plurality of wires 72 form a conductive path between the semiconductor element 61 and the semiconductor element 62. One wire 72 is conductively joined to one of the electrodes 611 of the semiconductor element 61 and a second electrode 622 of the semiconductor element 62. The semiconductor element 61 outputs a drive signal to the second electrode 622 via the wire 72. The other wires 72 are conductively joined to one of the electrodes 611 of the semiconductor element 61 and one of the electrodes of the semiconductor element 62. A source sense signal is input to the semiconductor element 61 via the wire 72 joined to the first electrode 621 (source electrode) of the semiconductor element 62. The semiconductor element 61 also inputs and outputs signals to and from the semiconductor element 62 via the other wires 72.

[0049] 2 and 8 , the plurality of wires 73 form a conductive path between the semiconductor element 62 and the die pad portion 11. Each wire 73 is conductively joined to one of the first electrodes 621 of the semiconductor element 62 and the main surface 111 of the die pad portion 11. As a result, the lead 1 is conductively connected to the first electrode 621 (source electrode) of the semiconductor element 62 and functions as a source terminal. In this embodiment, each wire 73 is joined to the first region 51 of the main surface 111.

[0050] As shown in FIGS. 2 and 7 , the multiple wires 74 form a conductive path between the semiconductor element 62 and the lead 2. Each wire 74 is conductively joined to one of the third electrodes 623 of the semiconductor element 62 and the main surface 211 of the pad portion 21 of the lead 2. As a result, the lead 2 is conductively connected to the third electrode 623 (drain electrode) of the semiconductor element 62 and functions as a drain terminal. In this embodiment, each wire 74 is joined to a bonding region 211a of the main surface 211. All of the wires 74 are inclined with respect to the first direction x when viewed in the thickness direction z. As shown in FIG. 7 , each wire 74 has a bonding portion 74a joined to the semiconductor element 62 and a bonding portion 74b joined to the lead 2. The bonding portion 74a is located on the first side y1 in the second direction y relative to the bonding portion 74b.

[0051] During the process of forming the sealing resin 8 in the manufacturing process of the semiconductor device A10, the material of the sealing resin 8 flows in the second direction y from the first side y1 to the second side y2 in the second direction y, as indicated by the dashed arrow 89 in FIG. Therefore, each wire 74 is curved toward the second side y2 in the second direction y. Furthermore, because each wire 74 is inclined with respect to the first direction x when viewed in the thickness direction z, the force applied to the wire 74 by the material of the sealing resin 8 is decomposed into a component parallel to the wire 74 and a component perpendicular to the wire 74. The perpendicular component, which affects so-called wire sweep, is smaller than when the wire 74 is parallel to the second direction y, thereby suppressing wire sweep. The greater the inclination angle α of the wire 74 with respect to the first direction x, the greater the effect of suppressing wire sweep can be expected.

[0052] The sealing resin 8 covers a portion of each of the leads 1 to 3, the semiconductor elements 61 and 62, and the wires 7. The sealing resin 8 has electrical insulating properties. The sealing resin 8 is made of a material containing, for example, black epoxy resin. However, the material of the sealing resin 8 is not limited.

[0053] The sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83. The resin main surface 81 and the resin back surface 82 face opposite each other in the thickness direction z. The resin main surface 81 faces a first side z1 in the thickness direction z, and the resin back surface 82 faces a second side z2 in the thickness direction z.

[0054] The four resin side surfaces 83 are each perpendicular to the resin main surface 81 and the resin back surface 82, connect the resin main surface 81 and the resin back surface 82, and face outward in the first direction x or the second direction y. Each resin side surface 83 is formed by singulation during a cutting process in the manufacturing process. The four resin side surfaces 83 include a first resin side surface 831, a second resin side surface 832, a third resin side surface 833, and a fourth resin side surface 834. The first resin side surface 831 and the second resin side surface 832 face opposite each other in the second direction y. The first resin side surface 831 is a surface located on a first side y1 in the second direction y and faces the first side y1, and the second resin side surface 832 is a surface located on a second side y2 in the second direction y and faces the second side y2. The third resin side surface 833 and the fourth resin side surface 834 face opposite each other in the first direction x. The third resin side surface 833 is a surface that is arranged on the first side x1 in the first direction x and faces the first side x1, and the fourth resin side surface 834 is a surface that is arranged on the second side x2 in the first direction x and faces the second side x2.

[0055] Each end face 123 of the lead 1 facing the first side x1 in the first direction x and each end face 323 of the leads 3a and 3c are exposed from the third resin side face 833 and are flush with the third resin side face 833. The end faces 123 and 323 exposed from the third resin side face 833 are spaced apart from each other and arranged at equal intervals along the second direction y. Each end face 123 of the lead 1 facing the first side y1 in the second direction y, each end face 323 of each lead 3b, and each end face 323 of the lead 3g facing the first side y1 are exposed from the first resin side face 831 and are flush with the first resin side face 831. The end faces 123 and 323 of each lead 3b exposed from the first resin side face 831 are spaced apart from each other and arranged at equal intervals along the first direction x. The end faces 123 of the lead 1 facing the second side y2 in the second direction y, the end faces 323 of the lead 3e, and the end faces 323 of the lead 3g facing the second side y2 are exposed from the second resin side face 832 and are flush with each other. The end faces 123 exposed from the second resin side face 832 and the end faces 323 of the leads 3e are spaced apart from each other and arranged at equal intervals along the first direction x. The end faces 223 of the terminal portions 22 of the lead 2, the end faces 323 of each lead 3f, and the end faces 323 of each lead 3g facing the second side x2 are exposed from the fourth resin side face 834 and are flush with each other. The end faces 223 and 323 exposed from the fourth resin side face 834 are spaced apart from each other and arranged at equal intervals along the second direction y. In addition, the back surface 112 of the die pad portion 11 of lead 1 and the back surface 122 of each terminal portion 12, the back surface 222 of each terminal portion 22 of lead 2, and the back surface 322 of the terminal portion 32 of each lead 3 are exposed from the resin back surface 82 and are flush with each other.

[0056] Next, the effects of the semiconductor device A10 will be described.

[0057] According to this embodiment, the semiconductor element 61 is mounted on the main surface 111 of the die pad portion 11 at a position shifted toward the first side y1 from the center in the second direction y. Furthermore, the pad portions 31 of each lead 3a extend toward the element center 61c as viewed in the thickness direction z. Therefore, the wire 71 bonded to each lead 3a can be formed so as not to overlap with the other lead 3a adjacent to the lead 3a to which the wire 71 is bonded as viewed in the thickness direction z. This prevents the wires 71 from contacting the other adjacent leads 3a in the semiconductor device A10. Furthermore, the semiconductor element 61 is mounted on the main surface 111 of the die pad portion 11 at a position shifted toward the first side x1 from the center in the first direction x. Furthermore, the pad portions 31 of each lead 3b extend toward the element center 61c as viewed in the thickness direction z. Therefore, the wire 71 bonded to each lead 3b can be formed so as not to overlap, as viewed in the thickness direction z, with other leads 3b adjacent to the lead 3b to which the wire 71 is bonded. This allows the semiconductor device A10 to prevent each wire 71 from contacting the other adjacent leads 3b.

[0058] Furthermore, according to this embodiment, each wire 74 is inclined with respect to the first direction x when viewed in the thickness direction z. Therefore, compared to when the wires 74 are parallel to the first direction x, the force exerted on each wire 74 by the material of the sealing resin 8 flowing in the second direction y during the process of forming the sealing resin 8 in the manufacturing process of the semiconductor device A10 is smaller. This suppresses wire sweep of each wire 74, thereby suppressing contact between wires 74 due to wire sweep in the semiconductor device A10. Furthermore, according to this embodiment, each wire 74 has its joint 74a located on the first side y1 in the second direction y relative to its joint 74b, and the inclination direction with respect to the first direction x is the same. Therefore, since the wire sweep occurring in each wire 74 is similar, contact between wires 74 due to wire sweep is suppressed in the semiconductor device A10.

[0059] According to this embodiment, the die pad portion 11 includes an opening 4, which is a recess recessed from the main surface 111 toward the second side z2 in the thickness direction z. The opening 4 is located between the first region 51 to which the wire 73 is bonded and the edge 111a in the first direction x, and includes an opening 41 extending in the second direction y. The opening 41 prevents peeling occurring at the edge 111a from progressing toward the second side x2 in the first direction x. Because the opening 41 prevents peeling from progressing toward the first region 51, the semiconductor device A10 can suppress peeling of the wire 73 from the die pad portion 11. According to this embodiment, the opening 4 includes an opening 42 connected to an end of the opening 41 on the first side y1 in the second direction y and extending toward the first side x1 in the first direction x. The opening 42 prevents peeling occurring at the edge 111a from progressing toward the first side y1 in the second direction y. Because the opening 42 prevents peeling from progressing to the first region 51 and the second region 52, the semiconductor device A10 can prevent the wire 73 from peeling from the die pad portion 11 and the semiconductor element 61 from peeling from the die pad portion 11.

[0060] According to the present embodiment, the opening 4 includes an opening 43 that is located in the first direction x between the second region 52 on which the semiconductor element 62 is mounted and the first region 51 to which the wire 73 is bonded, and that extends in the second direction y. Even if the molten bonding material 65 flows out when bonding the semiconductor element 62 to the die pad 11 during the manufacturing process, the opening 43 can prevent the molten bonding material 65 from flowing to the first region 51. This prevents the bonding material 65 from interfering with the bonding of the wire 73. Furthermore, the opening 43 prevents the sealing resin 8 from peeling from the die pad 11 toward the first side x1 in the first direction x, thereby contributing to preventing the wire 73 from peeling from the die pad 11. According to the present embodiment, the opening 4 includes an opening 44 that is connected to an end of the opening 43 on the first side y1 in the second direction y and extends toward the first side x1 in the first direction x. Even if the molten bonding material 65 flows out when bonding the semiconductor element 61 to the die pad portion 11 during the manufacturing process, the opening 44 can prevent the molten bonding material 65 from flowing to the first region 51. This prevents the bonding material 65 from interfering with the bonding of the wires 73. Furthermore, the opening 44 prevents the sealing resin 8 from peeling from the die pad portion 11 toward the second side y2 in the second direction y, thereby contributing to preventing the wires 73 from peeling from the die pad portion 11. Furthermore, according to this embodiment, the opening 4 includes an opening 45 that is connected to the end of the opening 43 on the first side y1 in the second direction y and extends toward the first side y1 in the second direction y. The opening 45 prevents stress concentration at the connection point between the opening 43 and the opening 44 and further strengthens the bond between the sealing resin 8 and the die pad portion 11. In addition, openings 43, 44, and 45 also have the function of dividing first region 51, second region 52, and third region 53, and clearly indicating the positions for mounting semiconductor elements 61 and 62.

[0061] Moreover, according to this embodiment, each end of the opening 4 is located inside the outer edge of the main surface 111 of the die pad portion 11. Therefore, the strength of the die pad portion 11 can be increased compared to when each end extends to the outer edge of the main surface 111. Furthermore, according to this embodiment, the opening 4 is a recess recessed from the main surface 111 toward the second side z2 in the thickness direction z. Therefore, the strength of the die pad portion 11 can be increased compared to when the opening 4 penetrates the die pad portion 11 in the thickness direction z.

[0062] Furthermore, in this embodiment, the distance between the back surface 112 of the die pad portion 11 and the back surface 222 of the terminal portion 22 of the lead 2 is sufficiently large. This prevents electrical conduction between the back surfaces 112 and 222 due to dielectric breakdown. On the other hand, the dimension of the pad portion 21 of the lead 2 in the first direction x is sufficiently large. This allows the length of the wire 74 that electrically connects the semiconductor element 62 and the pad portion 21 to be reduced.

[0063] Furthermore, according to this embodiment, the semiconductor device A10 includes leads 3c, 3e, 3f, and 3g, which are dummy leads. Therefore, the semiconductor device A10 has improved mounting reliability compared to a semiconductor device not including the leads 3c, 3e, 3f, and 3g. Furthermore, according to this embodiment, the lead 1 includes terminal portions 12a, 12b, and 12c. Therefore, the semiconductor device A10 has improved heat dissipation and improved strength to support the die pad portion 11 compared to a semiconductor device including leads spaced apart from the lead 1 instead of the terminal portions 12a, 12b, and 12c.

[0064] In the present embodiment, the opening 4 includes all of the openings 41 to 45, but this is not limiting. The opening 4 may not include any of the openings 41 to 45. The die pad portion 11 may not have an opening 4. In the present embodiment, the wires 74 are all inclined with respect to the first direction x when viewed in the thickness direction z, but this is not limiting. The wires 74 may be parallel to the first direction x when viewed in the thickness direction z. In the present embodiment, the pad portions 31 of the leads 3 a and 3 b extend toward the element center 61 c when viewed in the thickness direction z, but this is not limiting. The pad portions 31 of the leads 3 a may extend toward the second side x2 in the first direction x. The pad portions 31 of the leads 3 b may extend toward the second side y2 in the second direction y. Furthermore, the package format of the semiconductor device A10, the type and number of the semiconductor elements 61 and 62 mounted thereon, and the shape, number, and arrangement of the leads 1 to 3 are not particularly limited.

[0065] In addition, in the present embodiment, the case where the bonding region 211a is disposed closer to the second side y2 in the second direction y of the main surface 211 has been described, but this is not limiting. The bonding region 211a may be disposed closer to the first side y1 in the second direction y of the main surface 211. In this case, the bonding portion 74a of the wire 74 is located closer to the second side y2 in the second direction y than the bonding portion 74b.

[0066] 10 to 18 show modified examples of the semiconductor device A10 according to the first embodiment. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment, and redundant explanations will be omitted.

[0067] First Modification: Fig. 10 is a diagram for explaining a semiconductor device A11 according to a first modification of the first embodiment. Fig. 10 is a plan view showing the die pad portion 11 of the semiconductor device A11, and corresponds to Fig. 9. The semiconductor device A11 differs from the semiconductor device A10 in the configuration of the opening 4.

[0068] The opening 4 of the semiconductor device A11 according to this modification does not include the opening 42 or the opening 45. In this modification, the opening 4 also includes the opening 41, which prevents peeling that occurs at the edge 111a from progressing toward the first region 51, thereby suppressing peeling of the wire 73 from the die pad portion 11. Furthermore, the opening 4 includes the openings 43 and 44, which can suppress the outflow of the molten bonding material 65 into the first region 51 and also contribute to suppressing peeling of the wire 73 from the die pad portion 11.

[0069] Second Modification: Fig. 11 is a diagram for explaining a semiconductor device A12 according to a second modification of the first embodiment. Fig. 11 is a plan view showing the die pad portion 11 of the semiconductor device A12, and corresponds to Fig. 9. The semiconductor device A12 differs from the semiconductor device A10 in the configuration of the opening 4.

[0070] The opening 4 of the semiconductor device A12 according to this modification does not include the openings 43 to 45. In this modification as well, the opening 4 includes the openings 41 and 42, so that the progression of peeling to the first region 51 and the second region 52 is prevented, and peeling of the wire 73 and the semiconductor element 61 from the die pad portion 11 is suppressed.

[0071] Third Modification: Fig. 12 is a diagram for explaining a semiconductor device A13 according to a third modification of the first embodiment. Fig. 12 is a plan view showing the die pad portion 11 of the semiconductor device A13, and corresponds to Fig. 9. The semiconductor device A13 differs from the semiconductor device A10 in the configuration of the opening 4.

[0072] The opening 4 of the semiconductor device A13 according to this modification does not include the openings 41 and 42. In this modification, the opening 4 also includes the openings 43 and 44, which prevents the molten bonding material 65 from flowing into the first region 51 and also contributes to preventing the wire 73 from peeling off from the die pad portion 11. Furthermore, the opening 4 includes the opening 45, which prevents stress concentration at the connection point between the openings 43 and 44 and further strengthens the bond between the sealing resin 8 and the die pad portion 11. Furthermore, the openings 43 to 45 partition the main surface 111 of the die pad portion 11 into the first region 51, the second region 52, and the third region 53, which clarifies the positions for mounting the semiconductor elements 61 and 62.

[0073] As can be seen from Modifications 1 to 3, the opening 4 does not need to include all of the openings 41 to 45. The opening 4 only needs to include the necessary portions of the openings 41 to 45.

[0074] Fourth Modification: Fig. 13 is a diagram for explaining a semiconductor device A14 according to a fourth modification of the first embodiment. Fig. 13 is a plan view showing the die pad portion 11 of the semiconductor device A14, and corresponds to Fig. 9. The semiconductor device A14 differs from the semiconductor device A10 in the configuration of the opening 4.

[0075] In the openings 4 of the semiconductor device A14 according to this modification, openings 41 and 42 are not connected and are spaced apart, and openings 43, 44, and 45 are not connected and are spaced apart. Even though openings 41 to 45 are spaced apart and not connected to each other, each can hinder the progression of peeling and can also hinder the flow of molten bonding material 65. Note that, because there is a risk that peeling may progress through the spaced apart portions or that molten bonding material 65 may flow out from the spaced apart portions, it is desirable that the spaced apart portions be as small as possible, and it is even more desirable that they are connected.

[0076] Fifth Modification: Fig. 14 is a diagram for explaining a semiconductor device A15 according to a fifth modification of the first embodiment. Fig. 14 is a plan view showing the die pad portion 11 of the semiconductor device A15, and corresponds to Fig. 9. The semiconductor device A15 differs from the semiconductor device A10 in the configuration of the opening 4.

[0077] The opening 4 of the semiconductor device A15 according to this modification is such that the openings 41 to 45 do not each extend in the first direction x or the second direction y, but are composed of a plurality of portions 4a arranged in the first direction x or the second direction y. Each portion 4a has, for example, a rectangular shape when viewed in the thickness direction z, and is a recess recessed from the main surface 111 to the second side z2 in the thickness direction z. Note that the shape and size of each portion 4a when viewed in the thickness direction z are not limited. In this modification, the openings 41 to 45 each perform the same function as the openings 41 to 45 of the semiconductor device A10.

[0078] Sixth Modification: Fig. 15 is a diagram for explaining a semiconductor device A16 according to a sixth modification of the first embodiment. Fig. 15 is a plan view showing the die pad portion 11 of the semiconductor device A16, and corresponds to Fig. 9. The semiconductor device A16 differs from the semiconductor device A10 in the configuration of the opening 4.

[0079] The opening 4 of the semiconductor device A13 according to this modification is such that the openings 41 to 45 do not each have a shape extending in the first direction x or the second direction y, but are an aggregate of a plurality of portions 4b. Each portion 4b has, for example, a circular shape as viewed in the thickness direction z, and is a recess recessed from the main surface 111 to the second side z2 in the thickness direction z. Note that the shape and size of each portion 4a as viewed in the thickness direction z are not limited. In this modification, the openings 41 to 45 each perform the same function as the openings 41 to 45 of the semiconductor device A10.

[0080] Seventh Modification: Fig. 16 is a diagram for explaining a semiconductor device A17 according to a seventh modification of the first embodiment. Fig. 16 is a plan view showing the die pad portion 11 of the semiconductor device A17, and corresponds to Fig. 9. The semiconductor device A17 differs from the semiconductor device A10 in the configuration of the opening 4.

[0081] In the semiconductor device A13 according to this modification, the end portion on the second side y2 in the second direction y of the opening 41 reaches the outer edge of the main surface 111. Similarly, the end portion on the second side y2 in the second direction y of the opening 43, the end portion on the first side x1 in the first direction x of the opening 42, the end portion on the first side x1 in the first direction x of the opening 44, and the end portion on the first side y1 in the second direction y of the opening 45 also reach the outer edge of the main surface 111. In this modification, the openings 41 to 45 each perform the same functions as the openings 41 to 45 of the semiconductor device A10.

[0082] Eighth Modification: Fig. 17 is a diagram for explaining a semiconductor device A18 according to an eighth modification of the first embodiment. Fig. 17 is a plan view showing the die pad portion 11 of the semiconductor device A18, and corresponds to Fig. 9. The semiconductor device A18 differs from the semiconductor device A10 in the configuration of the opening 4.

[0083] The opening 4 of the semiconductor device A18 according to this modification further includes an opening 46 and an opening 47. The opening 46 connects to the end of the opening 41 on the second side y2 in the second direction y and the end of the opening 43 on the second side y2 in the second direction y, and extends in the first direction x. The opening 47 connects to the end of the opening 42 on the first side x1 in the first direction x and the end of the opening 44 on the first side x1 in the first direction x, and extends in the second direction y. The opening 46 prevents peeling from progressing toward the first side y1 in the second direction y and toward the first region 51. The opening 47 also prevents peeling from progressing toward the second side x2 in the first direction x and toward the first region 51. Therefore, the semiconductor device A18 can further suppress peeling of the wire 73 from the die pad portion 11.

[0084] Ninth Modification: Fig. 18 is a diagram for explaining a semiconductor device A19 according to a ninth modification of the first embodiment. Fig. 18 is a plan view showing the die pad portion 11 of the semiconductor device A19, and is a diagram corresponding to Fig. 9. The semiconductor device A19 differs from the semiconductor device A10 in the configuration of the opening 4.

[0085] The opening 41 of the semiconductor device A19 according to this modification is disposed at the same position in the first direction x as the end of the opening 44 on the first side x1 in the first direction x. The opening 41 may be connected to the opening 44. The opening 42 is connected to the end of the opening 41 on the second side y2 in the second direction y and extends toward the second side x2 in the first direction x. The opening 42 may be connected to the opening 43. In this modification, the opening 41 also performs the same function as the opening 41 of the semiconductor device A10. Meanwhile, the opening 42 prevents peeling from progressing toward the first side y1 in the second direction y, thereby preventing peeling from progressing toward the first region 51. Therefore, the semiconductor device A19 can further suppress peeling of the wire 73 from the die pad portion 11.

[0086] 19 to 23 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

[0087] Second Embodiment: FIG. 19 is a diagram illustrating a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 19 is a cross-sectional view showing the semiconductor device A20, and corresponds to FIG. 5. The semiconductor device A20 of this embodiment differs from the first embodiment in that the opening 4 penetrates the die pad portion 11 in the thickness direction z. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first embodiment and the modifications described above may be combined in any desired manner. In this embodiment, all of the openings 41 to 45 of the opening 4 penetrate the die pad portion 11 in the thickness direction z.

[0088] In this embodiment, the openings 41 to 45 also function similarly to the openings 41 to 45 of the semiconductor device A10, by preventing the progress of peeling and preventing the outflow of the molten bonding material 65. As a result, the semiconductor device A20 can prevent the wires 73 from peeling off from the die pad portion 11 and can prevent the bonding material 65 from interfering with the bonding of the wires 73. Furthermore, the semiconductor device A20 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0089] Third Embodiment: FIG. 20 is a diagram illustrating a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 20 is a plan view showing the semiconductor device A30, and corresponds to FIG. 2. In FIG. 20, for ease of understanding, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. The semiconductor device A30 of this embodiment differs from the first embodiment in the shape of the leads 2. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first and second embodiments and their modified examples may be combined in any desired manner.

[0090] The lead 2 according to this embodiment has a larger dimension in the second direction y than the lead 2 according to the first embodiment, and includes 14 terminal portions 22. The semiconductor device A30 does not include the lead 3f, and the pad portion 21 extends in the second direction y to the position where the lead 3f was located in the first embodiment. In other words, the lead 2 according to this embodiment is obtained by connecting the lead 3f in the first embodiment to the lead 2. In this embodiment, the larger dimension of the pad portion 21 in the second direction y allows the multiple wires 74 to be joined to the second side y2 of the main surface 211 of the pad portion 21 in the second direction y.

[0091] In this embodiment, each wire 74 is inclined with respect to the first direction x when viewed in the thickness direction z, thereby suppressing wire sweep and preventing contact between the wires 74 in the semiconductor device A30 due to wire sweep. Also in this embodiment, each wire 74 is inclined in the same direction with respect to the first direction x, thereby causing the wires 74 to sweep in the same direction, thereby preventing contact between the wires 74 in the semiconductor device A30 due to wire sweep. Furthermore, in this embodiment, the bonded portion 74b of each wire 74 is bonded closer to the second side y2 in the second direction y of the main surface 211 of the pad portion 21, thereby increasing the inclination angle α of each wire 74 with respect to the first direction x compared to the first embodiment. This reduces the components that affect wire sweep, thereby further preventing wire sweep in the semiconductor device A30. Furthermore, by sharing a configuration with the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0092] First Modification: Fig. 21 is a diagram illustrating a semiconductor device A31 according to a first modification of the third embodiment. Fig. 21 is a plan view showing the semiconductor device A31, and corresponds to Fig. 2. In Fig. 21, for ease of understanding, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. Note that in Fig. 21, elements that are the same as or similar to those in the third embodiment are given the same reference numerals as those in the above embodiment, and redundant description will be omitted. The semiconductor device A31 differs from the semiconductor device A30 in the shape of the leads 2.

[0093] The lead 2 of the semiconductor device A31 according to this modification has a larger dimension in the second direction y than the lead 2 according to the third embodiment and includes 16 terminal portions 22. The semiconductor device A31 does not include the lead 3g, and the pad portion 21 extends in the second direction y to the position where the lead 3g was located in the third embodiment. In other words, the lead 2 according to this modification is a lead 2 in which the lead 3g in the third embodiment is connected to the lead 2. In this modification, the dimension of the pad portion 21 in the second direction y is further increased, and therefore, the multiple wires 74 are joined to the second side y2 in the second direction y of the main surface 211 of the pad portion 21. According to this modification, the inclination angle α of each wire 74 with respect to the first direction x is larger than in the third embodiment. This reduces the component that affects wire sweep, thereby further suppressing wire sweep in the semiconductor device A31.

[0094] Fourth Embodiment: FIG. 22 is a diagram illustrating a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 22 is a plan view showing the semiconductor device A40, and corresponds to FIG. 2. In FIG. 22, for ease of understanding, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. The semiconductor device A40 of this embodiment differs from the first embodiment in the configuration of the leads 1. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to third embodiments and their modifications may be combined in any desired manner.

[0095] The lead 1 according to this embodiment does not include the terminal portion 12a, the terminal portion 12b, and the terminal portion 12c. The semiconductor device A40 includes a lead 3c instead of the terminal portion 12a, a lead 3d instead of the terminal portion 12b, and a lead 3e instead of the terminal portion 12c. The leads 3c, 3d, and 3e have the same configuration as the other leads 3 and are spaced apart from the die pad portion 11. Each lead 3c is disposed on the second side y2 relative to the multiple leads 3a in the second direction y. In each lead 3c, the pad portion 31 extends to the second side x2 in the first direction x. Each lead 3d is disposed on the second side x2 relative to the multiple leads 3b in the first direction x. In each lead 3d, the pad portion 31 extends to the second side y2 in the second direction y. Each lead 3e is disposed on the second side x2 relative to the terminal portion 12e in the first direction x. In each lead 3e, the pad portion 31 extends to the first side y1 in the second direction y. The leads 3c, 3d, and 3e are so-called dummy leads.

[0096] In this embodiment, the semiconductor device A40 has the same configuration as the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.

[0097] Fifth Embodiment: FIG. 23 is a diagram illustrating a semiconductor device A50 according to a fifth embodiment of the present disclosure. FIG. 23 is a plan view of the semiconductor device A50, corresponding to FIG. 2. In FIG. 23, for ease of understanding, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. The semiconductor device A50 of this embodiment differs from the first embodiment in that all of the multiple wires 74 are parallel (or approximately parallel) to the first direction x when viewed in the thickness direction z. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to fourth embodiments and their modifications may be combined in any desired manner.

[0098] In this embodiment, in each wire 74, the bonding portion 74a bonded to the semiconductor element 62 and the bonding portion 74b bonded to the lead 2 are located at the same position in the second direction y. That is, all of the multiple wires 74 are parallel (or approximately parallel) to the first direction x when viewed in the thickness direction z.

[0099] According to this embodiment, each wire 74 is parallel (or substantially parallel) to the first direction x when viewed in the thickness direction z, and therefore the wire length can be shorter than when the wires are inclined with respect to the first direction x. This allows the semiconductor device A50 to suppress the resistance value of the wires 74. Furthermore, by sharing a configuration with the semiconductor device A10, the semiconductor device A50 achieves the same effects as the semiconductor device A10.

[0100] In the first to fifth embodiments, the semiconductor element 61 is located on the first side x1 in the first direction x with respect to the semiconductor element 62 and on the first side y1 in the second direction y with respect to the semiconductor element 62, and is disposed at a position offset from the center of the main surface 111 of the die pad portion 11 on the first side x1 in the first direction x toward the first side y1 in the second direction y. However, this is not limiting. For example, the semiconductor element 61 may be arranged side by side with the semiconductor element 62 in the first direction x and on the first side x1 with respect to the semiconductor element 62. In this case, the semiconductor element 61 is offset from the center of the main surface 111 of the die pad portion 11 to the first side x1 in the first direction x and is disposed at the center of the main surface 111 in the second direction y. In this case, the pad portion 31 of the lead 3b extends toward the element center 61c, which is the center of the semiconductor element 61, as viewed in the thickness direction z, and the pad portion 31 of the lead 3a is formed to extend toward the center of the main surface 111 of the die pad portion 11 as viewed in the thickness direction z. Furthermore, the semiconductor element 61 may be arranged alongside the semiconductor element 62 in the second direction y and on the first side y1 with respect to the semiconductor element 62. In this case, the semiconductor element 61 is shifted from the center of the main surface 111 of the die pad portion 11 to the first side y1 in the second direction y and is arranged at the center of the main surface 111 in the first direction x. In this case, the pad portion 31 of the lead 3a is formed to extend toward an element center 61c that is the center of the semiconductor element 61 as viewed in the thickness direction z, and the pad portion 31 of the lead 3b is formed to extend toward the center of the main surface 111 of the die pad portion 11 as viewed in the thickness direction z.

[0101] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.

[0102] Supplementary Note 1. A semiconductor device (A10) comprising: a first lead (1) having a die pad portion (11); a first semiconductor element (61) mounted on the die pad portion; and a plurality of second leads (3a) arranged on a first side (x1) of a first direction (x) orthogonal to a thickness direction (z) of the die pad portion, along a second direction (y) orthogonal to the thickness direction and the first direction, wherein the die pad portion has a die pad main surface (111) facing the first side (z1) in the thickness direction, an element center (61c) that is the center of the first semiconductor element as viewed in the thickness direction is positioned offset from the center of the die pad main surface in the second direction, and each of the plurality of second leads has a second pad portion (31) extending toward the first semiconductor element as viewed in the thickness direction. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the second pad portion extends toward the element center as viewed in the thickness direction. Supplementary Note 3. The semiconductor device according to Supplementary Note 1 or 2, wherein the element center is located on the first side in the second direction (y1) relative to the center of the die pad main surface in the second direction. Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein the first lead further includes a first terminal portion (12a) connected to the die pad portion and arranged on a second side in the second direction (y2) opposite to the first side in the second direction with respect to the plurality of second leads in the second direction. Supplementary Note 5. (Fourth embodiment, FIG. 22) The semiconductor device according to Supplementary Note 3, further including a third lead (3c) spaced apart from the die pad portion and arranged on a second side in the second direction opposite to the first side in the second direction with respect to the plurality of second leads in the second direction, the third lead extending in the first direction. Supplementary Note 6. The semiconductor device according to any one of Supplementary Notes 1 to 5, further comprising a plurality of fourth leads (3b) arranged along the first direction on a first side (y1) in the second direction of the die pad portion, the element center being positioned offset from the center in the first direction of the die pad main surface, and each of the plurality of fourth leads comprising a fourth pad portion (31) extending toward the first semiconductor element as viewed in the thickness direction.Supplementary Note 7. The semiconductor device according to Supplementary Note 6, wherein the fourth pad portion extends toward the element center as viewed in the thickness direction.Appendix 8. The semiconductor device according to Appendix 6 or 7, wherein the element center is located on the first side in the first direction relative to the center of the die pad main surface in the first direction. Appendix 9. The semiconductor device according to Appendix 8, wherein the first lead further includes a second terminal portion (12b) connected to the die pad portion and arranged on a second side in the first direction (x2) opposite to the first side in the first direction with respect to the plurality of fourth leads in the first direction. Appendix 10. (Fourth embodiment, FIG. 22) The semiconductor device according to Appendix 8, further including a fifth lead (3d) spaced apart from the die pad portion and arranged on a second side in the first direction opposite to the first side in the first direction with respect to the plurality of fourth leads in the first direction, wherein the fifth lead extends in the second direction. Appendix 11. The semiconductor device according to any one of Supplementary Notes 6 to 10, further comprising a second semiconductor element (62) mounted on the die pad main surface, the second semiconductor element being disposed on the opposite side of the first semiconductor element from the plurality of second leads in the first direction and on the opposite side of the first semiconductor element from the plurality of fourth leads in the second direction, the second semiconductor element being a switching element, and the first semiconductor element being a driving element that drives the second semiconductor element. (Fig. 9) The semiconductor device according to Supplementary Note 11, further comprising a wire (73) conductively bonded to the second semiconductor element and the die pad main surface, the die pad main surface being located on a first side in the first direction of the second semiconductor element and comprising a first region (51) to which the wire is bonded, a second region (52) in which the second semiconductor element is mounted, and a third region (53) in which the first semiconductor element is mounted, the die pad portion having an open end in the die pad main surface and comprising an opening (4) that partitions the first region, the second region, and the third region. Supplementary Note 13. The semiconductor device according to Supplementary Note 12, wherein the opening is a recess recessed from the die pad main surface. Supplementary Note 14. The semiconductor device according to any of Supplementary Notes 11 to 13, wherein the second semiconductor element includes GaN.

[0103] A10 to A20, A30, A31, A40, A50: semiconductor device 1: lead 11: die pad portion 111: main surface 111a: edge 51: first region 52: second region 53: third region 112: back surface 113: back surface recess 4, 41 to 47: openings 4a, 4b: parts 12, 12a, 12b, 12c, 12d, 12e: terminal portion 121: main surface 122: back surface 123: end surface 2: lead 21: pad portion 211: main surface 211a: bonding region 211b: non-bonding region 212: back surface 213: through hole 22: terminal portion 221: main surface 222: back surface 223: end surface 3, 3a, 3b, 3c, 3d, 3e, 3f, 3g: Leads 31: Pad portion 311: Main surface 312: Back surface 32: Terminal portion 321: Main surface 322: Back surface 323: End surface 61: Semiconductor element 61a: Element main surface 61b: Element back surface 61c: Element center 611: Electrode 62: Semiconductor element 62a: Element main surface 62b: Element back surface 621: First electrode 622: Second electrode 623: Third electrode 65: Bonding member 7, 71 to 74: Wires 74a, 74b: Bonding portion 8: Sealing resin 81: Resin main surface 82: Resin back surface 83: Resin side surface 831: First resin side surface 832: Second resin side surface 833: Third resin side surface 834: Fourth resin side surface

Claims

1. a first lead having a die pad portion; a first semiconductor element mounted on the die pad portion; a plurality of second leads arranged on a first side in a first direction perpendicular to a thickness direction of the die pad portion, the second leads being arranged along a second direction perpendicular to the thickness direction and the first direction; Equipped with the die pad portion includes a die pad main surface facing a first side in the thickness direction, an element center that is a center of the first semiconductor element as viewed in the thickness direction is shifted from a center in the second direction of the main surface of the die pad, A semiconductor device, wherein each of the plurality of second leads has a second pad portion extending toward the first semiconductor element when viewed in the thickness direction.

2. The semiconductor device according to claim 1 , wherein the second pad portion extends toward a center of the element when viewed in the thickness direction.

3. 2 . The semiconductor device according to claim 1 , wherein the element center is located on a first side in the second direction from a center in the second direction of the main surface of the die pad.

4. 4. The semiconductor device according to claim 3, wherein the first lead further includes a first terminal portion connected to the die pad portion and arranged on a second side in the second direction opposite the first side in the second direction relative to the plurality of second leads in the second direction.

5. a third lead spaced apart from the die pad portion and disposed on a second side in the second direction opposite to the first side in the second direction with respect to the second leads in the second direction, The semiconductor device according to claim 3 , wherein the third lead extends in the first direction.

6. a plurality of fourth leads arranged along the first direction on a first side in the second direction of the die pad portion, the element center is positioned offset from the center of the die pad main surface in the first direction, The semiconductor device according to claim 1 , wherein each of the plurality of fourth leads includes a fourth pad portion extending toward the first semiconductor element when viewed in the thickness direction.

7. The semiconductor device according to claim 6 , wherein the fourth pad portion extends toward a center of the element when viewed in the thickness direction.

8. The semiconductor device according to claim 6 , wherein the element center is located on a first side in the first direction with respect to a center in the first direction of the main surface of the die pad.

9. 9. The semiconductor device according to claim 8, wherein the first lead further includes a second terminal portion connected to the die pad portion and arranged on a second side in the first direction opposite the first side in the first direction relative to the plurality of fourth leads in the first direction.

10. a fifth lead that is spaced apart from the die pad portion and that is disposed on a second side in the first direction opposite to a first side in the first direction with respect to the plurality of fourth leads in the first direction, The semiconductor device according to claim 8 , wherein the fifth lead extends in the second direction.

11. Further comprising a second semiconductor element mounted on the main surface of the die pad, the second semiconductor element is disposed on an opposite side of the first semiconductor element from the second leads in the first direction and on an opposite side of the first semiconductor element from the fourth leads in the second direction; the second semiconductor element is a switching element, 11. The semiconductor device according to claim 6, wherein the first semiconductor element is a drive element that drives the second semiconductor element.

12. The second semiconductor element further includes a wire electrically connected to the main surface of the die pad. the die pad main surface is located on a first side in the first direction of the second semiconductor element, and includes a first region to which the wire is bonded, a second region in which the second semiconductor element is mounted, and a third region in which the first semiconductor element is mounted, 12 . The semiconductor device according to claim 11 , wherein the die pad portion has an opening end on the die pad main surface, and is provided with an opening that divides the first region, the second region, and the third region.

13. The semiconductor device according to claim 12 , wherein the opening is a recess recessed from a main surface of the die pad.

14. The semiconductor device according to claim 11 , wherein the second semiconductor element includes GaN.