Laminated ceramic capacitor

JPWO2024202667A5Pending Publication Date: 2025-10-31
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Patent Information

Application Number
JP2025509906
Authority / Receiving Office
JP · JP
Patent Type
Applications
Filing Date
2025-08-19
Publication Date
2025-10-31

AI Technical Summary

Technical Problem

Conventional multilayer ceramic capacitors have high manufacturing costs and uneven cohesive force within the conductive resin layer due to a random spatial distribution of voids, leading to decreased mechanical strength.

Method used

A multilayer ceramic capacitor design featuring a conductive resin layer with a flat metal filler and strategically arranged voids on its surface, which reduces the fracture strength of the resin electrode and preferentially absorbs mechanical and thermal stress, thereby enhancing the mechanical strength by controlling crack growth and preventing dielectric layer destruction.

Benefits of technology

The design increases the mechanical strength of the multilayer ceramic capacitor by ensuring the resin electrode layer fails before the dielectric layer, thus improving durability and reliability.

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Abstract

Provided is a laminated ceramic capacitor having high mechanical strength. This laminated ceramic capacitor 1 comprises: a laminated body 2 including a plurality of dielectric layers 5 that are laminated; a first internal electrode layer 6a disposed above the plurality of dielectric layers 5 and exposed at a first end surface E1; a second internal electrode layer 6b disposed above the plurality of dielectric layers 5 and exposed at a second end surface E2; a first external electrode 20a disposed above the first end surface E1; and a second external electrode 20b disposed above the second end surface E2. The first external electrode 20a and the second external electrode 20b include: an underlying electrode layer 21 containing a metal component; a conductive resin layer 22 disposed above the underlying electrode layer 21 and containing a thermosetting resin 38 and a metal filler 30; and a plating layer disposed above the conductive resin layer 22. The metal filler 30 of the conductive resin layer 22 is a flat filler having a flat shape. A void 40 is provided on the surface of the flat filler.
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Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] The external electrodes of conventional multilayer ceramic capacitors are configured with a copper substrate external electrode, a resin external electrode, a Ni-plated layer, and a Sn-plated layer. Patent Document 1 describes a resin external electrode having a three-layer structure in the thickness direction. The first layer is the layer on the copper substrate side, the second layer is the middle layer, and the third layer is the layer on the plating side. The void volume of the first and second layers is described. The void volume of the first layer is 10% or less, and the void volume of the second layer is 16% or more. However, there is no description of the spatial distribution of voids within the resin electrode layer.

[0003] Japanese Patent Application Laid-Open No. 2020-88190

[0004] The multilayer ceramic capacitor of Patent Document 1 has the following problems. The conductive resin layer has a three-layer structure, which increases manufacturing costs. In addition, the spatial distribution of voids in the conductive resin layer is random, which causes uneven cohesion within the conductive resin layer. This uneven cohesion within the conductive resin layer causes a decrease in the mechanical strength of the multilayer ceramic capacitor.

[0005] SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a multilayer ceramic electronic component, particularly a multilayer ceramic capacitor having high mechanical strength.

[0006] The multilayer ceramic capacitor of the present invention includes a laminate including a plurality of stacked dielectric layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces; a first external electrode arranged on the first end surfaces; and a second external electrode arranged on the second end surfaces, wherein the first external electrode and the second external electrode have a base electrode layer containing a metal component, a conductive resin layer including a thermosetting resin and a metal filler arranged on the base electrode layer, and a plating layer arranged on the conductive resin layer, the metal filler in the conductive resin layer being a flat filler, and voids are arranged in the surface of the flat filler.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor having high mechanical strength.

[0008] 4 is a perspective view of the multilayer ceramic capacitor of the present embodiment, a cross-sectional view taken along line II in FIG. 1, a cross-sectional view taken along line II-II in FIG. 1, an enlarged view of a frame R1 in FIG. 2, and an enlarged view of a frame R2 in FIG.

[0009] An embodiment of the invention will be described with reference to FIG. 1. FIG. 1 is a perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present invention. (Laminate) The laminate 2 includes a plurality of laminated dielectric layers and a plurality of internal electrode layers. The shape of the laminate 2 is approximately a rectangular parallelepiped. In the laminate 2, the direction in which the dielectric layers and internal electrode layers are laminated is defined as the height direction T. The direction perpendicular to the height direction T is defined as the width direction W. The direction perpendicular to the height direction T and the width direction W is defined as the length direction L.

[0010] Of the two surfaces of the laminate 2 that face each other in the height direction T, one surface is designated as the first main surface M1. The remaining surface is designated as the second main surface M2. Of the two surfaces of the laminate 2 that face each other in the width direction W, one surface is designated as the first side surface S1. The remaining surface is designated as the second side surface. Of the two surfaces of the laminate 2 that face each other in the length direction L, one surface is designated as the first end surface E1. The remaining surface is designated as the second end surface E2. The mounting surface of the multilayer ceramic capacitor 1 is the second main surface M2. The mounting surface refers to the surface that faces a wiring board or the like when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0011] Regarding the cross section of the laminate 2, the cross section taken along line II in Fig. 1 is defined as the LT cross section, and the cross section taken along line II-II in Fig. 1 is defined as the WT cross section.

[0012] The intersections of three surfaces of the laminate 2 are defined as corners of the laminate 2, and the intersections of two surfaces of the laminate 2 are defined as ridges of the laminate 2. The corners and ridges are preferably rounded.

[0013] (Dielectric Layers) The total number of dielectric layers stacked in the laminate 2 is preferably 15 or more and 2000 or less. The main material of the dielectric layers is a ceramic material. Examples of ceramic materials are dielectric ceramics containing barium titanate, calcium titanate, strontium titanate, calcium zirconate, or the like as main components. The ceramic material may also be a dielectric ceramic in which a secondary component such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, or a nickel compound is added to these main components.

[0014] The thickness of each dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0015] (Division of Laminate) The division of the laminate 2 in the length direction L will be described with reference to Figure 2. Figure 2 is a cross-sectional view taken along line II in Figure 1. The laminate 2 can be divided into a first main surface side outer layer portion OL1, an inner layer area IL, and a second main surface side outer layer portion OL2 in the height direction T. The first main surface side outer layer portion OL1, the inner layer area IL, and the second main surface side outer layer portion OL2 are arranged in this order in the height direction T from the first main surface M1 to the second main surface M2.

[0016] The first outer layer portion OL1 is a portion between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The internal layer range IL is a range where internal electrode layers face each other. The second outer layer portion OL2 is a portion between the second main surface M2 and the internal electrode layer closest to the second main surface M2.

[0017] The first main surface side outer layer portion OL1 is located on the first main surface M1 side of the laminate 2. The first main surface side outer layer portion OL1 is formed by an assembly of multiple dielectric layers located between the first main surface M1 and the internal electrode layer closest to the first main surface M1. The first main surface side outer layer portion OL1 is formed by multiple dielectric layers located between the first main surface M1 and the outermost surface of the inner layer range IL on the first main surface M1 side and an extension of that outermost surface.

[0018] The second main surface side outer layer portion OL2 is located on the second main surface M2 side of the laminate 2. The second main surface side outer layer portion OL2 is formed by an assembly of multiple dielectric layers located between the second main surface M2 and the internal electrode layer closest to the second main surface M2. The second main surface side outer layer portion OL2 is formed by multiple dielectric layers located between the second main surface M2 and the outermost surface of the inner layer range IL on the second main surface M2 side and an extension of that outermost surface.

[0019] The inner layer area IL is an area sandwiched between the first outer layer portion OL1 on the main surface side and the second outer layer portion OL2 on the main surface side.

[0020] Of the dielectric layers, the dielectric layers arranged in the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2 are referred to as outer dielectric layers 3. Of the dielectric layers, the dielectric layers arranged in the inner layer range IL are referred to as inner dielectric layers 4.

[0021] The following terms may be used in describing lengths and positions:

[0022] The length in the length direction L is defined as the length direction length, the length in the width direction W is defined as the width direction length, and the length in the height direction T is defined as the height direction length.

[0023] The position that is half the length in the longitudinal direction is defined as the center position in the longitudinal direction L. The center position in the longitudinal direction L is defined as the longitudinal center position.

[0024] The position that is half the length in the width direction is defined as the center position in the width direction W. The center position in the width direction W is defined as the width direction center position.

[0025] The position that is half the length in the height direction is defined as the center position in the height direction T. The center position in the height direction T is defined as the height direction center position.

[0026] The ends in the length direction L are defined as length-direction ends, the ends in the width direction W are defined as width-direction ends, and the ends in the height direction T are defined as height-direction ends.

[0027] The size of the laminate 2 is not particularly limited. The length of the laminate in the longitudinal direction is preferably 0.2 mm or more and 10 mm or less. The length of the laminate 2 in the width direction is preferably 0.1 mm or more and 5 mm or less. The length of the laminate 2 in the height direction is preferably 0.1 mm or more and 5 mm or less.

[0028] (L Gap) The division of the laminate 2 in the longitudinal direction L will be described. The laminate 2 can be divided into a first end surface side outer layer portion LG1, a longitudinally facing portion LF, and a second end surface side outer layer portion LG2 in the longitudinal direction L. The first end surface side outer layer portion LG1, the longitudinally facing portion LF, and the second end surface side outer layer portion LG2 are arranged in this order in the longitudinal direction L from the first end surface E1 to the second end surface E2.

[0029] The longitudinal facing portion LF is a portion where the internal electrode layers face each other in the height direction T. The first end face side outer layer portion LG1 is a portion between the longitudinal facing portion LF and the first end face E1. The second end face side outer layer portion LG2 is a portion between the longitudinal facing portion LF and the second end face E2. The longitudinal facing portion LF is a portion corresponding to the facing electrode portion of the internal electrode layer. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are portions corresponding to the lead electrode portions of the internal electrode layer. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are also referred to as L gaps.

[0030] The counter electrode portion includes a first counter electrode portion 7 a and a second counter electrode portion 7 b. The lead-out electrode portion includes a first lead-out electrode portion 8 a and a second lead-out electrode portion 8 b. The counter electrode portion and the lead-out electrode portion will be described later.

[0031] The first end face side outer layer portion LG1 is located on the first end face E1 side, between the first end face E1 and the end of the second internal electrode layer 6b on the first end face E1 side.

[0032] The second end face side outer layer portion LG2 is located on the second end face E2 side, between the second end face E2 and the end of the first internal electrode layer 6 a on the second end face E2 side.

[0033] (W Gap) The division of the laminate 2 in the width direction W will be described with reference to Figure 3. Figure 3 is a cross-sectional view taken along line II-II in Figure 1. The laminate 2 can be divided into a first side surface outer layer portion WG1, a widthwise opposing portion WF, and a second side surface outer layer portion WG2 in the width direction W. The first side surface outer layer portion WG1, the widthwise opposing portion WF, and the second side surface outer layer portion WG2 are arranged in this order in the width direction W from the first side surface S1 to the second side surface S2.

[0034] The widthwise facing portion WF is a portion where internal electrode layers face each other in the height direction T. The first side surface side outer layer portion WG1 is a portion between the widthwise facing portion WF and the first side surface S1. The second side surface side outer layer portion WG2 is a portion between the widthwise facing portion WF and the second side surface S2. The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are also referred to as W gaps.

[0035] The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are portions where no internal electrode layers exist in the height direction T. The first side surface side outer layer portion WG1 is located on the first side surface S1 side. The first side surface side outer layer portion WG1 is formed by a plurality of dielectric layers located between the first side surface S1 and the outermost surface of the widthwise opposing portion WF on the first side surface S1 side.

[0036] The second side surface outer layer portion WG2 is located on the second side surface S2 side and is formed of a plurality of dielectric layers located between the second side surface S2 and the outermost surface of the widthwise facing portion WF on the second side surface S2 side.

[0037] (Internal Electrode Layers) The internal electrode layers include a plurality of first internal electrode layers 6 a and a plurality of second internal electrode layers 6 b. The first internal electrode layers 6 a are internal electrode layers exposed at the first end face E1. The second internal electrode layers 6 b are internal electrode layers exposed at the second end face E2.

[0038] The first internal electrode layer 6a can be divided into a first opposing electrode portion 7a and a first lead electrode portion 8a. The first opposing electrode portion 7a is a portion facing the second internal electrode layer 6b. The first lead electrode portion 8a is a portion led from the first opposing electrode portion 7a to the first end face E1 of the laminate 2.

[0039] The end of the first extension electrode 8a on the first end face E1 side is extended to the surface of the first end face E1 of the laminate 2. The end of the first extension electrode 8a extended to the first end face E1 forms an exposed portion at the first end face E1.

[0040] The second internal electrode layer 6b can be divided into a second opposing electrode portion 7b and a second lead electrode portion 8b. The second opposing electrode portion 7b is a portion facing the first internal electrode layer 6a. The second lead electrode portion 8b is a portion led from the second opposing electrode portion 7b to the second end face E2 of the laminate 2.

[0041] The end of the second extraction electrode 8b on the second end face E2 side is extracted to the surface of the second end face E2 of the laminate 2. The end of the second extraction electrode 8b extracted to the second end face E2 forms an exposed portion at the second end face E2.

[0042] The shapes of the first opposing electrode portion 7a and the second opposing electrode portion 7b are not particularly limited. The shapes of the first opposing electrode portion 7a and the second opposing electrode portion 7b are preferably rectangular. The corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may be rounded. The corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may be formed obliquely. Forming the corners obliquely means forming them in a tapered shape.

[0043] The shapes of the first extension electrode 8a and the second extension electrode 8b are not particularly limited. The shapes of the first extension electrode 8a and the second extension electrode 8b are preferably rectangular. The corners of the first extension electrode 8a and the second extension electrode 8b may be rounded. The corners of the first extension electrode 8a and the second extension electrode 8b may be formed obliquely. Forming the corners obliquely means forming them in a tapered shape.

[0044] The width of the first opposing electrode portion 7 a and the width of the first extension electrode portion 8 a may be the same, but either the width of the first opposing electrode portion 7 a or the width of the first extension electrode portion 8 a may be narrower than the remaining width.

[0045] The width of the second opposing electrode portion 7 b and the width of the second extension electrode portion 8 b may be the same, but either the width of the second opposing electrode portion 7 b or the width of the second extension electrode portion 8 b may be narrower than the remaining width.

[0046] The material of the first internal electrode layer 6a and the second internal electrode layer 6b can be, for example, a metal such as nickel, copper, silver, palladium, gold, etc. The material of the first internal electrode layer 6a and the second internal electrode layer 6b can be an alloy containing at least one of the above-mentioned metals, such as a silver-palladium alloy.

[0047] In the multilayer ceramic capacitor 1, capacitance is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b facing each other via the inner dielectric layer 4. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0048] The thickness of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 6a and the second internal electrode layers 6b is preferably 15 or more and 2000 or less.

[0049] (Inner layer portion) The portion where the first internal electrode layer 6a and the second internal electrode layer 6b face each other is referred to as the inner layer portion 10. The inner layer portion 10 is the portion where the lengthwise facing portion LF shown in FIG. 2 and the widthwise facing portion WF shown in FIG. 3 intersect with the inner layer range IL. The shape of the inner layer portion 10 is approximately a rectangular parallelepiped. In FIG. 2, the portion where the lengthwise facing portion LF and the inner layer range IL intersect is shown as the inner layer portion 10. In addition, in FIG. 3, the portion where the widthwise facing portion WF and the inner layer range IL intersect is shown as the inner layer portion 10.

[0050] (External Electrodes) The external electrodes will now be described. The external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is an external electrode connected to the first internal electrode layer 6a. The first external electrode 20a is disposed on the first end face E1, part of the first main surface M1, part of the second main surface M2, part of the first side surface S1, and part of the second side surface S2.

[0051] The second external electrode 20b is an external electrode connected to the second internal electrode layer 6b, and is arranged on the second end face E2, part of the first main surface M1, part of the second main surface M2, part of the first side surface S1, and part of the second side surface S2.

[0052] The external electrodes preferably include a base electrode layer, a conductive resin layer, and a plating layer. The plating layer preferably includes a Ni plating layer and a Sn plating layer. Hereinafter, an external electrode including a base electrode layer, a conductive resin layer, a Ni plating layer, and a Sn plating layer will be described.

[0053] (Base Electrode Layer) The base electrode layer includes a first base electrode layer 21a and a second base electrode layer 21b. The first base electrode layer 21a is disposed on the first end face E1, part of the first main surface M1, part of the second main surface M2, part of the first side surface S1, and part of the second side surface S2. The second base electrode layer 21b is disposed on the second end face E2, part of the first main surface M1, part of the second main surface M2, part of the first side surface S1, and part of the second side surface S2.

[0054] The base electrode layer includes a conductive metal and a glass component. The conductive metal is at least one of copper, nickel, silver, palladium, a silver-palladium alloy, gold, etc. The glass component is at least one of boron, silicon, barium, manganese, aluminum, lithium, etc.

[0055] The base electrode layer may be formed in a plurality of layers. The base electrode layer can be formed by applying a conductive paste containing a glass component and a metal to the laminate and then firing the laminate. The firing of the base electrode layer can be performed simultaneously with the firing of the internal electrode layer. Alternatively, the firing of the base electrode layer can be performed separately after the firing of the internal electrode layer.

[0056] When the base electrode layer is fired simultaneously with the internal electrode layer, it is preferable to add a dielectric material to the conductive paste instead of the glass component, thereby improving the adhesion between the base electrode layer and the laminate 2.

[0057] The thickness of the base electrode layer located on the first end face E1 or the first end face E2 at the center position in the height direction is preferably 10 μm or more and 150 μm or less.

[0058] When the base electrode layer is provided on the first main surface M1, the second main surface M2, the first side surface S1, and the second side surface S2, it is preferable that the thickness of the base electrode layer at the center position in the longitudinal direction on the first main surface M1, the second main surface M2, the first side surface S1, and the second side surface S2 is 5 μm or more and 50 μm or less.

[0059] The base electrode layer may also be a thin film layer. When the base electrode layer is a thin film layer, the thin film layer may be formed by a thin film formation method such as a sputtering method or a vapor deposition method. The formed thin film layer is a layer in which metal particles are deposited. The thickness of the thin film layer is preferably 1 μm or less.

[0060] (Conductive Resin Layer) A conductive resin layer is disposed on the base electrode layer. The conductive resin layer contains a resin component and a metal component. The conductive resin layer includes a first conductive resin layer 22 a and a second conductive resin layer 22 b.

[0061] The first conductive resin layer 22a is disposed on the first base electrode layer 21a. The first conductive resin layer 22a covers the first base electrode layer 21a. The second conductive resin layer 22b is disposed on the second base electrode layer 21b. The second conductive resin layer 22b covers the second base electrode layer 21b. It is preferable that the ends of the conductive resin layers are in contact with the laminate 2.

[0062] The conductive resin layer contains a thermosetting resin, and by containing the thermosetting resin, the conductive resin layer is more flexible than the underlying electrode layer.

[0063] The conductive resin layer functions as a buffer layer, so that when a bending stress is applied to the mounting substrate and this stress applies a physical impact to the multilayer ceramic capacitor 1, cracks are unlikely to occur in the multilayer ceramic capacitor 1. When an impact due to a thermal cycle is applied to the multilayer ceramic capacitor 1, cracks are unlikely to occur in the multilayer ceramic capacitor 1.

[0064] The thermosetting resin contained in the conductive resin layer can be a thermosetting resin such as an epoxy resin, a phenolic resin, a urethane resin, a silicone resin, or a polyimide resin. Among these resins, an epoxy resin is one of the most suitable resins. Epoxy resins have excellent heat resistance, moisture resistance, and adhesion. Alternatively, multiple types of resins, such as an epoxy resin and a phenolic resin, may be used.

[0065] The conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the thermosetting resin, the curing agent may be a phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, amide-imide-based compound, or the like.

[0066] As described above, the conductive resin layer contains a metal component. The inclusion of the metal component in the conductive resin layer makes the conductive resin layer conductive. The metal component contained in the conductive resin layer is contained in the conductive resin layer as metal powder, i.e., metal filler. Contact between metal fillers forms a conductive path inside the conductive resin layer. The formed conductive path makes the conductive resin layer conductive. The metal component will be explained later.

[0067] The thickness of the conductive resin layer 22 located on the first end face E1 or the second end face E2 at the center position in the height direction is preferably 10 μm or more and 200 μm or less.

[0068] When the conductive resin layer is provided on the first main surface M1, the second main surface M2, the first side surface S1, and the second side surface S2, it is preferable that the thickness of the conductive resin layer at the center position in the longitudinal direction on the first main surface M1, the second main surface M2, the first side surface S1, and the second side surface S2 is 10 μm or more and 200 μm or less.

[0069] (Plating Layer) The plating layer will be described. The plating layer includes a Ni plating layer and a Sn plating layer.

[0070] (Ni plating layer) The Ni plating layer is disposed on the conductive resin layer. The Ni plating layer covers at least a portion of the conductive resin layer. The Ni plating layer includes a first Ni plating layer 23a and a second Ni plating layer 23b. The first Ni plating layer 23a is disposed on the first conductive resin layer 22a. The second Ni plating layer 23b is disposed on the second conductive resin layer 22b.

[0071] The Ni plating layer prevents the underlying electrode layer and the like from being eroded by solder when the multilayer ceramic capacitor 1 is mounted.

[0072] (Sn plating layer) The Sn plating layer is disposed on the Ni plating layer. The Sn plating layer covers at least a portion of the Ni plating layer. The Sn plating layer includes a first Sn plating layer 24a and a second Sn plating layer 24b. The first Sn plating layer 24a is disposed on the first Ni plating layer 23a. The second Sn plating layer 24b is disposed on the second Ni plating layer 23b.

[0073] The Sn plating layer has good solder wettability, which makes it easy to mount the multilayer ceramic capacitor 1 on a substrate or the like.

[0074] The thickness of each of the Ni plating layer and the Sn plating layer is preferably 2 μm or more and 15 μm or less.

[0075] The size of the multilayer ceramic capacitor 1 is not particularly limited. The length in the longitudinal direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.2 mm or more and 10 mm or less. The length in the height direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.1 mm or more and 5 mm or less. The length in the width direction of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes is preferably 0.1 mm or more and 10 mm or less.

[0076] (Metal Component) The metal component contained in the conductive resin layer will be described below. The conductive resin layer contains a metal component to impart conductivity to the conductive resin layer.

[0077] The metal component contained in the conductive resin layer may be silver, copper, nickel, tin, bismuth, or an alloy containing any of these. The metal component preferably contains silver. The silver may be elemental silver. Alternatively, the silver may be an alloy containing silver. For example, the metal component may be at least one of silver, silver-coated copper, and silver-coated alloy powder.

[0078] As described above, the metal component is contained in the conductive resin layer as a metal filler. Fig. 4 is an enlarged view of the framed area R1 in Fig. 2. Fig. 5 is an enlarged view of the framed area R2 in Fig. 4. The following description will be given using the second conductive resin layer 22b as an example of the conductive resin layer. However, the following description also applies to the first conductive resin layer 22a.

[0079] 4, the second conductive resin layer 22b is provided with metal filler particles 30. A plurality of metal filler particles 30 are dispersed in the resin 38.

[0080] The metal filler particles 30 contained in the conductive resin layer have a flat shape. Hereinafter, the flat metal filler particles 30 may be referred to as flat filler particles 30.

[0081] Furthermore, voids 40 are arranged on the surface of the metal filler 30 .

[0082] In the multilayer ceramic capacitor 1 of this embodiment, the mechanical strength of the multilayer ceramic capacitor 1 can be improved. When breakdown occurs inside the conductive resin layer at the interface between the flat filler 30 and the resin 38, the uniform presence of voids 40 between the flat filler 30 and the resin 38 reduces the breakdown strength of the entire resin electrode. As a result, when thermal stress or mechanical stress is applied to the multilayer ceramic capacitor 1, the resin electrode layer breaks down preferentially over the dielectric layer of the laminate 2, preventing breakdown of the dielectric layer. As a result, the mechanical strength of the multilayer ceramic capacitor 1 can be increased. These points will be described in order below.

[0083] In the multilayer ceramic capacitor 1 of this embodiment, the conductive resin layer contains flat fillers as the metal fillers 30. The flat fillers refer to metal fillers 30 having the following shapes.

[0084] The flatness is defined as follows: Metal filler particles 30 having a flatness of 4 or more are considered to be flat filler particles 30 .

[0085] Flatness = a / b Direction A: The direction in which the metal filler 30 has the longest length. Longitudinal direction of the metal filler 30. Midpoint M: The midpoint of the metal filler 30 in direction A. Length a: The longest length of the metal filler 30 in the same direction as direction A at midpoint M. Length b: The shortest length of the metal filler 30 in the direction perpendicular to direction A at midpoint M.

[0086] As shown in Figures 4 and 5, voids 40 are arranged on the surface of the flat filler 30. In other words, the voids 40 are arranged around the flat filler 30. The flat filler 30 is oriented in a direction closer to horizontal than perpendicular to the plane of the element body. The element body refers to the laminate 2. The plane here refers to the second main surface M2 or the second end face E2. Oriented refers to the direction A of the flat filler 30 facing a predetermined direction. The flat filler 30 is oriented in the second conductive resin layer 22b on the second main surface M2 so as to extend in a direction approximately parallel to the longitudinal direction L of the laminate 2.

[0087] A line CL shown in FIG. 4 indicates the direction in which a crack propagates when an external stress is applied to the multilayer ceramic capacitor 1.

[0088] As shown in Fig. 4, the flat filler particles 30 extend in a direction substantially parallel to the longitudinal direction L. Furthermore, as shown in Fig. 5, the voids 40 arranged on the surface of the flat filler particles 30 are arranged along at least a portion of the outer periphery 42 of the flat filler particles 30. In particular, the voids 40 are arranged in a portion of the outer periphery 42 of the flat filler particles 30 that is substantially parallel to the longitudinal direction L.

[0089] By arranging the voids 40 in the flat filler 30 as described above, it is possible to control the propagation of cracks in the conductive resin layer when external stress is applied to the multilayer ceramic capacitor 1. Controlling the propagation of cracks means adjusting the degree of crack propagation. The degree of crack propagation is adjusted so that the external stress is alleviated by the cracks, making it difficult for the external stress to be applied to the dielectric layer. As a result, it is possible to prevent cracks that occur in the resin electrode layer from propagating into the dielectric layer.

[0090] Furthermore, it is preferable that the voids 40 arranged on the outer periphery 42 of the flat filler 30 are arranged within a length range of 5% or more and 90% or less of the circumferential length of the outer periphery 42 of the flat filler 30 observed in the LT cross section.

[0091] The following description will be given with reference to the drawings. In Fig. 5, the range D indicates the range in which the voids 40 are arranged on the outer periphery 42 of the flat filler 30. It is preferable that the length of the outer periphery 42 of the flat filler 30 included in range D is 5% to 90% of the total circumferential length of the outer periphery 42 of the flat filler 30.

[0092] By arranging the voids 40 as described above, it is possible to further prevent cracks occurring in the resin electrode layer from progressing into the dielectric layer.

[0093] Furthermore, a plurality of flat fillers 30 are arranged in the resin electrode layer, and within a predetermined range in the LT cross section, the proportion of metal fillers 30 in which voids 40 are arranged within a range of 5% to 90% of the circumferential length of the outer periphery 42 of the flat filler 30 is preferably 60% or more relative to the total number of flat fillers 30. Here, the predetermined range can be, for example, a rectangular range of 20 μm × 10 μm.

[0094] Furthermore, it is preferable that within a predetermined range in the LT cross section, the proportion of metal filler particles 30 having an inclination of 45° or less with respect to the direction parallel to the length direction L of the laminate 2 accounts for 50% or more of the total number of flat filler particles 30. As described above, the predetermined range can be, for example, a rectangular range of 20 μm × 10 μm.

[0095] The following description will be given based on the drawings. In Fig. 5, the angle of inclination of the flat filler 30 with respect to a direction parallel to the length direction L of the laminate 2 is indicated by angle A. Angle A is the angle between line L1 and line L2. Line L1 is a line indicating a direction parallel to the length direction L. Line L2 indicates the longitudinal direction of the flat filler 30.

[0096] It is preferable that the ratio of the flat filler particles 30 having an angle A of 45° or less is 50% or more.

[0097] By arranging the voids 40 as described above, it is possible to further prevent cracks occurring in the resin electrode layer from progressing into the dielectric layer.

[0098] In the multilayer ceramic capacitor 1 of this embodiment, as described above, the voids 40 are disposed on the surfaces of the flat filler 30, thereby enabling the voids 40 to be uniformly disposed between the metal filler 30 and the resin. This reduces the fracture strength of the entire resin electrode, and when thermal stress or mechanical stress is applied to the multilayer ceramic capacitor 1, the resin electrode layer fractures preferentially over the dielectric layer. As a result, fracture of the dielectric layer can be avoided, and the mechanical strength of the multilayer ceramic capacitor 1 can be improved.

[0099] The average particle size of the metal filler 30 is not particularly limited. The average particle size of the metal filler 30 can be, for example, 0.3 μm or more and 10 μm or less. The average particle size of the metal filler contained in the conductive resin layer can be calculated by a laser diffraction particle size measurement method (based on IOS 13320).

[0100] The amount of resin contained in the conductive resin layer is preferably 25 vmol% or more and 65 vmol% or less with respect to the total volume of the conductive resin layer.

[0101] The amount of the metal component contained in the conductive resin layer is preferably 35 vmol% or more and 75 vmol% or less with respect to the total volume of the conductive resin layer.

[0102] (Evaluation of Characteristics) Mechanical strength and other properties were evaluated as follows. The conditions of the multilayer ceramic capacitor used for the evaluation were as follows: The size of the multilayer ceramic capacitor was 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height. The capacitance of the multilayer ceramic capacitor was 0.010 μF. The rated voltage of the multilayer ceramic capacitor was 50 V.

[0103] The evaluation method and criteria for mechanical strength are as follows. Mechanical strength was evaluated based on the resistance to cracking. To evaluate mechanical strength, 10 completed multilayer ceramic capacitors were subjected to a deflection test according to the method of JIS C 6484, and the presence or absence of cracking in the dielectric layers was evaluated when the deflection amount was fixed at 5 mm. No cracks occurred in the multilayer ceramic capacitor 1 of this embodiment.

[0104] (Method of Measurement and Observation) The LT cross section shown in Fig. 4 can be observed, for example, as follows. The multilayer ceramic capacitor 1 is polished to the center position in the width direction. The cross section exposed by polishing is then observed using an optical microscope or the like. The length and thickness of each part can be measured from the observed cross section.

[0105] To observe the voids 40, the external electrodes of the multilayer ceramic capacitor 1 were cross-sectionally processed by ion milling, and the state of the voids was observed using a backscattered electron image of a FE-SEM (Field Emission Scanning Electron Microscope).

[0106] (Method for manufacturing a multilayer ceramic capacitor) A method for manufacturing the multilayer ceramic capacitor 1 will be described. (1) A conductive paste for the dielectric sheets and the internal electrode layers is prepared. The conductive paste for the dielectric sheets and the internal electrode layers contains a binder and a solvent. The binder and the solvent may be a known organic binder and organic solvent, etc.

[0107] (2) A conductive paste for the internal electrode layers is printed on the dielectric sheet in a predetermined pattern. The internal electrode layer pattern is formed by printing the conductive paste. The printing can be performed by, for example, screen printing or gravure printing.

[0108] (3) A predetermined number of dielectric sheets for the outer layer portion are stacked. No internal electrode layer pattern is printed on the dielectric sheets for the outer layer portion. Dielectric sheets on which internal electrode layer patterns are printed are stacked in order on the stacked dielectric sheets. Furthermore, a predetermined number of dielectric sheets for the outer layer portion are stacked on top of those. A laminated sheet is produced by stacking these sheets.

[0109] (4) The laminated sheet is pressed in the height direction to produce a laminated block. The pressing method can be isostatic pressing.

[0110] (5) The laminated block is cut to a predetermined size. This cutting process cuts out laminated chips. When cutting, the corners and ridges of the laminated chips may be rounded. The rounding process may be performed by barrel polishing.

[0111] (6) The laminated chip is fired. This firing produces a laminate. The firing temperature is preferably 900° C. or higher and 1200° C. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers.

[0112] External electrodes are provided on the laminate. (7) A conductive paste that will become the base electrodes is applied to both end surfaces of the laminate. The conductive paste contains a glass component and a metal. The application method can be, for example, a dipping method. After application, a firing process is performed. A base electrode layer is formed by this firing process. The preferred temperature for the firing process is 700°C or higher and 900°C or lower. The base electrode layer is a fired layer.

[0113] (8) A conductive resin layer is formed on the base electrode layer. A conductive resin paste is prepared. The conductive resin paste includes a resin component, a metal component, and a solvent. A thermosetting resin is used as the resin component. Specifically, at least one of an epoxy resin and a phenolic resin is used as the resin component.

[0114] In this embodiment, the solvent used for the conductive resin paste is diethylene glycol monobutyl ether (molecular weight 162.23, boiling point 230°C) to which the following high boiling point solvents of 250°C or higher have been added: dibutyl sebacate (molecular weight 314.47, boiling point 345°C) diethyl sebacate (molecular weight 258.36, boiling point 309°C) dibutyl adipate (molecular weight 258.36, boiling point 305°C) dimethyl sebacate (molecular weight 230.30, boiling point 294°C) diethyl suberate (molecular weight 230.30, boiling point 283°C) dibutyl succinate (molecular weight 230.30, boiling point 274°C) diethyl adipate (molecular weight 202.25, boiling point 251°C)

[0115] Only one type of high boiling point solvent may be added, or multiple types may be added. In this embodiment, for example, dibutyl adipate (molecular weight 258.36, boiling point 305° C.) is used.

[0116] As the metal component, a metal powder, i.e., a metal filler, is added. The metal filler is at least one of silver, silver-coated copper, and silver-coated alloy powder. The shape of the metal filler is flat. Note that a spherical metal filler may also be added.

[0117] A conductive resin paste is applied onto the base electrode layer by a dipping method.

[0118] After application, the coating is subjected to a heat treatment. The heat treatment involves drying in a hot air oven at 150°C to 180°C for 10 minutes, followed by curing in an air atmosphere at 200°C to 280°C for 60 minutes. This thermal curing forms a conductive electrode layer.

[0119] By forming the conductive electrode layer in this manner, voids can be formed on the surface of the metal filler particles. The ratio of the voids to the perimeter of the metal filler particles can be adjusted by changing the type of high-boiling-point solvent, the amount of high-boiling-point solvent added, drying conditions, curing conditions, etc.

[0120] The heat treatment is preferably performed in a nitrogen gas atmosphere. The preferred oxygen concentration is 100 ppm or less. This oxygen concentration makes it difficult for the resin to scatter. Also, this oxygen concentration makes it difficult for various metal components to be oxidized.

[0121] (9) After forming the conductive resin layer, a Ni plating layer is formed on the surface of the conductive resin layer. This Ni plating layer becomes a first Ni plating layer and a second Ni plating layer. The Ni plating layer can be formed by electrolytic plating. A preferred plating method is barrel plating.

[0122] (10) A Sn plating layer is formed on the Ni plating layer. A first Sn plating layer is formed on the first Ni plating layer. A second Sn plating layer is formed on the second Ni plating layer. By forming the Sn plating layer, the wettability of the solder used for mounting can be improved when mounting the multilayer ceramic capacitor 1 on a substrate or the like. This makes it easier to mount the multilayer ceramic capacitor 1 on a substrate or the like. The Sn plating layer can be formed by electrolytic plating. A preferred plating method is barrel plating.

[0123] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0124] <1> A multilayer ceramic capacitor including: a laminate including a plurality of stacked dielectric layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces; a first external electrode arranged on the first end surfaces; and a second external electrode arranged on the second end surfaces, wherein the first external electrode and the second external electrode have a base electrode layer containing a metal component, a conductive resin layer including a thermosetting resin and a metal filler arranged on the base electrode layer, and a plating layer arranged on the conductive resin layer, the metal filler in the conductive resin layer being a flat filler, and voids are arranged in the surface of the flat filler.

[0125] <2> The multilayer ceramic capacitor according to <1>, wherein the voids arranged on the surface of the flat filler are arranged along at least a part of the outer periphery of the flat filler.

[0126] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the voids are arranged in a range of 5% to 90% of the circumferential length of the flat filler in a cross section parallel to the height direction and length direction of the laminate.

[0127] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the flat filler extends in a direction substantially parallel to the length direction.

[0128] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the flat fillers are arranged in plurality in the conductive resin layer, and when observed at a predetermined cross section in the conductive resin layer, the proportion of the flat fillers in which voids are arranged within a length range of 5% to 90% of the circumferential length of the flat fillers is 60% or more relative to the total number of the flat fillers.

[0129] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 Outer dielectric layer 4 Inner dielectric layer 5a First dielectric layer 5b Second dielectric layer 6a First internal electrode layer 6b Second internal electrode layer 10 Inner layer portion 20a First external electrode 20b Second external electrode 21a First base electrode layer 21b Second base electrode layer 22a First conductive resin layer 22b Second conductive resin layer 23a First Ni plating layer 23b Second Ni plating layer 24a First Sn plating layer 24b Second Sn plating layer 30 Metal filler (flat filler) 38 Resin 40 Void 42 Outer periphery of metal filler

Claims

1. a laminate including a plurality of stacked dielectric layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed at the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed at the second end surface; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; In a multilayer ceramic capacitor having The first external electrode and the second external electrode are a base electrode layer containing a metal component; a conductive resin layer including a thermosetting resin and a metal filler disposed on the base electrode layer; a plating layer disposed on the conductive resin layer, the metal filler in the conductive resin layer is a flat filler, Voids are arranged on the surface of the flat filler. Multilayer ceramic capacitor.

2. The voids arranged on the surface of the flat filler are arranged along at least a part of the outer periphery of the flat filler. The multilayer ceramic capacitor according to claim 1 .

3. the voids are arranged in a range of 5% to 90% of the circumferential length of the flat filler particles in a cross section parallel to the height direction and length direction of the laminate; 3. The multilayer ceramic capacitor according to claim 1.

4. The flat filler extends in a direction substantially parallel to the length direction.

3. The multilayer ceramic capacitor according to claim 1.

5. a plurality of the flat fillers are arranged in the conductive resin layer, When observed at a predetermined cross section of the conductive resin layer, the proportion of the flat fillers in which voids are arranged within a length range of 5% to 90% of the circumferential length of the flat fillers is 60% or more, relative to the total number of the flat fillers.

3. The multilayer ceramic capacitor according to claim 1.