Semiconductor device and method for fabricating the same

Abstract

This invention discloses a semiconductor device with different gate structure configurations and a method for manufacturing the semiconductor device. The method includes: depositing a high-k dielectric layer surrounding a nanostructure channel region; performing a first doping step on a first portion and a second portion of the high-k dielectric layer using a rare-earth metal-based dopant at a first rare-earth metal-based dopant concentration; and performing a second doping step on the first portion and a third portion of the high-k dielectric layer using a rare-earth metal-based dopant at a second rare-earth metal-based dopant concentration different from the first rare-earth metal-based dopant concentration. The semiconductor manufacturing method further includes depositing a work function metal layer on the high-k dielectric layer and depositing a gate filling layer on the work function metal layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a nanostructure and a method for manufacturing the same. Prior Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to miniaturize semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (finFETs). This miniaturization increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] This invention provides a method for manufacturing a semiconductor device. The method includes: forming a nanostructure channel region in a fin structure; depositing a high-dielectric-constant gate dielectric layer surrounding the nanostructure channel region; selectively performing a first doping process using rare-earth metal-based dopants on a first portion and a second portion of the high-dielectric-constant gate dielectric layer, wherein the first doping process uses a first rare-earth metal-based dopant concentration to dope the first and second portions of the high-dielectric-constant gate dielectric layer; selectively performing a second doping process using rare-earth metal-based dopants on the first and third portions of the high-dielectric-constant gate dielectric layer, wherein the second doping process uses a second rare-earth metal-based dopant concentration to dope the first and third portions of the high-dielectric-constant gate dielectric layer, the second rare-earth metal-based dopant concentration being different from the first rare-earth metal-based dopant concentration; depositing a work function metal layer on the high-dielectric-constant gate dielectric layer; and depositing a gate metal filling layer on the work function metal layer.

[0004] This invention also provides a method for manufacturing a semiconductor device. The method includes: forming a first fin structure and a second fin structure of an n-type field-effect transistor and a p-type field-effect transistor, respectively; forming a first nanostructure channel region and a second nanostructure channel region in the first fin structure and the second fin structure, respectively; depositing a high-dielectric-constant gate dielectric layer surrounding the first nanostructure channel region and the second nanostructure channel region; selectively forming a first rare-earth metal substrate on a first portion and a second portion of the high-dielectric-constant gate dielectric layer located on the first nanostructure channel region and the second nanostructure channel region; performing a first annealing process on the first rare-earth metal substrate; selectively forming a second rare-earth metal substrate on a first portion and a third portion of the high-dielectric-constant gate dielectric layer located on the first nanostructure channel region and the second nanostructure channel region; performing a second annealing process on the second rare-earth metal substrate; depositing a work function metal layer on the high-dielectric-constant gate dielectric layer; and depositing a gate metal filling layer on the work function metal layer.

[0005] This invention also provides a semiconductor device. The semiconductor device includes a first gate structure, a second gate structure, and a third gate structure. The first gate structure includes a first interface oxide layer, a first high-dielectric-constant gate dielectric layer, and a first dipole layer. The first high-dielectric-constant gate dielectric layer is disposed on the first interface oxide layer and has a first rare-earth metal oxide dopant concentration. The first dipole layer is disposed at the interface between the first interface oxide layer and the first high-dielectric-constant gate dielectric layer and has a first rare-earth metal dipole concentration. The second gate structure includes a second interface oxide layer, a second high-dielectric-constant gate dielectric layer, and a second dipole layer. The second high-dielectric-constant gate dielectric layer is disposed on the second interface oxide layer and has a second rare-earth metal oxide dopant concentration. The second dipole layer is disposed at the interface between the second interface oxide layer and the second high-dielectric-constant gate dielectric layer and has a second rare-earth metal dipole concentration. The third gate structure includes a third interface oxide layer, a third high-dielectric-constant gate dielectric layer, and a third dipole layer. The third high-dielectric-constant gate dielectric layer is disposed on the third interface oxide layer and has a third rare-earth metal oxide dopant concentration. The third dipole layer is disposed at the interface between the third interface oxide layer and the third high-dielectric-constant gate dielectric layer and has a third rare-earth metal dipole concentration. The first, second, and third rare-earth metal oxide dopant concentrations are different from each other, and the first, second, and third rare-earth metal dipole concentrations are also different from each other. Simple Explanation of the Diagram

[0006] A more comprehensive understanding of the embodiments of the present invention will be achieved by reading the accompanying drawings in conjunction with the detailed description. It should be noted that, in accordance with industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0007] Figures 1A, 1B to 1C, and 1D to 1Q are isometric views, cross-sectional views, and device features of semiconductor devices with different gate structures, respectively, according to some embodiments.

[0008] Figure 2 is a flowchart of a method for manufacturing semiconductor devices with different gate structures according to some embodiments.

[0009] Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A and 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B are cross-sectional views illustrating various stages in the process of manufacturing semiconductor devices with different gate structures, according to some embodiments.

[0010] Figures 8C, 8D, and 11C to 11E illustrate, according to some embodiments, the device features at various stages in the process of manufacturing semiconductor devices with different gate structures.

[0011] Exemplary embodiments will be described with reference to the accompanying drawings. In the drawings, similar element symbols generally refer to the same, functionally similar, and / or structurally similar elements. Implementation

[0012] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first component forming on a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that they are not in direct contact. As used herein, forming a first component on a second component means forming the first component so that it is in direct contact with the second component. Furthermore, the embodiments of the invention may repeat element symbols and / or letters in various examples. Such repetition is not in itself intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0013] This document may use spatially relative terms, such as "below," "under," "below," "above," "above," etc., to facilitate the description of the relationship between one element or component and another element or component(s) in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations depicted in the diagram. When the device is rotated to different orientations (90 degrees or other orientations), the spatially relative terms used herein will also be interpreted according to the orientation after the rotation.

[0014] It should be noted that the terms "an embodiment," "an exemplary embodiment," "an illustrative embodiment," etc., used in the specification refer to the fact that the described embodiment may include specific components, structures, or features, but each embodiment may not necessarily include specific components, structures, or features. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific component, structure, or feature is described in conjunction with an embodiment, whether explicitly described or not, implementing such a component, structure, or feature in conjunction with other embodiments is within the scope of knowledge of those skilled in the art to which this invention pertains.

[0015] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, and therefore the terminology or terminology in the specification shall be interpreted by those skilled in the art in connection with the present invention based on the teachings herein.

[0016] As used in this article, the term "etch selectivity" refers to the ratio of the etching rates of two different materials under the same etching conditions.

[0017] As used herein, the term "high-k" refers to a high dielectric constant value. In the field of semiconductor device structure and manufacturing processes, high-k refers to a dielectric constant greater than that of SiO2 (e.g., greater than about 3.9).

[0018] As used herein, the term "p-type" is defined as a structure, film, and / or region doped with a p-type dopant such as boron.

[0019] As used herein, the term "n-type" is defined as a structure, film, and / or region doped with an n-type dopant such as phosphorus.

[0020] As used herein, the term "nanostructure" is defined as a structure, film, and / or region having a horizontal dimension (e.g., along the X or Y axis) and / or a vertical dimension (e.g., along the Z axis) of less than 100 nm.

[0021] As used herein, the term "n-type work function metal (nWFM)" defines a metal or metal-containing material whose work function value is closer to the conduction band energy of a field-effect transistor channel region material than to the valence band energy. In some embodiments, the term "n-type work function metal" is defined as a metal or metal-containing material having a work function value of less than 4.5 eV.

[0022] As used herein, the term "p-type work function metal (pWFM)" defines a metal or metal-containing material whose work function is closer to the valence band energy of a field-effect transistor channel region material than to the conduction band energy. In some embodiments, the term "p-type work function metal" is defined as a metal or metal-containing material having a work function value equal to or greater than 4.5 eV.

[0023] As used in this paper, the term "effective work function value" is defined as the difference between the work function value of the metal layer of the field-effect transistor gate structure and the potential difference induced across the dipole layer, which is formed between the high dielectric constant dielectric layer and the interface layer of the field-effect transistor gate structure.

[0024] In some embodiments, the terms "about" and "substantially" may refer to a given quantity of value within, for example, 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, or ±5%).

[0025] The fin structures disclosed herein can be patterned using any suitable method. For example, the fin structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes to create patterns with, for example, smaller pitches than those obtained using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0026] The gate voltage—the critical voltage Vt—required to turn on a field-effect transistor (FET) depends on the semiconductor material of the FET channel region and the work function value of the work function metal layer of the FET gate structure. For example, for an n-type FET, reducing the difference between the work function value of the n-type work function metal layer of the FET gate structure and the conduction band energy of the n-type FET channel region material (e.g., 4.1 eV for Si or 3.8 eV for SiGe) reduces the critical voltage of the n-type FET. For a p-type FET, reducing the difference between the work function value of the p-type work function metal layer of the p-type FET gate structure and the valence band energy of the p-type FET channel region material (e.g., 5.2 eV for Si or 4.8 eV for SiGe) reduces the critical voltage of the p-type FET. The critical voltage of the FET gate structure can also depend on the thickness and / or material composition of the layers in the FET gate structure. In this way, field-effect transistors with different critical voltages can be manufactured by adjusting the thickness and / or material composition of the gate structure.

[0027] The growing demand for low-power portable devices has led to a corresponding increase in the need for field-effect transistors (FETs) with low critical voltages, such as less than 100 mV. One way to achieve such a low critical voltage in FETs is by using a work function metal layer with a thickness greater than about 4 nm (e.g., about 5 nm to about 10 nm) in the gate structure. However, the thickness of the work function metal layer in the gate structure can be limited by the geometry of the FET gate structure. For example, in gate-all-around (GAA) FETs, the thickness of the work function metal layer may be limited by the spacing between the nanostructure channel regions of the GAA FET. Furthermore, depositing such a thick work function metal layer may become increasingly difficult as FETs continue to be miniaturized (e.g., GAA FETs).

[0028] This invention provides exemplary structures of field-effect transistors (FETs) with gate structures having different effective work function values ​​(e.g., finned FETs or fully wound FETs), providing exemplary methods for forming such FETs on the same substrate with different and / or low critical voltages. These exemplary methods form FETs with different conductivity types and different effective work function values ​​without increasing the thickness of the work function metal layer. Compared to other methods of forming FETs with similar channel dimensions and critical voltages on the same substrate, these exemplary methods are less complex and more cost-effective in fabricating reliable gate structures in FETs with nanostructured channel regions and different and / or low critical voltages. Furthermore, compared to other methods of forming FETs with similar critical voltages, these exemplary methods can form FET gate structures with smaller dimensions (e.g., thinner gate stacks).

[0029] In some embodiments, n-type and p-type field-effect transistors (FETs) with different gate structure configurations can be selectively formed on the same substrate. To enable the n-type and p-type FETs to have different and / or low critical voltages, high-dielectric-constant gate dielectric layers in the gate structures of the n-type and p-type FETs can be doped with different concentrations of rare-earth metal-based dopants. Different concentrations of rare-earth metal-based dopants can create dipole layers with varying dipole concentrations in the gate structures of the n-type and p-type FETs. Tuning the dipole concentration can tune the effective work function value of the gate structure of the n-type and p-type FETs, and thus adjust the critical voltage of the n-type and p-type FETs. In this way, n-type and p-type FETs with different and / or low critical voltages can be obtained without increasing the thickness of the work function metal layer.

[0030] According to some embodiments, a semiconductor device 100 having n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4 is described with reference to Figures 1A to 1Q. Figure 1A is an isometric view of the semiconductor device 100 according to some embodiments. Figures 1B and 1C are cross-sectional views of the semiconductor device 100 drawn along lines AA and BB of Figure 1A, respectively, according to some embodiments. Figures 1D to 1Q illustrate the device features of the semiconductor device according to some embodiments. Although eight field-effect transistors are discussed with reference to Figures 1A to 1Q, the semiconductor device 100 may have any number of field-effect transistors. Unless otherwise stated, the discussion of the elements of the n-type field-effect transistors 102N1-102N4 and the p-type field-effect transistors 102P1-102P4 using the same annotations can be applied interchangeably. The isometric views and cross-sectional views of the semiconductor device 100 are shown for illustrative purposes and may not be drawn to scale.

[0031] Referring to Figures 1A to 1C, n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4 may be formed on substrate 106. Substrate 106 may be a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 106 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 106 may include: (i) elemental semiconductors, such as germanium (Ge); (ii) compound semiconductors, including silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and / or group III-V semiconductor materials; (iii) alloy semiconductors, including silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium tin (GeSn), germanium tin silicon (SiGeC), and germanium tin silicon (SiGeC). (iv) gallium arsenide (GaAsP), gallium indium phosphide (GaInP), gallium indium arsenide (GaInAs), gallium indium arsenide (GaInAsP), aluminum arsenide (AlAs), and / or aluminum gallium arsenide (AlGaAs); (v) silicon-on-insulator (SOI) structure; (v) silicon-germanium-on-insulator (SiGeOI) structure; (vi) germanium-on-insulator (GeOI) structure; or (vii) a combination of the foregoing. Furthermore, the substrate 106 may be doped (e.g., a p-type substrate or an n-type substrate) depending on design requirements. In some embodiments, p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic) may be used to dope the substrate 106.

[0032] The n-type field-effect transistors 102N1-102N4 and the p-type field-effect transistors 102P1-102P4 may respectively include fin structures 1081 and 1082 extending along the x-axis, epitaxial fin regions 110A and 110B, gate structures 112N1-112N4 and 112P1-112P4 (also called fully wound gate structures 112N1-112N4 and 112P1-112P4), inner spacer 142, and gate spacer 114.

[0033] As shown in Figures 1B to 1C, fin structure 1081 may include a fin base 108A1 and a stacked fin portion 108B1 disposed on the fin base 108A1, and fin structure 1082 may include a fin base 108A2 and a stacked fin portion 108B2 disposed on the fin base 108A2. In some embodiments, fin bases 108A1 and 108A2 may include a material similar to that of substrate 106. Fin bases 108A1 and 108A2 may be formed by optically photolithographically patterning and etching substrate 106. Stacked fin portions 108B1 and 108B2 may include a first semiconductor layer 120 and a second semiconductor layer 122 stacked in an alternating configuration. Each first semiconductor layer 120 of the stacked fin portion 108B1 may have (i) a nanostructure region 120A below the epitaxial fin region 110A (as shown in Figure 1B), and (ii) a nanostructure channel region 120B surrounded by gate structures 112N1-112N4 (as shown in Figure 1B). Each second semiconductor layer 122 of the stacked fin portion 108B2 may have (i) a nanostructure region 122A below the epitaxial fin region 110B (as shown in Figure 1C), and (ii) a nanostructure channel region 122B surrounded by gate structures 112P1-112P4 (as shown in Figure 1C).

[0034] The first semiconductor layer 120 and the second semiconductor layer 122 may comprise semiconductor materials that are different from each other. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may comprise semiconductor materials that have different oxidation rates and / or etching selectivity. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may comprise semiconductor materials that are similar to or different from the substrate 106. The first semiconductor layer 120 and the second semiconductor layer 122 may comprise (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors comprising group III-V semiconductor materials; (iii) alloy semiconductors, including SiGe, germanium-tin, or germanium-tin oxide; or (iv) combinations thereof.

[0035] In some embodiments, for n-type field-effect transistors 102N1-102N4, the first semiconductor layer 120 may include Si, SiAs, silicon phosphide (SiP), SiC, or silicon carbide phosphide (SiCP), and for p-type field-effect transistors 102P1-102P4, the second semiconductor layer 122 may include SiGe, silicon germanium boride (SiGeB), germanium boride (GeB), silicon germanium tin boride (SiGeSnB), or a group III-V semiconductor compound. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may each include Si, SiAs, SiP, or SiCP for n-type field-effect transistors 102N1-102N4, or may each include SiGe, SiGeB, GeB, SiGeSnB, or a group III-V semiconductor compound for p-type field-effect transistors 102P1-102P4. In some embodiments, for n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4, the first semiconductor layer 120 and the second semiconductor layer 122 may comprise materials similar to each other. Although Figure 1B illustrates rectangular cross-sections of nanostructure channel regions 120B and 122B, nanostructure channel regions 120B and 122B may have cross-sections of other geometries (e.g., circular, elliptical, triangular, or polygonal).

[0036] Referring to Figures 1A to 1C, epitaxial fin regions 110A can be grown to cover and surround the stacked fin portion 108B1. Similarly, epitaxial fin regions 110B can be grown to cover and surround the stacked fin portion 108B2. In some embodiments, epitaxial fin regions 110A and 110B can be grown on the fin bases 108A1 and 108A2, respectively, without covering and surrounding the stacked fin portions 108B1 and 108B2. Epitaxial fin regions 110A and 110B, along with the underlying nanostructure regions 120A and 122A, can respectively form source / drain regions 126A and 126B.

[0037] Epitaxial fin regions 110A and 110B may comprise epitaxial growth semiconductor materials that are similar to or different from each other. In some embodiments, the epitaxial growth semiconductor material may comprise a material that is the same as or different from the substrate 106 material. Epitaxial fin regions 110A and 110B may be n-type and p-type, respectively. In some embodiments, the n-type epitaxial fin region 110A may be made of SiAs, SiC, or SiCP. The p-type epitaxial fin region 110B may comprise SiGe, SiGeB, GeB, SiGeSnB, a III-V group semiconductor compound, or a combination thereof.

[0038] The gate structures 112N1-112N4 and 112P1-112P4 can be multilayer structures, and can respectively encapsulate and surround the nanostructure channel regions 120B and 122B. The gate structures 112N1-112N4 and 112P1-112P4 can be called "fully wound gate structures" or "horizontal fully wound gate structures". The n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4 can be called "fully wound gate field-effect transistors 102N1-102N4 and 102P1-102P4" or "fully wound gate n-type field-effect transistors 102N1-102N4 and fully wound gate p-type field-effect transistors 102P1-102P4".

[0039] Referring to Figures 1A to 1C, the gate structures 112N1-112N4 and 112P1-112P4 may include an interface oxide layer 127, high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4, a gate work function metal layer 130, and a gate metal filling layer 132. Even though Figures 1B and 1C show that all the film layers of the gate structures 112N1-112N4 and 112P1-112P4 respectively cover and surround the nanostructure channel regions 120B and 122B, the nanostructure channel regions 120B and 122B may be at least covered and surrounded by the interface oxide layer 127 and the high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4 to fill the space between adjacent nanostructure channel regions 120B and 122B. In this way, the nanostructure channel regions 120B and 122B can be electrically isolated from each other to prevent short circuits between the gate structures 112N1-112N4 and 112P1-112P4 and the source / drain regions 126A and 126B when the n-type field-effect transistors 102N1-102N4 and the p-type field-effect transistors 102P1-102P4 are operating. In some embodiments, not all the film layers of the gate structures 112N1-112N4 and 112P1-112P4 respectively cover and surround the nanostructure channel regions 120B and 122B, but the nanostructure channel regions 120B and 122B may be covered and surrounded by at least the interface oxide layer 127, the high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4 and the gate work function metal layer 130, so as to fill the space between adjacent nanostructure channel regions 120B and 122B.

[0040] The interface oxide layer 127 may be disposed on the nanostructure channel regions 120B and 122B, and may include silicon oxide with a thickness between about 0.5 nm and about 1.5 nm. The high-dielectric-constant gate dielectric layers 128N1-128N4 and 128P1-128P4 may each have a thickness approximately 2 to 3 times that of the interface oxide layer 127 (e.g., approximately 1 nm to approximately 3 nm), and may include (i) a high-dielectric-constant dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2); (ii) having lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), pium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), thionium (Gd), and tbium (Tb). High dielectric constant dielectric materials of oxides of dysprosium (Dy), holmium (Ho), erbium (Er), thionium (Tm), ytterbium (Yb) or argonium (Lu); or (iii) combinations thereof.

[0041] In some embodiments, the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 may include rare-earth metal-based dopants. These dopants may include oxides of rare-earth metals, such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), cerium oxide (CeO2), ytterbium oxide (Yb2O3), erbium oxide (Er2O3), or combinations thereof. The concentrations of the rare-earth metal-based dopants in the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 may be similar or different from each other. In some embodiments, high-dielectric-constant gate dielectric layers 128N1 and 128P1 may have a rare-earth metal-based dopant concentration C1, high-dielectric-constant gate dielectric layers 128N2 and 128P2 may have a rare-earth metal-based dopant concentration C2, and high-dielectric-constant gate dielectric layers 128N3 and 128P3 may have a rare-earth metal-based dopant concentration C3. In some embodiments, concentration C1 is greater than concentrations C2 and / or C3. In some embodiments, concentration C1 is greater than concentrations C2 and C3, and concentration C2 is greater than concentration C3. In some embodiments, concentration C1 is greater than concentrations C2 and C3, and concentration C3 is greater than concentration C2. In some embodiments, high-dielectric-constant gate dielectric layers 128N4 and 128P4 may have a rare-earth metal-based dopant concentration C4, which may be equal to 0. In some embodiments, the rare-earth metal-based dopant concentrations C1-C3 may be between about 0.1 atomic percent and about 15 atomic percent.

[0042] According to some embodiments, Figure 1D plots the doping profiles of rare-earth metal-based dopants in the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 along a vertical axis (e.g., the z-axis). As shown in Figure 1D, the rare-earth metal-based dopants may have a lower concentration in the regions of the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 near the work function metal layer 130 compared to the region near the interface oxide layer 127.

[0043] Referring to Figure 1E, according to some embodiments, the rare earth metal-based dopants in the high-dielectric-constant gate dielectric layers 128N1-128N3, rare earth metal-based dipole layers 129N1-129N3, interface oxide layer 127, and nanostructure channel region 120B of the n-type field-effect transistors 102N1-102N3 may have graded doping profiles along line segments D, E, and / or F shown in Figure 1B. As shown in Figure 1E, the concentration of rare earth metal-based dopants may gradually decrease from the top surface of the high-dielectric-constant gate dielectric layers 128N1-128N3 to the nanostructure channel region 120B. In some embodiments, the high dielectric constant gate dielectric layers 128P1-128P3, rare earth metal-based dipole layers 129P1-129P3, interface oxide layer 127, and rare earth metal-based dopants in nanostructure channel region 122B of p-type field-effect transistors 102P1-102P3 may have a gradient doping profile similar to that in Figure 1E along line segments G, H, and / or I (shown in Figure 1C).

[0044] Referring to Figure 1F, in some embodiments, the interface between the high-dielectric-constant gate dielectric layer 128N1-128N4 of the n-type field-effect transistor gate structure 112N1-112N4 and the interface layer 127 may have rare-earth metal-based dopant concentrations B1-B4, wherein concentration B1 is greater than concentration B2, and concentration B2 is greater than concentration B3. Concentration B4 may be equal to 0. In some embodiments, the rare-earth metal-based dopant concentrations B1-B3 may be between about 0.1 atomic percent and about 15 atomic percent. In some embodiments, based on the manufacturing method of the n-type field-effect transistor 102N1-102N3 described with reference to Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 8C, 8D and 11C, 11D, concentration B1 may be the sum of concentrations B2 and B3. In some embodiments, as shown in Figure 1G, the interface between the high dielectric constant gate dielectric layers 128N1-128N3 and the interface layer 127 may have a rare earth metal-based dopant concentration of B5-B7 instead of concentrations B1-B3, wherein concentration B5 is greater than concentration B7, and concentration B7 is greater than concentration B6. Based on the manufacturing method of the n-type field-effect transistors 102N1-102N3 described with reference to Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 8C, 8D, 11C, and 11E, concentration B5 may be the sum of concentrations B6 and B7. Furthermore, according to some embodiments, referring to Figures 1F and 1G, the discussion on the rare earth metal dopant concentrations B1-B4 and B5-B7 can be applied to the rare earth metal dopant concentration at the interface between the high dielectric constant gate dielectric layer 128P1-128P4 and the interface layer 127 of the p-type field-effect transistor gate structure 112P1-112P4.

[0045] In some embodiments, rare earth metal-based dopants can be used to tune the effective work function values ​​W1-W4 of gate structures 112N1-112N4 and 112P1-112P4, and thus the critical voltages TN1-TN4 and TP1-TP4 of gate structures 112N1-112N4 and 112P1-112P4 can be adjusted respectively. In some embodiments, the term "effective work function value" is defined as the difference between the work function value of the work function metal layer (e.g., work function metal layer 130) of the field-effect transistor gate structure (e.g., gate structures 112N1-112N4 and 112P1-112P4) and the potential difference induced across the dipole layer (e.g., dipole layers 129N1-129N3 and 129P1-129P3), which is formed between the high dielectric constant dielectric layer (e.g., high dielectric constant gate dielectric layers 128N1-128N3 and 128P1-128P3) of the field-effect transistor gate structure and the interface layer (e.g., interface oxide layer 127). In some embodiments, gate structures 112N1 and 112P1 may have an effective work function value W1, gate structures 112N2 and 112P2 may have an effective work function value W2, gate structures 112N3 and 112P3 may have an effective work function value W3, and gate structures 112N4 and 112P4 may have an effective work function value W4. As shown in Figures 1H and 1I, the rare earth metal matrix dopant concentration of the high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4 may be inversely proportional to the individual effective work function values ​​of gate structures 112N1-112N4 and 112P1-112P4.

[0046] As shown in Figures 1B and 1C, due to the rare earth metal-based dopants in the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3, rare earth metal-based dipole layers 129N1-129N3 and 129P1-129P3 can be formed at the interface between the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 and the interface oxide layer 127. In some embodiments, the dipole layers 129N1-129N3 and 129P1-129P3 may include dipoles between rare earth metal ions and oxygen ions. In some embodiments, dipole layers 129N1 and 129P1 may have a rare earth metal-based dipole concentration D1, dipole layers 129N2 and 129P2 may have a rare earth metal-based dipole concentration D2, and dipole layers 129N3 and 129P3 may have a rare earth metal-based dipole concentration D3. Because the high dielectric constant gate dielectric layers 128N4 and 129N4 do not have rare earth metal-based dopants, the rare earth metal-based dipole concentration D4 at the interface between the interface oxide layer 127 and the high dielectric constant gate dielectric layers 128N4 and 128P4 may be equal to 0.

[0047] The concentration of rare-earth metal-based dipoles is directly proportional to the concentration of rare-earth metal-based dopants, and therefore the rare-earth metal-based dipole concentration profiles shown in Figures 1J to 1M are similar to the rare-earth metal-based dopant concentration profiles shown in Figures 1H and 1I. Referring to Figures 1J and 1K, similar to the rare-earth metal-based dopant concentrations, the rare-earth metal-based dipole concentrations of dipole layers 129N1-129N4 and 129P1-129P4 are inversely proportional to the individual effective work function values ​​of gate structures 112N1-112N4 and 112P1-112P4. Referring to Figures 1L and 1M, the rare-earth metal-based dipole concentration of dipole layers 129N1-129N4 is inversely proportional to the individual critical voltages of gate structures 112N1-112N4, and the rare-earth metal-based dipole concentration of dipole layers 129P1-129P4 is directly proportional to the individual critical voltages of gate structures 112P1-112P4. Therefore, n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4 can have gate structures with different and / or low critical voltages, while their gate structures have the same gate work function metal layer 130 and different rare-earth metal-based dopant concentrations in the high-dielectric-constant gate dielectric layers 128N1-128N4 and 128P1-128P4.

[0048] In some embodiments, the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 may have aluminum-based dopants instead of rare-earth metal-based dopants. The aluminum-based dopants may include aluminum oxides (AlxOy), such as Al2O3. The doping profile and concentration of the aluminum-based dopants in the high-dielectric-constant gate dielectric layers 128N1-128N3 and 128P1-128P3 may be similar to the doping profile and concentration of the rare-earth metal-based dopants shown in Figures 1H and 1I. Similar to rare-earth metal-based dopants, aluminum-based dopants can be used to tune the effective work function values ​​of the gate structures 112N1-112N4 and 112P1-112P4, and thus the threshold voltages of the gate structures 112N1-112N4 and 112P1-112P4 can be adjusted respectively. As shown in Figures 1N to 1Q, in some embodiments, gate structures 112N1 and 112P1 having individual high-dielectric-constant gate dielectric layers 128N1 and 128P1 doped with aluminum-based dopant can have an effective work function value W5; gate structures 112N2 and 112P2 having high-dielectric-constant gate dielectric layers 128N2 and 128P2 doped with aluminum-based dopant can have an effective work function value W6; gate structures 112N3 and 112P3 having high-dielectric-constant gate dielectric layers 128N3 and 128P3 doped with aluminum-based dopant can have an effective work function value W7; and gate structures 112N4 and 112P4 having high-dielectric-constant gate dielectric layers 128N4 and 128P4 doped with aluminum-based dopant can have an effective work function value W8. The aluminum-based dopant concentration of the high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4 is proportional to the individual effective work function values ​​of the gate structures 112N1-112N4 and 112P1-112P4.

[0049] As shown in Figures 1B and 1C, similar to rare-earth metal-based dopants, aluminum-based dopants can form aluminum-based dipole layers 129N1-129N3 and 129P1-129P3. In some embodiments, the aluminum-based dipole layers 129N1-129N3 and 129P1-129P3 may include dipoles between aluminum ions and oxygen ions. As shown in Figures 1N to 1Q, in some embodiments, dipole layers 129N1 and 129P1 may have an aluminum-based dipole concentration D5, dipole layers 129N2 and 129P2 may have an aluminum-based dipole concentration D6, and dipole layers 129N3 and 129P3 may have an aluminum-based dipole concentration D7. Because the high dielectric constant gate dielectric layers 128N4 and 128P4 do not have aluminum-based dopants, the aluminum-based dipole concentration D8 at the interface between the interface oxide layer 127 and the high dielectric constant gate dielectric layers 128N4 and 128P4 can be equal to 0.

[0050] Referring to Figures 1N and 1O, the aluminum-based dipole concentrations of dipole layers 129N1-129N4 and 129P1-129P4 are directly proportional to the individual effective work function values ​​W5-W8 of gate structures 112N1-112N4 and 112P1-112P4. Referring to Figures 1P and 1Q, the aluminum-based dipole concentrations of dipole layers 129N1-129N4 are directly proportional to the individual critical voltages TN5-TN8 of gate structures 112N1-112N4, and inversely proportional to the individual critical voltages TP5-TP8 of gate structures 112P1-112P4. Therefore, n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4 can have gate structures with different and / or low critical voltages, and the gate structures have the same gate work function metal layer 130 and different aluminum dopant concentrations in the high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4.

[0051] Referring to Figures 1B and 1C, in some embodiments, the gate work function metal layer 130 may be disposed on and in solid contact with the high dielectric constant gate dielectric layers 128N1-128N4 and 128P1-128P4, and may include an n-type work function metal layer and / or a p-type work function metal layer. In some embodiments, the n-type work function metal layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped desalinated tantalum, or a combination thereof. In some embodiments, each n-type work function metal layer may have a thickness between about 1 nm and about 3 nm. The thickness within this range allows the n-type work function metal layer to cover the nanostructure channel regions 120B and 122B, thereby providing a low critical voltage without being limited by the spacing between adjacent nanostructure channel regions 120B and 122B.

[0052] In some embodiments, the p-type work function metal layer may comprise (i) a titanium-based nitride or alloy, such as TiN, TiSiN, titanium-gold alloy, titanium-copper alloy, titanium-chromium alloy, titanium-cobalt alloy, titanium-molybdenum alloy, or titanium-nickel alloy, that is substantially aluminum-free (e.g., without aluminum); (ii) a tantalum-based nitride or alloy, such as TaN, TaSiN, tantalum-gold alloy, tantalum-copper alloy, tantalum-tungsten alloy, tantalum-platinum alloy, tantalum-molybdenum alloy, tantalum-titanium alloy, or tantalum-nickel alloy; or (iii) a combination of the foregoing. In some embodiments, the p-type work function metal layer may comprise a thickness between about 1 nm and about 3 nm. A thickness within this range allows the p-type work function metal layer to cover the nanostructure channel regions 120B and 122B, thereby providing a low critical voltage unrestricted by the spacing between adjacent nanostructure channel regions 120B and 122B.

[0053] The gate metal filler layer 132 may comprise a single metal layer or a stack of metal layers. The metal layer stack may comprise metals that are different from each other. In some embodiments, the gate metal filler layer 132 may comprise a suitable conductive material, such as W, Ti, Ag, Ru, Mo, Cu, Co, Ni, metal alloys, and / or combinations thereof. While gate structures 112N1-112N4 and 112P1-112P4 are illustrated as having a fully wound gate structure, other gate structures (e.g., vertical fully wound gate structures or gate structures without a fully wound gate structure) are also within the scope and spirit of the embodiments of the present invention.

[0054] Referring to Figures 1B and 1C, the gate spacer 114 and the inner spacer 142 can form the sidewalls of the gate structures 112N1-112N4 and 112P1-112P4. According to some embodiments, the gate spacer 114 and / or the inner spacer 142 can each be in solid contact with the interface oxide layer 127 and the gate dielectric layers 128N1-128N4 and 128P1-128P4. The gate spacer 114 and the inner spacer 142 can each comprise an insulating material, such as silicon oxide, silicon nitride, a low dielectric constant material, or a combination thereof. The gate spacer 114 and the inner spacer 142 can each have a low dielectric constant material with a dielectric constant less than about 3.9.

[0055] Referring to Figures 1A to 1D, the semiconductor device 100 may further include an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 138. The contact etch stop layer 116 may be disposed on the sidewalls of the gate spacer 114 and on the epitaxial regions 110A and 110B. The contact etch stop layer 116 can be used to protect the gate structures 112N1-112N4 and 112P1-112P4 and / or the source / drain regions 126A and 126B. In some embodiments, for example, the contact etch stop layer 116 may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), boron silicon nitride (SiBN), silicon carbide-boron nitride (SiC-BN), or a combination thereof.

[0056] Interlayer dielectric layer 118 may be disposed on contact etch stop layer 116 and may include dielectric material deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon carbide). In some embodiments, the dielectric material is silicon oxide. Shallow trench isolation region 138 may be used to provide electrical isolation between n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4, between adjacent field-effect transistors (not shown) on substrate 106, and / or between adjacent active and passive elements (not shown) integrated with or deposited on substrate 106. In some embodiments, the shallow trench isolation region 138 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectric material, and / or other suitable insulating material.

[0057] The cross-sectional shapes of the semiconductor device 100 and its components (e.g., fin structures 1081-1082, gate structures 112N1-112N4 and 112P1-112P4, epitaxial fin regions 110A-110B, inner spacer 142, gate spacer 114 and / or shallow trench isolation region 138) are illustrative and not intended to be limiting.

[0058] Figure 2 is a flowchart of an exemplary manufacturing method 200 for a semiconductor device 100 according to some embodiments. For illustrative purposes, the operation steps shown in Figure 2 will be described with reference to an exemplary process for manufacturing the semiconductor device 100 as shown in Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 8C, 8D, and 11C to 11E. Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A and 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B are cross-sectional views along lines AA and BB at various stages in the manufacturing process of the semiconductor device 100 according to some embodiments. The operation steps may be performed in a different order or not at all, depending on the specific application. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only a few other processes are briefly described herein. The components with the same annotations as those in the components in the figures 1A to 1Q are described above in figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 8C, 8D, and 11C to 11E.

[0059] In operation 205, the polycrystalline silicon structure and epitaxial fin region are formed on the fin structures of the n-type and p-type field-effect transistors. For example, as shown in Figures 3A and 3B, the polycrystalline silicon structure 312 can be formed on the fin structures 1081 and 1082, and the gate spacer 114 can be formed on the sidewall of the polycrystalline silicon structure 312. In subsequent processing, the polycrystalline silicon structure 312 can be replaced by a gate replacement process to form gate structures 112N1-112N4 and 112P1-112P4. In some embodiments, the formation process of the polycrystalline silicon structure 312 may include blanket deposition of a layer of polycrystalline silicon material on the fin structures 1081 and 1082, and etching the blanket deposition layer of polycrystalline silicon material through a patterned hard mask layer (not shown) formed on this layer of polycrystalline silicon material.

[0060] The blanket deposition step of the polycrystalline silicon material layer may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the etching step of the polycrystalline silicon material blanket deposition layer may include a dry etching process, a wet etching process, or a combination thereof. As shown in Figures 3A and 3B, after forming the polycrystalline silicon structure 312, gate spacers 114 may be formed on the sidewalls of the polycrystalline silicon structure 312.

[0061] Referring to Figures 3A and 3B, after forming the gate spacer 114, n-type and p-type epitaxial fin regions 110A and 110B can be selectively formed on the portions of the fin structures 1081 and 1082 that are not below the polycrystalline silicon structure 312 (e.g., nanostructure regions 120A and 122A).

[0062] Before forming the epitaxial fin region 110A, a photoresist layer (not shown) can be patterned on the p-type field-effect transistors 102P1-102P4 to protect the p-type field-effect transistors 102P1-102P4. The epitaxial fin region 110A can be grown on the nanostructure region 120A. In some embodiments, the epitaxial fin region 110A can be grown using (i) chemical vapor deposition, such as low pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), or any suitable chemical vapor deposition; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination of the foregoing. The n-type epitaxial fin region 110A may include Si but substantially has no Ge content (e.g., no Ge), and the n-type epitaxial fin region 110A may be in-situ doped using n-type dopants such as phosphorus or arsenic during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors such as, but not limited to, phosphine (PH3), arsine (AsH3) and / or other n-type doping precursors may be used.

[0063] After forming the epitaxial region 110A, the photoresist layer can be removed from the p-type field-effect transistors 102P1-102P4, and another photoresist layer (not shown) can be patterned on the n-type field-effect transistors 102N1-102N4 to protect the n-type field-effect transistors 102N1-102N4 during the subsequent processing step of forming the epitaxial region 110B. The epitaxial fin region 110B can be grown on the nanostructure region 122A. The epitaxial fin region 110B can be grown in a similar manner to the epitaxial fin region 110A, but a p-type dopant such as boron, indium, or gallium can be used during the epitaxial growth process to in-situ dope the epitaxial fin region 110B with SiGe. For p-type in-situ doping, p-type doping precursors such as, but not limited to, diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors can be used. After forming the epitaxial region 110B, the photoresist layer can be removed from the n-type field-effect transistors 102N1-102N4, and the contact etch stop layer 116 and the interlayer dielectric layer 118 can be formed to form the structure shown in Figures 3A and 3B.

[0064] Referring to Figure 2, in operation 210, gate openings are formed on and within one or more fin structures. For example, as shown in Figures 4A and 4B, gate openings 412N and 412P associated with n-type field-effect transistors 102N1-102N4 and p-type field-effect transistors 102P1-102P4 can be formed on and within fin structures 1081 and 1082, respectively. The steps for forming gate opening 412N may include the following sequential steps: (i) forming a photoresist layer (not shown) on the p-type field-effect transistors 102P1-102P4; (ii) etching the polycrystalline silicon structure 312 of the n-type field-effect transistors 102N1-102N4 from the structure in Figure 3A; and (iii) etching the nanostructure region 122B from the structure in Figure 3A. In some embodiments, the etching step of the nanostructure region 122B may include a dry etching process or a wet etching process that has higher selectivity for SiGe compared to Si. For example, a wet etching process may include using a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) and / or a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide, and deionized water (APM).

[0065] After forming gate opening 412N, gate opening 412P can be formed. The formation steps of gate opening 412P may include the following sequential steps: (i) removing the photoresist layer from p-type field-effect transistors 102P1-102P4; (ii) forming a photoresist layer (not shown) in gate opening 412N to protect nanostructure channel region 120B; (iii) etching the polycrystalline silicon structure 312 of p-type field-effect transistors 102P1-102P4; and (iv) etching nanostructure region 120B from the structure of Figure 3B. In some embodiments, the etching step of nanostructure region 120B may include using a wet etching process that has higher selectivity for Si compared to SiGe. For example, the wet etching process may include using a mixture (NH4OH) containing HCl. After forming gate opening 412P, the photoresist layer may be removed from gate opening 412N to form the structures of Figures 4A and 4B.

[0066] Referring to Figure 2, in operations 215 to 230, a fully wrapped gate structure is formed in the gate opening. For example, as described in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A and 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, using the steps described in operations 215 to 230, gate structures 112N1-112N4 and 112P1-112P4 can be formed to cover and surround the nanostructure channel regions 120B and 122B.

[0067] In operation 215, an interface oxide layer and a high-dielectric-constant gate dielectric layer are deposited and annealed within the gate openings. For example, as shown in Figures 5A and 5B, an interface oxide layer 127 and a gate dielectric layer 128 can be deposited and annealed on the nanostructure channel regions 120B and 122B within the gate openings 412N and 412P (shown in Figures 4A and 4B). As shown in Figures 1A to 1C, in subsequent processing, the high-dielectric-constant gate dielectric layer 128 can form high-dielectric-constant gate dielectric layers 128N1-128N4 and 128P1-128P4.

[0068] Interfacial oxide layers 127 can be formed on the exposed surfaces of nanostructure channel regions 120B and 122B within gate openings 412N and 412P, respectively. In some embodiments, the nanostructure channel regions 120B and 122B can be exposed to an oxidizing environment to form the interfacial oxide layers 127. For example, the oxidizing environment may include a combination of ammonium hydroxide, a mixture of hydrogen peroxide and water (SC1 solution), ozone (O3), and / or a mixture of hydrochloric acid, hydrogen peroxide, and water (SC2 solution). Due to the oxidation process, an oxide layer of about 0.5 nm to about 1.5 nm can be formed on the exposed surfaces of the nanostructure channel regions 120B and 122B.

[0069] The deposition step of the high-dielectric-constant gate dielectric layer 128 may include blanket deposition of the high-dielectric-constant gate dielectric layer 128 on a portion of the semiconductor device 100 (not shown) after the formation of the interface oxide layer 127. As shown in Figures 5A and 5B, the blanket-deposited high-dielectric-constant gate dielectric layer 128 may be substantially conformally deposited on the interface oxide layer 127 and on the exposed surfaces of the portion of the semiconductor device 100 (e.g., the sidewalls of gate openings 412N, 412P and the top surface of the interlayer dielectric layer 118). In some embodiments, the high-dielectric-constant gate dielectric layer 128 may include a dielectric material with a dielectric constant greater than about 3.9. In some embodiments, the high dielectric constant gate dielectric layer 128 may include (i) a high dielectric constant dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), or zirconium silicate (ZrSiO2); (ii) having lithium (Li), beryllium (Be), magnesium (Mg), or calcium ( High dielectric constant materials of oxides of Ca, Sr, Scandium, Yttrium, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dysprosium, Ho, Erbium, Tm, Yb, or Lu; or (iii) combinations thereof. In some embodiments, a high dielectric constant gate dielectric layer 128 may be formed by atomic layer deposition at a temperature between about 250°C and about 350°C using hafnium chloride (HfCl4) as a precursor. In some embodiments, the high dielectric constant gate dielectric layer 128 may have a thickness between about 1 nm and about 3 nm to cover the nanostructure channel regions 120B and 122B without being limited by the spacing between adjacent nanostructure channel regions 120B and adjacent nanostructure channel regions 122B.

[0070] Referring to Figure 2, in operation 220, a first doping process is selectively performed on the high-dielectric-constant gate dielectric layer portions of the first n-type field-effect transistor, the p-type field-effect transistor, and the second n-type field-effect transistor and the p-type field-effect transistor. For example, as shown in Figures 6A-6B, 7A-7B, and 8A-8D, rare-earth metal-based dopants can be used to dope the portions of the high-dielectric-constant gate dielectric layer 128 located within the gate openings 412N and 412P of the n-type field-effect transistors 102N1-102N2 and the p-type field-effect transistors 102P1-102P2 to form dipole layers 129N1*, 129N2 and 129P1*, 129P2. The first doping process may include the following sequential steps: (i) blanket deposition of a rare earth metal substrate 644 on the structure of Figures 5A and 5B (Figures 6A and 6B); (ii) patterning the rare earth metal substrate 644 as shown in Figures 7A and 7B to form a patterned rare earth metal substrate 644* on the portion of the high dielectric constant gate dielectric layer 128 located between the gate openings 412N and 412P of the n-type field-effect transistors 102N1-102N2 and the p-type field-effect transistors 102P1-102P2; (iii) performing a drive-in annealing process (first drive-in annealing process) on the patterned rare earth metal substrate 644* as shown in Figures 7A and 7B; and (iv) removing the patterned rare earth metal substrate 644* to form the structure of Figures 8A and 8B.

[0071] The blanket deposition step of the rare earth metal substrate 644 may include blanket deposition of a rare earth metal substrate 644 with a thickness of about 0.05 nm to about 0.4 nm on a high dielectric constant gate dielectric layer 128 using atomic layer deposition or chemical vapor deposition processes. The rare earth metal substrate 644 may include (i) rare earth metals, such as lanthanum (La), yttrium (Y), cerium (Ce), ytterbium (Yb), erbium (Er), or combinations thereof and / or (ii) oxides of rare earth metals, such as lanthanum oxide (La2O3), yttrium oxide (Y2O3), cerium oxide (CeO2), ytterbium oxide (Yb2O3), erbium oxide (Er2O3), or combinations thereof. The patterning step of the rare earth metal substrate 644 may include using photolithography and etching processes. In some embodiments, the etching process may include a chemical etching step using an acid group (e.g., using HCl). The first induction annealing process may include annealing a patterned rare earth metal substrate 644* at a temperature of about 550°C to about 850°C and a pressure of about 1 to 30 tor for a period of about 0.1 seconds to about 30 seconds. In some embodiments, the first induction annealing process may include two annealing processes: (i) a soak annealing process at a temperature of about 550°C to about 850°C for about 2 seconds to about 60 seconds; and (ii) a spike annealing process at a temperature of about 700°C to about 900°C for about 0.1 seconds to about 2 seconds.

[0072] After the first penetration annealing process, the doped portion of the high-dielectric-constant gate dielectric layer 128 located within the gate openings 412N and 412P of the n-type field-effect transistors 102N1-102N1 and the p-type field-effect transistors 102P1-102P2 may have a rare-earth metal-based dopant concentration C2 as discussed above with reference to Figures 1A-1C and 1H, 1I. In some embodiments, as shown in Figures 8A and 8B, after the first penetration annealing process, dipole layers 129N1*, 129N2 and 129P1*, 129P2 may be formed at the interface between the interface oxide layer 127 and the doped portion of the high-dielectric-constant gate dielectric layer 128. The dipole layers 129N1*, 129N2 and 129P1*, 129P2 may have a rare-earth metal-based dipole concentration D2 as discussed above with reference to Figures 1J-1M.

[0073] In some embodiments, after the first drive-in process, the high-dielectric-constant gate dielectric layer 128, the rare-earth metal-based dipole layers 129N1*, 129N2, the interface oxide layer 127, and the rare-earth metal-based dopants in the nanostructure channel region 120B of the n-type field-effect transistors 102N1-102N2 may have a gradual doping profile along line segments J and / or K of Figure 8A (as shown in Figure 8C). Similarly, the high-dielectric-constant gate dielectric layer 128, the rare-earth metal-based dipole layers 129P1*, 129P2, the interface oxide layer 127, and the rare-earth metal-based dopants in the nanostructure channel region 122B of the p-type field-effect transistors 102P1-102P2 may have a gradual doping profile along line segments L and / or M of Figure 8B (as shown in Figure 8C).

[0074] In some embodiments, after the first induction process, the interface between the high-dielectric-constant gate dielectric layer 128 of the n-type field-effect transistor gate structure 112N1-112N4 and the interface oxide layer 127 may have rare-earth metal-based dopant concentrations B1'-B4' as shown in Figure 8D, wherein concentration B1' is equal to concentration B2' and concentrations B3' and B4' are equal to 0. Concentrations B1' and B2' may depend on the thickness of the rare-earth metal substrate 644 and / or the first induction annealing temperature.

[0075] Referring to Figure 2, in operation 225, a second doping process is selectively performed on the high-dielectric-constant gate dielectric layer portions of the first n-type field-effect transistor, the p-type field-effect transistor, and the third n-type field-effect transistor and the p-type field-effect transistor. For example, as shown in Figures 9A-9B, 10A-10B, and 11A-11E, rare-earth metal-based dopants can be used to dope the portions of the high-dielectric-constant gate dielectric layer 128 located within the gate openings 412N and 412P of the n-type field-effect transistors 102N1 and 102N3 and the p-type field-effect transistors 102P1 and 102P3 to form dipole layers 129N1, 129N3 and 129P1, 129P3. The second doping process may include the following sequential steps: (i) blanket deposition of a rare earth metal substrate 646 on the structure of Figures 8A and 8B (Figures 9A and 9B); (ii) patterning the rare earth metal substrate 646 as shown in Figures 10A and 10B to form a patterned rare earth metal substrate 646* on a portion of the high dielectric constant gate dielectric layer 128 located between the gate openings 412N and 412P of the n-type field-effect transistors 102N1 and 102N3 and the p-type field-effect transistors 102P1 and 102P3; (iii) performing a drive-in annealing process on the patterned rare earth metal substrate 646* as shown in Figures 10A and 10B (second drive-in annealing process); and (iv) removing the patterned rare earth metal substrate 646* to form the structure of Figures 11A and 11B.

[0076] The blanket deposition and patterning steps of the rare earth metal substrate 646 may be similar to those of the rare earth metal substrate 644. In some embodiments, the rare earth metal substrate 646 may have a material and / or structural composition similar to or different from that of the rare earth metal substrate 644. In some embodiments, the drive-in annealing step of the patterned rare earth metal substrate 646* may be similar to or different from the drive-in annealing step of the patterned rare earth metal substrate 644*. In some embodiments, the temperature of the first drive-in annealing process (e.g., a temperature between about 550°C and about 850°C) is higher than the temperature of the second drive-in heating process (e.g., a temperature between about 550°C and about 700°C). Following the second drive-in annealing process in the second doping process, the rare-earth metal-based dopant concentration of the doped portion of the high-k dielectric gate layer 128 located within the gate openings 412N and 412P of the n-type field-effect transistor 102N1 and the p-type field-effect transistor 102P1 increases from concentration C2 to concentration C1 due to the first and second doping processes. Furthermore, the doped portion of the high-k dielectric gate layer 128 located within the gate openings 412N and 412P of the n-type field-effect transistor 102N3 and the p-type field-effect transistor 102P3 may have a rare-earth metal-based dopant concentration C3 as discussed above with reference to Figures 1A-1C and 1H, 1I. In some embodiments, after the second drive-in annealing process of the second doping process, the dipole layers 129N1, 129N3, 129P1 and 129P3 shown in Figures 11A and 11B may be formed at the interface between the high dielectric constant gate dielectric layer 128 doped in the second doping process and the interface oxide layer 127.

[0077] In some embodiments, after the second drive-in process, the rare earth metal-based dopants in the high-dielectric-constant gate dielectric layer 128, the rare earth metal-based dipole layers 129N1-129N3, the interface oxide layer 127, and the nanostructure channel region 120B of the n-type field-effect transistors 102N1-102N3 may have a gradually changing doping profile along the line segments N, O, and / or P of Figure 11A (dashed lines in Figure 11C). Figure 11C illustrates that, compared to the rare earth metal-based dopant concentration in the high-dielectric-constant gate dielectric layer 128 and the interface oxide layer 127 after the first drive-in annealing process, the rare earth metal-based dopant concentration may decrease in the high-dielectric-constant gate dielectric layer 128 and increase in the interface oxide layer 127 after the second drive-in annealing process. Similar to n-type field-effect transistors 102N1-102N3, after the second drive-in process, the high-dielectric-constant gate dielectric layer 128, the rare-earth metal-based dipole layers 129P1-129P3, the interface oxide layer 127, and the rare-earth metal-based dopants in the nanostructure channel region 122B of p-type field-effect transistors 102P1-102P3 may have a gradually changing doping profile along the line segments Q, R, and / or S in Figure 11B.

[0078] Referring to Figures 11D and 11E, in some embodiments, after the second induction process, the concentration of rare earth metal matrix dopant at the interface between the high dielectric constant gate dielectric layer 128 and the interface oxide layer 127 of the n-type field-effect transistor gate structure 112N1-112N4 can be increased from concentration B1' to concentration B1 or concentration B5, from concentration B2' to concentration B2 or concentration B6, and from concentration B3' to concentration B3 or concentration B7. In some embodiments, when the rare earth metal substrate 646* is thicker than the rare earth metal substrate 644* and / or the second induction annealing temperature is greater than the first induction annealing temperature, concentrations B5 and B7 can be greater than concentrations B1 and B3, respectively.

[0079] Referring to Figure 2, in operation 230, a gate work function metal layer and a gate metal filler layer are formed on a high-dielectric-constant gate dielectric layer. For example, as shown in Figures 12A and 12B, a gate work function metal layer 130 and a gate metal filler layer 132 can be formed on the structures shown in Figures 11A and 11B. The material of the gate work function metal layer 130 can be deposited in a blanket deposition on the structures shown in Figures 11A and 11B, and the material of the gate metal filler layer 132 can be deposited in a blanket deposition on the material of the gate work function metal layer 130. After these blanket deposition steps, a chemical mechanical polishing process can be used to polish the high-dielectric-constant gate dielectric layer 128, the material of the gate work function metal layer 130, and the material of the gate metal filler layer 132 to form the structures shown in Figures 12A and 12B. Therefore, as described in operations 215 to 230, using a dual rare-earth metal substrate and a dual doping process, gate structures 112N1-112N4 and 112P1-112P4 can be formed with at least four different rare-earth metal substrate dopant concentrations and rare-earth metal substrate dipole concentrations, such that gate structures 112N1-112N4 and 112P1-112P4 have at least four different critical voltages.

[0080] This invention provides exemplary field-effect transistor (FET) structures with gate structures having different effective work function values ​​(e.g., n-type FETs 102N1-102N4 and p-type FETs 102P1-102P4) to provide different and / or low threshold voltages, and provides exemplary methods for forming these FETs on the same substrate. These exemplary methods form FETs with different conductivity types and different effective work function values ​​without increasing the thickness of the work function metal layer. Compared to other methods for forming FETs with similar channel sizes and threshold voltages on the same substrate, these exemplary methods are less complex and more cost-effective in fabricating reliable gate structures in FETs with nanostructured channel regions and different and / or low threshold voltages. Furthermore, compared to other methods for forming FETs with similar threshold voltages, these exemplary methods can form FET gate structures with smaller dimensions (e.g., thinner gate stacks).

[0081] In some embodiments, n-type and p-type field-effect transistors (FETs) with different gate structure configurations can be selectively formed on the same substrate. To enable the n-type and p-type FETs to have different and / or low critical voltages, high-dielectric-constant gate dielectric layers (e.g., high-dielectric-constant gate dielectric layers 128N1-128N4 and 128P1-128P4) can be doped with different concentrations of rare-earth metal-based dopants in the gate structures of the n-type and p-type FETs. Different concentrations of rare-earth metal-based dopants can generate dipole layers with varying dipole concentrations (e.g., dipole layers 129N1-129N4 and 129P1-129P4) in the gate structures of the n-type and p-type FETs. Tuning the dipole concentration can tune the effective work function value of the gate structures of the n-type and p-type FETs, and thus adjust the critical voltages of the n-type and p-type FETs. In this way, without increasing the thickness of the work function metal layer, n-type and p-type field-effect transistors with different and / or low critical voltages can be obtained.

[0082] In some embodiments, a method of manufacturing a semiconductor device includes: forming a nanostructure channel region in a fin structure; depositing a high-k dielectric gate dielectric layer surrounding the nanostructure channel region; selectively performing a first doping process using rare-earth metal-based dopants on a first portion and a second portion of the high-k dielectric gate dielectric layer; and selectively performing a second doping process using rare-earth metal-based dopants on the first portion and a third portion of the high-k dielectric gate dielectric layer. The first doping process dops the first and second portions of the high-k dielectric gate dielectric layer with a first rare-earth metal-based dopant concentration. The second doping process dops the first and third portions of the high-k dielectric gate dielectric layer with a second rare-earth metal-based dopant concentration different from the first rare-earth metal-based dopant concentration. The method of manufacturing a semiconductor device further includes depositing a work function metal layer on the high-k dielectric gate dielectric layer and depositing a gate metal filler layer on the work function metal layer. In some embodiments, the step of selectively performing the first doping process includes selectively forming a rare earth metal substrate on a first portion and a second portion of a high-dielectric-constant gate dielectric layer, and performing a drive-in annealing process on the rare earth metal substrate. In some embodiments, the step of selectively forming the rare earth metal substrate includes depositing a rare earth metal base material on the high-dielectric-constant gate dielectric layer, and selectively etching the portion of the rare earth metal base material located on a third portion of the high-dielectric-constant gate dielectric layer. In some embodiments, the step of depositing the rare earth metal base material includes depositing a layer of lanthanum oxide. In some embodiments, the step of performing the drive-in annealing process includes annealing the rare earth metal substrate at a temperature of about 550°C to about 850°C. In some embodiments, the step of selectively forming the rare earth metal substrate includes depositing a rare earth metal base material on the high-dielectric-constant gate dielectric layer, and selectively etching the portion of the rare earth metal base material located on a second portion of the high-dielectric-constant gate dielectric layer. In some embodiments, the step of performing a drive-in annealing process includes holding the rare earth metal substrate at a temperature of about 550°C to about 800°C, and performing a spike annealing of the rare earth metal substrate at a temperature of about 700°C to about 900°C. In some embodiments, the step of selectively performing a second doping process includes selectively forming a rare earth metal substrate on a first portion and a third portion of a high-dielectric-constant gate dielectric layer, and performing a drive-in annealing process on the rare earth metal substrate. In some embodiments, the step of selectively performing a second doping process includes doping the first portion and the third portion of the high-dielectric-constant gate dielectric layer with a second rare earth metal base dopant concentration, wherein the second rare earth metal base dopant concentration is less than the first rare earth metal base dopant concentration. In some embodiments, the step of selectively performing a second doping process includes doping the first portion and the third portion of the high-dielectric-constant gate dielectric layer with a second rare earth metal base dopant concentration, wherein the second rare earth metal base dopant concentration is greater than the first rare earth metal base dopant concentration.

[0083] In some embodiments, a method for manufacturing a semiconductor device includes: forming a first fin structure and a second fin structure of an n-type field-effect transistor and a p-type field-effect transistor, respectively; forming a first nanostructure channel region and a second nanostructure channel region in the first fin structure and the second fin structure, respectively; depositing a high-dielectric-constant gate dielectric layer surrounding the first nanostructure channel region and the second nanostructure channel region; selectively forming a first rare-earth metal substrate on a first portion and a second portion of the high-dielectric-constant gate dielectric layer located on the first nanostructure channel region and the second nanostructure channel region; performing a first annealing process on the first rare-earth metal substrate; selectively forming a second rare-earth metal substrate on a first portion and a third portion of the high-dielectric-constant gate dielectric layer located on the first nanostructure channel region and the second nanostructure channel region; performing a second annealing process on the second rare-earth metal substrate; depositing a work function metal layer on the high-dielectric-constant gate dielectric layer; and depositing a gate metal filling layer on the work function metal layer. In some embodiments, the method of manufacturing a semiconductor device further includes forming an interface oxide layer surrounding the first nanostructure channel region and the second nanostructure channel region. In some embodiments, the step of selectively forming a first rare earth metal base layer includes depositing a rare earth metal base material on a high-dielectric-constant gate dielectric layer, and selectively etching a portion of the rare earth metal base material on a third portion of the high-dielectric-constant gate dielectric layer, the third portion being located on the first nanostructure channel region and the second nanostructure channel region. In some embodiments, the step of depositing the rare earth metal base material includes depositing a layer of lanthanum oxide. In some embodiments, the step of selectively forming a first rare earth base layer includes depositing a first layer of rare earth metal base material on a high-dielectric-constant gate dielectric layer, wherein the step of selectively forming a second rare earth metal base layer includes depositing a second layer of rare earth metal base material on the high-dielectric-constant gate dielectric layer, and wherein the first layer of rare earth metal base material is thicker than the second layer of rare earth metal base material. In some embodiments, the step of performing a first annealing process includes annealing the first rare earth metal base layer at a first temperature, and the step of performing a second annealing process includes annealing the second rare earth metal base layer at a second temperature different from the first temperature.

[0084] In some embodiments, the semiconductor device includes a first gate structure, a second gate structure, and a third gate structure. The first gate structure includes: a first interface oxide layer; a first high-dielectric-constant gate dielectric layer disposed on the first interface oxide layer, the first high-dielectric-constant gate dielectric layer having a first rare-earth metal oxide dopant concentration; and a first dipole layer disposed at the interface between the first interface oxide layer and the first high-dielectric-constant gate dielectric layer, the first dipole layer having a first rare-earth metal dipole concentration. The second gate structure includes: a second interface oxide layer; a second high-dielectric-constant gate dielectric layer disposed on the second interface oxide layer, the second high-dielectric-constant gate dielectric layer having a second rare-earth metal oxide dopant concentration; and a second dipole layer disposed at the interface between the second first interface oxide layer and the second high-dielectric-constant gate dielectric layer, the second dipole layer having a second rare-earth metal dipole concentration. The third gate structure includes: a third interface oxide layer; a third high-dielectric-constant gate dielectric layer disposed on the third interface oxide layer, the third high-dielectric-constant gate dielectric layer having a third rare-earth metal oxide dopant concentration; and a third dipole layer disposed at the interface between the third interface oxide layer and the third high-dielectric-constant gate dielectric layer, the third dipole layer having a third rare-earth metal dipole concentration. The first rare-earth metal oxide dopant concentration, the second rare-earth metal oxide dopant concentration, and the third rare-earth metal oxide dopant concentration are different from each other, and the first rare-earth metal dipole concentration, the second rare-earth metal dipole concentration, and the third rare-earth metal dipole concentration are also different from each other. In some embodiments, the effective work function values ​​of the first gate structure, the second gate structure, and the third gate structure are different from each other. In some embodiments, the first gate structure, the second gate structure, and the third gate structure are fully wound gate structures. In some embodiments, the first gate structure, the second gate structure, and the third gate structure have gate work function metal layers of similar thickness.

[0085] The components of several embodiments have been outlined above to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0086] 100: Semiconductor devices

[0087] 102N1, 102N2, 102N3, 102N4: n-type field-effect transistors

[0088] 102P1, 102P2, 102P3, 102P4: p-type field-effect transistors

[0089] 106:Substrate

[0090] 1081, 1082: Fin structure

[0091] 108A1, 108A2: Fin base

[0092] 108B1, 108B2: Stacked fin section

[0093] 110A, 110B: Epitaxial Fin Region

[0094] 112N1, 112N2, 112N3, 112N4, 112P1, 112P2, 112P3, 112P4: Gate structure

[0095] 114: Gate spacer

[0096] 116: Contact Etching Stop Layer

[0097] 118: Interlayer dielectric layer

[0098] 120: First semiconductor layer

[0099] 120A, 122A: Nanostructure Regions

[0100] 120B, 122B: Nanostructured channel region

[0101] 122: Second semiconductor layer

[0102] 126A, 126B: Source / Drain Regions

[0103] 127: Interface oxide layer

[0104] 128, 128N1, 128N2, 128N3, 128N4, 128P1, 128P2, 128P3, 128P4: High dielectric constant gate dielectric layers

[0105] 129N1, 129N1*, 129N2, 129N3, 129P1, 129P1*, 129P2, 129P3: Rare earth metal-based dipole layers

[0106] 130: Gate work function metal layer

[0107] 132: Gate metal filler layer

[0108] 138: Shallow trench isolation zone

[0109] 142: Internal spacer

[0110] 200: Method

[0111] 205,210,215,220,225,230: Operations

[0112] 312: Polycrystalline silicon structure

[0113] 412N, 412P: Gate Opening

[0114] 644,644*,646,646*: Rare earth metal base layer

[0115] AA,BB,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S: line segments

[0116] B1,B1',B2,B2',B3,B3',B4,B4',B5,B6,B7,C1,C2,C3,C4: Rare earth metal-based dopant concentration

[0117] D1, D2, D3, D4: Rare earth metal-based dipole concentrations

[0118] D5, D6, D7, D8: Aluminum-based dipole concentration

[0119] TN1, TN2, TN3, TN4, TN5, TN6, TN7, TN8, TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8: Critical Voltage

[0120] W1, W2, W3, W4, W5, W6, W7, W8: Effective work function values

Claims

1. A method for manufacturing a semiconductor device, comprising: Multiple nanostructured channel regions are formed within a single fin structure; An interface oxide layer is deposited surrounding the nanostructure channel regions; a high-dielectric-constant gate dielectric layer is deposited surrounding the interface oxide layer; a first doping process using a rare-earth metal-based dopant is selectively performed on a plurality of first portions and a plurality of second portions of the high-dielectric-constant gate dielectric layer, wherein the first doping process dops the first portions and the second portions of the high-dielectric-constant gate dielectric layer with a first rare-earth metal-based dopant concentration; A second doping process using a rare-earth metal-based dopant is selectively performed on the first portions and multiple third portions of the high-dielectric-constant gate dielectric layer, wherein the second doping process dops the first portions and third portions of the high-dielectric-constant gate dielectric layer with a second rare-earth metal-based dopant concentration that differs from the first rare-earth metal-based dopant concentration, wherein the first portions of the high-dielectric-constant gate dielectric layer, the interface oxide layer, and the nanostructure channel regions include the rare-earth metal-based dopant having a gradient doping profile; a work function metal layer is deposited on the high-dielectric-constant gate dielectric layer; and a gate metal filling layer is deposited on the work function metal layer.

2. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of selectively performing the first doping process includes: A rare earth metal substrate is selectively formed on the first and second portions of the high dielectric constant gate dielectric layer; And a drive-in annealing process is performed on the rare earth metal substrate.

3. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of selectively forming the rare earth metal substrate includes: A rare earth metal-based material is deposited on the high dielectric constant gate dielectric layer; And selectively etching portions of the rare earth metal base material located on the third portions of the high dielectric constant gate dielectric layer.

4. A method for manufacturing a semiconductor device, comprising: Multiple first fin structures and multiple second fin structures are formed for n-type and p-type field-effect transistors, respectively; multiple first nanostructure channel regions and multiple second nanostructure channel regions are formed in the first fin structures and the second fin structures, respectively; an interface oxide layer is deposited, the interface oxide layer surrounding the first nanostructure channel regions and the second nanostructure channel regions; a high-dielectric-constant gate dielectric layer is deposited, the high-dielectric-constant gate dielectric layer surrounding the interface oxide layer; a first rare-earth metal base layer is selectively formed on multiple first portions and multiple second portions of the high-dielectric-constant gate dielectric layer located on the first nanostructure channel regions and the second nanostructure channel regions; a first annealing process is performed on the first rare-earth metal base layer; a second rare-earth metal base layer is selectively formed on multiple third portions of the high-dielectric-constant gate dielectric layer located on the first portions and multiple third portions of the high-dielectric-constant gate dielectric layer located on the first nanostructure channel regions and the second nanostructure channel regions; A second annealing process is performed on the second rare earth metal substrate, wherein the first portions of the high dielectric constant gate dielectric layer, the interface oxide layer, the first nanostructure channel regions and the second nanostructure channel regions include rare earth metal base dopants with a gradient doping profile; a work function metal layer is deposited on the high dielectric constant gate dielectric layer; and a gate metal filling layer is deposited on the work function metal layer.

5. A method for manufacturing a semiconductor device as claimed in claim 4, wherein the step of selectively forming the first rare earth base layer includes depositing a first layer of rare earth metal base material on the high dielectric constant gate dielectric layer; wherein the step of selectively forming the second rare earth metal base layer includes depositing a second layer of rare earth metal base material on the high dielectric constant gate dielectric layer, and wherein the first layer of rare earth metal base material is thicker than the second layer of rare earth metal base material.

6. A semiconductor device, comprising: Multiple nanostructured channel regions; A first gate structure surrounding the nanostructure channel regions, the first gate structure comprising: a first interface oxide layer; a first high-dielectric-constant gate dielectric layer disposed on the first interface oxide layer, the first high-dielectric-constant gate dielectric layer having a first rare-earth metal oxide dopant concentration, wherein the first high-dielectric-constant gate dielectric layer, the first interface oxide layer, and the nanostructure channel regions include a rare-earth metal base dopant having a gradient doping profile; and a first dipole layer disposed at an interface between the first interface oxide layer and the first high-dielectric-constant gate dielectric layer, the first dipole layer having a first rare-earth metal dipole concentration; and a second gate structure surrounding the nanostructure channel regions, the second gate structure comprising: a second interface oxide layer; A second high-dielectric-constant gate dielectric layer is disposed on the second interface oxide layer, the second high-dielectric-constant gate dielectric layer having a second rare-earth metal oxide dopant concentration; a second dipole layer is disposed at an interface between the second interface oxide layer and the second high-dielectric-constant gate dielectric layer, the second dipole layer having a second rare-earth metal dipole concentration; and a third gate structure surrounds the nanostructure channel regions, the third gate structure comprising: a third interface oxide layer; a third high-dielectric-constant gate dielectric layer is disposed on the third interface oxide layer, the third high-dielectric-constant gate dielectric layer having a third rare-earth metal oxide dopant concentration; and a third dipole layer is disposed at an interface between the third interface oxide layer and the third high-dielectric-constant gate dielectric layer, the third dipole layer having a third rare-earth metal dipole concentration; wherein the first rare-earth metal oxide dopant concentration, the second rare-earth metal oxide dopant concentration, and the third rare-earth metal oxide dopant concentration are different from each other. Furthermore, the first rare earth metal dipole concentration, the second rare earth metal dipole concentration, and the third rare earth metal dipole concentration are different from each other.

7. A semiconductor device, comprising: One substrate; A fin structure is disposed on the substrate; A stack of nanostructure layers is disposed on the fin structure, wherein the stack of nanostructure layers includes multiple nanostructure channel regions; A gate structure surrounding the nanostructure channel region, wherein the gate structure includes: an oxide layer surrounding the nanostructure channel region; A high-dielectric-constant gate dielectric layer is disposed on the oxide layer, wherein the high-dielectric-constant gate dielectric layer, the oxide layer, and the nanostructure channel regions include a rare-earth metal-based dopant with a gradient doping profile; a metal dipole layer is disposed between the oxide layer and the high-dielectric-constant gate dielectric layer; and an epitaxial semiconductor layer is stacked around the portion of the nanostructure layer that is not covered by the gate structure.

8. A semiconductor device, comprising: Multiple nanostructured channel regions; A first gate structure surrounding the nanostructure channel regions includes: a first oxide layer; a first gate dielectric layer disposed on the first oxide layer, wherein the first gate dielectric layer, the first oxide layer, and the nanostructure channel regions include a rare-earth metal-based dopant having a gradient doping profile; and a first dipole layer disposed between the first oxide layer and the first gate dielectric layer, the first dipole layer having a first dipole concentration; and a second gate structure surrounding the nanostructure channel regions includes: a second oxide layer; a second gate dielectric layer disposed on the second oxide layer; and a second dipole layer disposed between the second oxide layer and the second gate dielectric layer, the second dipole layer having a second dipole concentration, wherein the first dipole concentration and the second dipole concentration are different from each other.

9. A semiconductor device, comprising: An n-type transistor has a first gate structure surrounding a plurality of nanostructure channel regions, the first gate structure comprising: a first oxide layer; and a first gate dielectric layer disposed on the first oxide layer, the first gate dielectric layer having a first concentration of rare earth metal-based dopant, wherein the first concentration, the first oxide layer, and the nanostructure channel regions have a gradient doping profile of the rare earth metal-based dopant; and a p-type transistor has a second gate structure surrounding the nanostructure channel regions, the second gate structure comprising: a second oxide layer; and a second gate dielectric layer disposed on the second oxide layer, the second gate dielectric layer having a second concentration of the rare earth metal-based dopant, wherein the first concentration and the second concentration are different from each other.

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