Gate driver

Abstract

A gate drive circuit. The gate drive circuit includes a timing input circuit, a timing output circuit, a first mode selection circuit, a drive output circuit, a second mode selection circuit, a control circuit, and a voltage regulator circuit. The timing input circuit provides a first control voltage based on a first subsequent shielding signal. The timing output circuit provides a timing signal based on the first control voltage. The first mode selection circuit provides a second control voltage based on the first control voltage, a first local shielding signal, and a second local shielding signal. The drive output circuit provides a drive output signal based on the second control voltage. The control circuit and the second mode selection circuit provide a regulated control voltage based on a second subsequent shielding signal, so as to regulate the first control voltage, the second control voltage, the timing signal, and the drive output signal via the voltage regulator circuit.

Description

Technical Field

[0001] This invention relates to a gate drive circuit, and more particularly to a gate drive circuit with the ability to adjust the refresh frequency. Prior Technology

[0002] Progressive scan is a display technology commonly used in modern digital displays. It continuously scans all pixels of an image from top to bottom, line by line, resulting in a more stable and clearer image without the flickering common in interlaced scanning. However, the fixed update mechanism of progressive scan refreshes at the same frequency regardless of whether the image content changes, leading to wasted power consumption when displaying static images.

[0003] To meet user needs, monitors adjust their refresh rates based on the content. Dynamic areas (such as animations or videos) use higher refresh rates to maintain smooth visuals, while static areas (such as text content or social media interfaces) use lower refresh rates to further reduce the dynamic power consumption of the drive circuitry and improve overall energy efficiency. Therefore, meeting user needs is a key challenge in monitor design. Summary of the Invention

[0004] This invention provides a gate drive circuit that can shield scanning signals at a specific frame rate to reduce the number of frame refreshes.

[0005] The gate drive circuit of the present invention includes a timing input circuit, a timing output circuit, a first mode selection circuit, a drive output circuit, a second mode selection circuit, a control circuit, and a voltage regulator circuit. The timing input circuit receives a first timing signal, a second timing signal, a system high voltage, and a first subsequent shielding signal to provide a first control voltage. The timing output circuit is coupled to the timing input circuit to receive the first control voltage and a clock signal to provide a third timing signal. The first mode selection circuit is coupled to the timing input circuit to receive the first control voltage and the second timing signal, a first local shielding signal, a system high voltage, a second local shielding signal, and the third timing signal to provide a second control voltage. The drive output circuit is coupled to the first mode selection circuit and receives a clock signal to provide a drive output signal. The control circuit receives the first control voltage, the system high voltage, and the system low voltage to provide a regulated control voltage. The second mode selection circuit is coupled to the regulated control voltage and receives a second subsequent shielding signal and a system low voltage to set the regulated control voltage based on the second subsequent shielding signal and the system low voltage. The voltage regulator circuit is coupled to a first control voltage, a third timing signal, a second control voltage, and a drive output signal, and receives a regulated control voltage, a system high voltage, and a first timing signal. It pulls up the first control voltage, the third timing signal, the second control voltage, and the drive output signal to the system high voltage based on the regulated control voltage, and pulls up the drive output signal to the system high voltage based on the first timing signal.

[0006] Based on the above, the gate driving circuit of this embodiment of the invention, through the first mode selection circuit, can determine whether the first control voltage is transmitted to the drive output circuit, that is, whether the drive output signal is output; on the other hand, through the first subsequent shielding signal and the second mode selection circuit, it can determine whether the first control voltage is set, that is, whether the third timing signal is output. In this way, the gate driving circuit can shield the drive output signal for a specific number of frames (i.e., the scan signal for a specific number of outputs), thereby reducing the number of frame refreshes for a specific column / area, and maintaining the state of the previous frame through the internal storage structure / element of the pixel.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figure 1 is a schematic diagram of a gate drive circuit according to an embodiment of the present invention. Figure 2 is a schematic diagram of the driving timing of a gate drive circuit according to an embodiment of the present invention. Figures 3A to 3C are schematic diagrams of the operation of a gate drive circuit in timing scan mode according to an embodiment of the present invention. Figures 4A to 4C are schematic diagrams of the operation of a gate drive circuit in local shielded scanning mode according to an embodiment of the present invention. Figures 5A to 5B are schematic diagrams of the operation of a gate drive circuit according to an embodiment of the present invention in a subsequent shielded scanning mode. Implementation

[0009] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0010] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, “first element,” “component,” “region,” “layer,” or “part” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0011] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “or” signifies “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0012] Figure 1 is a system schematic diagram of a gate drive circuit according to an embodiment of the present invention. Referring to Figure 1, in this embodiment, the gate drive circuit 100 includes a timing input circuit 110, a timing output circuit 120, a first mode selection circuit 130, a drive output circuit 140, a second mode selection circuit 150, a control circuit 160, and a voltage regulator circuit 170.

[0013] The timing input circuit 110 receives timing signals Carry[n+1] (corresponding to the first timing signal), Carry[n-1] (corresponding to the second timing signal), the system high voltage VDD, and the shielding signal Mask2 (corresponding to the first subsequent shielding signal) to provide a control voltage Cn (corresponding to the first control voltage). The timing output circuit 120 is coupled to the timing input circuit 110 to receive the control voltage Cn and the clock signal CLK[n] to provide the timing signal Carry[n] (corresponding to the third timing signal), where n is a positive integer.

[0014] The first mode selection circuit 130 is coupled to the timing input circuit 110 to receive the control voltage Cn, and also receives the timing signal Carry[n-1], the mask signal Mask1 (corresponding to the first local mask signal), the system high voltage VDD, the mask signal Mask1b (corresponding to the second local mask signal), and the timing signal Carry[n] to provide the control voltage Qn (corresponding to the second control voltage). The drive output circuit 140 is coupled to the first mode selection circuit 130 and receives the clock signal CLK[n] to provide the drive output signal Out[n].

[0015] The control circuit 160 receives the control voltage Cn, the system high voltage VDD, and the system low voltage VSS to provide the regulated control voltage Qbn. The second mode selection circuit 150 is coupled to the regulated control voltage Qbn and receives the mask signal Mask2b (corresponding to the second subsequent mask signal) and the system low voltage VSS to set the regulated control voltage Qbn based on the mask signal Mask2b and the system low voltage VSS.

[0016] The voltage regulator circuit 170 is coupled to the control voltages Cn and Qn, the timing signal Carry[n], and the drive output signal Out[n]. It also receives the regulated control voltage Qbn, the system high voltage VDD, and the timing signal Carry[n+1]. Based on the regulated control voltage Qbn, it pulls the control voltages Cn and Qn, the timing signal Carry[n], and the drive output signal Out[n] to the system high voltage VDD. Based on the timing signal Carry[n+1], it pulls the drive output signal Out[n] to the system high voltage VDD.

[0017] Based on the above, the first mode selection circuit 130 determines whether the control voltage Cn is transmitted to the drive output circuit 140, which in turn determines whether the drive output signal Out[n] is output. On the other hand, the masking signal Mask2 and the second mode selection circuit 150 determine whether the control voltage Cn is set, which in turn determines whether the timing signal Carry[n] is output. In this way, the gate drive circuit 100 can mask the drive output signal Out[n] of a specific number of frames (i.e., the scan signal of a specific number of outputs) to reduce the number of frame refreshes in a specific column / area, and maintain the state of the previous frame through the internal storage structure / element of the pixel.

[0018] In this embodiment, the timing input circuit 110 includes, for example, transistors MP1 and MP2 (corresponding to the first and second transistors). Transistor MP1 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the timing signal Carry[n+1], and a second terminal for providing the control voltage Cn. Transistor MP2 has a first terminal coupled to the second terminal of transistor MP1, a control terminal for receiving the timing signal Carry[n-1], and a second terminal for receiving the mask signal Mask2.

[0019] In this embodiment, the timing output circuit 120 includes a transistor MP3 (corresponding to a third transistor) and a capacitor C1 (corresponding to a first capacitor). The transistor MP3 has a first terminal that provides a timing signal Carry[n], a control terminal that receives a control voltage Cn, and a second terminal that receives a clock signal CLK[n]. The capacitor C1 is coupled between the first terminal and the control terminal of the transistor MP3.

[0020] In this embodiment, the first mode selection circuit 130 includes transistors MP4 to MP7 (corresponding to the fourth to seventh transistors). Transistor MP4 has a first terminal for receiving control voltage Cn, a control terminal, and a second terminal for providing control voltage Qn. Transistor MP5 has a first terminal coupled to the control terminal of transistor MP4, a control terminal for receiving timing signal Carry[n-1], and a second terminal for receiving mask signal Mask1. Transistor MP6 has a first terminal for receiving system high voltage VDD, a control terminal for receiving mask signal Mask1b, and a second terminal. Transistor MP7 has a first terminal coupled to the second terminal of transistor MP6, a control terminal for receiving timing signal Carry[n], and a second terminal coupled to the second terminal of the fourth transistor MP4.

[0021] In this embodiment, the drive output circuit 140 includes a transistor MP8 (corresponding to the eighth transistor) and a capacitor C2 (corresponding to the second capacitor). The transistor MP8 has a first terminal for receiving the drive output signal Out[n], a control terminal for receiving the control voltage Qn, and a second terminal for receiving the clock signal CLK[n]. The capacitor C2 is coupled between the first terminal and the control terminal of the transistor MP8.

[0022] In this embodiment, the second mode selection circuit 150 includes a transistor MP9 (corresponding to the ninth transistor). The transistor MP9 has a first terminal coupled to the regulated control voltage Qbn, a control terminal for receiving the shielding signal Mask2b, and a second terminal for receiving the system low voltage VSS.

[0023] In this embodiment, the control circuit 160 includes transistors MP10 to MP13 (corresponding to the tenth to thirteenth transistors). Transistor MP10 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the control voltage Cn, and a second terminal. Transistor MP11 has a first terminal coupled to the second terminal of transistor MP10, a control terminal for receiving the system low voltage VSS, and a second terminal for receiving the system low voltage VSS. Transistor MP12 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the control voltage Cn, and a second terminal for providing a regulated control voltage Qbn. Transistor MP13 has a first terminal coupled to the second terminal of transistor MP12, a control terminal coupled to the second terminal of transistor MP10, and a second terminal for receiving the system low voltage VSS.

[0024] In this embodiment, the voltage regulator circuit 170 includes transistors MP14 to MP18 (corresponding to the fourteenth to eighteenth transistors). Transistor MP14 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the regulated control voltage Qbn, and a second terminal coupled to the control voltage Cn. Transistor MP15 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the regulated control voltage Qbn, and a second terminal coupled to the timing signal Carry[n]. Transistor MP16 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the regulated control voltage Qbn, and a second terminal coupled to the control voltage Qn. Transistor MP17 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the regulated control voltage Qbn, and a second terminal coupled to the drive output signal Out[n]. Transistor MP18 has a first terminal for receiving the system high voltage VDD, a control terminal for receiving the timing signal Carry[n+1], and a second terminal coupled to the drive output signal Out[n].

[0025] In this embodiment, transistors MP1 to MP18 are, for example, P-type transistors, but the embodiments of the present invention are not limited thereto.

[0026] In this embodiment of the invention, multiple gate drive circuits (such as 100) can be connected in series to form a gate driver (not shown), and provide multiple drive output signals (such as Out[n]) sequentially to a pixel array (not shown) composed of multiple pixels.

[0027] Figure 2 is a schematic diagram of the driving timing of a gate drive circuit according to an embodiment of the present invention. Referring to Figures 1 and 2, in this embodiment, three scanning modes are illustrated, namely, sequential scanning mode, local masking scanning mode, and subsequent masking scanning mode. Each scanning mode occurs, for example, during different frame periods, but the embodiments of the present invention are not limited thereto.

[0028] In the timing scan mode, mask signals Mask1 and Mask2 are the enable level (e.g., low voltage level), and mask signals Mask1b and Mask2b are the disable level (e.g., high voltage level).

[0029] In the local masked scan mode, after the masking signal Mask1 switches from the enable level to the disable level, the masking signal Mask1b switches from the disable level to the enable level after a horizontal scan interval. That is, the time when the masking signal Mask1 switches to the disable level is one horizontal scan interval earlier than the time when the masking signal Mask1b switches to the enable level. The duration of the masking signal Mask1 being at the disable level is equal to the duration of the masking signal Mask1b being at the enable level and reflects the number of scan lines (or gate lines) to be executed in the local masked scan mode. Furthermore, the masking signal Mask2 remains at the enable level, and the masking signal Mask2b remains at the disable level.

[0030] In subsequent masking scan modes, after the masking signal Mask2 switches from the enable level to the disable level, the masking signal Mask2b switches from the disable level to the enable level after a horizontal scan interval. That is, the time for Mask2 to switch to the disable level is one horizontal scan interval earlier than the time for Mask2b to switch to the enable level. The duration of Mask2 being in the disable level is equal to the duration of Mask2b being in the enable level and is fixed at one horizontal scan interval. Furthermore, the masking signal Mask1 remains in the enable level, and the masking signal Mask1b remains in the disable level.

[0031] Figures 3A to 3C are schematic diagrams of the operation of a gate drive circuit in timing scan mode according to an embodiment of the present invention. Referring to Figures 1, 2 and 3A to 3C, in this embodiment, the operation mode of a single gate drive circuit (such as 100) in timing scan mode is illustrated by taking three periods P11 to P13 as an example, where the clock signal CKL[2] is used as the clock signal CKL[n].

[0032] As shown in Figures 2 and 3A, during period P11, transistors MP2 and MP5 are turned on due to the low voltage level of the timing signal Carry[n-1], and transistor MP4 is turned on due to the low voltage level of the masking signal Mask1. Therefore, transistors MP3 and MP8 are turned on due to the low voltage level of the masking signal Mask2. At this time, transistor MP3 outputs clock signal CKL[2] as the timing signal Carry[n], and transistor MP8 outputs clock signal CKL[2] as the drive output signal Out[n].

[0033] Furthermore, transistors MP1 and MP18 are cut off due to the high voltage level of the timing signal Carry[n+1], transistor MP6 is cut off due to the high voltage level of the masking signal Mask1b, transistor MP7 is cut off due to the high voltage level of the timing signal Carry[n], and transistor MP9 is cut off due to the high voltage level of the masking signal Mask2b.

[0034] Transistors MP11 and MP13 are coupled as diodes and are turned on due to forward bias, while transistors MP10 and MP12 are turned on due to the low voltage level of the control voltage Cn, causing the regulated control voltage Qbn to approach the system high voltage VDD. At this time, transistors MP14 to MP17 are turned off due to the high voltage level of the regulated control voltage Qbn.

[0035] As shown in Figures 2 and 3B, during period P12, unlike period P11, transistors MP2 and MP5 are turned off due to the high voltage level of the timing signal Carry[n-1], transistor MP7 is turned on due to the low voltage level of the timing signal Carry[n], transistor MP3 is turned on due to the low voltage level of the control voltage Cn, and MP8 is turned on due to the low voltage level of the control voltage Cn. The conduction state of transistor MP4 depends on the voltage at the control terminal.

[0036] As shown in Figures 2 and 3C, during period P13, transistors MP1 and MP18 are turned on due to the low voltage level of the timing signal Carry[n+1], resulting in a high voltage level for the control voltage Cn and the drive output signal Out[n]. At this time, transistors MP2 and MP5 are turned off due to the high voltage level of the timing signal Carry[n-1], transistor MP6 is turned off due to the high voltage level of the masking signal Mask1b, transistor MP7 is turned off due to the high voltage level of the timing signal Carry[n], and transistor MP9 is turned off due to the high voltage level of the masking signal Mask2b.

[0037] Next, transistors MP3, MP10, and MP12 are turned off due to the high voltage level of the control voltage Cn, causing the regulated control voltage Qbn to approach the system low voltage VSS. At this time, transistors MP14~MP17 are turned on due to the low voltage level of the regulated control voltage Qbn, and the control voltages Cn and Qn, the timing signal Carry[n], and the drive output signal Out[n] are raised due to the influence of the system high voltage VDD.

[0038] Based on the above, in the timing scan mode, the gate drive circuit (e.g., 100) performs a non-downclocking operation. During the preamplification stage (i.e., during period P11), the timing signal Carry[n-1] preamplifies the pre-discharge point (i.e., the control voltage Cn) to a low voltage level. Then, during period P12, the clock signal CLK[n] (here, the clock signal CLK[2]) will switch to a low voltage level. Then, through parasitic capacitance coupling, the voltage of the pre-discharge point is pulled down to a lower voltage. Then, the transistor MP8 pulls the voltage of the drive output signal Out[n] to a low voltage level to output a square wave. Next, during period P13, the timing signal Carry[n+1] will charge the drive output signal Out[n] and the pre-discharge point to a high voltage level, and the noise suppression block (i.e., the voltage regulator circuit 170) will start to function.

[0039] Figures 4A to 4C are schematic diagrams of the operation of a gate drive circuit in a local shielded scanning mode according to an embodiment of the present invention. Referring to Figures 1, 2 and 4A to 4C, in this embodiment, the operation mode of a single gate drive circuit (such as 100) in a local shielded scanning mode is illustrated using three periods P21 to P23 as examples, where the clock signal CKL[2] is used as the clock signal CKL[n].

[0040] As shown in Figures 2 and 4A, during period P21, transistors MP2 and MP5 are turned on due to the low voltage level of the timing signal Carry[n-1], and transistor MP3 is turned on due to the low voltage level of the masking signal Mask2. Furthermore, transistor MP4 is turned off due to the high voltage level of the masking signal Mask1, and therefore transistor MP8 is turned off due to the high voltage level of the control voltage Qn. At this time, transistor MP3 outputs the clock signal CKL[2] as the timing signal Carry[n], and transistor MP8 cannot output the clock signal CKL[2] as the drive output signal Out[n].

[0041] Furthermore, transistors MP1 and MP18 are cut off due to the high voltage level of the timing signal Carry[n+1], transistor MP6 is cut off due to the high voltage level of the masking signal Mask1b, transistor MP7 is cut off due to the high voltage level of the timing signal Carry[n], and transistor MP9 is cut off due to the high voltage level of the masking signal Mask2b.

[0042] Transistors MP11 and MP13 are coupled as diodes and are turned on due to forward bias, while transistors MP10 and MP12 are turned on due to the low voltage level of the control voltage Cn, causing the regulated control voltage Qbn to approach the system high voltage VDD. At this time, transistors MP14 to MP17 are turned off due to the high voltage level of the regulated control voltage Qbn.

[0043] As shown in Figures 2 and 4B, during period P22, unlike period P21, transistors MP2 and MP5 are turned off due to the high voltage level of the timing signal Carry[n-1], transistor MP7 is turned on due to the low voltage level of the timing signal Carry[n], transistor MP6 is turned on due to the low voltage level of the masking signal Mask1b, and transistor MP3 remains turned on due to the low voltage level of the control voltage Cn. At this time, the control voltage Qn is maintained at a high voltage level due to the influence of the system high voltage VDD, therefore transistor MP8 remains in the off state.

[0044] As shown in Figures 2 and 4C, during period P23, transistors MP1 and MP18 are turned on due to the low voltage level of the timing signal Carry[n+1], resulting in a high voltage level for the control voltage Cn and the drive output signal Out[n]. At this time, transistors MP2 and MP5 are turned off due to the high voltage level of the timing signal Carry[n-1], transistor MP6 is turned on due to the low voltage level of the masking signal Mask1b, transistor MP7 is turned off due to the high voltage level of the timing signal Carry[n], and transistor MP9 is turned off due to the high voltage level of the masking signal Mask2b.

[0045] Next, transistors MP3, MP10, and MP12 are turned off due to the high voltage level of the control voltage Cn, causing the regulated control voltage Qbn to approach the system low voltage VSS. At this time, transistors MP14~MP17 are turned on due to the low voltage level of the regulated control voltage Qbn, and the control voltages Cn and Qn, the timing signal Carry[n], and the drive output signal Out[n] are raised due to the influence of the system high voltage VDD.

[0046] Based on the above, in the local shielding scan mode, the frequency reduction function of the drive output signal Out[n] can be enabled. The frequency reduction of the drive output signal Out[n] is achieved by the timing signal Carry[n-1] pulling the low voltage level into the control voltage Cn during period P21, and by switching the shielding signal Mask1 to a high voltage level, turning off the transistor MP4 to block the voltage of the control terminal of the transistor MP8 from being discharged, thereby preventing the output of the drive output signal Out[n].

[0047] Next, during the P22 phase, the clock signal CLK[n] will switch to a low voltage level to pull down the control voltage Qn. Under the condition that the control voltage Qn can be completely controlled at a clean high voltage level, the timing control can be set through the masking signal Mask1b in the circuit design to pull the control voltage Qn point clean, so as to completely block the output of the drive output signal Out[n] and not be affected by the clock signal CLK[n].

[0048] Finally, during stage P23, the timing signal Carry[n+1] will charge the drive output signal Out[n] and the pre-discharge point (i.e., the control voltage Cn) to a high voltage level, and the noise suppression block (i.e., the voltage regulator circuit 170) will begin to function. On the other hand, for the subsequent gate drive circuit (such as 100), the discharge path can be restored by switching the shielding signal Mask1 back to a low voltage level, so that the pre-discharge point (i.e., the control voltage Qn) of the subsequent gate drive circuit can be re-pre-discharged through the discharge path (as shown in Figure 3A), and the subsequent operating frequency will return to the original frequency to end the frequency reduction operation.

[0049] Figures 5A to 5B are schematic diagrams of the operation of a gate drive circuit in a subsequent shielded scan mode according to an embodiment of the present invention. Referring to Figures 1, 2 and 5A to 4C, in this embodiment, two periods P31 to P32 are used as examples to illustrate the operation mode of a single gate drive circuit (such as 100) in the subsequent shielded scan mode, wherein the clock signal CKL[2] is used as the clock signal CKL[n].

[0050] As shown in Figures 2 and 5A, during period P31, transistors MP2 and MP5 are turned on due to the low voltage level of the timing signal Carry[n-1], and transistor MP4 is turned on due to the low voltage level of the masking signal Mask1. Therefore, transistors MP3 and MP8 are turned off due to the high voltage level of the masking signal Mask2. At this time, transistors MP3 and MP8 cannot provide the timing signal Carry[n] and the drive output signal Out[n].

[0051] Furthermore, transistors MP1 and MP18 are cut off due to the high voltage level of the timing signal Carry[n+1], transistor MP6 is cut off due to the high voltage level of the masking signal Mask1b, transistor MP7 is cut off due to the high voltage level of the timing signal Carry[n], and transistor MP9 is cut off due to the high voltage level of the masking signal Mask2b.

[0052] Transistors MP11 and MP13 are coupled as diodes and are turned on due to forward bias, while transistors MP10 and MP12 are turned off due to the high voltage level of the control voltage Cn, causing the regulated control voltage Qbn to approach the system low voltage VSS. At this time, transistors MP14 to MP17 are turned on due to the low voltage level of the regulated control voltage Qbn.

[0053] As shown in Figures 2 and 5B, during period P32, transistors MP1 and MP18 are cut off due to the high voltage level of the timing signal Carry[n+1], transistors MP2 and MP5 are cut off due to the high voltage level of the timing signal Carry[n-1], transistor MP3 is cut off due to the high voltage level of the control voltage Cn, transistor MP6 is cut off due to the high voltage level of the shielding signal Mask1b, transistor MP7 is cut off due to the high voltage level of the timing signal Carry[n], and transistor MP8 is cut off due to the high voltage level of the control voltage Qn.

[0054] Then, transistor MP9 turns on due to the low voltage level of the shielding signal Mask2b, causing the regulated control voltage Qbn to approach the system's low voltage VSS. At this time, transistors MP14~MP17 turn on due to the low voltage level of the regulated control voltage Qbn, and the control voltage Cn, Qn, timing signal Carry[n], and drive output signal Out[n] are raised by the system's high voltage VDD. Meanwhile, transistors MP3, MP10, and MP12 are turned off due to the high voltage level of the control voltage Cn.

[0055] Based on the above, in the subsequent shielded scanning mode, the frequency reduction function of the drive output signal Out[n] can be enabled. The frequency reduction method of the drive output signal Out[n] is that during P31, the shielded signal Mask2 causes the transistor MP2 to charge the pre-discharge point (i.e., control voltage Cn) to a high voltage level during the stage when it should be discharging. This forces the transistors MP3 and MP8 to turn off, and at the same time blocks the discharge of control voltages Cn and Qn. Not only does the drive output signal Out[n] stop outputting, but the timing signal Carry[n] also stops driving the subsequent gate drive circuit (such as 100), thus achieving the frequency reduction effect.

[0056] During the P32 stage, the clock signal CKL[n] will switch to a low voltage level to pull down the control voltages Qn and Cn. Under the condition that the control voltage Qn can be completely controlled at a clean high voltage level, in the circuit design, the control voltages Qn and Cn can be pulled down cleanly by controlling the masking signal Mask2b, which can completely block the output of the drive output signal Out[n] and not be affected by the clock signal CKL[n]. Since the timing signal Carry[n] is also masked, it will not drive the subsequent gate drive circuit (such as 100). Therefore, the frequency can be reduced all the way to the last gate drive circuit (such as 100).

[0057] As described above, the gate drive circuit 100 of this embodiment supports three operating modes, namely, sequential scan mode, local masked scan mode, and subsequent masked scan mode. It can dynamically adjust whether to reduce the frequency according to the display requirements, and can flexibly specify the area range of frequency reduction: In sequential scan mode, the gate drive circuit 100 does not perform the general operation of frequency reduction, and the system continuously updates the entire screen by scanning line by line at a fixed reference refresh frequency; In local masked scan mode, the gate drive circuit 100 blocks the output of the drive output signal Out[n] of the selected area, and the timing signal Carry[n] will still continue to be passed to the next stage; In subsequent masked scan mode, the gate drive circuit 100 blocks the output of the drive output signal Out[n] of the selected area and also blocks the downward transmission of the timing signal Carry[n].

[0058] In this embodiment of the invention, the local shielding scan mode and the subsequent shielding scan mode can be implemented separately during each frame, or the subsequent shielding scan mode can be implemented after the local shielding scan mode is implemented, depending on the circuit design, and this embodiment of the invention is not limited thereto.

[0059] In summary, the gate drive circuit of this embodiment of the invention, through the first mode selection circuit, can determine whether the first control voltage is transmitted to the drive output circuit, that is, whether the drive output signal is output; on the other hand, through the first subsequent shielding signal and the second mode selection circuit, it can determine whether the first control voltage is set, that is, whether the third timing signal is output. Therefore, the gate drive circuit can shield the drive output signal for a specific number of frames (i.e., the scan signal for a specific number of outputs), thereby reducing the number of frame refreshes for a specific column / area, and maintain the state of the previous frame through the internal storage structure / element of the pixel.

[0060] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0061] 100: Gate drive circuit 110: Timing Input Circuit 120: Timing Output Circuit 130: First Mode Selection Circuit 140: Drive output circuit 150: Second Mode Selection Circuit 160: Control Circuit 170: Voltage Regulator Circuit Carry[n-1]~Carry[n+2]: Timing signals CLK[n], CLK[1], CLK[2]: Clock signals Cn, Qn: Control voltage Mask1, Mask1b, Mask2, Mask2b: Signal shielding MP1~MP18: Transistors Out[n-1]~Out[n+2]: Drive output signals Qbn: Regulated control voltage VDD: System high voltage VSS: System Low Voltage

Claims

1. A gate drive circuit, comprising: A timing input circuit receives a first timing signal, a second timing signal, a system high voltage, and a first subsequent shielding signal to provide a first control voltage. A timing output circuit, coupled to the timing input circuit, receives the first control voltage and a clock signal to provide a third timing signal; a first mode selection circuit, coupled to the timing input circuit, receives the first control voltage and the second timing signal, a first local shielding signal, a system high voltage, a second local shielding signal, and the third timing signal to provide a second control voltage; a drive output circuit, coupled to the first mode selection circuit, receives the clock signal to provide a drive output signal; and a control circuit receives the first control voltage, the system high voltage, and a system low voltage to provide a regulated control voltage. A second mode selection circuit, coupled to the regulated control voltage, and receiving a second subsequent shielding signal and the system low voltage, to set the regulated control voltage based on the second subsequent shielding signal and the system low voltage; and a voltage regulator circuit, coupled to the first control voltage, the third timing signal, the second control voltage and the drive output signal, and receiving the regulated control voltage, the system high voltage and the first timing signal, to pull up the first control voltage, the third timing signal, the second control voltage and the drive output signal to the system high voltage based on the regulated control voltage, and to pull up the drive output signal to the system high voltage based on the first timing signal.

2. The gate drive circuit as claimed in claim 1, wherein the timing input circuit includes: A first transistor has a first terminal for receiving a high voltage of the system, a control terminal for receiving the first timing signal, and a second terminal for providing the first control voltage; And a second transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal for receiving the second timing signal, and a second terminal for receiving the first subsequent shielding signal.

3. The gate drive circuit as claimed in claim 2, wherein the timing output circuit comprises: A third transistor has a first terminal for providing the third timing signal, a control terminal for receiving the first control voltage, and a second terminal for receiving the clock signal; a first capacitor is coupled between the first terminal of the third transistor and the control terminal of the third transistor.

4. The gate drive circuit as claimed in claim 3, wherein the first mode selection circuit comprises: A fourth transistor has a first terminal for receiving the first control voltage, a control terminal, and a second terminal for providing the second control voltage; a fifth transistor has a first terminal coupled to the control terminal of the fourth transistor, a control terminal for receiving the second timing signal, and a second terminal for receiving the first local shielding signal; a sixth transistor has a first terminal for receiving the system high voltage, a control terminal for receiving the second local shielding signal, and a second terminal; and a seventh transistor has a first terminal coupled to the second terminal of the sixth transistor, a control terminal for receiving the third timing signal, and a second terminal coupled to the second terminal of the fourth transistor.

5. The gate drive circuit as claimed in claim 4, wherein the drive output circuit comprises: An eighth transistor has a first terminal for receiving the drive output signal, a control terminal for receiving the second control voltage, and a second terminal for receiving the clock signal; And a second capacitor, coupled between the first terminal of the eighth transistor and the control terminal of the eighth transistor.

6. The gate drive circuit as claimed in claim 5, wherein the second mode selection circuit comprises: A ninth transistor has a first terminal coupled to the regulated control voltage, a control terminal for receiving the second subsequent shielding signal, and a second terminal for receiving the system low voltage.

7. The gate drive circuit as claimed in claim 6, wherein the control circuit includes: A tenth transistor has a first terminal for receiving a high voltage of the system, a control terminal for receiving a first control voltage, and a second terminal; an eleventh transistor has a first terminal coupled to the second terminal of the tenth transistor, a control terminal for receiving a low voltage of the system, and a second terminal for receiving a low voltage of the system; a twelfth transistor has a first terminal for receiving a high voltage of the system, a control terminal for receiving the first control voltage, and a second terminal for providing the regulated control voltage; and a thirteenth transistor has a first terminal coupled to the second terminal of the twelfth transistor, a control terminal coupled to the second terminal of the tenth transistor, and a second terminal for receiving a low voltage of the system.

8. The gate drive circuit as claimed in claim 7, wherein the voltage regulator circuit comprises: A fourteenth transistor has a first terminal for receiving the system's high voltage, a control terminal for receiving the regulated control voltage, and a second terminal coupled to the first control voltage; a fifteenth transistor has a first terminal for receiving the system's high voltage, a control terminal for receiving the regulated control voltage, and a second terminal coupled to the third timing signal; a sixteenth transistor has a first terminal for receiving the system's high voltage, a control terminal for receiving the regulated control voltage, and a second terminal coupled to the second control voltage; a seventeenth transistor has a first terminal for receiving the system's high voltage, a control terminal for receiving the regulated control voltage, and a second terminal coupled to the drive output signal; and an eighteenth transistor has a first terminal for receiving the system's high voltage, a control terminal for receiving the first timing signal, and a second terminal coupled to the drive output signal.

9. The gate drive circuit as claimed in claim 8, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are each a P-type transistor.

10. The gate drive circuit as claimed in claim 1, wherein in a timing scan mode, the first local shield signal and the first subsequent shield signal are each an enable level, and the second local shield signal and the second subsequent shield signal are each a disable level; in a local shield scan mode, after the first local shield signal switches to the disable level, the second local shield signal switches to the enable level, the first subsequent shield signal is the enable level, and the second subsequent shield signal is the disable level, wherein the time when the first local shield signal switches to the disable level is one horizontal scan period earlier than the time when the second local shield signal switches to the enable level; In a subsequent masking scan mode, after the first subsequent masking signal switches to the disable level, the second subsequent masking signal switches to the enable level. The first local masking signal is the enable level, and the second local masking signal is the disable level. The time when the first subsequent masking signal switches to the disable level is one horizontal scan period earlier than the time when the second subsequent masking signal switches to the enable level.

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