Low-voltage floating inverter amplifier and switched-capacitor analog-to-digital converter

Abstract

The present invention relates to the technical field of analog circuits. Disclosed are a low-voltage floating inverter amplifier and a switched-capacitor analog-to-digital converter. The low-voltage floating inverter amplifier comprises a first self-biased inverter, a second self-biased inverter, and an energy storage capacitor connected in parallel. Both the first self-biased inverter and the second self-biased inverter are clock-controlled inverters that self-generate bias voltages. One end of the parallel connection is connected to a power supply voltage by means of a reset switch, and the other end of the parallel connection is connected to a ground voltage by means of a reset switch. Each of an input end of the first self-biased inverter and an input end of the second self-biased inverter is connected to an input signal, and is connected to a ground voltage by means of a reset switch. Each of an output end of the first self-biased inverter and an output end of the second self-biased inverter is provided with an amplification switch. The reset switches and the amplification switches are closed in an alternating manner by means of clock control. The low-voltage floating inverter amplifier is compatible with power supplies below 1 V under low-cost conditions, reducing power consumption and enhancing energy efficiency.

Description

A low-voltage floating inverting amplifier and switched capacitor analog-to-digital converter Technical Field

[0001] The present invention belongs to the technical field of analog circuits, and in particular relates to a low-voltage floating inverting amplifier and a switched capacitor analog-to-digital converter. Background Art

[0002] IoT applications require low-power sensor chips to extend battery life. Reducing the chip's power supply voltage is an effective way to achieve low power consumption. Achieving compatibility with chips operating at sub-1V power supplies is crucial. However, analog circuit design becomes significantly more challenging with sub-1V power supplies. Amplifiers are fundamental analog circuit building blocks and are widely used. However, with sub-1V power supplies, complex amplifier designs are impractical, requiring simpler structures to implement the amplifier function. As shown in Figure 1, the floating inverting amplifier, a simple dynamic amplifier, offers numerous advantages: high energy efficiency due to the lack of static power consumption; adjustable bandwidth and power consumption with the operating frequency; and stable common-mode output, eliminating the need for additional common-mode feedback circuitry. However, existing floating inverting amplifiers are not suitable for sub-1V power supply scenarios.

[0003] Explanation of terms:

[0004] Sub-1V: below 1V

[0005] FIA: Floating InverterAmplifier, floating inverting amplifier

[0006] LVFIA: Low voltage FIA, low voltage floating inverting amplifier

[0007] Summary of the Invention

[0008] Purpose of the invention: The technical problem to be solved by the present invention is to provide a low-voltage floating inverting amplifier switched capacitor analog-to-digital converter in response to the shortcomings of the existing technology.

[0009] In order to solve the above technical problems, a low voltage floating inverting amplifier is disclosed in the first aspect, comprising: a first self-biased inverter, a second self-biased inverter and a storage capacitor C RES The first self-biased inverter and the second self-biased inverter are both clock-controlled inverters that can generate bias voltages themselves; the first self-biased inverter, the second self-biased inverter and the energy storage capacitor C RES Connect in parallel, one end of the parallel connection is connected to the power supply voltage V through the reset switch DD The other end of the parallel connection is connected to the ground voltage V through the reset switch SS .

[0010] The input terminal of the first self-biased inverter and the input terminal of the second self-biased inverter are both connected to the input signal and the ground voltage V through the reset switch. SS The output end of the first self-biased inverter and the output end of the second self-biased inverter are both provided with an amplifying switch for controlling the output of the output signal; the reset switch and the amplifying switch are alternately closed by clock control.

[0011] Furthermore, the first self-biased inverter includes a capacitor biased PMOS circuit and a capacitor biased NMOS circuit, and the capacitor biased PMOS circuit is connected to the power supply voltage V DD , the capacitor biased NMOS circuit is connected to the ground voltage V through the reset switch SS One end of the capacitor bias PMOS circuit is connected to one end of the capacitor bias NMOS circuit, and the connection is connected to the input voltage and the ground voltage V through the reset switch. SS , the other end of the capacitor biased PMOS circuit and the other end of the capacitor biased NMOS circuit are connected through an amplifying switch; the second self-biased inverter and the first self-biased inverter are mirrored.

[0012] Furthermore, the capacitor biased PMOS circuit includes a first auto-zero capacitor C C1 and PMOS tube, the first auto-zero capacitor C C1 The first charging switch is connected to the gate of the PMOS tube, and the first bias switch is provided at the connection point. The first charging switch is connected to the ground voltage V SS The first bias switch is connected to the drain of the PMOS tube; the source of the PMOS tube is connected to the source of the PMOS tube of the second self-biased inverter, and the connection points are respectively connected to the energy storage capacitor C RES , the reset switch is connected; the first charging switch and the first bias switch are alternately closed through clock control.

[0013] Furthermore, the capacitor biased NMOS circuit includes a second automatic zeroing capacitor C C2 and NMOS tube, the second auto-zero capacitor C C2 and connected to the gate of the NMOS tube, a second charging switch and a second bias switch are provided at the connection, and the second charging switch is connected to the power supply voltage V DD , the second bias switch is connected to the drain of the NMOS tube; the source of the NMOS tube is connected to the source of the NMOS tube of the second self-biased inverter, and the connection points are respectively connected to the energy storage capacitor C RES , the reset switch is connected; the second charging switch and the second bias switch are alternately closed through clock control.

[0014] The first auto-zero capacitor C C1 and the second auto-zero capacitor C C2Connection, the connection is connected to the input voltage and the ground voltage V through the reset switch SS ; The drain of the PMOS tube and the drain of the NMOS tube are connected through an amplifying switch.

[0015] Furthermore, the clock control sequence includes a reset phase Φ RST and amplification stage Φ EN , reset phase Φ RST Including the capacitor charging stage Φ1 and the bias voltage generation stage Φ2, all reset switches are in the reset stage Φ RST Close to form a path, amplify the stage Φ EN Disconnected; All charging switches are closed to form a path in the capacitor charging phase Φ1 and disconnected in other phases; All bias switches are closed to form a path in the bias voltage generation phase Φ2 and disconnected in other phases; All amplification switches are closed in the amplification phase Φ EN Close to form a path, reset stage Φ RST disconnect.

[0016] Furthermore, during the bias voltage generation phase Φ2, all auto-zero capacitors are discharged, and the target bias voltage is obtained by controlling the high level time of the bias voltage generation phase Φ2; the PMOS transistor and the NMOS transistor respectively realize auto-zeroing to eliminate the offset voltage and 1 / f noise.

[0017] Furthermore, during the bias voltage generation phase Φ2, the magnitude of the bias voltage generated by the discharge of all auto-zero capacitors is related to the Φ2 high-level time and the size of the auto-zero capacitor. The longer the Φ2 high-level time, the more discharge occurs, and the greater the bias voltage change. The larger the auto-zero capacitor, the slower the discharge, and the slower the bias voltage change.

[0018] A second aspect discloses a switched capacitor analog-to-digital converter, comprising the low-voltage floating inverting amplifier described in any one of the above items.

[0019] Furthermore, the switched capacitor analog-to-digital converter is a ΣΔ analog-to-digital converter, which includes a second-order 1-bit ΣΔ modulator, which includes a first-stage integrator, a second-stage integrator and a comparator, and both the first-stage integrator and the second-stage integrator include the low-voltage floating inverting amplifier.

[0020] Furthermore, the second-order 1-bit ΣΔ modulator includes a pair of non-overlapping clocks Φ A and Φ B , the non-overlapping clock Φ A and Φ BUsed to control the sampling and integration of the first-stage integrator and the second-stage integrator, and at the same time input to the low-voltage floating inverting amplifier, serving as the reset and amplification clock in the low-voltage floating inverting amplifier; the reset clock of the low-voltage floating inverting amplifier in the first-stage integrator includes sub-clocks Φ1 and Φ2, which are the capacitor charging phase and the bias voltage generation phase respectively; the reset clock of the low-voltage floating inverting amplifier in the second-stage integrator includes sub-clocks Φ'1 and Φ'2, which are the capacitor charging phase and the bias voltage generation phase respectively.

[0021] Beneficial Effects: Under low-cost conditions, the system achieves compatibility with floating inverting amplifiers operating under power supplies below 1V, reduces power consumption, and improves energy efficiency. This is specifically reflected in the following aspects.

[0022] 1) Since the present invention adopts the capacitor charging + diode discharging method, the PMOS and NMOS can be freely biased according to the threshold voltage of the MOS tube, thereby improving flexibility and reducing the minimum supply voltage.

[0023] 2) Since the present invention adopts the method of PMOS and NMOS to independently perform automatic zeroing and discharge, there is no current path between the two, and they do not interfere with each other, further reducing the demand for power supply.

[0024] 3) Automatic zeroing technology is used to reduce offset and 1 / f noise. Since automatic zeroing itself requires an automatic zeroing capacitor and a MOS transistor connected in a diode manner, the present invention uses the automatic zeroing capacitor and the MOS transistor connected in a diode manner to form a discharge path to determine the bias voltage. There is no need to introduce additional energy storage capacitors, floating current source capacitors and MOS transistors, which reduces hardware consumption, simplifies the circuit, and simplifies the timing.

[0025] The low-voltage floating inverting amplifier can be applied to common analog integrated circuits, including but not limited to switched capacitor analog-to-digital converters, comparators, etc. The circuit using the low-voltage floating inverting amplifier can operate at a lower power supply voltage to achieve low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0027] Figure 1 is a diagram of the FIA ​​circuit topology and related operating voltage changes.

[0028] Figure 2 shows the phase-amplified PMOS tube V GS Schematic diagram of changes.

[0029] FIG3 is a circuit diagram of a low-voltage floating inverting amplifier proposed in an embodiment of the present application.

[0030] FIG4 is a circuit diagram of a low-voltage floating inverting amplifier in a capacitor charging stage Φ1 according to an embodiment of the present application.

[0031] FIG5 is a circuit diagram of a low-voltage floating inverting amplifier in a bias voltage generation stage Φ2 according to an embodiment of the present application.

[0032] FIG6 is a diagram of a low voltage floating inverting amplifier in the amplification phase Φ proposed in an embodiment of the present application. EN Schematic diagram of the circuit.

[0033] FIG7 is a schematic diagram of a second-order 1-bit ΣΔ modulator circuit in a switched capacitor analog-to-digital converter according to an embodiment of the present application.

[0034] FIG8 is a schematic diagram of a post-simulation spectrum diagram of a second-order 1-bit ΣΔ modulator in a switched capacitor analog-to-digital converter proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0036] As a simple dynamic amplifier, the floating inverting amplifier offers numerous advantages: high energy efficiency due to the lack of static power consumption; adjustable bandwidth and power consumption with the operating frequency; and stable output common-mode operation, eliminating the need for additional common-mode feedback circuitry. Figure 1 shows the circuit topology and operating voltage variations.

[0037] The work of FIA is divided into two phases, reset phase and amplification phase. In the reset phase, C RES is charged, the op amp outputs V OP and V ON Set to V cm (FIA output common-mode voltage); in the amplification phase, C RES Power the amplifier circuit on the right, and the amplifier circuit amplifies. V S+ and V S- Towards V cm Approaching, until the amplifier tube is basically cut off, the amplification ends, V S+ ,V S- and output no longer change.

[0038] However, FIA cannot work under sub-1V power supply for the following reasons: Assume that the common mode voltage at the FIA ​​input is V CM =V DD / 2, at the beginning of the amplification phase, the gate-source voltage difference on the PMOS tube is recorded as V GS0 , as the amplification progresses, the gate-source voltage gradually changes, recorded as V GS , as shown in Figure 2. 1) If V GS0 >|V THP |, VTHP Indicates the threshold voltage of the PMOS tube. As the amplification progresses, when V S+ <V CM +|V THP |,V S ->V CM -V THN , the amplifier is cut off, so the FIA ​​output swing is limited to |V THP |+V THN Inside, V THN Indicates the threshold voltage of the NMOS tube. 2) If V GS0 <|V THP |, the amplifier tube is already in the cut-off state at the beginning of the amplification phase, and the FIA ​​cannot work normally. Under the sub-1V power supply, V DD / 2 is difficult to meet the requirement of being greater than the MOS tube threshold voltage V TH Therefore, the traditional FIA is faced with the dilemma of being unable to work.

[0039] References: [1]

[0040] Traditional FIA: Since PMOS and NMOS are biased at the same bias voltage, under sub-1V power supply, the gate-source voltage difference of the amplifier tube Vgs < V TH , the amplifier tube is cut off, so the FIA ​​cannot work properly.

[0041] The purpose of the embodiments of the present invention is to achieve compatibility with FIA powered by less than 1V at a low cost, reduce power consumption, and improve energy efficiency.

[0042] The first embodiment of the present invention provides an LVFIA suitable for low voltage power supply. FIG3 is a circuit topology diagram of the LVFIA, which includes a first self-biased inverter, a second self-biased inverter and an energy storage capacitor C RES The first self-biased inverter and the second self-biased inverter are both clock-controlled inverters that can generate bias voltages themselves; the first self-biased inverter, the second self-biased inverter and the energy storage capacitor C RES Connect in parallel, one end of the parallel connection is connected through the reset switch S RST1 Connect the power supply voltage V DD The other end of the parallel connection is connected through the reset switch S RST2 Connect the ground voltage V SS .

[0043] The input terminals of the first self-biased inverter and the second self-biased inverter are both connected to the input signal and the reset switch S RST3 and S RST4 Connect the ground voltage V SS The output end of the first self-biased inverter and the output end of the second self-biased inverter are both provided with an amplifying switch S EN1 、S EN2 , used to control the output of the output signal; the reset switch S RST1 、S RST2 、S RST3 、S RST4 and amplification switch S EN1 、S EN2 The reset switch S is closed alternately through clock control. RST1 、S RST2 、S RST3 、S RST4 and amplification switch S EN1 、S EN2 PMOS, NMOS or CMOS switches can be used; the energy storage capacitor C RES MIM capacitors, MOM capacitors or MOS capacitors can be used.

[0044] The first self-biased inverter includes a capacitor biased PMOS circuit and a capacitor biased NMOS circuit. The capacitor biased PMOS circuit is reset by a reset switch S RST1 Connect the power supply voltage V DD , the capacitor biases the NMOS circuit through the reset switch S RST2 Connect the ground voltage V SS One end of the capacitor biased PMOS circuit is connected to one end of the capacitor biased NMOS circuit, and the connection is connected to the input voltage and the reset switch S RST3 Connect the ground voltage V SS The other end of the capacitor biased PMOS circuit and the other end of the capacitor biased NMOS circuit are connected through the amplifier switch S EN1 Connection; the second self-biased inverter and the first self-biased inverter are mirrored.

[0045] The capacitor bias PMOS circuit includes a first auto-zero capacitor C C1 and PMOS tube M P1 , the first auto-zero capacitor C C1 and PMOS tube M P1 The gate is connected, and a first charging switch S is provided at the connection. chg1 and the first bias switch S bias1 , the first charging switch S chg1 Connect the ground voltage VSS , the first bias switch S bias1 Connect the PMOS tube M P1 Drain; the PMOS tube M P1 The source and the PMOS tube M of the second self-biased inverter P2 The source is connected to the energy storage capacitor C RES , reset switch S RST1 Connect; first charging switch S chg1 and the first bias switch S bias1 The first charging switch S is alternately closed by clock control. chg1 NMOS or CMOS switches can be used, the first bias switch S bias1 PMOS, NMOS or CMOS switches can be used. The first auto-zero capacitor C C1 Either MIM capacitors or MOM capacitors can be used.

[0046] The capacitor biased NMOS circuit includes a second auto-zero capacitor C C2 and NMOS tube M N1 , the second auto-zero capacitor C C2 and NMOS tube M N1 The gate is connected, and a second charging switch S is provided at the connection. chg2 and the second bias switch S bias2 , the second charging switch S chg2 Connect the power supply voltage V DD , the second bias switch S bias2 Connect the NMOS tube M N1 Drain; the NMOS tube M N1 The source and the NMOS tube M of the second self-biased inverter N2 The source is connected to the energy storage capacitor C RES , reset switch S RST2 Connection; Second charging switch S chg2 and the second bias switch S bias2 By clock control, the second charging switch S chg2 PMOS or CMOS switches can be used, and the second bias switch S bias2 PMOS, NMOS or CMOS switches can be used, and the second auto-zero capacitor C C2 Either MIM capacitors or MOM capacitors can be used.

[0047] The first auto-zero capacitor C C1 and the second auto-zero capacitor C C2 Connection, the connection is connected to the input voltage and the reset switch S RST3 Connect the ground voltage VSS The PMOS tube M P1 Drain and NMOS tube M N1 The drain is connected to the amplifier switch S EN1 connect.

[0048] The second self-biased inverter is mirrored to the first self-biased inverter. To distinguish them, the auto-zero capacitor of the capacitor biased PMOS circuit of the second self-biased inverter is denoted as C C3 , the auto-zero capacitor of the capacitor biased NMOS circuit is C C4 , PMOS tube M P2 Drain and NMOS tube M N2 The drain is connected to the amplifier switch S EN2 connect.

[0049] The operation of LVFIA is divided into two main stages, including the reset stage (Φ RST ) and the amplification stage (Φ EN ), where the reset phase is divided into two small phases, controlled by sub-clocks Φ1 and Φ2, also known as the capacitor charging phase Φ1 and the bias voltage generation phase Φ2. All reset switches are in the reset phase Φ RST Close to form a path, amplify the stage Φ EN Disconnected; All charging switches are closed to form a path in the capacitor charging phase Φ1 and disconnected in other phases; All bias switches are closed to form a path in the bias voltage generation phase Φ2 and disconnected in other phases; All amplification switches are closed in the amplification phase Φ EN Close to form a path, reset stage Φ RST disconnect.

[0050] The operation of LVFIA in each phase is as follows.

[0051] 1) As shown in Figure 4, in the capacitor charging stage Φ1,

[0052] Energy storage capacitor C RES and all auto-zero capacitors C C1 、C C2 、C C3 、C C4 Charging; the drain of the amplifier tube (PMOS tube and NMOS tube) is suspended and there is no current path.

[0053] 2) As shown in Figure 5, in the bias voltage generation stage Φ2,

[0054] Both PMOS and NMOS tubes are diode-connected and have unity-gain connections. PMOS and NMOS tubes achieve automatic zeroing to eliminate offset and 1 / f noise, respectively.

[0055] All auto-zero capacitors C C1 、CC2 、C C3 、C C4 The target bias voltage V is obtained by discharging through the curve path shown in FIG5 and controlling the high level time of Φ2. BP1 、V BP2 、V BN1 、V BN2 The bias voltage value is related to the discharge time (the longer the Φ2 high level time is, the more discharge there is, and the greater the bias voltage change is), C C Size (C C The larger the bias voltage, the slower the change. C Regardless of the initial voltage value to which Φ1 is charged, the bias voltage V BP1 、V BP2 、V BN1 、V BN2 The robustness of the generation method with changes in the supply voltage.

[0056] 3) As shown in Figure 6, in the amplified phase Φ EN ,

[0057] By the energy storage capacitor C RES To power the differential circuit, V BP1 、V BP2 and V BN1 、V BN2 The bias voltage value determined by the Φ2 phase, the input signal V X and V Y The signal is coupled to the amplifier tube (PMOS and NMOS tube) through the automatic zero adjustment capacitor Cc, and the amplifier tube performs amplification.

[0058] The above is the working process of LFIA in a complete cycle. During the above working process, the minimum power supply of the amplifier only needs to be greater than Vgs, and it can easily achieve a power supply below 1V.

[0059] The LVCIA can be applied to common analog integrated circuits, including but not limited to switched capacitor ADCs and comparators. Thanks to the working characteristics of the LVCIA, the circuit using the LVCIA can operate at a lower supply voltage and achieve low power consumption.

[0060] A second embodiment of the present invention provides a switched capacitor analog-to-digital converter, comprising the low-voltage floating inverting amplifier described in the first embodiment. The switched capacitor analog-to-digital converter can be a first-order multi-bit or multi-order N-bit ΣΔ analog-to-digital converter, where N≥1.

[0061] The switched capacitor analog-to-digital converter is a ΣΔ analog-to-digital converter, which includes a second-order 1-bit ΣΔ modulator, and its circuit topology is shown in Figure 7. The second-order 1-bit ΣΔ modulator includes a first-stage integrator, a second-stage integrator, and a comparator, and both the first-stage integrator and the second-stage integrator include the low-voltage floating inverting amplifier.

[0062] Φ A and Φ B A pair of non-overlapping clocks for the second-order 1-bit ΣΔ modulator controls the sampling and integration of the integrator and is input to the LFFIA at the same time as the RST and EN clocks in the LFFIA; Φ1 and Φ2 are input to the LFFIA in the first-stage integrator as the sub-clocks Φ1 and Φ2 of its reset phase, which are the capacitor charging phase and the bias voltage generation phase respectively; Φ'1 and Φ'2 are input to the LFFIA in the second-stage integrator as the sub-clocks Φ1 and Φ2 of its reset phase, which are the capacitor charging phase and the bias voltage generation phase respectively.

[0063] Leveraging the aforementioned features of the LVCIA, the modulator achieves a fully dynamic structure with a 0.8V supply, enabling linear scaling of bandwidth and power consumption with the sampling frequency. With a default sampling frequency of 1.5MHz and an OSR of 200, corresponding to an input signal bandwidth of 3.75kHz, the modulator's performance is primarily limited by thermal noise, achieving a maximum SNDR (Signal to Noise and Distortion Ratio) of 91.82dB, an ENOB (effective number of bits) of 14.96 bits, an SNR (Signal to Noise Ratio) of 91.44dB, and a SFDR (Spurious Free Dynamic Range) of 99.45dB. The simulated spectrum is shown in Figure 8.

[0064] Finally, the total power consumption of the modulator under 0.8V power supply is 25.40μA, achieving a FoM of 176.1dB. SNDR Value (FoM SNDR : represents the overall quality factor of the ΣΔ modulator). In the most advanced full-dynamic ΣΔ modulator design, this application achieves optimal energy efficiency under sub-1V power supply.

[0065] The present invention provides a low-voltage floating inverting amplifier and a switched-capacitor analog-to-digital converter. There are numerous methods and approaches for implementing this technical solution. The foregoing description is merely a specific embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A low voltage floating inverting amplifier, characterized in that: include: The first self-biased inverter, the second self-biased inverter and the energy storage capacitor C RES The first self-biased inverter and the second self-biased inverter are both clock-controlled inverters that can generate bias voltages themselves; the first self-biased inverter, the second self-biased inverter and the energy storage capacitor C RES Connect in parallel, one end of the parallel connection is connected to the power supply voltage V through the reset switch DD The other end of the parallel connection is connected to the ground voltage V through the reset switch SS ; The input end of the first self-biased inverter and the input end of the second self-biased inverter are both connected to the input signal and the ground voltage V through the reset switch. SS ; The output end of the first self-biased inverter and the output end of the second self-biased inverter are both provided with an amplifying switch for controlling the output of the output signal; the reset switch and the amplifying switch are alternately closed by clock control; The first self-biased inverter includes a capacitor biased PMOS circuit and a capacitor biased NMOS circuit. The capacitor biased PMOS circuit is connected to a power supply voltage V DD , the capacitor biased NMOS circuit is connected to the ground voltage V through the reset switch SS ; One end of the capacitor bias PMOS circuit is connected to one end of the capacitor bias NMOS circuit, and the connection is connected to the input voltage and the ground voltage V through the reset switch SS , the other end of the capacitor biased PMOS circuit and the other end of the capacitor biased NMOS circuit are connected through an amplifying switch; the second self-biased inverter and the first self-biased inverter are mirrored; The capacitor biased PMOS circuit includes a first auto-zero capacitor C C1 and PMOS tube, the first auto-zero capacitor C C1 The first charging switch is connected to the gate of the PMOS tube, and a first charging switch and a first bias switch are provided at the connection. The first charging switch is connected to the ground voltage V SS , a first bias switch is connected to the drain of the PMOS tube; The source electrode of the PMOS tube is connected to the source electrode of the PMOS tube of the second self-biased inverter, and the connection points are respectively connected to the energy storage capacitor C RES , a reset switch is connected; and the first charging switch and the first bias switch are alternately closed by clock control; The capacitor biased NMOS circuit includes a second auto-zero capacitor C C2 and NMOS tube, the second auto-zero capacitor C C2 and connected to the gate of the NMOS tube, a second charging switch and a second bias switch are provided at the connection, and the second charging switch is connected to the power supply voltage V DD The second bias switch is connected to the drain of the NMOS tube; the source of the NMOS tube is connected to the source of the NMOS tube of the second self-biased inverter, and the connection points are respectively connected to the energy storage capacitor C RES , reset switch connection; controlling the second charging switch and the second bias switch to be alternately closed by clock control; The first auto-zero capacitor C C1 and the second auto-zero capacitor C C2 Connection, the connection is connected to the input voltage and the ground voltage V through the reset switch SS ; The PMOS tube drain and the NMOS tube drain are connected through an amplifying switch.

2. A low voltage floating inverting amplifier according to claim 1, characterized in that: The clock control sequence includes the reset phase Φ RST and the amplification stage Φ EN , reset phase Φ RST Including the capacitor charging stage Φ1 and the bias voltage generation stage Φ2, all reset switches are in the reset stage Φ RST Close to form a path, amplification stage Φ EN Disconnect; all charging switches are closed to form a path in the capacitor charging stage Φ1, and are disconnected in other stages; All bias switches are closed to form a path during the bias voltage generation phase Φ2, and are open at other phases; All amplifier switches are in the amplifier stageΦ EN Close to form a path, reset stage Φ RST disconnect.

3. A low voltage floating inverting amplifier according to claim 2, characterized in that: During the bias voltage generation phase Φ2, all automatic zeroing capacitors are discharged, and the target bias voltage is obtained by controlling the high level time of the bias voltage generation phase Φ2; all PMOS tubes and NMOS tubes are automatically zeroed to eliminate offset voltage and 1 / f noise.

4. A low voltage floating inverting amplifier according to claim 3, characterized in that: During the bias voltage generation stage Φ2, the magnitude of the bias voltage generated by the discharge of all automatic zeroing capacitors is related to the Φ2 high level time and the magnitude of the automatic zeroing capacitor. Specifically, the longer the Φ2 high level time is, the more the automatic zeroing capacitor is discharged, and the greater the change in the generated bias voltage is; the larger the automatic zeroing capacitor is, the slower the change in the generated bias voltage is.

5. A switched capacitor analog-to-digital converter, characterized in that: A low voltage floating inverting amplifier comprising any one of claims 1 to 4.

6. The switched capacitor analog-to-digital converter according to claim 5, characterized in that: The switched capacitor analog-to-digital converter is a ΣΔ analog-to-digital converter, which includes a 2nd-order 1-bit ΣΔ modulator, which includes a first-stage integrator, a second-stage integrator and a comparator, and both the first-stage integrator and the second-stage integrator include the low-voltage floating inverting amplifier.

7. The switched capacitor analog-to-digital converter according to claim 6, characterized in that: The second-order 1-bit ΣΔ modulator comprises a pair of non-overlapping clocks Φ A and Φ B , the non-overlapping clock Φ A and Φ B Used to control the sampling and integration of the first-stage integrator and the second-stage integrator, and simultaneously input to the low-voltage floating inverting amplifier as the reset and amplification clock in the low-voltage floating inverting amplifier; the reset clock of the low-voltage floating inverting amplifier in the first-stage integrator includes sub-clocks Φ1 and Φ2, which are the capacitor charging phase and the bias voltage generating phase respectively; the reset clock of the low-voltage floating inverting amplifier in the second-stage integrator includes sub-clocks Φ'1 and Φ'2, which are the capacitor charging phase and the bias voltage generating phase respectively.

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