Instruction processing method and device, and storage medium and electronic device

Abstract

Provided in the embodiments of the present disclosure are an instruction processing method and device, and a storage medium and an electronic device. The method comprises: on the basis of a preset instruction code, determining from among a plurality of instructions to be processed a first-type instruction to be processed; using an update mode corresponding to said first-type instruction to update a first vector parameter to a second vector parameter; and on the basis of the second vector parameter, splitting into a plurality of micro-operations a long vector instruction in the other instructions to be processed, and performing renaming processing on said other instructions on the basis of the plurality of micro-operations, wherein said other instructions are instructions among the plurality of instructions to be processed other than said first-type instruction. By means of the present disclosure, the problems in the related art of an execution part circuit in a processor being excessively complex and having an excessively large area and an enormous power consumption overhead due to the occurrence of a long vector in vector instructions are solved.

Description

Instruction processing method, device, storage medium and electronic device

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310963613.4 and invention name “Instruction processing method, device, storage medium and electronic device”, the entire content of which is incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of RISC-V high-performance out-of-order processor microarchitecture, and more specifically, to an instruction processing method, device, storage medium, and electronic device. Background Art

[0003] RISC-V is an open, reduced instruction set architecture (RISC-V). It adheres to the RISC design philosophy and the experience and lessons accumulated over decades of computer architecture development to design a sophisticated instruction set architecture. The modular standard extended instruction subsets include M / A / F / D / C / B / P / V, etc., which can be used in different application fields.

[0004] The RISC-V standard vector extension currently includes vector instructions such as addition, subtraction, multiplication, multiply-accumulate, bitwise logical AND, OR, XOR, compare, shift, min / max, permutation, and reduction. The instructions are fixed at 32 bits and support 32 general-purpose vector registers, a conditional mask register (Predicate), and related control status registers (CSRs). Conditional execution of instructions and multiple memory access modes are supported, including unit-stride, strided, and indexed scatter / gather. Furthermore, dynamic typing is particularly noteworthy. The vector length (grouping of vector registers) and individual element width (sew) can be set using the vsetvl / vsetvli / vsetivli instructions, saving coding space, supporting mixed precision, and maintaining software compatibility across different vector lengths. The vector register grouping parameters are configured using the vsetvl / vsetvli / vsetivli instructions, allowing multiple vector registers to be concatenated into a larger vector register, up to eight registers, effectively increasing the operable register width to eight times the currently implemented hardware register width. This feature makes program writing more concise and significantly reduces the amount of code to be executed. The CSR register VTYPE (vector type, vector parameter, referred to as VTYPE) stores the above-mentioned vector register grouping parameter LMUL (Vector register group multiplier (LMUL) setting, vector register group configuration, referred to as LMUL). After the vsetvl / vsetvli / vsetivli instructions configure this parameter, subsequent vector instructions will group vector registers according to this parameter, and the processing width of a single vector instruction operation will also be based on this group length until a new vsetvl / vsetvl / vsetivli instruction re-updates the parameter. After the update, all subsequent vector instructions younger than the vsetvl / vsetvli / vsetivli instruction must be executed according to the latest configuration value;

[0005] In the related art, the methods for dealing with the above-mentioned problem include the following methods: Method 1, the pipeline of a high-performance processor core is generally divided into multiple processing stages, the instruction cache (cache memory) caches the instructions to be executed, and the instruction fetch process reads the instructions to be executed from the instruction cache and sends them to the instruction decoder for decoding. Figure 3 is a schematic diagram of an instruction processing flow in the related art. When the instruction decoder recognizes that the current instruction is a vsetvl instruction that updates the vector parameter register, the vector's pause flag signal is set to 1, indicating that subsequent vector instructions need to wait for the vsetvl instruction to be executed before the next stage of renaming can be processed. Method 2, Figure 2 is a schematic diagram of another instruction processing flow in the related art. After the instruction is decoded, a vector register group value history table is added to predict the value updated by the vsetvl instruction on the register group.

[0006] However, the above-mentioned method 1 is prone to pipeline stalls due to waiting for the completion of the vsetvl instruction to obtain the vector register group value (LMUL) or the bit width (sew) of the vector element, and the design process of renaming according to the instruction granularity in the renaming stage is complicated; although the second method can alleviate the stall problem caused by the first solution, there is still one vector instruction in the first solution that needs to support register renaming far more than ordinary instructions because it supports register grouping. It needs to occupy the read and write ports of multiple renaming mapping tables or requires read and write port arbitration, which is complex in design and has high power consumption and area costs.

[0007] Currently, no effective solution has been found to the problem that the execution circuit of the processor in the vector instruction is too complex and the area and power consumption are too large.

[0008] Application Contents

[0009] The embodiments of the present disclosure provide an instruction processing method, device, storage medium, and electronic device to at least solve the problems in the related art of overly complex execution circuits in processors for vector instructions, and excessive area and power consumption overhead.

[0010] According to one embodiment of the present disclosure, a method for processing instructions is provided, comprising: determining a first category of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first category of instructions to be processed is used to update a first vector parameter in a speculative value register; updating the first vector parameter to a second vector parameter using an update method corresponding to the first category of instructions to be processed; splitting long vector instructions in other instructions to be processed into multiple micro-operations based on the second vector parameter, and renaming the other instructions to be processed according to the multiple micro-operations, wherein the other instructions to be processed are instructions other than the first category of instructions to be processed in the multiple instructions to be processed.

[0011] According to another embodiment of the present disclosure, a bandwidth adjustment system is provided, including: a determination module, configured to determine a first type of pending instructions from multiple pending instructions according to a preset instruction code, wherein the first type of pending instructions is used to update a first vector parameter in a speculative value register; an update module, configured to update the first vector parameter to a second vector parameter using an update method corresponding to the first type of pending instructions; and a processing module, configured to split long vector instructions in other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first type of pending instructions.

[0012] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0013] According to another embodiment of the present disclosure, an electronic device is provided, which may include a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0014] Through the above steps, in the system architecture corresponding to the CPU core, the preset instruction code is used to identify the first type of pending instructions to be executed, so as to speculatively obtain the second vector parameter between the instruction decoders, and then instruct the instruction disassembly sub-unit configured in the instruction decoding unit to split the long vector instructions in other pending instructions into multiple micro-operations based on the register vector grouping value contained in the second vector parameter, thereby reducing the area and power consumption overhead of the renaming and instruction issuance units for long vector processing through fine-grained micro-operations, and also reducing the complexity and power consumption overhead of the micro-operation disassembly of the long vector instructions in the execution unit. That is, by determining the vector parameters in advance and using the vector parameters to disassemble the long vector before executing the corresponding long vector, the problem of excessive complexity of the execution circuit in the processor in the vector instruction in the related art and excessive area and power consumption overhead is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic diagram of an instruction processing flow in the related art;

[0016] FIG2 is a schematic diagram of another instruction processing flow in the related art;

[0017] FIG3 is a hardware structure block diagram of a chip of an instruction processing method according to an embodiment of the present disclosure;

[0018] FIG4 is a flow chart of a method for processing instructions according to an embodiment of the present disclosure;

[0019] FIG5 is a schematic diagram of a system structure of a method for processing instructions in a CPU chip according to an embodiment of the present disclosure;

[0020] FIG6 is a schematic diagram of encoding of a Risc-v vector extension instruction vset{i}vl{i} according to an embodiment of the present disclosure;

[0021] FIG7 is a schematic diagram showing a structure of a vtype_sp update source in a method for processing instructions according to an embodiment of the present disclosure;

[0022] FIG8 is a schematic diagram of a vector register grouping configuration according to an embodiment of the present disclosure;

[0023] FIG9 is a schematic diagram of two different computing resource configurations according to an embodiment of the present disclosure;

[0024] FIG10 is a schematic structural diagram of an instruction processing device according to an embodiment of the present disclosure;

[0025] FIG11 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0028] Example 1

[0029] The method embodiment provided in the first embodiment of the present disclosure can be executed in a chip, a computer terminal or a similar computing device. Taking running on a chip as an example, Figure 3 is a hardware structure block diagram of a chip of a method for processing an instruction in an embodiment of the present disclosure. As shown in Figure 3, the chip 10 may include one or more (only one is shown in the figure) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions. It can be understood by those skilled in the art that the structure shown in Figure 3 is only for illustration and does not limit the structure of the above-mentioned electronic device. For example, the chip 10 may also include more or fewer components than those shown in Figure 3, or have a configuration different from that shown in Figure 3.

[0030] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / modules corresponding to the instruction processing method in the embodiment of the present disclosure. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the chip 10 via a network. Examples of the above-mentioned network may include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0031] The transmission device 106 is used to receive or send data via a network. Specific examples of the aforementioned network may include a wireless network provided by the communication provider of the chip 10. In one embodiment, the transmission device 106 may include a network interface controller (NIC), which can be connected to other network devices via a base station to communicate with the Internet. In one embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0032] In an exemplary embodiment, in actual application, the above instruction processing method can be applied to a CPU processor and a Risc-v CPU core IP or a SOC chip integrating a Risc-vCPU core, and the present disclosure does not impose too many restrictions on this.

[0033] In this embodiment, a method for processing an instruction is provided. FIG4 is a flow chart of the method for processing an instruction according to an embodiment of the present disclosure. As shown in FIG4 , the flow may include, but is not limited to, the following steps:

[0034] Step S202 , determining a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed are used to update a first vector parameter in a speculative value register;

[0035] In an optional embodiment, the above-mentioned preset instruction code can be a vector extension instruction determined based on the 32-bit instruction code of Risc-v, such as: vset{i}vl{i} instruction code, and the vset{i}vl{i} instruction code includes: vsetvl, vsetvli, vsetivli, etc., wherein vsetvl is used to indicate instructions that require reading registers to obtain configuration values ​​(including but not limited to vselvl), and vsetvli is used to indicate instructions that do not require reading registers and can obtain parameter configuration values ​​from the instruction code (immediate value) (including but not limited to vsetvli and vsetivli); thereby, when the instruction with the above-mentioned vset{i}vl{i} instruction code is identified in the instructions to be processed, the parameters used to update the vector parameter generation unit can be quickly determined according to the content corresponding to the instruction code.

[0036] Step S204: updating the first vector parameter to a second vector parameter using the update method corresponding to the first type of instructions to be processed;

[0037] It should be noted that after the vector parameter configured in the speculative value register is updated using the vsetvl / vsetvli / vsetivli instruction, subsequent vector instructions will group the vector registers according to the second vector parameter, and the operation processing width of a single vector instruction will also be based on this grouping length until a new vsetvl / vsetvl / vsetivli instruction is used to re-update the second vector parameter. After the update, all subsequent vector instructions younger than the vsetvl / vsetvli / vsetivli instruction must be executed according to the latest vector parameter configuration value in the speculative value register.

[0038] Step S206: Split the long vector instructions in the other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first category of pending instructions.

[0039] Through the above steps, in the system architecture corresponding to the CPU core, a preset instruction code is used to identify the first type of pending instructions to be executed, so as to speculatively obtain a second vector parameter between the instruction decoders. Then, based on the register vector grouping value contained in the second vector parameter, the instruction decomposition sub-unit configured in the instruction decoding unit is instructed to decompose the long vector instructions in other pending instructions into multiple micro-operations. This reduces the area and power consumption overhead of long vector processing by the renaming and instruction issuance units through fine-grained micro-operations, and also reduces the complexity and power consumption overhead of micro-operation decomposition of long vector instructions in the execution unit. That is, by determining the vector parameters in advance and using the vector parameters to decompose the long vector before executing the corresponding long vector, the problems of excessive complexity, area, and power consumption overhead of the execution circuit in the processor in the vector instruction in the related art are solved, thereby achieving the effect of reducing the design complexity of the execution circuit and achieving a better processing frequency within a limited area, thereby improving the user experience.

[0040] It is understandable that the presence of long vectors in vector instructions causes the naming circuits (e.g., the source register of a long vector instruction needs to query multiple registers, the destination register of the instruction needs to apply for multiple physical registers, the instruction emission circuits (e.g., the emission queue needs to save multiple register IDs and perform wake-up operations on multiple registers), and the instruction execution circuits (e.g., the long vector circuit disassembles the micro-operations of multiple short vectors, requiring the pipeline to be stalled) to be overly complex, resulting in high area and power consumption, making it impossible to execute vector instructions quickly, and greatly reducing the overall instruction processing effect. By using the above method, long vectors are disassembled in the instruction decoding unit. After disassembly, the naming circuits in the later stages of the pipeline will no longer need to be aware of the vector register grouping configuration LMUL and the change in the bit width SEW of the vector elements. The required disassembly logic circuits are reduced, thereby reducing the circuit complexity of the later stages of the pipeline and optimizing the area and power consumption.

[0041] As an optional implementation, the above method can also be applied to high-performance vector computing scenarios, such as multimedia (audio, video, image, etc.) data processing, digital signal processing, scientific computing, AI, and other computationally intensive fields, as well as high-performance CPU applications such as scalar-to-quantum optimization in compilers. In practice, by utilizing speculative vector parameter retrieval to split long vector instructions and resource-constrained vector instructions, the hardware resource overhead (area, power consumption, etc.) posed by long vector instructions in the pipeline is reduced, achieving a more optimal PPA (performance, power, area, abbreviated as PPA) balance.

[0042] In an exemplary embodiment, when the above-mentioned instruction processing method is applied in a CPU chip, the corresponding system structure will be increased: a vector parameter generation unit, a vector instruction disassembly subunit is added to the instruction decoding unit, a transmission queue vtype_sp (vector parameter speculative value) is added to the instruction emission unit, and a vtype (vector parameter) speculative correction subunit is added to the vsetvl instruction execution unit.

[0043] In an exemplary embodiment, FIG5 is a schematic diagram of a system structure of a method for processing instructions in a CPU chip according to an embodiment of the present disclosure, including:

[0044] The instruction cache unit 32 is configured to cache instructions retrieved from the next level of cache. When instructions are looped or repeatedly executed, they can be retrieved from the instruction cache (cache memory) without having to retrieve them from the lower level cache, thereby reducing the latency of accessing values ​​and improving performance.

[0045] The instruction fetch processing unit 34 is configured to query the instruction cache unit for instructions to be executed according to the instruction fetch instruction, including virtual-to-real address conversion, querying whether there is a hit, and if there is a miss, issuing a request to query the next level of cache, and performing alignment operations after obtaining the instruction;

[0046] The instruction pre-decoding unit 36 ​​is configured to identify the three instructions vsetvl, vsetvli, and vsetivli according to the 32-bit instruction encoding of Risc-v, and notify the vector parameter generation unit of the identification result;

[0047] In an exemplary embodiment, the encoding contents of the above three instructions vsetvl, vsetvli, and vsetivli are shown in FIG6 , which is a schematic diagram of encoding the Risc-v vector extension instruction vset{i}vl{i} according to an embodiment of the present disclosure.

[0048] The vector parameter generating unit 38 is configured to determine vector parameters for processing subsequent vector instructions; mainly determining the value of the vector parameter to be stored in the vector parameter speculation value register in a variety of ways.

[0049] Specifically, when it is determined that the current instruction identified by the instruction pre-decoding unit 36 ​​is a vsetvli or vsetivli instruction, an immediate value to be updated in the vtype register is parsed from the 32-bit instruction code corresponding to the vsetvli or vsetivli instruction, and the vector parameter of the vtype_sp register is updated with the immediate value.

[0050] If the current instruction is a vsetvl instruction, the characteristic information of the current thread (such as ASID and VMID, etc.) is used as matching information to search the vector parameter prediction table for matching prediction information. If so, the predicted value of vtype is obtained from the prediction table and updated to the vtype_sp register with the predicted value. It should be noted that if there is no match, the original value can be maintained, or updated to the commonly used LMUL=1 and other preset possible solutions.

[0051] It should be noted that the vector parameter in the vtype_sp register is equivalent to the speculative value of the vtype register, because it can be updated using the vsetvli / vsetivli instructions on the wrong branch path, or updated through prediction using the vsetvl instruction, so it is a speculative value;

[0052] If the vsetvl instruction occurs and the speculation correction subunit in the execution unit detects that the speculation fails, the vtype_sp register will be updated with the execution result corresponding to the processing device;

[0053] In an exemplary embodiment, if a Pipeline Flush based on the oldest instruction boundary, such as an interrupt or exception, occurs in the processing device, the vtype_sp register needs to be updated with the value of the vtype register (committed value);

[0054] The instruction decoding unit 40 is configured to be responsible for decoding all instructions. When the current instruction is identified as a vector instruction, the vector instruction disassembly subunit is used to split the subsequent vector instructions according to the LMUL value carried by the vector instruction from the vtype_sp register of the vector parameter generation unit;

[0055] The renaming unit 42 is configured to rename the split vector instructions.

[0056] It should be noted that the purpose of register renaming is to eliminate the two types of false data hazards between instructions: write-after-write and read-after-write, reduce pipeline stalls caused by these two types of false data hazards, and improve ILP (Instruction level parallelism, TLP for short), thereby achieving better performance; in high-performance processors, register renaming operations that process multiple instructions in a single clock cycle are usually supported, and the renaming unit generally supports the renaming of scalar registers (general purpose registers, scalar registers or general purpose registers, abbreviated as GPR), vector registers, and CSR (control status register); this unit is generally equipped with a mapping table from logical registers to physical registers to record the mapping relationship between the two.

[0057] The instruction emission unit 44 is configured to process the disassembled instructions according to the splitting granularity of the vector instructions. Normally, the emission queue needs to save the register ID of the instruction, which is used to query and determine whether the instruction operands in the emission queue are ready. The instruction can only be emitted after all operands are ready. If not ready, the register ID is also used for matching and waking up, and it can be emitted normally after waking up.

[0058] In actual applications, the vsetvl instruction will obtain the speculative vector parameter value, i.e., the vtype_sp value, from the vector parameter generation unit and will carry this value to each downstream processing unit. In the instruction issuance unit, each type of instruction (such as integer instructions, floating-point instructions, memory access instructions, etc.) has one or more issuance queues. The vtype_sp value carried by vsetvl must be saved in the issuance queue storing the vsetvl instruction. After the instruction is issued, the vtype_sp value must also be passed to the vsetvl execution unit and set as the vtype speculative correction judgment.

[0059] Instruction execution unit 46 is configured to execute the vsetvl instruction. The key to executing the vsetvl instruction is obtaining the configuration value of the vector parameter vtype from the general register and using this configuration value to update the vtype register during the instruction submission phase. Another key function is to correct the vtype speculative value. The vtype configuration value in the vsetvl execution result is compared with the vtype_sp value passed from the instruction issue unit. If the two are unequal, the speculation fails; if they are equal, the speculation succeeds. If the speculation fails, a flush pipeline is initiated to invalidate the instructions in the invalid pipeline and correct the value of the vtype_sp register in the vector parameter generation unit. Consequently, after completing the invalid pipeline instructions, all instructions younger than the vsetvl instruction will not use the vtype_sp speculative value that failed the speculation for instruction splitting. Instead, younger instructions will use the corrected speculative value for instruction splitting.

[0060] In an exemplary embodiment, before updating the first vector parameter to the second vector parameter using the update method corresponding to the first type of pending instructions, the above method also includes: determining the number of instructions of the first type of pending instructions existing in the multiple pending instructions; when the number of instructions is greater than a preset number, determining the update time for each instruction of the multiple first type of pending instructions to update the first vector parameter, and obtaining multiple update times; determining multiple update intervals based on the time relationship of the multiple update times, wherein the target other pending instructions processed in each update interval use the target second vector parameter most recently updated in the update interval.

[0061] Simply put, when using the first type of pending instructions to update the first vector parameter in the speculative value register, when it is determined that there are multiple first type pending instructions, in order to avoid abnormal disassembly of subsequent long vector instructions caused by unordered vector parameter updates, it is necessary to identify the time when each first type pending instruction updates the vector parameter currently stored in the speculative value register during the update, and then use the latest vector parameter in the current clock cycle to update when using the updated vector parameter to disassemble the long vector.

[0062] In an exemplary embodiment, the vector parameter generation unit can process multiple vtype vector parameter updates in the same clock cycle. For example, if two vsetvli instructions update the vtype vector parameter in the same clock cycle, the vtype_sp vector parameter speculative value register will be updated with the latest value at the same time. In addition, the order relationship between the vector instructions that use the vtype value and the vset{i}vl{i} update value must be ensured to ensure that the vector instructions can obtain a reasonable vtype_sp.

[0063] For example, there are 4 instruction sequences in the same clock, as follows:

[0064] / / cycle-1 clock cycle 1

[0065] vsetvli t0,a0,e8,m2 / / LMUL=2

[0066] vadd.vv vd,vs2,vs1,vm

[0067] vsetvli t0,a0,e16,m8 / / LMUL=8

[0068] vsub.vv vd,vs2,vs1,vm

[0069] / / cycle-2 clock cycle 2

[0070] vmul.vv vd,vs2,vs1

[0071] vadd.vv vd,vs2,vs1,vm

[0072] vsetvli t0,a0,e16,m8 / / LMUL=4

[0073] vsub.vv vd,vs2,vs1,vm,

[0074] The order of instructions from top to bottom is increasingly new, so in clock cycle 1, the vadd instruction should be split according to LMUL=2, then the LMUL carried by the vadd instruction to the decoding unit should be equal to 2, and the vsub instruction should carry LMUL=8 to the decoding unit for instruction splitting; at the end of clock cycle 1, the immediate update value of the second instruction (i.e. LMUL=8) should be updated to the vtype_sp register; further, in clock cycle 2, the vmul and vadd instructions should carry the value of vtype_sp updated in clock cycle 1 (i.e. vtype of LMUL=8) to the decoding code, and the last vsub should carry the value to be updated by the third vsetvli instruction (i.e. LMUL=4) to the decoding unit for instruction splitting.

[0075] In an exemplary embodiment, the first vector parameter is updated to a second vector parameter using an update method corresponding to the first type of pending instructions, including: when the first type of pending instructions is an immediate instruction, the first vector parameter is updated to a second vector parameter according to the encoding information of the immediate instruction; when the first type of pending instructions is a non-immediate instruction, the first vector parameter is updated to a second vector parameter through a prediction value associated with the non-immediate instruction.

[0076] That is to say, if the instruction to be processed is identified as the vsetivli / vsetvli instruction (immediate value) under the vset{i}vl{i} extended instruction, the configuration value can be obtained according to the encoded immediate value of the instruction itself, and the current vtype speculative value (the value of the vtype_sp register) can be updated with this configuration value. All subsequent vector instructions will carry this vtype speculative value to the instruction decoding unit until there is a new vset{i}vl{i} instruction to update or the instruction submission part repairs the vtype speculative value, or the current value saved in the vtype_sp register is corrected after the vector parameter speculation fails.

[0077] If the instruction to be processed is identified as a vsetvl instruction (non-immediate value) under the vset{i}vl{i} extended instruction, a vtype prediction value is obtained by prediction based on thread feature information, and vtype_sp (vtype speculative value) is updated with the prediction value; wherein the above non-immediate value is used to indicate that the configuration value needs to be obtained through a register.

[0078] In addition, it should be noted that if the instruction to be processed is not any of the vset{i}vl{i} extended instructions, the current vtype speculative value needs to be maintained, and subsequent vector instructions carry the current vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction or instruction submission unit updates the speculative value of the vector parameter generation unit.

[0079] In an exemplary embodiment, updating the first vector parameter to a second vector parameter according to the encoding information of the immediate instruction includes: determining a first configuration value of the vector register group configuration and a second configuration value corresponding to the bit width of the vector element according to the encoding information of the immediate instruction; and updating the first vector parameter to a second vector parameter using the first configuration value and the second configuration value.

[0080] In an exemplary embodiment, updating the first vector parameter to a second vector parameter using a prediction value associated with the non-immediate instruction includes: determining characteristic information corresponding to a thread processing the non-immediate instruction; searching for a prediction value matching the characteristic information in a preset vector parameter prediction table, and using the prediction value to update the first vector parameter to a second vector parameter.

[0081] In an exemplary embodiment, after using the predicted value to update the first vector parameter to the second vector parameter, the above method also includes: obtaining the execution result corresponding to the non-immediate instruction, and determining the actual value corresponding to the execution result; comparing the actual value and the predicted value to determine whether the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid based on the comparison result.

[0082] It is understandable that since the vsetvl instruction (equivalent to the above-mentioned non-immediate instruction) is mostly used to restore the context after thread switching, the thread history record can be used for prediction, but the prediction may be wrong. In order to promptly and effectively determine the wrong prediction, the vsetvl instruction can carry the vtype prediction value obtained from the prediction table and carry it to the execution unit along with the vsetvl instruction itself. When the execution unit has obtained the source operand, it executes the instruction and obtains the execution result. By comparing the execution result with the vtype prediction value, it is tested whether the prediction is normal.

[0083] In an exemplary embodiment, the actual value and the predicted value are compared to determine whether a speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid based on the comparison result, including: when the actual value is the same as the predicted value, determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid; when the actual value is different from the predicted value, determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid.

[0084] In an exemplary embodiment, when the execution result of the execution unit is not equal to the vtype prediction value, it indicates that the prediction is wrong, the speculation fails, and a new vtype prediction value needs to be re-determined; if the execution result of the execution unit is equal to the vtype prediction value, the speculation is successful, and the vtype prediction value is used to split and rename multiple long vectors in the clock cycle after the vsetvl instruction.

[0085] In an exemplary embodiment, when the actual value is different from the predicted value, after determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid, the method further includes: updating the first vector parameter in the speculative value register using the actual value to obtain a third vector parameter; identifying a target pending instruction to be processed after the non-immediate instruction among the multiple pending instructions; when the target pending instruction is a long vector, using the third vector parameter to split the target pending instruction into multiple target micro-operations; and renaming the target pending instruction according to the multiple target micro-operations.

[0086] In one exemplary embodiment, since all pending instructions newer than the vsetvl instruction are processed based on the vtype prediction value, when speculation fails, to ensure that these pending instructions newer than the vsetvl instruction can be effectively processed, these pending instructions are flushed to invalidate the pipeline instructions. This invalidates the vtype prediction values ​​carried by these pending instructions, making it impossible to split the vector instructions based on the vtype prediction values ​​that failed speculation. Subsequently, the vtype_sp value needs to be updated with the execution result of the vsetvl instruction, and instruction fetching and execution restart from the instruction following the vsetvl instruction, ensuring that the re-fetched instructions can be subsequently processed based on the correct vtype_sp value.

[0087] Obviously, the embodiments described above are only part of the embodiments of the present disclosure, rather than all the embodiments. In order to better understand the above method, the above process is described below in conjunction with the embodiments, but it is not intended to limit the technical solutions of the embodiments of the present disclosure. Specifically:

[0088] In an exemplary embodiment, a RISC-V vector instruction processing method is provided, which specifically includes the following steps:

[0089] Step 1: Pre-decode the instruction fetched and identify whether it is a vset{i}vl{i} instruction. Based on the identification result, determine the source of the vector parameter used to update the speculative value in the vtype_sp register. Figure 7 is a schematic diagram of the structure of the vtype_sp update source in the instruction processing method according to an embodiment of the present disclosure. The specific details involved are as follows:

[0090] Case 1: Since vsetvl is obtained through the prediction table and is a speculative prediction value, the execution unit compares the execution result of the vsetvl instruction with the prediction value. If it does not match, it means the prediction is wrong and the vtype speculation fails. It is necessary to synchronize the execution result of the vsetvl instruction to correct the speculative value saved in the vtype_sp register. That is, the execution unit will send the correct vtype value to restore the vtype_sp speculative value, and subsequent instructions will be split based on the restored speculative value.

[0091] Case 2: If it is a vsetvl instruction (non-immediate value, that is, the configuration value needs to be obtained through a register), the vtype prediction value is obtained by prediction based on the thread feature information, and the vtype_sp (vtype speculative value) is updated with the prediction value; wherein, the above prediction is used to indicate that the vtype prediction value of the corresponding thread is searched in the vector parameter register prediction table according to the thread feature information.

[0092] Case 3: If it is a vsetivli / vsetvli instruction (immediate value), the configuration value obtained from the encoded immediate value of the instruction itself can be used to update the current vtype speculative value (the value of the vtype_sp register). All subsequent vector instructions will carry this vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction is used to update it or the instruction submission part repairs the vtype speculative value, or vtype_sp is corrected after the vector parameter speculation fails.

[0093] It should be noted that if it is not a vset{i}vl{i} instruction, the current vtype speculative value is maintained, and subsequent vector instructions carry the current vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction or instruction submission unit updates the speculative value;

[0094] Case 4: When a pipeline flush invalidates instructions on the pipeline due to a branch prediction error or an interrupt or exception, it is necessary to restore the value in the vtype vector parameter register and the value in the vtype_sp vector parameter speculative value register, because the vset{i}vl{i} instruction on the instruction stream before the flush point will update vtype to an inaccurate value.

[0095] Step 2: The instruction decoding unit disassembles the vector instruction according to the configuration value of LMUL in the vtype speculative value.

[0096] For example, currently LMUL=8 indicates that 8 vector registers form a group, and the vector length is 8*VLEN, where VLEN is a constant parameter determined by the specific implementation and is set to specify the width of a single vector register, such as 128-bit. FIG8 is a schematic diagram of a vector register grouping configuration according to an embodiment of the present disclosure.

[0097] The instruction decoding unit disassembles a vector instruction affected by LMUL into 8 uops (micro-operations) according to the VLEN granularity. The length of a single uop is equivalent to the vector length when LMUL=1. Since the decoding unit only outputs a specific number of decoded instructions per clock, there is a maximum number limit. For example, a maximum of 4 decoded instructions are output per clock cycle. Then the above-mentioned vector instruction will require 2 clock cycles to complete the disassembly.

[0098] If long vector instructions are not decomposed, such as LMUL=8, then a vector instruction with two source operands and one destination operand needs to read the renaming mapping of 8x2=16 registers and apply for 8 free physical registers as the destination registers. High-performance processor cores generally process multiple instructions in a single clock. For example, if there are 4 instructions, a single clock cycle requires 8x16=128 renaming mapping table read ports to obtain the mapping relationship. At the same time, a single clock cycle requires 32 free physical registers to apply. In addition, the instruction issuance unit needs to save multiple source registers and destination registers, and multiple source registers need to be compared during instruction wakeup. The area and power consumption are very high. The power consumption is relatively large. If the long vector instructions are disassembled and processed at the granularity of LMUL=1, the processing logic related to the registers in the back-end pipeline can be reduced to 1 / 8 of the original, which greatly simplifies the complexity and area of ​​the design, and the power consumption overhead; high-performance processing is generally a high-frequency design, and the frequency generally reaches more than 3GHz. After the instruction is disassembled and simplified, the design can achieve a better frequency; in addition, the rename unit has 128 read ports, or the wakeup circuits of multiple registers of the instruction issuance unit will cause congestion due to excessive connections in the local area in physical implementation, which is not conducive to physical implementation, and may further make the timing worse and the power consumption overhead greater.

[0099] In an exemplary embodiment, in order to achieve a balance between area, power consumption, and performance, the execution units of certain special vector instructions (e.g., a single execution unit with a large area) are not equipped with execution units according to the maximum number of vector elements vlmax; assuming that the bit width of the vector element sew = 16 bits and VLEN = 128 bits, then vlmax = 128 / 16 = 8, and the instruction decoder can then disassemble the vector instruction according to the sew configuration. The method for obtaining sew is the same as LMUL, obtained from the previous vector parameter generation unit, and the vector parameter generation unit also processes sew in the same way;

[0100] Disassembling through the instruction decoder reduces the complexity, area, and power consumption of further disassembly in the execution unit and the emission unit. Because most execution units process instructions in a pipeline manner, instructions will enter the pipeline back to back. If an instruction in the middle needs to be disassembled, it is necessary to stall the pipeline and give up resources to let the disassembled uop process, which is easy to cause pipeline bubbles and cause pipeline Flush, flush those instructions that have been issued but cannot enter the execution unit for execution, because the instruction disassembly temporarily stalls the pipeline process and cannot enter the execution unit. It needs to be re-issued after flushing, which wastes a lot of power consumption. If the instruction is disassembled in the emission unit, it is necessary to add a disassembly logic circuit for each record entry in the emission queue. Usually, the emission queue consists of multiple record entries. If each record entry requires a set of disassembly logic, the area and power consumption overhead will also be large. However, through the above disassembly process, the instruction decoding unit only needs to disassemble according to the decoding width. Generally, the decoding width is much smaller than the number of emission queue entries. After disassembly, the later stages of the pipeline (renaming, emission unit, etc.) do not need to perceive the changes in LMUL and SEW. Therefore, the circuit complexity of the later stages of the pipeline is reduced, and the area and power consumption are optimized.

[0101] Step 3: The rename unit processes the instructions according to the uop granularity;

[0102] It should be noted that after the above processing, although LMUL=8, the vector register width seen by the renaming unit is always the VLEN width, which is not affected by changes in the vector register grouping configuration LMUL; the renaming unit does not need more renaming mapping table read ports and read port arbitration logic to adapt to the situation where LMUL>1, and does not need to allocate 8 times the number of free registers (the maximum number of LMUL is 8) per clock cycle. It also simplifies the free physical register allocation and management logic, which can achieve better timing, power consumption, and area.

[0103] Step 4: The issue unit processes the disassembled instructions according to the uop granularity. Normally, the issue queue needs to save the register ID (identification, identifier, abbreviated as ID) of the instruction, which is used to query and determine whether the instruction operands in the issue queue are ready. Only when all operands are ready can they be issued. If not ready, the register ID is also used for matching and awakening. Only after awakening can it be issued normally; after the decoding unit disassembles the vector instruction, the entry of the issue queue only needs to save the register ID with uop and VLEN as the granularity, and does not need to save the register ID of the entire instruction. It should be noted that since the maximum LMUL is 8, the maximum number of register IDs for a single instruction is 8 times that of a single uop), that is, the issue unit does not need to be affected by the change of LMUL, which can greatly reduce the area overhead of saving the register ID; in addition, the process of waking up the instruction of the issue queue needs to compare the register ID saved in the entry, so the fewer the register ID, the fewer the corresponding comparators, and the naturally less area and power consumption. And it is necessary to check whether all source operands are ready. If there are too many registers, the timing will naturally be worse. After the instruction is disassembled, it is only necessary to determine the number of registers at the uop granularity, and the timing will be better.

[0104] Step 5: The execution unit processes the disassembled instructions according to the uop granularity. It does not need to equip the computing components according to the vector bit width configured by LMUL, such as: LMUL=8, the vector width is 8 times the physical register width. At this time, if the execution components are equipped with 8 times the number, the area and power consumption will be relatively large. And when the value of LMUL is configured to be relatively small, the execution components cannot be fully utilized.

[0105] FIG9 is a schematic diagram of two different computing resource configurations according to an embodiment of the present disclosure. To implement a 128-bit VLEN constant parameter, a comparison is made between supporting four 32-bit dividers and 32 dividers. If dividers are configured based on the maximum vector (vector register grouping configuration LMUL=8), when LMUL=1, 32-4=28 dividers are idle, resulting in very low area efficiency. LMUL=1 is also used more often. Therefore, a more balanced design configures computing resources (e.g., the number of dividers) based on the VLEN width and achieves a better balance between area and performance by disassembling uops. As previously shown, disassembling uops in the decode stage (before rename) is the best approach. The later the uop is, the more information needs to be transmitted in the pipeline, resulting in greater power consumption and area overhead.

[0106] In an exemplary embodiment, an optional embodiment of the present disclosure further provides a fast recovery solution for a vsetvl speculation failure. As shown in FIG5 , the vsetvl instruction can carry a vtype prediction value obtained from a prediction table and carry it along with the vsetvl instruction itself to the execution unit. The execution unit has obtained the source operand and can execute the instruction and obtain an execution result. By comparing the execution result with the vtype prediction value, it can be detected whether the prediction is normal. If they are not equal, it indicates that the prediction is wrong and the speculation failed; if they are equal, the speculation succeeds. Because all instructions newer than vsetvl are processed based on the prediction value (or speculation value), if the speculation fails, it is necessary to flush all instructions newer than vsetvl, and then restart instruction fetching and execution from the next instruction after vsetvl. However, before this, the value of vtype_sp needs to be updated with the execution result of vsetvl to ensure that the re-fetched instruction can perform subsequent processing (such as disassembling uop) based on the correct vtype_sp value.

[0107] It should be noted that since the source operand of the vsetvl instruction (used to update the vtype register) comes from a GPR (general purpose register), it is possible that this source operand is the result of an older instruction that has not undergone register renaming or other related processing. Therefore, the source operand is unavailable during the instruction pre-decode and decode stages. Furthermore, vector instruction decomposition depends on the vtype vector parameter. One solution is to stall the vsetvl instruction in the pipeline, awaiting the result of the older instruction and then processing it once the result is available. However, this causes a pipeline stall (the vsetvl instruction relies on memory access data return, which can be very long if there are multiple cache misses. If it does not rely on the results of other instructions, it can typically stall for 5-10 cycles, depending on the specific microarchitecture implementation), blocking subsequent out-of-order execution of instructions and significantly impacting performance. Another solution is to use thread feature information for prediction. Since the vsetvl instruction is often used to restore context after a thread switch, thread history records can be used for prediction. However, predictions can be incorrect. Therefore, such errors must be detected and quickly recovered from, eliminating the need to wait until the instruction reaches the commit stage to check whether the prediction is correct. This improves performance. Because thread feature information is relatively clear, the probability of incorrect predictions is relatively high. Prediction can reduce pipeline stalls, significantly improving performance.

[0108] In an exemplary embodiment, in actual application, the above implementation can also be applied to the following specific scenarios:

[0109] Scenario 1: All general-purpose CPU cores that support vector instructions;

[0110] Scenario 2: Application to DSP processor, vector processor or GPU;

[0111] Scenario 3: When applied to processors that only support scalar operations, some complex scalar instructions may require speculative uop disassembly based on certain configuration parameters and rapid recovery after speculation fails;

[0112] Scenario 4: Application in SOC chips, for example, in the main control SOC chip of communication equipment (routers, switches, base station controllers, etc.), used to control and manage various operations of communication equipment; or used in baseband signal processing SOC chips.

[0113] Through the above embodiment, vector instruction disassembly is performed by speculatively obtaining vector parameter information (including LMUL, but not limited to LMUL, such as SEW) in advance, without pausing the pipeline to wait for the execution result of vsetvl; if Vsetvl may depend on the results of other instructions, the waiting time will be relatively long, and the pipeline pause time will be relatively long. By predicting and obtaining the vtype value in advance, the pipeline pause can be reduced, thereby achieving better performance; by disassembling long vector instructions, the design complexity of the CPU core back-end pipeline (including the rename unit, instruction issue unit, instruction execution unit, etc.) can be reduced, the area and power consumption overhead can be reduced, and better surface effect and energy efficiency can be achieved. Furthermore, high-performance processing cores generally submit instructions sequentially. Through the above-mentioned fast recovery method after prediction failure, there is no need to wait for the vsetvl instruction to reach the submission stage to check whether the vtype prediction is correct. Instead, the vsetvl instruction is immediately restored after obtaining the instruction result in the instruction execution stage, thereby reducing the time between the completion of instruction execution and instruction submission, and recovering in advance to achieve better performance; because instructions are queued and submitted in sequence according to programorder, if there are more instructions before vsetvl, the time between the completion of instruction execution and instruction submission will be longer. By using the fast recovery method in the above embodiment to immediately recover after the instruction execution is completed, this time can be reduced to achieve better performance.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as read-only memory / random access memory (ROM / RAM), a magnetic disk, or an optical disk), and can include a number of instructions to enable a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

[0115] Example 2

[0116] In this embodiment, a method and apparatus for processing instructions is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments. Details already described are omitted for clarity. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0117] FIG10 is a schematic diagram of the structure of an instruction processing device according to an embodiment of the present disclosure. As shown in FIG10 , the device may include:

[0118] a determination module 72 configured to determine a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed are used to update a first vector parameter in a speculative value register;

[0119] An updating module 74 is configured to update the first vector parameter to a second vector parameter using an updating method corresponding to the first type of instructions to be processed;

[0120] The processing module 76 is configured to split the long vector instructions in other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first type of pending instructions.

[0121] Through the above-mentioned device, in the system architecture corresponding to the CPU core, a preset instruction code is used to identify the first type of pending instructions to be executed, so as to speculatively obtain a second vector parameter between the instruction decoders. Then, based on the register vector grouping value contained in the second vector parameter, the instruction decomposition sub-unit configured in the instruction decoding unit is instructed to decompose the long vector instructions in other pending instructions into multiple micro-operations. This reduces the area and power consumption overhead of the renaming and instruction issuance units for long vector processing through fine-grained micro-operations, and can also reduce the complexity and power consumption overhead of micro-operation decomposition of long vector instructions in the execution unit. That is, by determining the vector parameters in advance and using the vector parameters to decompose the long vectors between the execution of the corresponding long vectors, the problems of excessive complexity, area and power consumption overhead of the execution circuit in the processor in the vector instructions in the related art are solved, thereby achieving the effect of reducing the design complexity of the execution circuit and achieving a better processing frequency within a limited area, thereby improving the user experience.

[0122] As an optional embodiment, the above-mentioned device may also include: a time module, which is configured to determine the number of instructions of the first type of pending instructions existing in the multiple pending instructions before updating the first vector parameter to the second vector parameter using the update method corresponding to the first type of pending instructions; when the number of instructions is greater than the preset number, determine the update time for each instruction in the multiple first types of pending instructions to update the first vector parameter, and obtain multiple update times; determine multiple update intervals based on the time relationship of the multiple update times, wherein the target other pending instructions processed in each update interval use the target second vector parameter most recently updated in the update interval.

[0123] As an optional embodiment, the above-mentioned update module is also used to update the first vector parameter to a second vector parameter according to the encoding information of the immediate instruction when the first type of pending instruction is an immediate instruction; and to update the first vector parameter to a second vector parameter through the prediction value associated with the non-immediate instruction when the first type of pending instruction is a non-immediate instruction.

[0124] As an optional implementation, the above-mentioned update module is also used to determine the first configuration value of the vector register group configuration and the second configuration value corresponding to the bit width of the vector element based on the encoding information of the immediate instruction; and use the first configuration value and the second configuration value to update the first vector parameter to the second vector parameter.

[0125] As an optional implementation, the above-mentioned update module is also used to determine the characteristic information corresponding to the thread that processes the non-immediate instruction; search for a prediction value matching the characteristic information in a preset vector parameter prediction table, and use the prediction value to update the first vector parameter to a second vector parameter.

[0126] As an optional embodiment, the above-mentioned update module also includes: a comparison unit, which is configured to obtain the execution result corresponding to the non-immediate instruction after using the predicted value to update the first vector parameter to the second vector parameter, and determine the actual value corresponding to the execution result; compare the actual value and the predicted value to determine whether the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid based on the comparison result.

[0127] As an optional embodiment, the above-mentioned comparison unit is also used to determine that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid when the actual value is the same as the predicted value; and to determine that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid when the actual value is different from the predicted value.

[0128] As an optional embodiment, the above-mentioned update module also includes: an update unit, configured to use the actual value to update the first vector parameter in the speculative value register to obtain a third vector parameter; identify the target pending instruction to be processed after the non-immediate instruction among the multiple pending instructions; when the target pending instruction is a long vector, use the third vector parameter to split the target pending instruction into multiple target micro-operations; and rename the target pending instruction according to the multiple target micro-operations.

[0129] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0130] To facilitate understanding of the technical solutions provided by the present disclosure, embodiments of specific scenarios will be described in detail below.

[0131] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0132] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0133] An embodiment of the present disclosure further provides an electronic device, which may include a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0134] Optionally, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0135] S1, determining a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed are used to update a first vector parameter in a speculative value register;

[0136] S2, updating the first vector parameter to a second vector parameter using an update method corresponding to the first type of pending instructions;

[0137] S3. Split the long vector instructions in other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first category of pending instructions.

[0138] Alternatively, those skilled in the art will appreciate that the structure shown in FIG11 is merely illustrative, and the electronic device may also be a smartphone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile internet device (MID), a PAD, or other terminal device. FIG11 does not limit the structure of the electronic device. For example, the electronic device may include more or fewer components (such as a network interface, etc.) than those shown in FIG11, or may have a configuration different from that shown in FIG11.

[0139] The memory 902 can be used to store software programs and modules, such as the program instructions / modules corresponding to the instruction processing method and apparatus in the embodiments of the present disclosure. The processor 904 executes the software programs and modules stored in the memory 902 to execute various functional applications and data processing, thereby implementing the above-mentioned instruction processing method. The memory 902 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 902 may further include a memory remotely located relative to the processor 904, and these remote memories may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof. As an example, as shown in FIG11 , the memory 902 may include, but is not limited to, the determination module 72, the update module 74, and the processing module 76 of the instruction processing method apparatus. In addition, other module units of the instruction processing method apparatus may also be included, but are not limited to, the above-mentioned instruction processing method apparatus, which will not be further described in this example.

[0140] Optionally, the transmission device 906 is used to receive or send data via a network. Specific examples of the network may include wired networks and wireless networks. In one embodiment, the transmission device 906 includes a network interface controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In one embodiment, the transmission device 906 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0141] In addition, the electronic device further includes: a display 908 configured to display the instructions to be processed; and a connection bus 910 configured to connect various module components in the electronic device.

[0142] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0143] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0144] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0145] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be within the scope of protection of the present disclosure.

Claims

1. A method for processing an instruction, comprising: Determining a first type of pending instructions from a plurality of pending instructions according to a preset instruction code, wherein the first type of pending instructions is used to update a first vector parameter in a speculative value register; Using the update method corresponding to the first type of pending instructions, the first vector parameter is updated to a second vector parameter; Based on the second vector parameter, a long vector instruction in other pending instructions is split into multiple micro-operations, and the other pending instructions are renamed according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions except the first type of pending instructions.

2. The method according to claim 1, wherein: Before updating the first vector parameter to a second vector parameter using the update method corresponding to the first type of instructions to be processed, the method further includes: Determining the number of instructions of the first category of pending instructions existing in the plurality of pending instructions; When the number of instructions is greater than a preset number, determining an update time for each of a plurality of first-category to-be-processed instructions to update the first vector parameter, to obtain a plurality of update times; A plurality of update intervals are determined according to the time relationship of the plurality of update times, wherein the target other instructions to be processed in each update interval use the target second vector parameters of the most recently updated target in the update interval.

3. The method according to claim 1, wherein: Updating the first vector parameter to a second vector parameter using an update method corresponding to the first type of instructions to be processed includes: When the first type of to-be-processed instruction is an immediate instruction, updating the first vector parameter to a second vector parameter according to encoding information of the immediate instruction; In a case where the first type of to-be-processed instruction is a non-immediate instruction, the first vector parameter is updated to a second vector parameter by using a prediction value associated with the non-immediate instruction.

4. The method according to claim 3, wherein: Updating the first vector parameter to a second vector parameter according to the encoding information of the immediate instruction includes: Determine, according to the encoding information of the immediate instruction, a first configuration value of the vector register group configuration and a second configuration value corresponding to the bit width of the vector element; The first vector parameter is updated to a second vector parameter using the first configuration value and the second configuration value.

5. The method according to claim 3, wherein: Updating the first vector parameter to a second vector parameter using a prediction value associated with the non-immediate instruction comprises: Determine characteristic information corresponding to the thread processing the non-immediate instruction; A prediction value matching the feature information is searched in a preset vector parameter prediction table, and the first vector parameter is updated to a second vector parameter using the prediction value.

6. The method according to claim 5, wherein: After updating the first vector parameter to a second vector parameter using the predicted value, the method further includes: Obtaining an execution result corresponding to the non-immediate instruction, and determining an actual value corresponding to the execution result; The actual value and the predicted value are compared to determine whether a speculative operation of updating the first vector parameter to a second vector parameter using the predicted value is valid according to the comparison result.

7. The method according to claim 6, wherein: Comparing the actual value with the predicted value to determine whether a speculative operation of updating the first vector parameter to a second vector parameter using the predicted value is valid according to the comparison result, comprising: In the case where the actual value is the same as the predicted value, determining that a speculative operation of updating the first vector parameter to a second vector parameter using the predicted value is valid; In the case where the actual value is not the same as the predicted value, it is determined that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid.

8. The method according to claim 7, wherein: In the case where the actual value is different from the predicted value, after determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid, the method further includes: Using the actual value to update the first vector parameter in the speculative value register, to obtain a third vector parameter; identifying a target pending instruction among the plurality of pending instructions to be processed after the non-immediate instruction; In the case where the target instruction to be processed is a long vector, splitting the target instruction to be processed into a plurality of target micro-operations using the third vector parameter; The target to-be-processed instruction is renamed according to the multiple target micro-operations.

9. An instruction processing device, comprising: a determination module, configured to determine a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed is used to update a first vector parameter in a speculative value register; An updating module, configured to update the first vector parameter to a second vector parameter using an updating method corresponding to the first type of instructions to be processed; A processing module is configured to split a long vector instruction in other instructions to be processed into multiple micro-operations based on the second vector parameter, and rename the other instructions to be processed according to the multiple micro-operations, wherein the other instructions to be processed are instructions in the multiple instructions to be processed except the first type of instructions to be processed.

10. A computer-readable storage medium having a computer program stored therein, wherein: When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 8 are implemented.

11. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in any one of claims 1 to 8 when executing the computer program.

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