Multiplier, multiply-accumulate circuit, operational circuit, processor, and computing device

Abstract

Provided are a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a computing device. The operational circuit comprises an input processing circuit (200) and a multiply-accumulate circuit (100). The input processing circuit (200) receives a first number, if the first number is a signed number, negates a sign bit of the first number and then outputs the first number as a first multiplicator for feeding into the multiply-accumulate circuit (100), and if the first number is an unsigned number, directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit (100). The input processing circuit (200) further receives a pre-known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit (100). The multiply-accumulate circuit (100) comprises a multiply sub-circuit (111) and an accumulate sub-circuit (112). The multiply sub-circuit (111) comprises a multiplier for performing multiplication of the first multiplicator and the second multiplicator and providing an unsigned output. The accumulate sub-circuit (112) receives and accumulates the output of the multiply sub-circuit.

Description

Multiplier, multiplication and accumulation circuit, operation circuit, processor and computing device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims priority to the Chinese patent application with Chinese application number 202311056807.2 and application date August 22, 2023. The disclosed content of the Chinese patent application is hereby introduced as a whole into this application. Technical Field

[0003] The present disclosure relates to the technical field of data processing, and more particularly, to a multiplier, a multiplication-accumulation circuit, an operation circuit, and a processor and a computing device including the multiplier or the multiplication-accumulation circuit or the operation circuit. Background Art

[0004] Multiply and Accumulate (MAC) circuits are used to perform multiply-accumulate operations such as vector multiplication, matrix multiplication, and vector-matrix multiplication. They are extremely important computational subsystems in processors such as coprocessors, digital signal processors, central processing units, special-purpose instruction processors, and neural network processors. In particular, the rapid development of artificial intelligence has highlighted the important role of neural network processors, making neural network processors the cornerstone of intelligent computing technology. The convolutional computing unit is the core unit of the neural network processor. Its implementation is inseparable from the multiply-accumulate circuits that perform multiplication and accumulation operations on activation data and weight data. Therefore, the design of the multiply-accumulate circuit is crucial for the convolutional computing unit and neural network processor.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a multiplier is provided for performing a multiplication operation between a first multiplier and a second multiplier, wherein the first multiplier is an unsigned number and the second multiplier is a pre-known unsigned number or a signed number. The multiplier includes: a partial product generation circuit configured to receive the first multiplier and the second multiplier and output their partial products; and a partial product summation circuit, wherein the input of the partial product summation circuit is coupled to the output of the partial product generation circuit and the partial product summation circuit is configured to receive and sum the partial products output by the partial product generation circuit. The partial product generation circuit includes a first partial product generation unit for outputting a partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit is configured to: if the second multiplier is an unsigned number, output the partial product of the most significant bit of the second multiplier and the first multiplier; and if the second multiplier is a signed number, output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier.

[0007] In some embodiments, the first partial product generating unit is configured to: receive a sign flag indicating whether the second multiplier is an unsigned number or a signed number; when the sign flag indicates that the second multiplier is an unsigned number, output the partial product of the highest bit of the second multiplier and the first multiplier; when the sign flag indicates that the second multiplier is a signed number, output the inverted result of the partial product of the highest bit of the second multiplier and the first multiplier.

[0008] In some embodiments, the first partial product generating unit includes: an AND gate group, configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; an XOR gate group, configured to receive the AND operation result of the AND gate group and the sign flag and perform an XOR operation on them, wherein the XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit.

[0009] In some embodiments, the first partial product generating unit includes: a NAND gate group, configured to receive the highest bit of the second multiplier and the first multiplier and perform a NAND operation on them; an XOR gate group, configured to receive the NAND operation result of the NAND gate group and the sign flag and perform an XOR operation on them, wherein the XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit.

[0010] In some embodiments, the first partial product generating unit includes: an XOR gate, configured to receive the highest bit of the second multiplier and the sign flag bit and perform an XOR operation on them; a multiplexer group, each multiplexer in the multiplexer group is configured to receive the sign flag bit as a first input, receive the XOR operation result of the XOR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer group is provided as the output of the first partial product generating unit.

[0011] In some embodiments, the first partial product generating unit includes: an XOR gate, configured to receive the highest bit of the second multiplier and the sign flag and perform an XOR operation on them; an inverting multiplexer group, each inverting multiplexer in the inverting multiplexer group being configured to receive the sign flag as a first input, receive the XOR operation result of the XOR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the inverting multiplexer group is provided as the output of the first partial product generating unit.

[0012] In some embodiments, the first partial product generating unit includes: an AND gate group, configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; a multiplexer group, configured to receive the AND operation result of the AND gate group as a first input, receive the inverted result of the AND operation result of the AND gate group as a second input, receive the sign flag as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer group is provided as the output of the first partial product generating unit.

[0013] In some embodiments, the multiplier has a dual output terminal, and the partial product summation circuit includes: a partial product compression circuit, the input terminal of the partial product compression circuit being coupled to the output terminal of the partial product generation circuit, the partial product compression circuit being configured to receive the partial products output by the partial product generation circuit and compress and sum them to output the sum digits and carries of the compressed summation results of the partial products. In some embodiments, the multiplier has a single output terminal, and the partial product summation circuit includes: a partial product compression circuit, the input terminal of the partial product compression circuit being coupled to the output terminal of the partial product generation circuit, the partial product compression circuit being configured to receive the partial products output by the partial product generation circuit and compress and sum them to output the sum digits and carries of the compressed summation results of the partial products; and a final addition circuit, the input terminal of the final addition circuit being coupled to the output terminal of the partial product compression circuit, the final addition circuit being configured to receive the sum digits and carries output by the partial product compression circuit and sum them.

[0014] In some embodiments, the partial product generation circuit further includes a second partial product generation unit for outputting a partial product of a modified second multiplier and the first multiplier, the modified second multiplier being obtained by removing the highest bit of the second multiplier and being an unsigned number, and the second partial product generation unit including a multiplier for performing an unsigned-unsigned-number multiplication operation.

[0015] In some embodiments, the partial product generation circuit further includes a plurality of second partial product generation units, each of the plurality of second partial product generation units being configured to output a partial product of a corresponding bit of the second multiplier except for a highest bit and the first multiplier.

[0016] In some embodiments, each of the plurality of second partial product generating units comprises an AND gate group configured to receive corresponding bits of the second multiplier other than the most significant bit and the first multiplier and perform an AND operation thereon, wherein the AND operation result of the AND gate group is provided as the output of the second partial product generating unit. In some embodiments, each of the plurality of second partial product generating units comprises a NAND gate group configured to receive corresponding bits of the second multiplier other than the most significant bit and the first multiplier and perform a NAND operation thereon, wherein the NAND operation result of the NAND gate group is provided as the output of the second partial product generating unit.

[0017] In some embodiments, the output of the partial product summation circuit is coupled to the input of an additional adding circuit, wherein the additional adding circuit is configured to add the output of the partial product summation circuit to a constant when the second multiplier is a signed number, wherein the constant is (1-2 w )·2 w-1 , where w is the bit width of the second multiplier.

[0018] According to a second aspect of the present disclosure, a multiplication-accumulation circuit is provided for performing a plurality of multiplication-accumulation operations on a first number and a second number, wherein the second number is known in advance. The multiplication-accumulation circuit includes at least one multiplication-accumulation unit. The multiplication-accumulation unit includes: a multiplication subcircuit, the multiplication subcircuit including a multiplier for performing a multiplication operation on a first multiplier and a second multiplier, the first multiplier being obtained from the first number and being an unsigned number, the second multiplier being obtained from the second number and being an unsigned number or a signed number known in advance, the multiplier being configured to provide an output as an unsigned number; and an accumulation subcircuit, the input end of the accumulation subcircuit being coupled to the output end of the multiplication subcircuit, the accumulation subcircuit being configured to receive the output of the multiplication subcircuit and accumulate it.

[0019] In some embodiments, the multiplier of the multiplication subcircuit is the multiplier according to any embodiment of the first aspect of the present disclosure.

[0020] In some embodiments, the multiplication subcircuit includes a plurality of the multipliers, each of the multipliers being configured to receive a corresponding pair of the first multiplier and the second multiplier and to perform a product of the corresponding pair of the first multiplier and the second multiplier.

[0021] In some embodiments, the accumulation subcircuit includes: an n-level compression tree, a first adder, a second adder and a register group, the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the first adder, the output end of the first adder is coupled to the corresponding input end of the second adder, the output end of the second adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the second adder, wherein n is a positive integer, i=1, 2,…, n-1.

[0022] In some embodiments, the accumulation subcircuit includes: an n-level compression tree, a full adder, an adder and a register group, the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the full adder, the output end of the full adder is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the full adder, wherein n is a positive integer, i=1, 2, ..., n-1.

[0023] In some embodiments, the accumulation subcircuit includes: an n-level compression tree, an adder and a register group, the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree in the n-level compression tree, the output end of the i-th level compression tree in the n-level compression tree is coupled to the corresponding input end of the (i+1)-th level compression tree in the n-level compression tree, the output end of the n-level compression tree in the n-level compression tree is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the first-level compression tree in the n-level compression tree, wherein n is a positive integer, i=1, 2,…, n-1.

[0024] In some embodiments, the accumulation subcircuit includes: a full adder module having one or more stages of full adders, an adder, and a register group. The output of the multiplication subcircuit is coupled to the corresponding input of the full adder module, the output of the full adder module is coupled to the corresponding input of the adder, the output of the adder is coupled to the input of the register group, and the output of the register group is coupled to the corresponding input of the full adder module.

[0025] In some embodiments, the at least one multiplication-accumulation unit includes two or more of the multiplication-accumulation units, and the multiplication-accumulation circuit also includes a summing unit, the input end of the summing unit is coupled to the output end of the two or more multiplication-accumulation units, and the summing unit is configured to receive the output of the two or more multiplication-accumulation units and sum them.

[0026] In some embodiments, the summation unit includes an s-level compression tree and an adder, the output end of each of the two or more multiplication and accumulation units is coupled to the corresponding input end of the 1st-level compression tree in the s-level compression tree, the output end of the i-th-level compression tree in the s-level compression tree is coupled to the corresponding input end of the (i+1)-th-level compression tree in the s-level compression tree, and the output end of the s-th-level compression tree in the s-level compression tree is coupled to the corresponding input end of the adder, wherein s is a non-negative integer, i=1, 2,…, s-1.

[0027] In some embodiments, the summing unit further includes an additional register group, an input of the additional register group is coupled to the output of the adder, and an output of the additional register group is coupled to a corresponding input of the first-level compression tree in the s-level compression tree.

[0028] In some embodiments, the multiplication-accumulation circuit further includes a control element arranged between the output end of each multiplication-accumulation unit in the two or more multiplication-accumulation units and the corresponding input end of the summing unit, and the control element is configured to receive a control signal and the output of the corresponding multiplication-accumulation unit and control whether the output of the corresponding multiplication-accumulation unit is provided to the summing unit at the output end of the control element according to the control signal.

[0029] In some embodiments, the input end of the multiplication subcircuit is also coupled to the output end of the input processing circuit, and the input processing circuit is configured to receive the first number and the second number and: when the first number is a signed number, output the first number as the first multiplier for feeding into the multiplier by inverting the sign bit of the first number, and output the second number as the second multiplier for feeding into the multiplier; when the first number is an unsigned number, output the first number as the first multiplier for feeding into the multiplier, and output the second number as the second multiplier for feeding into the multiplier.

[0030] In some embodiments, the input processing circuit includes: an XOR gate configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is an unsigned number or a signed number and perform an XOR operation thereon, wherein the XOR operation result of the XOR gate is provided as the most significant bit of the first number output by the input processing circuit. In some embodiments, the input processing circuit includes: a multiplexer configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive the sign flag indicating whether the first number is an unsigned number or a signed number as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

[0031] In some embodiments, the input of the multiplication subcircuit is further coupled to the output of an input processing circuit, the input processing circuit being configured to receive the first number and the second number. The input processing circuit is further configured to split the first number according to the bit width of the multiplier, and the multiply-accumulate circuit further includes a shifter coupled to the output of the multiplication subcircuit, the shifter being configured to perform a shift operation corresponding to the split. In some embodiments, the input processing circuit is further configured to split the second number according to the bit width of the multiplier. In some embodiments, the input processing circuit is configured to receive the second number pre-split according to the bit width of the multiplier.

[0032] In some embodiments, the output of the accumulation subcircuit is coupled to the input of an output processing circuit, and the output processing circuit is configured to perform at least one of the following: subtracting the output of the accumulation subcircuit from a first constant, where the first constant is the sum of all second numbers in the plurality of pairs of first and second numbers that are paired with the first number as a signed number and shifted left by (z-1), where z is the bit width of the first number; or adding the output of the accumulation subcircuit to a second constant, where the second constant is (1-2 w )·2 w-1 y, where w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all the second numbers in the plurality of pairs of first and second numbers.

[0033] According to a third aspect of the present disclosure, an arithmetic circuit is provided, comprising: the multiplication-accumulation circuit according to any embodiment of the second aspect of the present disclosure; and an input processing circuit, wherein the output of the input processing circuit is coupled to the input of the multiplication-accumulation circuit. The input processing circuit is configured to receive a first number and a second number and: if the first number is a signed number, output the first number as a first multiplier for feeding into the multiplier by inverting the sign bit of the first number, and output the second number as a second multiplier for feeding into the multiplier; if the first number is an unsigned number, output the first number as the first multiplier for feeding into the multiplier, and output the second number as the second multiplier for feeding into the multiplier.

[0034] In some embodiments, the input processing circuit includes: an XOR gate configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is an unsigned number or a signed number and perform an XOR operation thereon, wherein the XOR operation result of the XOR gate is provided as the most significant bit of the first number output by the input processing circuit. In some embodiments, the input processing circuit includes: a multiplexer configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive the sign flag indicating whether the first number is an unsigned number or a signed number as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

[0035] In some embodiments, the input processing circuit is further configured to split the first number according to the bit width of the multiplier, and the multiply-accumulate circuit further includes a shifter coupled to the output of the multiplication subcircuit, the shifter configured to perform a shift operation corresponding to the split. In some embodiments, the input processing circuit is further configured to split the second number according to the bit width of the multiplier. In some embodiments, the input processing circuit is configured to receive the second number pre-split according to the bit width of the multiplier.

[0036] In some embodiments, the arithmetic circuit further includes an output processing circuit, and the output terminal of the multiplication and accumulation circuit is coupled to the input terminal of the output processing circuit. The output processing circuit is configured to perform at least one of the following: subtracting the output of the multiplication and accumulation circuit from a first constant, the first constant being the sum of all the second numbers in the plurality of pairs of first numbers and second numbers that are paired with the first number as a signed number after being left shifted by (z-1), where z is the bit width of the first number; or adding the output of the multiplication and accumulation circuit to a second constant, the second constant being (1-2w )·2 w-1 y, where w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all the second numbers in the plurality of pairs of first and second numbers.

[0037] According to a fourth aspect of the present disclosure, there is provided an arithmetic circuit, comprising: the multiplier according to any embodiment of the first aspect of the present disclosure; and an additional adding circuit, wherein an output terminal of the multiplier is coupled to an input terminal of the additional adding circuit, and the additional adding circuit is configured to add an output of the partial product summation circuit to a constant when the second multiplier is a signed number, the constant being (1-2 w )·2 w-1 , where w is the bit width of the second multiplier.

[0038] According to a fifth aspect of the present disclosure, a processor is provided, comprising the multiplier according to any embodiment of the first aspect of the present disclosure, the multiplication and accumulation circuit according to any embodiment of the second aspect of the present disclosure, or the operation circuit according to any embodiment of the third and fourth aspects of the present disclosure.

[0039] According to a sixth aspect of the present disclosure, a computing device is provided, comprising the processor according to the fifth aspect of the present disclosure.

[0040] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0042] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0043] 1 to 3 respectively show circuit diagrams of multiplication-accumulation circuits according to some comparative examples of the present disclosure;

[0044] 4 and 5 respectively show schematic block diagrams of operation circuits according to some embodiments of the present disclosure;

[0045] 6 to 9 respectively illustrate example circuit diagrams of input processing circuits for implementing the operation circuits of FIG. 4 and FIG. 5 according to some embodiments of the present disclosure;

[0046] 10 to 17 respectively illustrate example circuit diagrams of multiplication-accumulation circuits for implementing the arithmetic circuits of FIG. 4 and FIG. 5 according to some embodiments of the present disclosure;

[0047] FIG18 shows a schematic block diagram of a multiplication-accumulation circuit for implementing the operation circuits of FIG4 and FIG5 according to some embodiments of the present disclosure;

[0048] 19 to 22 respectively illustrate example circuit diagrams for implementing the multiplication-accumulation circuit of FIG. 18 according to some embodiments of the present disclosure;

[0049] FIG23 shows a schematic block diagram of a multiplier according to some embodiments of the present disclosure;

[0050] 24 to 27 respectively illustrate example circuit diagrams for implementing the multiplier of FIG. 23 according to some embodiments of the present disclosure;

[0051] 28 to 30 respectively illustrate example circuit diagrams for implementing a first partial product generating unit of the multiplier of FIG. 23 according to some embodiments of the present disclosure;

[0052] FIG31 shows a schematic block diagram of an arithmetic circuit including the multiplier of FIG23 and an additional adding circuit according to some embodiments of the present disclosure.

[0053] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0054] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0055] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0056] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure, its application, or use. In other words, the structures and methods herein are presented in an exemplary manner to illustrate various embodiments of the structures and methods of the present disclosure. However, those skilled in the art will appreciate that these are merely exemplary of the disclosure that may be implemented, and are not exhaustive. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components.

[0057] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0058] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0059] FIG1 shows a multiplication-accumulation circuit 10, which includes a multiplier 11, an adder 12, and a register 13. Assume that the multiplication-accumulation circuit 10 is to calculate the multiplication-accumulation of the logarithm of x (a1·b1+a2·b2+…a x b x , x is a positive integer), then in each cycle of x periods, the corresponding pair of numbers a in the x logarithms is k 、b k (k=1, 2, ..., x) is fed into the multiplier 11 as a multiplier to calculate the product a of the pair k b k , then a k b k It is accumulated through adder 12 and register 13. For example, if the x logarithms are fed sequentially from 1 to x, then at the end of the first cycle the result stored in register 13 is a1·b1, at the end of the second cycle the result stored in register 13 is a1·b1+a2·b2, and so on until the end of the xth cycle the result stored in register 13 is a1·b1+a2·b2+…a x b x .

[0060] However, the multiplication-accumulation circuit 10 is not compatible with multiplication-accumulation operations of different data types, including signed and unsigned numbers. For signed numbers, the highest bit is used to represent the sign and can be called the sign bit. A sign bit of 0 represents a positive number, and a sign bit of 1 represents a negative number. For unsigned numbers, the highest bit is only used to represent the value. For example, suppose a k =0b10101010, b k =0b01010101: If a k 、b k are all signed numbers, then a k b k The decimal representation is (-86×85)=-7310; if a k 、b k are all unsigned numbers, then a k b kThe decimal representation of is (170×85)=14450. It can be seen that if the multiplication-accumulation circuit 10 is designed to perform multiplication-accumulation operations on signed numbers, an erroneous operation result will be obtained once an unsigned number is input into the multiplication-accumulation circuit 10. Similarly, if the multiplication-accumulation circuit 10 is designed to perform multiplication-accumulation operations on unsigned numbers, an erroneous operation result will be obtained once a signed number is input into the multiplication-accumulation circuit 10.

[0061] In order to make the same multiplication-accumulation circuit compatible with multiplication-accumulation operations of different data types, it is possible to k 、b k Before feeding into the multiply-accumulate circuit, k 、b k Perform sign bit extension. Specifically, the sign bit of the signed number is extended (i.e., the sign bit is added to the high bit), and the unsigned number is extended by 0 (i.e., the 0 is added to the high bit). For example, for the signed number 0101, one bit is extended to 00101, and four bits are extended to 00000101; for the signed number 1010, one bit is extended to 11010, and four bits are extended to 11111010; for the unsigned number 0101, one bit is extended to 00101, and four bits are extended to 00000101; for the unsigned number 1010, one bit is extended to 01010, and four bits are extended to 0000101. The specific number of bits extended can be determined according to the design bit width of the multiplier, or conversely, the multiplier can be designed according to the specific number of bits extended. The core of sign bit extension is to only expand the data bit width without changing the data size. Before the sign bit is extended, a k 、b k Both may be signed or unsigned, but after sign extension, a k 、b k Figure 2 shows a multiplication and accumulation circuit 20, which includes a multiplier 21 that supports multiplication of signed numbers by signed numbers and provides signed output, an adder 22, and a register 23 for multiplying the signed number by the sign bit. k 、b k Perform multiplication and accumulation operations. The multiplication and accumulation circuit 20 is compatible with multiplication and accumulation operations of different data types. However, on the one hand, the sign bit extension increases the data bit width, causing the correspondingly designed multiplier 21 to consume more resources. On the other hand, the multiplier 21 performs signed-by-signed multiplication and provides a signed output, which complicates the subsequent data path (not only the adder 22 and register 23 in the multiplication and accumulation circuit 20, but also other circuits coupled to the output of the multiplication and accumulation circuit 20), increasing the design difficulty, circuit area, and power consumption.

[0062] Alternatively, the signed number a can be deduced by the following mathematical derivation k (assuming the bit width is z) and the signed number bk The sum operation (assuming the bit width is w) is unified into an unsigned number operation.

[0063] Let A k =a k +2 z-1 (equivalent to a k The sign bit of

[0064] Let B k =b k +2 w-1 (equivalent to b k The sign bit of

[0065] x·2 z+w-2 can be extracted as a constant term. The multiplication and accumulation circuit 30 shown in FIG3 can be used for processing. As shown in FIG3, the multiplication and accumulation circuit 30 includes a multiplier 31 that supports multiplication of unsigned numbers by unsigned numbers and provides unsigned output, an adder 32, and a register 33, as well as an adder 34 and a subtractor 35. The multiplier 31 is used to calculate A k ·B k , adder 34 is used to calculate (2 w-1 A k +2 z-1 B k ), the subtractor 35 is used to calculate [A k ·B k -(2 w-1 A k +2 z-1 B k )], the adder 32 and the register 33 are used for accumulation.

[0066] Similarly, the signed number a can be deduced by the following mathematical derivation k (assuming the bit width is z) and the unsigned number b k The sum operation (assuming the bit width is w) is unified into an unsigned number operation.

[0067] Let A k =a k +2 z-1 (equivalent to a k The sign bit of

[0068] The same can be done with the multiplication and accumulation circuit 30, but a first control element 361 is required to set the input at the first input terminal of the adder 34 to 0, and the second input terminal of the adder 34 can receive 2 z-1 b k Such a first control element 361 can be realized, for example, by an AND gate, the first input of which can receive an input (2 w-1 A k or 2 which will be described later w-1 a k ,) and the second input terminal can receive the control signal Sc1, and the output terminal can be coupled to the first input terminal of the adder 34. For the AND gate, the first input terminal of the adder 34 is prohibited from receiving the input at the first input terminal of the AND gate by setting Sc1=0, and the first input terminal of the adder 34 is allowed to receive the input at the first input terminal of the AND gate by setting Sc1=1.

[0069] Similarly, the unsigned number a can be deduced by the following mathematical derivation k (assuming the bit width is z) and the signed number b k The sum operation (assuming the bit width is w) is unified into an unsigned number operation.

[0070] Let B k =b k +2 w-1 (equivalent to b k The sign bit of

[0071] The same can be done with the multiplication and accumulation circuit 30, but a second control element 362 is required to set the input at the second input terminal of the adder 34 to 0, and the first input terminal of the adder 34 can receive 2 w-1 a k Such a second control element 362 can also be realized by, for example, an AND gate, the first input of which can receive an input (2 z-1 B k or 2 z-1 b k ,) and the second input terminal can receive the control signal Sc2, and the output terminal can be coupled to the second input terminal of the adder 34. For the AND gate, by setting Sc2=0, the second input terminal of the adder 34 is prohibited from receiving the input at the first input terminal of the AND gate, and by setting Sc2=1, the second input terminal of the adder 34 is allowed to receive the input at the first input terminal of the AND gate.

[0072] For an unsigned number ak (assuming the bit width is z) and the unsigned number b k (assuming the bit width is w) multiplication and accumulation operation The same process can be performed using the multiplication-accumulation circuit 30 , where the first control element 361 and the second control element 362 are configured to prohibit the first input terminal and the second input terminal of the adder 34 from receiving the input at the first input terminal of the AND gate.

[0073] Thus, the multiplication-accumulation circuit 30 is compatible with multiplication-accumulation operations of different data types. Since no sign bit extension is required, the multiplier 31 of the multiplication-accumulation circuit 30 consumes fewer resources than the multiplier 21 of the multiplication-accumulation circuit 20. However, the multiplication-accumulation circuit 30 has significantly more circuit elements than the multiplication-accumulation circuit 20. On the one hand, the multiplication-accumulation circuit 30 includes an additional adder 34 and control elements 361 and 362 to handle the additional accumulated terms. This consumes a lot of adder resources, and the introduction of control elements 361 and 362 also complicates the control logic. On the other hand, although the multiplier 31 supports unsigned multiplication by unsigned numbers and provides an unsigned output, the multiplication-accumulation circuit 30 also includes a subtractor 35, which still provides a signed output. This complicates the data path after the subtractor 35 (not only the adder 32 and register 33 in the multiplication-accumulation circuit 30, but also other circuits coupled to the output of the multiplication-accumulation circuit 30), increasing design difficulty, circuit area, and power consumption.

[0074] The inventors of the present disclosure have noticed that in some application scenarios involving multiplication and accumulation operations on two sets of data, one set of data may be known in advance. For example, in the convolution calculation unit of a neural network processor, a multiplication and accumulation circuit is required to perform multiplication and accumulation operations on activation data and weight data. For non-restrictive illustrative purposes, the activation data may be image data, which may be derived from, for example, an image captured in real time by a camera to be used for target detection by a neural network model carried by a neural network processor, and the weight data may be derived from the weight parameters of the neural network model. Since the weight parameters of the trained neural network model are fixed, the weight data is known in advance. In contrast, the activation data is unknown in advance and can only be determined when it is to be processed. This feature can be used to optimize the operation circuit.

[0075] Specifically, the unknown a can be deduced by the following mathematical derivation k (assuming the bit width is z) and the previously known b k The sum operation (assuming the bit width is w) is unified into the following operation.

[0076] when a k is an unsigned number and b k Is a signed or unsigned number,

[0077] Therefore, the multiply-accumulate circuit is used to calculate That's it.

[0078] when a k is a signed number and b k Is a signed or unsigned number,

[0079] Let A k =a k +2 z-1 (equivalent to a k The sign bit of

[0080] Because b k is known in advance, so (-2 z-1 b k ) can be extracted as a constant term. Therefore, we only need to use the multiplication and accumulation circuit to calculate That's it.

[0081] To this end, the present disclosure provides an arithmetic circuit capable of performing multiple multiplication-accumulation operations on a first number and a pre-known second number using the aforementioned arithmetic principle. The arithmetic circuit according to various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that actual arithmetic circuits may include additional components, and to avoid obscuring the key points of the present disclosure, these additional components are not shown in the drawings and are not discussed in this disclosure.

[0082] FIG4 shows an operation circuit 1000 according to some embodiments of the present disclosure, which is used to perform a plurality of first numbers a k and the second number b k The multiplication and accumulation operation, where the second number b k is known in advance. Assume that the first number a k The bit width is z, the second number b k The bit width of a is w, which is for illustration purposes only and is not intended to limit the first number a k and the second number b k The bit widths of a and b are the same or different. In fact, the present disclosure can be applied to the first number a k and the second number b k The bit widths of the two cases are the same or different. In many practical cases, the first number a k and the second number b k The bit width is the same.

[0083] As shown in FIG4 , the arithmetic circuit 1000 includes a multiplication-accumulation circuit 100 and an input processing circuit 200. The input terminal of the input processing circuit 200 can provide an input terminal IN of the arithmetic circuit 1000. The output terminal of the input processing circuit 200 is coupled to the input terminal of the multiplication-accumulation circuit 100. The output terminal of the multiplication-accumulation circuit 100 can provide an output terminal OUT of the arithmetic circuit 1000.

[0084] FIG5 shows another example 1000′ of the operation circuit 1000, which further includes an output processing circuit 300 compared to the operation circuit 1000. The output terminal of the multiplication and accumulation circuit 100 is coupled to the input terminal of the output processing circuit 300. The output terminal of the output processing circuit 300 can provide the output terminal OUT of the operation circuit 1000′. The output processing circuit 300 is used to process the constant term extracted in the above mathematical derivation. Specifically, the output processing circuit 300 can be configured to subtract the output of the multiplication and accumulation circuit 100 from a first constant, where the first constant is the sum of the multiple pairs of first numbers a. k and the second number b k All the first number a in the k The second number of the pair b k After left shifting by (z-1) bits (2 z-1 b k ). In some cases, the operation circuit 1000 of Figure 4 is sufficient, and there is no need to set up a dedicated output processing circuit 300 to process these constant terms. For example, in the convolution calculation unit of the neural network processor, in addition to performing multiplication and accumulation operations on the activation data and weight data, it is also necessary to add the result of the multiplication and accumulation operation to the bias term (Bias). In the convolution calculation unit, the addition of the bias term itself is already handled by dedicated hardware, so the above-mentioned constant term can be integrated with the bias term in advance without paying additional hardware costs for processing.

[0085] The input processing circuit 200 may be configured to receive a first number a k and the second number b k The input processing circuit 200 may also be configured to k In the case of a signed number, the first number a k The sign bit of is inverted to output the first number A k As a first multiplier for feeding into the multiplier of the multiply-accumulate circuit 100, and outputting a second number b k As a second multiplier for feeding into the multiplier of the multiply-accumulate circuit 100. The input processing circuit 200 may also be configured to k If it is an unsigned number, output the first number a k As a first multiplier for feeding into the multiplier of the multiply-accumulate circuit 100, and outputting a second number b kAs the second multiplier for feeding into the multiplier of the multiplication-accumulation circuit 100. That is, the input processing circuit 200 does not process the second number b k Do any transformation, regardless of the second number b k Is it a signed number or an unsigned number. As for the first unknown number a k The input processing circuit 200 will only process the first number a as a signed number. k Do the transformation of the inverted sign bit without changing the first number a as an unsigned number k Do any transformations.

[0086] Any suitable circuit can be designed to implement the first number a k The data type of the first number a is selected k Perform the transformation to invert the sign bit.

[0087] In some embodiments, the input processing circuit 200 may include a circuit configured to receive the first number a k The highest digit and indicates the first number a k The XOR gate is used to determine whether the number is an unsigned number or a signed number and to perform an XOR operation on the sign flag bit of the unsigned number or the signed number. The XOR operation result of the XOR gate is provided as the first number A output by the input processing circuit 200. k FIG6 shows an example 200A of the input processing circuit 200, which includes an XOR gate XOR. The XOR gate XOR receives the first number a k The highest digit a k(z-1) and indicates the first number a k Flag1 is an unsigned or signed number and performs an XOR operation on it. Flag1 = 0 indicates that the first number a k Is an unsigned number, then the output of the XOR gate is a k(z-1) Flag1=1 indicates the first number a k Is a signed number, then the output of the XOR gate is a k(z-1) The inverted result of the XOR gate is added to the first number a. k The highest digit a k(z-1) Other bits except a k(z-2):0 Splice into A k In addition, the input processing circuit 200 does not process the second number b k Do any transformation, so you can directly output b k .

[0088] Alternatively, in some other embodiments, the input processing circuit 200 may also include a multiplexer, which may be configured to receive the first number a k The highest bit is taken as the first input, receiving the first number a kThe inverted result of the highest bit of is taken as the second input, and the first number a is received. k The sign flag bit indicating whether it is an unsigned number or a signed number is used as a selection signal, and the first input or the second input is output according to the selection signal. The output of the multiplexer can be provided as the first number A output by the input processing circuit 200. k The highest bit of the first number a can be received by using a NOT gate k The highest bit of the first number a is obtained by performing a NOT operation on it. k FIG7 shows an example 200B of the input processing circuit 200, which includes a multiplexer MUX and a NOT gate NOT. The NOT gate NOT is used to obtain the first number a. k The highest digit a k(z-1) The multiplexer MUX receives the first number a k The highest digit a k(z-1) As a first input, a first number a is received k The highest digit a k(z-1) The inverted result of is taken as the second input, receiving the first number a k The sign flag Flag1 is used as a selection signal to indicate whether the first number is an unsigned number or a signed number, and the first input or the second input is output according to the selection signal. k It is an unsigned number. At this time, the output of the multiplexer MUX is the first input, i.e. a k(z-1) The selection signal Flag1=1 indicates the first number a k Is a signed number, at this time the output of the multiplexer MUX is the second input, i.e. a k(z-1) The output of the multiplexer MUX is inverted with the first number a k The highest digit a k(z-1) Other bits except a k(z-2):0 Splice into A k In addition, the input processing circuit 200 does not process the second number b k Do any transformation, so you can directly output b k .

[0089] The multiplication and accumulation circuit 100 can be designed to adapt to the first number a k and the second number b k Conversely, the first number a can also be split according to the design bit width of the multiplication and accumulation circuit 100, especially the multiplier thereof. k and the second number b k . Take the first number a k and the second number b k Taking the bit width of 2r and the design bit width of the multiplier as an example, the operation principle of the splitting is explained as follows.

[0090] a kh is the first number a k The highest r bits, a kl is the first number a k The lowest r bits, b kh is the second number b k The highest r bits, b kl is the second number b k Thus, a large bit width 2r multiplication operation can be equivalent to 4 small bit width r multiplication operations. 2r ”, “·2 r " is a shift operation, representing left shift of 2r bits and left shift of r bits, which can be performed by a shifter.

[0091] Therefore, in some embodiments, the input processing circuit 200 may be further configured to split the first number a according to the bit width of the multiplier of the multiplication-accumulation circuit 100. k , and the multiplication-accumulation circuit 100 further includes a shifter coupled to the output terminal of the multiplication subcircuit 111, wherein the shifter is configured to perform a shift operation corresponding to the splitting. In addition, for a pre-known second number b k , which can also be split by the input processing circuit 200, that is, the input processing circuit 200 can also be configured to split the second number b according to the bit width of the multiplier of the multiplication and accumulation circuit 100 k FIG8 shows an example 200C of the input processing circuit 200, which further includes A in comparison with the example 200A. k Split into A kh (A k The high part of A kl (A k The lower part of b k Split into b kh (b k The high part of b kl (b k Note that the split shown here is for illustration purposes only and is not limiting. For example, A k and b k Each of the two numbers b is split into more parts, and the bit width of each part can be the same or different. k is known in advance, so its split can be pre-processed (for example, by software such as a compiler), so the input processing circuit 200 can alternatively be configured to receive the second number b that is pre-split according to the bit width of the multiplier. k FIG9 shows an example 200D of the input processing circuit 200, which, compared to the example 200C, does not perform b kInstead of splitting, it directly receives the pre-split b kh and b kl Therefore, compared with example 200C, example 200D has a lower hardware cost because the hardware cost for splitting b is eliminated. k It is understandable that, although FIG8 and FIG9 show that the transformation is first performed and then the splitting is performed, the splitting is first performed and then the transformation is also feasible.

[0092] After the input processing circuit 200 processes the first number and the second number, the multiplication-accumulation circuit 100 performs a multiplication-accumulation operation on the first number, which is an unsigned number, and the pre-known second number. Referring back to Figures 4 and 5, the multiplication-accumulation circuit 100 may include at least one multiplication-accumulation unit 110. The multiplication-accumulation unit 110 includes a multiplication sub-circuit 111 and an accumulation sub-circuit 112. The multiplication sub-circuit 111 may include a multiplier for performing a multiplication operation on the first multiplier and the second multiplier. The first multiplier is obtained from the first number (e.g., processed by the input processing circuit 200) and is an unsigned number. The second multiplier is obtained from the second number (e.g., processed by the input processing circuit 200) and is a pre-known unsigned number or a signed number. The multiplier of the multiplication sub-circuit 111 supports both unsigned number multiplication by unsigned number multiplication and unsigned number multiplication by signed number multiplication, and is configured to provide an output that is an unsigned number. The input terminal of the accumulation sub-circuit 112 is coupled to the output terminal of the multiplication sub-circuit 111. The accumulation sub-circuit 112 is configured to receive and accumulate the output of the multiplication sub-circuit 112 .

[0093] In some embodiments, the multiplication subcircuit 111 may include one or more multipliers, each of which is configured to receive a corresponding pair of first and second multipliers and calculate the product of the corresponding pair of first and second multipliers. The multipliers in the multiplication subcircuit 111 may have a single output terminal or a dual output terminal, depending on specific needs. When the multiplication subcircuit 111 includes multiple multipliers, parallel computing can be implemented.

[0094] In some embodiments, the accumulation subcircuit 112 may include an n-level compression tree, a first adder, a second adder and a register group, the output end of the multiplication subcircuit 111 is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the first adder, the output end of the first adder is coupled to the corresponding input end of the second adder, the output end of the second adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the second adder, wherein n is a positive integer, i=1, 2,…, n-1.

[0095] In some embodiments, the accumulation subcircuit 112 may include an n-level compression tree, a full adder, an adder and a register group. The output end of the multiplication subcircuit 111 is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the full adder, the output end of the full adder is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the full adder, wherein n is a positive integer, i=1, 2,…, n-1.

[0096] In some embodiments, the accumulation subcircuit 112 may include an n-level compression tree, an adder and a register group. The output end of the multiplication subcircuit 111 is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, wherein n is a positive integer, i=1, 2,…, n-1.

[0097] Each level of the n-level compression tree can include a single compression tree or multiple compressed trees in parallel. Common compression trees include 4:2 compression trees, 3:2 compression trees, and other compression trees with two outputs, as well as 5:3 compression trees, 6:3 compression trees, and 7:3 compression trees with three outputs. The compression tree used in accumulation subcircuit 112 can be an existing or later-developed compression tree with any number of inputs and outputs, or a compression tree module with any number of inputs and outputs implemented by combining multiple existing compression trees, as long as it can compress the output result of multiplication subcircuit 111.

[0098] In other embodiments, the compression tree may alternatively be implemented as a full adder or a combination of a full adder and a half adder. For example, in some embodiments, the accumulation subcircuit 112 may include a full adder module having one or more stages of full adders, an adder, and a register bank. The output of the multiplication subcircuit 111 is coupled to the corresponding input of the full adder module, the output of the full adder module is coupled to the corresponding input of the adder, the output of the adder is coupled to the input of the register bank, and the output of the register bank is coupled to the corresponding input of the full adder module.

[0099] The number of registers included in a register group may depend on the bit width of the registers and the bit width of the input data. Furthermore, similar to the register group, the number of circuit elements in the various circuit element groups mentioned elsewhere herein (including AND gate groups, NOT gate groups, NAND gate groups, XOR gate groups, multiplexer groups, inverting multiplexer groups, etc.) may depend on the circuit design bit width.

[0100] For non-limiting illustrative purposes, FIG. 10 to FIG. 17 respectively illustrate exemplary circuit diagrams of a multiplication-accumulation circuit 100 for implementing the operation circuits 1000 and 1000 ′ of FIG. 4 and FIG. 5 according to some embodiments of the present disclosure.

[0101] As shown in FIG10 , the multiplication and accumulation circuit 100A includes a multiplication and accumulation unit 110, which includes a multiplication subcircuit 111 and an accumulation subcircuit 112. In the example of FIG10 , the multiplication subcircuit 111 includes a multiplier 1110 with a single output terminal. Assume that the multiplication and accumulation circuit 100 is used for the multiplication and accumulation of the logarithm of x (a1·b1+a2·b2+…a x b x , x is a positive integer), where a k (k=1, 2, . . . , x) has been processed into A by the input processing circuit 200A of FIG. 6, for example. k , then in each cycle of x periods, the corresponding pair of x logarithms A can be k 、b k The first and second multipliers are fed into the multiplier 1110 respectively, and the multiplier 1110 calculates the product A of the pair k b k and provide unsigned output, then A k b k is accumulated via the accumulation sub-circuit 112. The accumulation sub-circuit 112 includes an adder ADD and a register bank 1121. A first input terminal of the adder ADD is coupled to the output terminal of the multiplier 1110, a second input terminal is coupled to the output terminal of the register bank 1121, and an output terminal is coupled to the input terminal of the register bank 1121. Assuming that the logarithms of x to be calculated by the multiplication and accumulation circuit 100A are fed to the multiplier 1110 in sequence from 1 to x, then at the end of the first cycle, the result stored in the register bank 1121 is A1·b1, and at the end of the second cycle, the result stored in the register bank 1121 is (A1·b1+A2·b2), and so on until the end of the xth cycle, the result stored in the register bank 1121 is (A1·b1+A2·b2+… ... x b x ).

[0102] Compared to the multiplication-accumulation circuit 20 of FIG. 2 , the multiplier 1110 of the multiplication-accumulation circuit 100A of FIG. 10 provides an unsigned output, simplifying the subsequent data path and reducing design difficulty, circuit area, and power consumption. Compared to the multiplication-accumulation circuit 30 of FIG. 3 , the multiplication-accumulation circuit 100A of FIG. 10 has a reduced number of components (one adder, one subtractor, and two control elements are eliminated), eliminating the need for complex control logic. Furthermore, the subsequent data paths of the multiplier 1110 are all unsigned, reducing design difficulty, circuit area, and power consumption.

[0103] FIG11 shows a multiplication-accumulation circuit 100B. Compared to the multiplication-accumulation circuit 100A of FIG10 , the difference lies in that the multiplier 1110 has a dual output terminal instead of a single output terminal, and accordingly, the adder ADD is changed to a full adder (FA). A multiplier typically includes three parts: a partial product generating part, a partial product accumulation adding part, and a final addition part. Compared to a multiplier with a single output terminal, a multiplier with a dual output terminal can reduce the final addition part, that is, one adder can be reduced. Therefore, using a multiplier with a dual output terminal can achieve lower power consumption compared to using a multiplier with a single output terminal. In addition, replacing the adder ADD with a full adder FA also reduces power consumption.

[0104] FIG12 shows a multiplication-accumulation circuit 100C, which differs from the multiplication-accumulation circuit 100A of FIG10 in that the multiplication subcircuit 111 includes m parallel multipliers 11101, 11102, ..., 1110. m (m is a positive integer greater than 1), and accordingly the accumulation subcircuit 112 further includes a 2m:2 compression tree 1120 and an adder ADD0, wherein the multipliers 11101, 11102, ..., 1110 m The output end of is coupled to the corresponding input end of the compression tree 1120, the output end of the compression tree 1120 is coupled to the corresponding input end of the adder ADD0, and the output end of the adder ADD0 is coupled to the input end of the adder ADD. When the 2m:2 compression tree is inconvenient to design, a combination of existing compression trees can also be used to achieve compression from m inputs to 2 outputs. Through the parallel design of the multipliers, the multiplication and accumulation circuit 100C can achieve m logarithmic multiplication and accumulation in each cycle. Compared with the x cycles required by the multiplication and accumulation circuit 100A of Figure 10, the multiplication and accumulation circuit 100C only needs (x / m) cycles, thereby having improved computational efficiency. The number m of parallel multipliers can be flexibly configured according to actual needs.

[0105] In contrast, the multiplication-accumulation circuit 20 of FIG2 is difficult to implement parallel computation of the multiplier 21 because the multiplier 21 provides a signed output, which makes the design of the compression tree extremely complex. Consequently, the computational efficiency of the multiplication-accumulation circuit 20 is low. While the multiplication-accumulation circuit 30 of FIG3 provides an unsigned output, making it relatively easy to design a compression tree to facilitate parallel computation, it also requires the addition of multiple adders 34 and related control elements 361 and 362 to accommodate the multiple multipliers 31. This significantly increases the number of circuit elements, resulting in increased circuit area and power consumption.

[0106] FIG13 shows a multiply-accumulate circuit 100D. Compared to the multiply-accumulate circuit 100C of FIG12 , the multiply-accumulate circuit 100D differs in that the adder ADD0 is replaced by a full adder FA. The outputs of the compression tree 1120 are coupled to corresponding inputs of the full adder FA, which in turn is coupled to corresponding inputs of the adder ADD. The outputs of the register bank 1121 are instead coupled to corresponding inputs of the full adder FA. By replacing the adder ADD0 with the full adder FA, the multiply-accumulate circuit 100D saves resources and reduces power consumption.

[0107] Figure 14 shows a multiplication-accumulation circuit 100E, which differs from the multiplication-accumulation circuit 100D in Figure 13 in that the full adder FA is omitted, wherein the output end of the compression tree 1120 is coupled to the corresponding input end of the adder ADD, and the output end of the register group 1121 is coupled to the corresponding input end of the compression tree 1120 instead.

[0108] FIG15 illustrates an example arrangement of a compression tree 1120 that can be used in each of FIG12 through FIG14 . As shown in FIG15 , compression tree 1120 includes two levels of compression trees, where the first level of the compression tree includes two parallel compression trees 11201, and the second level of the compression tree includes a single compression tree 11202. FIG15 is equivalent to implementing an 8:2 compression tree using a combination of three 4:2 compression trees. The compression tree in FIG15 can have a simpler design than the compression tree in each of FIG12 through FIG14 . From another perspective, while FIG15 and FIG12 through FIG14 employ the same compression tree, the former can accommodate a larger multiplier size, further improving circuit processing performance.

[0109] FIG16 shows a multiply-accumulate circuit 100F, which differs from the multiply-accumulate circuit 100E of FIG14 in that the compression tree 1120 is replaced by a full adder module 1120 ′ having multiple stages of full adders FA.

[0110] FIG17 shows a multiplication-accumulation circuit 100G, which differs from the multiplication-accumulation circuit 100E of FIG14 in that shifters 11231 and 11232 are further provided between the output of the compression tree 1120 and the corresponding input of the full adder FA. k 、b k If the bits are processed by the input processing circuit 200 of Figures 8 and 9, the shift operation corresponding to the splitting performed by the input processing circuit 200 can be implemented through the shift configuration of the shifters 11231 and 11232. Therefore, the multiplication and accumulation circuit 100G has the ability to support mixed-bit multiplication and accumulation operations. As an alternative, a corresponding shifter can be provided between each output terminal of each multiplier 1110 and the corresponding input terminal of the compression tree 1120, but this obviously requires a much larger number of shifters, resulting in an unnecessary increase in circuit area and power consumption.

[0111] It can be understood that the aforementioned multiplication-accumulation circuits can be increased in their ability to support mixed-bit multiplication-accumulation operations by adding shifters. For example, in FIG10 , a shifter can be added between the output of the multiplier 1110 and the input of the adder ADD; in FIG11 , a shifter can be added between each output of the multiplier 1110 and the corresponding input of the full adder FA; in FIG12 , a shifter can be added between each output of each multiplier 1110 and the corresponding input of the compression tree 1120, or between each output of the compression tree 1120 and the corresponding input of the adder ADD0, or between the output of the adder ADD0 and the adder ADD1. 13 , a shifter may be added between each output end of each multiplier 1110 and the corresponding input end of the compression tree 1120, or a shifter may be added between each output end of the compression tree 1120 and the corresponding input end of the full adder FA; in FIG14 , a shifter may be added between each output end of each multiplier 1110 and the corresponding input end of the compression tree 1120; in FIG16 , a shifter may be added between each output end of each multiplier 1110 and the corresponding input end of the full adder module 1120′.

[0112] FIG18 shows a multiplication-accumulation circuit 100′ that can be used to implement the multiplication-accumulation circuit 100 of the operation circuit 1000 of FIG4 and FIG5 according to some embodiments of the present disclosure. The multiplication-accumulation circuit 100′ includes two or more multiplication-accumulation units 1101, 1102, ... 110 j (j is a positive integer greater than 1) and summing unit 120. Multiplication and accumulation units 1101, 1102, ... 110 j The output terminal of each multiplication and accumulation unit in is coupled to the corresponding input terminal of the summing unit 120. jAn input terminal of each multiplication-accumulation unit in the multiplication-accumulation circuit 100 ′ may provide an input terminal IN of the multiplication-accumulation circuit 100 ′, and an output terminal of the summing unit 120 may provide an output terminal OUT of the multiplication-accumulation circuit 100 ′.

[0113] Multiplication and accumulation units 1101, 1102, ... 110 j Each includes a multiplication subcircuit 1111, 1112, ... 111 j and accumulation subcircuits 1121, 1122, ... 112 j The summing unit 120 is configured to receive the multiplication and accumulation units 1101, 1102, ... 110 j The output of and sum them.

[0114] Multiplication and accumulation units 1101, 1102, ... 110 j Each of the multiplication and accumulation units in the circuit is similar to the multiplication and accumulation unit 110 of the aforementioned multiplication and accumulation circuit 100, so the above description of the multiplication and accumulation unit 110 and its various embodiments are also applicable here, and will not be repeated here. It can be understood that the multiplication and accumulation units 1101, 1102, ... 110 j They may have the same design or different designs.

[0115] Compared to the multiplication-accumulation circuit 100 having only one multiplication-accumulation unit 110, the multiplication-accumulation circuit 100' has a plurality of parallel multiplication-accumulation units 1101, 1102, ... 110. j Each multiplication and accumulation unit takes on part of the accumulation function, so that each multiplication and accumulation unit can be kept at an appropriate scale, avoiding the difficulty of timing convergence caused by the circuit scale of a single multiplication and accumulation unit being too large, and facilitating the reduction of glitch power consumption and optimization of circuit speed.

[0116] The summation unit 120 may include an s-level compression tree and an adder, multiplication and accumulation units 1101, 1102, ... 110 j The output end of each multiplication and accumulation unit is coupled to the corresponding input end of the first-level compression tree in the s-level compression tree, the output end of the i-th level compression tree in the s-level compression tree is coupled to the corresponding input end of the (i+1)-th level compression tree in the s-level compression tree, and the output end of the s-th level compression tree in the s-level compression tree is coupled to the corresponding input end of the adder, wherein s is a non-negative integer, i=1, 2,…, s-1. It should be understood that when s=0, it means that the summation unit 120 only includes an adder but not a compression tree. For example, when j is 2, the summation unit 120 may only include an adder. Each level of compression tree may include one compression tree or multiple compression trees in parallel. Similar to the above, the compression tree here can also be alternatively implemented as a full adder or a combination of a full adder and a half adder.

[0117] In addition, in some embodiments, the summing unit 120 may further include an additional register group, the input end of the additional register group is coupled to the output end of the adder, and the output end of the additional register group is coupled to the corresponding input end of the first-level compression tree in the s-level compression tree. It should be understood that when s=0, the summing unit 120 only includes an adder. In this case, the summing unit 120 may also include a second adder and an additional register group, the input end of the additional register group is coupled to the output end of the second adder, and the output end of the additional register group and the output end of the adder are coupled to the corresponding input end of the second adder. Due to the introduction of the additional register group, the summing unit 120 also has an accumulation function, which enables the multiplication and accumulation units 1101, 1102, ... 110 j The accumulation subcircuit of each multiplication-accumulation unit does not need to fully accumulate, which reduces the bit width requirement of the register group of the accumulation subcircuit, so that the registers in the register group of the accumulation subcircuit can have a smaller number of bits and thus have lower area and power consumption.

[0118] Since the multiplication and accumulation units 1101, 1102, ... 110 j During the entire operation process, the summing unit 120 has to flip (flip means the circuit changes from 0 to 1 or from 1 to 0) to perform the summing operation, resulting in a high dynamic power consumption of the multiplication and accumulation circuit 100'. Therefore, in some embodiments, the multiplication and accumulation circuit 100' further includes multiplication and accumulation units 1101, 1102, ... 110 j A control element is provided between the output terminal of each multiplication-accumulation unit in the summing unit 120 and the corresponding input terminal of the summing unit 120. The control element may be configured to receive a control signal and the output of the corresponding multiplication-accumulation unit and control, based on the control signal, whether to provide the output of the corresponding multiplication-accumulation unit to the summing unit 120 at the output terminal of the control element. For example, the control element may include at least one of the following: an AND gate, a NAND gate, a multiplexer, and an inverting multiplexer.

[0119] The control signal may be configured to cause the control element to not provide the output of the corresponding multiplication-accumulation unit to the summing unit 120 at its output terminal before the corresponding multiplication-accumulation unit completes each round of accumulation, and to cause the control element to provide the output of the corresponding multiplication-accumulation unit to the summing unit 120 at its output terminal after the corresponding multiplication-accumulation unit completes each round of accumulation and before starting the next round of accumulation. Note that "each round of accumulation" herein refers to the accumulation performed from the time the register bank of each multiplication-accumulation unit clears the results stored therein in preparation for accumulation to the next time the register bank clears the results stored therein in preparation for accumulation, and does not refer to each time the register bank updates the results stored therein.

[0120] Under the control of the control element, the summing unit 120 will not receive the output of each multiplication and accumulation unit before each multiplication and accumulation unit completes the current round of accumulation, and thus will not perform the summing operation. In other words, under the control of the control element, the input received by the summing unit 120 before each multiplication and accumulation unit completes the current round of accumulation is always zero. Only after each multiplication and accumulation unit completes the current round of accumulation, the summing unit 120 will receive the output of each multiplication and accumulation unit and sum them under the control of the control element. In other words, between the multiplication and accumulation units 1101, 1102, ... 110 j During the whole operation process, each multiplication and accumulation unit is always flipped, but the summing unit 120 does not flip. j After the operation is completed, the summing unit 120 will flip over a cycle for summing. By isolating the control elements, the flipping frequency of the summing unit 120 is lower than that of the multiplication and accumulation units 1101, 1102, ... 110 j The flip frequency is much lower. j The summing unit 120 can be regarded as the active region of the multiplication-accumulation circuit 100', while the summing unit 120 can be regarded as the quiet region of the multiplication-accumulation circuit 100'. By dividing the active region and the quiet region, the multiplication-accumulation circuit 100' achieves reduced power consumption.

[0121] For non-limiting illustrative purposes, FIG. 19 to FIG. 22 respectively illustrate example circuit diagrams for implementing the multiplication-accumulation circuit 100 ′ of FIG. 18 according to some embodiments of the present disclosure.

[0122] FIG19 shows a multiplication-accumulation circuit 100H. Compared with the multiplication-accumulation circuit 100G in FIG17 , the difference is that the number of multiplication-accumulation units is changed from 1 to j, and a summing unit 120 is added to sum the multiplication-accumulation units 1101, ..., 110 j The summing unit 120 includes a first-level compression tree 1210 and an adder 1200. When j=2, the compression tree 1210 can be omitted. j Due to the parallel design, each multiplication-accumulation unit of the multiplication-accumulation circuit 100H can perform m logarithmic multiplications and accumulations in each cycle. Compared to the (x / m) cycles required for the multiplication-accumulation circuit 100G of Figure 17, the multiplication-accumulation circuit 100H of Figure 19 only requires (x / jm+1) cycles, thereby improving operational efficiency. The number j of parallel multiplication-accumulation units can be flexibly configured according to actual needs. In addition, compared to the multiplication-accumulation circuit 100G which uses a single accumulation sub-circuit for accumulation, the multiplication-accumulation circuit 100H uses multiple accumulation sub-circuits for accumulation, which can avoid the difficulty of timing convergence caused by the excessive circuit scale of a single accumulation sub-circuit.

[0123] 20, it shows that the summing unit 120 sets a two-level compression tree before the adder 1200, wherein the first-level compression tree includes two parallel compression trees 12101 and 12102, and the second-level compression tree includes a compression tree 1220. j The output end of can be coupled to the corresponding input ends of the first-level compression trees 12101 and 12102, and the output ends of the first-level compression trees 12101 and 12102 can be coupled to the corresponding input ends of the second-level compression tree 1220. The output end of the second-level compression tree 1220 can be coupled to the adder 1200. The output end of the adder 1200 can provide the output end of the summing unit 120 and the output end of the multiplication and accumulation circuit. Figure 20 is equivalent to implementing an 8:2 compression tree by combining three 4:2 compression trees. The compression tree of the summing unit 120 of Figure 20 can have a simpler design than the compression tree of the summing unit 120 of Figure 19. From another perspective, when the summing unit 120 of Figure 20 and the summing unit 120 of Figure 19 use the same compression tree, the former can accommodate a larger multiplication and accumulation unit scale, thereby further improving the circuit processing performance.

[0124] FIG21 shows a multiplication-accumulation circuit 100I, which differs from the multiplication-accumulation circuit 100H of FIG19 in that the summing unit 120 further includes an additional register group 1201, the input end of the additional register group 1201 is coupled to the output end of the adder 1200, and the output end of the additional register group 1201 is coupled to the corresponding input end of the first-level compression tree 1210. The introduction of the additional register group 1201 enables the summing unit 120 to also have an accumulation function, which enables the multiplication-accumulation units 1101, ..., 110 j The accumulation subcircuit of each multiplication-accumulation unit does not need to fully accumulate, which reduces the bit width requirement of the register group of the accumulation subcircuit, so that the registers in the register group of the accumulation subcircuit can have a smaller number of bits and thus have lower area and power consumption.

[0125] FIG22 shows a multiplication-accumulation circuit 100J, which differs from the multiplication-accumulation circuit 100I of FIG21 in that the multiplication-accumulation units 1101, ..., 110 j Control elements 1131, ... 113 are further provided between the output end of j , control elements 1131, ... 113 j Receive corresponding multiplication and accumulation units 1101, ... 110 j Output and control signals Sc1, ...Sc j as input and configured to be responsive to control signals Sc1, . . . Sc j And whether the control is in the control element 1131, ... 113 jThe output end of the summing unit 120 provides the corresponding multiplication and accumulation units 1101, ... 110 j Output of control element 1131, ... 113 j Each of the control elements 1131, ... 113 may include at least one of the following: an AND gate, a NAND gate, a multiplexer, and an inverting multiplexer. j Each of the control elements 1131, 1132, 1133 may include an AND gate group, a NAND gate group, a multiplexer group, or an inverting multiplexer group. The number of elements in the AND gate group, the NAND gate group, the multiplexer group, or the inverting multiplexer group may depend on the data bit width. For example, when the control elements 1131, 113 ... j When each includes an AND gate group, the control signals Sc1, ...Sc j When the output of the register group of the corresponding multiplication and accumulation unit is 0, the output of the register group of the corresponding multiplication and accumulation unit is not provided at the output terminal (instead, 0 can be output at the output terminal) and the control signals Sc1, ...Sc j When the control element 1131, ... 113 is 1, the output of the register group of the corresponding multiplication and accumulation unit is provided at its output terminal. j When each includes a multiplexer group, the control signals Sc1, ...Sc j can serve as a selection signal, 0 can serve as a first input, and the output of the register group of the corresponding multiplication and accumulation unit can serve as a second input, so that the multiplexer group can control the signals Sc1, ...Sc j =0, the first input is provided as 0 at its output (ie, the second input as the output of the register group of the corresponding multiply-accumulate unit is not provided at its output) and the control signals Sc1, ...Sc j =1, the second input of the register group of the corresponding multiply-accumulate unit is provided at its output. j When each includes a NAND gate group and when the control elements 1131, ... 113 j The situations when each includes an inverting multiplexer group are respectively the same as when the control elements 1131, ... 113 j Each includes a gate group and a control element 1131, ... 113 j The situation when each includes a multiplexer group is similar, but an inverted output is provided, which can be corrected inside the summing unit 120 by adjusting the configuration of the summing unit 120 (for example, adding a NOT gate or an inverter, etc.).

[0126] For example, suppose the multiplication and accumulation circuit 100J is to implement 1024 logarithmic multiplication and accumulation (A1·b1+A2·b2+...A 1024 b 1024), the multiplication-accumulation circuit 100J includes 4 multiplication-accumulation units (j=4), and the multiplication sub-circuit of each multiplication-accumulation unit includes 4 multipliers (m=4), so the typical multiplication-accumulation operation process can be carried out as follows: 16 multipliers calculate in parallel to output 16 multiplication operation results in each cycle; 4 accumulation sub-circuits accumulate in parallel, and the register group in each accumulation sub-circuit is configured to output the stored results and clear them every 8 cycles (meaning that one round of accumulation includes 8 cycles), so under the control of the corresponding control element, the output provided to the summation unit each time by each multiplication-accumulation unit includes 32 logarithmic multiplication-accumulation results, that is, the summation unit will receive 128 logarithmic multiplication-accumulation results every 8 cycles; in order to complete the multiplication-accumulation of 1024 logarithms, the compression tree, adder and additional register group in the summation unit only need to be flipped 8 times, thereby achieving power consumption reduction.

[0127] As mentioned above, since the first number a is unknown in advance k Can be processed as an unsigned number A k Therefore, the multiplier of the multiplication-accumulation circuit 100, 100' only needs to support the unsigned number A k With the pre-known number b k The multiplication operation of the unsigned number A can be done by the following mathematical derivation. k (assuming the bit width is z) and the pre-known number b k The operation process of the multiplication operation mul (assuming the bit width is w) is unified as follows.

[0128] When b k When it is an unsigned number, mul=A k b k mul=A k ·(b k(w-1) 2 w-1 +bk[(w-2):0]) mul=A k b k(w-1) 2 w-1 +A k bk[(w-2):0]

[0129] Among them, b k(w-1) It is b k The highest bit, bk[(w-2):0] is b k Divide the highest digit b by k(w-1) Other bits except "·2 w-1 ” is a shift operation, which means shifting left by (w-1) bits.

[0130] When b k When it is a signed number, mul=A k b k mul=Ak ·(-b k(w-1) 2 w-1 +bk[(w-2):0]) mul=A k ·(-b k(w-1) 2 w-1 )+A k bk[(w-2):0] mul=~A k b k(w-1) 2 w-1 +A k ·bk[(w-3):0]+(1-2 w )·2 w-1

[0131] Among them, ~ is the bitwise negation operator. (1-2 w )·2 w-1 can be extracted as a constant term. Therefore, the unsigned number A k With the pre-known unsigned number b k The operation process is similar to the unsigned number A k With the pre-known signed number b k The calculation process of A k with b k Divide the highest digit b by k(w-1) The partial product of the other bits bk[(w-2):0] (A k bk[(w-2):0]) are the same, the difference is that A k with b k The highest bit b k(w-1)] In terms of the partial product, because for the signed number b k The highest bit is the sign bit and does not represent the value.

[0132] Based on the above-mentioned operational principles, the present disclosure provides a multiplier that can be used to perform a multiplication operation on a first multiplier and a second multiplier, where the first multiplier is an unsigned number and the second multiplier is a pre-known unsigned number or a signed number. Such a multiplier may include a partial product generation circuit and a partial product summation circuit. The partial product generation circuit is configured to receive the first multiplier and the second multiplier and output their partial products. The input of the partial product summation circuit is coupled to the output of the partial product generation circuit. The partial product summation circuit is configured to receive the partial products output by the partial product generation circuit and sum them. In particular, the partial product generation circuit may include a first partial product generation unit for outputting the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit is configured to: if the second multiplier is an unsigned number, output the partial product of the most significant bit of the second multiplier and the first multiplier; if the second multiplier is a signed number, output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier. For example, the first partial product generating unit may be configured to: receive a sign flag indicating whether the second multiplier is an unsigned number or a signed number; if the sign flag indicates that the second multiplier is an unsigned number, output the partial product of the most significant bit of the second multiplier and the first multiplier; and if the sign flag indicates that the second multiplier is a signed number, output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generating unit may also determine whether the second multiplier is an unsigned number or a signed number by other means.

[0133] FIG23 illustrates a multiplier 1110 according to some embodiments of the present disclosure. As shown in FIG23 , the multiplier 1110 includes a partial product generation circuit 510 and a partial product summation circuit 520. An input of the partial product generation circuit 510 may provide an input IN of the multiplier 1110. An input of the partial product summation circuit 520 is coupled to an output of the partial product generation circuit 510. An output of the partial product summation circuit 520 may provide an output OUT of the multiplier 1110.

[0134] The partial product generation circuit 510 is configured to receive a first multiplier as an unsigned number and a pre-known second multiplier and output the partial product thereof. The partial product generation circuit 510 may include a first partial product generation unit 511 for outputting the partial product of the most significant bit of the second multiplier and the first multiplier. The first partial product generation unit 511 may receive the most significant bit of the second multiplier and the first multiplier and a sign flag indicating whether the second multiplier is an unsigned number or a signed number. The first partial product generation unit 511 is configured to output the partial product of the most significant bit of the second multiplier and the first multiplier if the received sign flag indicates that the second multiplier is an unsigned number. The first partial product generation unit 511 is further configured to output the inverse of the partial product of the most significant bit of the second multiplier and the first multiplier if the received sign flag indicates that the second multiplier is a signed number.

[0135] In some embodiments, the first partial product generating unit 511 includes: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation thereon; and an XOR gate group configured to receive the AND operation result of the AND gate group and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an XOR operation thereon. The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit 511.

[0136] In some embodiments, the first partial product generating unit 511 includes: a NAND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform a NAND operation thereon; and an XOR gate group configured to receive the NAND operation result of the NAND gate group and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an XOR operation thereon. The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit 511.

[0137] In some embodiments, the first partial product generating unit 511 includes: an XOR gate configured to receive the highest bit of the second multiplier and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an XOR operation thereon; and a multiplexer group, each multiplexer in the multiplexer group configured to receive the sign flag as a first input, receive the XOR operation result of the XOR gate as a second input, receive a corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal. The output of the multiplexer group is provided as the output of the first partial product generating unit 511.

[0138] In some embodiments, the first partial product generating unit 511 includes: an XOR gate configured to receive the highest bit of the second multiplier and a sign flag indicating whether the second multiplier is an unsigned number or a signed number and perform an XOR operation on them; an inverting multiplexer group, each inverting multiplexer in the inverting multiplexer group configured to receive the sign flag as a first input, receive the XOR operation result of the XOR gate as a second input, receive a corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal. The output of the inverting multiplexer group is provided as the output of the first partial product generating unit 511.

[0139] In some embodiments, the first partial product generating unit 511 includes: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation on them; a multiplexer group configured to receive the AND operation result of the AND gate group as a first input, receive the negation of the AND operation result of the AND gate group as a second input, receive a sign flag indicating whether the second multiplier is an unsigned number or a signed number as a selection signal, and output the first input or the second input based on the selection signal. The output of the multiplexer group is provided as the output of the first partial product generating unit 511. A NOT gate group can be used to receive the AND operation result of the AND gate group and perform a NOT operation on it to obtain the negation of the AND operation result of the AND gate group. Furthermore, the AND gate group can be replaced by a NAND gate group. Additionally or alternatively, the multiplexer group can be replaced by an inverting multiplexer group.

[0140] The partial product generation circuit 510 may further include a second partial product generation unit 512 for outputting a partial product of the first multiplier and bits other than the most significant bit of the second multiplier.

[0141] In some embodiments, the second partial product generating unit 512 may be configured to output the modified second multiplier (bk[(w-2):0]) and the first multiplier (A k ), the modified second multiplier (bk[(w-2):0]) is obtained by removing the second multiplier (b k )'s highest digit (b k(w-1) In such an embodiment, the second partial product generating unit 512 may include a multiplier for performing a multiplication operation of an unsigned number with an unsigned number.

[0142] Instead of generating partial products by taking bk[(w-2):0] as a whole, bk[(w-2):0] may be split into multiple parts to generate partial products respectively, each part may include one or more bits in bk[(w-2):0]. For example, the second partial product generating unit 512 may include multiple second partial product generating units, each of which is used to output the second multiplier (b k ) except the highest digit (b k(w-1) ) and the corresponding bits other than the first multiplier (A k ). In some embodiments, each second partial product generating unit may include an AND gate group configured to receive corresponding bits of the second multiplier other than the highest bit and the first multiplier and perform an AND operation thereon. The AND operation result of the AND gate group is provided as the output of each second partial product generating unit. In other embodiments, each second partial product generating unit may also include a NAND gate group configured to receive corresponding bits of the second multiplier other than the highest bit and the first multiplier and perform a NAND operation thereon. The NAND operation result of the NAND gate group is provided as the output of each second partial product generating unit.

[0143] Continuing with FIG. 23 , the partial product summation circuit 520 is configured to receive and sum the partial products output by the partial product generation circuit 510. If the multiplier 1110 is configured with dual output terminals, the partial product summation circuit 520 may include a partial product compression circuit 521. The input terminal of the partial product compression circuit 521 is coupled to the output terminal of the partial product generation circuit 510. The partial product compression circuit 521 is configured to receive the partial products output by the partial product generation circuit 510 and compress and sum them to output the sum digit and the carry digit of the compressed summation result of the partial products. If the multiplier 1110 is configured with a single output terminal, the partial product summation circuit 520 may further include a final addition circuit 522 in addition to the partial product compression circuit 521. The input terminal of the final addition circuit 522 is coupled to the output terminal of the partial product compression circuit 521. The final addition circuit 522 is configured to receive and sum the sum digit and the carry digit output by the partial product compression circuit 521.

[0144] For non-limiting illustrative purposes, FIG. 24 to FIG. 27 respectively illustrate example circuit diagrams for implementing the multiplier 1110 of FIG. 23 according to some embodiments of the present disclosure.

[0145] As shown in FIG24 , the multiplier 1110A has two output terminals and includes a partial product generating circuit 510 and a partial product summing circuit 520. The partial product generating circuit 510 includes a first partial product generating unit 511 and a plurality of second partial product generating units 5120, ..., 512. w-3 , 512 w-2The first partial product generating unit 511 includes an AND gate group AND and an XOR gate group XOR, wherein the AND gate group AND receives the first multiplier A k and the second multiplier b k The highest bit b k(w-1) The AND operation is performed on the AND gates, and the XOR gate group receives the AND operation result of the AND gate group and the sign flag Flag2 indicating whether the second multiplier is an unsigned number or a signed number and performs an XOR operation on them. The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit 511. The second partial product generating units 5120, ..., 512 w-3 , 512 w-2 Each of the AND gates includes an AND gate group AND, the AND gate group AND receives the first multiplier A k and the second multiplier b k b k0 ,……,b k(w-3) 、b k(w-2) The AND operation is performed on the corresponding one of the first partial product generating unit and the AND operation result is provided as the output of the second partial product generating unit. The partial product summing circuit 520 may include a compression tree as a partial product compression circuit 521. The first partial product generating unit 511 and the plurality of second partial product generating units 5120, ..., 512 w-3 , 512 w-2 The output terminals of the partial product compression circuit 521 are respectively coupled to corresponding input terminals of the partial product compression circuit 521, and the two output terminals of the partial product compression circuit 521 provide the two output terminals of the multiplier 1110A. In FIG24 , the partial product compression circuit 521 is shown as a single w:2 compression tree, but it can also adopt a combination of multiple compression trees (for example, a cascade of multiple stages of compression trees, each stage of compression tree may include a compression tree or multiple compression trees in parallel), or can alternatively be implemented as a full adder or a combination of a full adder and a half adder.

[0146] FIG25 shows a multiplier 1110B, which differs from the multiplier 1110A in FIG24 in that the partial product summation circuit 520 further includes an adder as a final adding circuit 522, so that the multiplier 1110B has a single output terminal.

[0147] FIG26 illustrates a multiplier 1110C, which differs from the multiplier 1110A in FIG24 in that the AND gate group in the partial product generation circuit 510 is replaced with a NAND gate group. This results in the output of the partial product generation circuit 510 of the multiplier 1110C being inverted relative to the output of the partial product generation circuit 510 of the multiplier 1110A. Accordingly, the partial product compression circuit 521′ of the multiplier 1110C needs to be adjusted accordingly compared to the partial product compression circuit 521 of the multiplier 1110A to internally correct for the inverted output of the partial product generation circuit 510 of the multiplier 1110C. This adjustment can be achieved, for example, but not limited to, by incorporating a NOT gate or an inverter into the partial product compression circuit 521′.

[0148] FIG27 shows a multiplier 1110D, which differs from the multiplier 1110C in FIG26 in that the partial product summation circuit 520 further includes an adder as a final adding circuit 522, so that the multiplier 1110D has a single output terminal.

[0149] For non-limiting illustrative purposes, FIG. 28 to FIG. 30 also respectively illustrate example circuit diagrams for implementing the first partial product generating unit 511 of the multiplier 1110 of FIG. 23 according to some embodiments of the present disclosure.

[0150] As shown in FIG. 28 , the first partial product generating unit 511A includes an XOR gate XOR configured to receive the second multiplier b k The highest bit b k(w-1) The first partial product generating unit 511A further includes a multiplexer group MUX. Each multiplexer MUX is configured to receive the sign flag Flag2 as a first input q0, receive the XOR operation result of the XOR gate XOR as a second input q1, and receive the first multiplier A. k The corresponding bit (A k0 、……A k(z-2) 、A k(z-1) ) as a selection signal, and outputs the first input q0 or the second input q1 according to the selection signal. Specifically, when the selection signal is 0, the multiplexer MUX outputs the first input q0, and when the selection signal is 1, the multiplexer MUX outputs the second input q1. The output of the multiplexer group MUX is provided as the output of the first partial product generation unit 511A. The first partial product generation unit 511A in Figure 28 can have a smaller number of logic gates than the first partial product generation unit 511 in Figures 24 and 25.

[0151] FIG29 illustrates a first partial product generating unit 511B, which differs from the first partial product generating unit 511A in FIG28 in that the multiplexer group MUX is replaced with an inverting multiplexer group MUXI. This results in the output of the first partial product generating unit 511B being inverted relative to the output of the first partial product generating unit 511A. Accordingly, the partial product compression circuit 521 of the multiplier 1110 also needs to be adjusted accordingly to internally correct the inverted output of the first partial product generating unit 511B. This adjustment can be achieved, for example, but not limited to, by incorporating a NOT gate or an inverter into the partial product compression circuit 521. The first partial product generating unit 511B in FIG29 can have fewer logic gates than the first partial product generating unit 511 in FIG26 and FIG27.

[0152] FIG30 shows a first partial product generating unit 511C, which includes an AND gate group AND, a NOT gate group NOT, and a multiplexer group MUX. The AND gate group AND is configured to receive the second multiplier b k The highest bit b k(w-1) With the first multiplier A k The NOT gate group NOT is configured to receive the AND operation result of the AND gate group AND and perform a NOT operation (inversion) on it. The multiplexer group MUX is configured to receive the AND operation result of the AND gate group AND as a first input, receive the NOT operation result of the NOT gate group NOT as a second input, and receive the second multiplier b. k The sign flag Flag2, which indicates whether the number is unsigned or signed, is used as a selection signal, and the first input or the second input is output according to the selection signal. The output of the multiplexer group MUX is provided as the output of the first partial product generating unit 511. Similar to the above, the AND gate group can also be replaced by a NAND gate group. Additionally or alternatively, the multiplexer group can also be replaced by an inverting multiplexer group. Accordingly, the partial product compression circuit 521 of the multiplier 1110 can be adjusted accordingly as appropriate.

[0153] In addition, regarding the constant term (1-2 w )·2 w-1 In some embodiments, referring to FIG. 31 , the output of the partial product summing circuit 520 of the multiplier 1110 is coupled to the input of the additional adding circuit 600 , which may be configured to add the second multiplier b to the output of the partial product summing circuit 520 of the multiplier 1110 . k If the number is a signed number, the output of the partial product summation circuit 520 is added to a constant, and the constant is (1-2 w )·2 w-1 , where w is the second multiplier b kIn some embodiments, the multiplier 1110 may further include an additional adding circuit 600. In other embodiments, the additional adding circuit 600 may not be used, and the constant term (1-2 w )·2 w-1 The constant term (-2 z-1 b k ) are processed together. For example, in some embodiments, the output processing circuit 300 shown in FIG5 may be configured to perform at least one of the following: subtracting the output of the accumulation subcircuit 112 from a first constant, the first constant being the sum of the plurality of pairs of first numbers a k and the second number b k All the first number a in the k The second number of the pair b k After left shifting by (z-1) bits (2 z-1 b k ), where z is the first number a k or the output of the accumulation sub-circuit 112 is added to a second constant, the second constant being (1-2 w )·2 w-1 y, where w is the second multiplier b k The bit width, y is the first number from the multiple pairs a k and the second number b k All the second numbers b in k The second multiplier b obtained as a signed number k In some cases, it is not necessary to set up a dedicated output processing circuit 300 or an additional adding circuit 600 to process these constant terms (1-2 w )·2 w-1 For example, in the convolution calculation unit of the neural network processor, in addition to performing multiplication and accumulation operations on the activation data and weight data, the result of the multiplication and accumulation operation needs to be added to the bias term. In the convolution calculation unit, the addition of the bias term itself is already handled by dedicated hardware, so the above constant term (1-2 w )·2 w-1 and (-2 z-1 b k ) can be integrated with the bias term in advance without paying additional hardware cost for processing.

[0154] In another aspect, the present disclosure further provides a processor, which may include the multiplier according to any of the aforementioned embodiments, or the multiplication-accumulation circuit according to any of the aforementioned embodiments, or the arithmetic circuit according to any of the aforementioned embodiments. For example, such a processor may be a coprocessor, a digital signal processor, a central processing unit, a dedicated instruction processor, a neural network processor, or other processors. In the case where such a processor is a neural network processor, its convolution calculation unit may include the multiplier according to any of the aforementioned embodiments, or the multiplication-accumulation circuit according to any of the aforementioned embodiments, or the arithmetic circuit according to any of the aforementioned embodiments.

[0155] The present disclosure further provides, on another aspect, a computing device, which may include the processor according to any of the foregoing embodiments. Examples of computing devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of computing devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer / dryers, peripheral devices, clocks, and the like. In addition, computing devices may include incomplete products.

[0156] The words "left," "right," "front," "back," "top," "bottom," "up," "down," "high," "low," and the like, if any, in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein, for example, are capable of operation in orientations other than those illustrated or otherwise described herein. For example, features previously described as "above" other features could be described as "below" the other features when the apparatus in the drawings is turned over. The apparatus can also be otherwise oriented (rotated 90 degrees or in other orientations) and relative spatial relationships would be interpreted accordingly.

[0157] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "in contact with," etc., another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly in contact with the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly" "on," "directly attached," "directly connected," "directly coupled," or "in direct contact with" another element, there will be no intervening elements. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0158] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0159] As used herein, the term "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0160] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0161] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0162] In addition, when used in this application, the words "herein," "above," "below," "hereunder," "supra," and words of similar meaning shall refer to this application as a whole and not to any particular portion of this application. Furthermore, unless expressly stated otherwise or otherwise understood in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to express that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0163] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0164] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0165] Those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all of the embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative, not restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways.

[0166] The various embodiments of the present disclosure may be described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In the present disclosure, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0167] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A multiplier for performing a multiplication operation of a first multiplier and a second multiplier, wherein the first multiplier is an unsigned number and the second multiplier is a pre-known unsigned number or a signed number, the multiplier comprising: a partial product generating circuit configured to receive the first multiplier and the second multiplier and output a partial product thereof; a partial product summing circuit, the input end of the partial product summing circuit being coupled to the output end of the partial product generating circuit, the partial product summing circuit being configured to receive the partial products output by the partial product generating circuit and sum them, The partial product generating circuit comprises a first partial product generating unit for outputting a partial product of the highest bit of the second multiplier and the first multiplier, and the first partial product generating unit is configured as follows: When the second multiplier is an unsigned number, outputting a partial product of the most significant bit of the second multiplier and the first multiplier; When the second multiplier is a signed number, a negated result of a partial product of the most significant bit of the second multiplier and the first multiplier is output.

2. The multiplier according to claim 1, wherein: The first partial product generating unit is configured as follows: receiving a sign flag indicating whether the second multiplier is an unsigned number or a signed number; When the sign flag indicates that the second multiplier is an unsigned number, outputting a partial product of the most significant bit of the second multiplier and the first multiplier; When the sign flag indicates that the second multiplier is a signed number, a negated result of a partial product of the most significant bit of the second multiplier and the first multiplier is output.

3. The multiplier according to claim 2, wherein: The first partial product generating unit comprises: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation thereon; an XOR gate group, configured to receive the AND operation result of the AND gate group and the sign flag bit and perform an XOR operation on them, The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit.

4. The multiplier according to claim 2, wherein: The first partial product generating unit comprises: A NAND gate group is configured to receive the highest bit of the second multiplier and the first multiplier and perform NAND on them. Operation; an XOR gate group, configured to receive the NAND operation result of the NAND gate group and the sign flag bit and perform an XOR operation on them, The XOR operation result of the XOR gate group is provided as the output of the first partial product generating unit.

5. The multiplier according to claim 2, wherein: The first partial product generating unit comprises: an XOR gate configured to receive the highest bit of the second multiplier and the sign flag bit and perform an XOR operation thereon; a multiplexer group, each multiplexer in the multiplexer group being configured to receive the sign flag bit as a first input, receive the XOR operation result of the XOR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, The output of the multiplexer group is provided as the output of the first partial product generating unit.

6. The multiplier according to claim 2, wherein: The first partial product generating unit comprises: an XOR gate configured to receive the highest bit of the second multiplier and the sign flag bit and perform an XOR operation thereon; an inverting multiplexer group, each inverting multiplexer in the inverting multiplexer group being configured to receive the sign flag bit as a first input, receive the XOR operation result of the XOR gate as a second input, receive the corresponding bit of the first multiplier as a selection signal, and output the first input or the second input according to the selection signal, The output of the inverting multiplexer group is provided as the output of the first partial product generating unit.

7. The multiplier according to claim 2, wherein: The first partial product generating unit comprises: an AND gate group configured to receive the highest bit of the second multiplier and the first multiplier and perform an AND operation thereon; a multiplexer group, configured to receive the AND operation result of the AND gate group as a first input, receive the inverted result of the AND operation result of the AND gate group as a second input, receive the sign flag as a selection signal, and output the first input or the second input according to the selection signal, The output of the multiplexer group is provided as the output of the first partial product generating unit.

8. The multiplier according to any one of claims 1 to 7, wherein: The partial product generation circuit also includes a second partial product generation unit for outputting a partial product of a modified second multiplier and the first multiplier, wherein the modified second multiplier is obtained by removing the highest bit of the second multiplier and is an unsigned number, and the second partial product generation unit includes a multiplier for performing a multiplication operation of an unsigned number and an unsigned number.

9. The multiplier according to any one of claims 1 to 7, wherein: The partial product generating circuit further includes a plurality of second partial product generating units, each of which is configured to output a partial product of a corresponding bit of the second multiplier except for a highest bit and the first multiplier.

10. The multiplier according to claim 9, wherein: Each of the plurality of second partial product generating units comprises one of the following: an AND gate group configured to receive corresponding bits of the second multiplier except the highest bit and the first multiplier and perform an AND operation thereon, wherein an AND operation result of the AND gate group is provided as an output of the second partial product generating unit; or A NAND gate group is configured to receive corresponding bits of the second multiplier except the highest bit and the first multiplier and perform a NAND operation thereon, wherein a NAND operation result of the NAND gate group is provided as an output of the second partial product generating unit.

11. The multiplier according to claim 1, wherein: The output terminal of the partial product summation circuit is coupled to the input terminal of the additional adding circuit, and the additional adding circuit is configured to add the output of the partial product summation circuit to a constant when the second multiplier is a signed number, and the constant is (1-2 w )·2 w-1 , where w is the bit width of the second multiplier.

12. A multiplication-accumulation circuit, for performing a plurality of multiplication-accumulation operations on a first number and a second number, wherein the second number is known in advance, the multiplication-accumulation circuit comprising at least one multiplication-accumulation unit, wherein the multiplication-accumulation unit comprises: a multiplication subcircuit comprising a multiplier for performing a multiplication operation of a first multiplier obtained from the first number and being an unsigned number and a second multiplier obtained from the second number and being a pre-known unsigned number or a signed number, the multiplier being configured to provide an output as an unsigned number; as well as An accumulation subcircuit, wherein an input terminal of the accumulation subcircuit is coupled to an output terminal of the multiplication subcircuit, and the accumulation subcircuit is configured to receive and accumulate an output of the multiplication subcircuit.

13. The multiplication-accumulation circuit according to claim 12, wherein: The multiplier of the multiplication subcircuit is a multiplier according to any one of claims 1 to 11.

14. The multiplication-accumulation circuit according to claim 12, wherein: The multiplication subcircuit includes a plurality of the multipliers, each of the multipliers being configured to receive a corresponding pair of a first multiplier and a second multiplier and to product the corresponding pair of the first multiplier and the second multiplier.

15. The multiplication-accumulation circuit according to claim 14, wherein: The accumulation subcircuit includes one of the following: n-level compression trees, a first adder, a second adder and a register group, the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the first adder, the output end of the first adder is coupled to the corresponding input end of the second adder, the output end of the second adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the second adder, wherein n is a positive integer, i=1, 2, ..., n-1; or n-level compression trees, full adders, adders and register groups, the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the full adder, the output end of the full adder is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the full adder, wherein n is a positive integer, i=1, 2, ..., n-1; or n-level compression trees, an adder and a register group, the output end of the multiplication subcircuit is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, the output end of the i-th-level compression tree among the n-level compression trees is coupled to the corresponding input end of the (i+1)-th-level compression tree among the n-level compression trees, the output end of the n-level compression tree among the n-level compression trees is coupled to the corresponding input end of the adder, the output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the first-level compression tree among the n-level compression trees, wherein n is a positive integer, i=1, 2, ..., n-1; or A full adder module, an adder and a register group having one or more full adders, wherein the output end of the multiplication subcircuit is coupled to the corresponding input end of the full adder module, and the output end of the full adder module is coupled to the corresponding input end of the adder. The output end of the adder is coupled to the input end of the register group, and the output end of the register group is coupled to the corresponding input end of the full adder module.

16. The multiplication-accumulation circuit according to any one of claims 12 to 15, wherein: The at least one multiplication-accumulation unit includes two or more multiplication-accumulation units, and the multiplication-accumulation circuit also includes a summing unit, an input end of the summing unit is coupled to the output ends of the two or more multiplication-accumulation units, and the summing unit is configured to receive the outputs of the two or more multiplication-accumulation units and sum them.

17. The multiplication-accumulation circuit according to claim 16, wherein: The summing unit includes an s-level compression tree and an adder, an output end of each of the two or more multiplication-accumulation units is coupled to a corresponding input end of a 1st-level compression tree among the s-level compression trees, an output end of an i-th-level compression tree among the s-level compression trees is coupled to a corresponding input end of an (i+1)th-level compression tree among the s-level compression trees, and an output end of an s-th-level compression tree among the s-level compression trees is coupled to a corresponding input end of the adder, Wherein, s is a non-negative integer, i=1, 2,…, s-1.

18. The multiplication-accumulation circuit according to claim 17, wherein: The summing unit further includes an additional register group, an input terminal of the additional register group is coupled to an output terminal of the adder, and an output terminal of the additional register group is coupled to a corresponding input terminal of a first-stage compression tree in the s-stage compression tree.

19. The multiplication-accumulation circuit according to claim 16, wherein: The multiplication-accumulation circuit also includes a control element arranged between the output end of each multiplication-accumulation unit of the two or more multiplication-accumulation units and the corresponding input end of the summation unit, and the control element is configured to receive a control signal and the output of the corresponding multiplication-accumulation unit and control whether the output of the corresponding multiplication-accumulation unit is provided to the summation unit at the output end of the control element according to the control signal.

20. The multiply-accumulate circuit according to claim 12, wherein: The input of the multiplication subcircuit is also coupled to an output of an input processing circuit, the input processing circuit being configured to receive the first number and the second number and: In the case where the first number is a signed number, outputting the first number as a first multiplier for feeding into the multiplier by inverting a sign bit of the first number, and outputting the second number as a second multiplier for feeding into the multiplier; In the case where the first number is an unsigned number, the first number is output as a first multiplier for feeding into the multiplier, and the second number is output as a second multiplier for feeding into the multiplier.

21. The multiplication-accumulation circuit according to claim 20, wherein: The input processing circuit includes one of the following: an XOR gate configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is an unsigned number or a signed number and perform an XOR operation thereon, wherein the XOR operation result of the XOR gate is provided as the most significant bit of the first number output by the input processing circuit; or A multiplexer is configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive a sign flag indicating whether the first number is an unsigned number or a signed number as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

22. The multiply-accumulate circuit according to claim 12, wherein: The input end of the multiplication subcircuit is also coupled to the output end of the input processing circuit, the input processing circuit is configured to receive the first number and the second number, the input processing circuit is also configured to split the first number according to the bit width of the multiplier, and the multiplication and addition circuit also includes a shifter coupled to the output end of the multiplication subcircuit, and the shifter is configured to perform a shift operation corresponding to the split.

23. The multiply-accumulate circuit according to claim 22, wherein: The input processing circuit is further configured to split the second number according to the bit width of the multiplier; or The input processing circuit is configured to receive the second number pre-split according to a bit width of the multiplier.

24. The multiply-accumulate circuit according to claim 12, wherein: The output terminal of the accumulation subcircuit is coupled to the input terminal of the output processing circuit, and the output processing circuit is configured to perform at least one of the following: subtracting the output of the accumulation subcircuit from a first constant, the first constant being the sum of all the second numbers of the plurality of pairs of first numbers and second numbers paired with the first number as a signed number after being shifted left by (z-1) bits, where z is the bit width of the first number; or The output of the accumulation subcircuit is added to a second constant, wherein the second constant is (1-2 w )·2 w-1 y, wherein w is the bit width of the second multiplier, and y is obtained from all the second numbers of the plurality of pairs of first numbers and second numbers as The number of second multipliers for the signed number.

25. An operation circuit, comprising: The multiply-accumulate circuit according to any one of claims 12 to 24; as well as an input processing circuit, wherein an output terminal of the input processing circuit is coupled to an input terminal of the multiplication-accumulation circuit, the input processing circuit being configured to receive the first number and the second number and: In the case where the first number is a signed number, outputting the first number as a first multiplier for feeding into the multiplier by inverting a sign bit of the first number, and outputting the second number as a second multiplier for feeding into the multiplier; In the case where the first number is an unsigned number, the first number is output as a first multiplier for feeding into the multiplier, and the second number is output as a second multiplier for feeding into the multiplier.

26. The operation circuit according to claim 25, wherein: The input processing circuit includes one of the following: an XOR gate configured to receive the most significant bit of the first number and a sign flag indicating whether the first number is an unsigned number or a signed number and perform an XOR operation thereon, wherein the XOR operation result of the XOR gate is provided as the most significant bit of the first number output by the input processing circuit; or A multiplexer is configured to receive the most significant bit of the first number as a first input, receive the inverted result of the most significant bit of the first number as a second input, receive a sign flag indicating whether the first number is an unsigned number or a signed number as a selection signal, and output the first input or the second input according to the selection signal, wherein the output of the multiplexer is provided as the most significant bit of the first number output by the input processing circuit.

27. The operation circuit according to claim 25, wherein: The input processing circuit is further configured to split the first number according to the bit width of the multiplier, and the multiplication-accumulation circuit further includes a shifter coupled to the output terminal of the multiplication subcircuit, the shifter being configured to perform a shift operation corresponding to the splitting.

28. The operation circuit according to claim 27, wherein: The input processing circuit is further configured to split the second number according to the bit width of the multiplier; or The input processing circuit is configured to receive the second number pre-split according to a bit width of the multiplier.

29. The operation circuit according to claim 25, further comprising: An output processing circuit, wherein the output terminal of the multiplication-accumulation circuit is coupled to the input terminal of the output processing circuit, and the output processing circuit is configured to perform at least one of the following: subtracting the output of the multiplication-accumulation circuit from a first constant, the first constant being the sum of all the second numbers of the plurality of pairs of first numbers and second numbers paired with the first number as a signed number after being left shifted by (z-1) bits, where z is the bit width of the first number; or The output of the multiplication and accumulation circuit is added to a second constant, wherein the second constant is (1-2 w )·2 w-1 y, wherein w is the bit width of the second multiplier, and y is the number of second multipliers as signed numbers obtained from all the second numbers of the plurality of pairs of first numbers and second numbers.

30. An operation circuit, comprising: A multiplier according to any one of claims 1 to 11; as well as an additional adding circuit, the output terminal of the multiplier being coupled to the input terminal of the additional adding circuit, the additional adding circuit being configured to add the output of the partial product summation circuit to a constant when the second multiplier is a signed number, the constant being (1-2 w )·2 w-1 , where w is the bit width of the second multiplier.

31. A processor, comprising the multiplier according to any one of claims 1 to 11, the multiplication-accumulation circuit according to any one of claims 12 to 24, or the operation circuit according to any one of claims 25 to 30.

32. A computing device comprising a processor according to claim 31.

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