Bandpass filter

Abstract

A bandpass filter (1) includes: an input terminal (2A) to which a high-frequency signal is input; an output terminal (2B) from which an output signal is output; differential switches (4 to 9) provided between the input terminal (2A) and the output terminal (2B), in which a plurality of switches (10 to 21) controlled by a clock signal are connected in a tournament type, each of which comprises two switches; and capacitors (22 to 25), one end of which is connected to a connection point of a switch between the differential switches, and the other end of which is grounded.

Description

Bandpass Filter

[0001] The present disclosure relates to bandpass filters.

[0002] Bandpass filters are used in wireless communications to remove interference or unwanted signals. Technology exists for bandpass filter circuits that pass only signals of desired frequency components by varying the center frequency or attenuation of the operating frequency band to a desired value. The bandpass filter includes a switch connected between the input and output and switching the input signal voltage at the system clock frequency, a switched capacitor connected between the switch and ground potential, multiple sample-and-hold capacitors connected between the output and ground potential, and multiple sample-and-hold switches connected between the output and ground potential and connected in series to each sample-and-hold capacitor. The sample-and-hold switches are sequentially turned on one by one at the sampling clock frequency, holding the signal voltage appearing at the sample time in the sample-and-hold capacitor, and cyclically switching the sample-and-hold switches.

[0003] On the other hand, for example, Non-Patent Document 1 describes a bandpass filter in which two sample-and-hold switches are connected in series to increase the duty ratio of a sampling clock signal compared to conventional circuit configurations, and the sample-and-hold switches are driven by a sampling clock signal with a duty ratio of 50%. Since it is difficult to generate a sampling clock signal with a low duty ratio in the high-frequency band, the configuration described in Non-Patent Document 1 is expected to improve pass characteristics in the high-frequency band.

[0004] M. Pashaeifar, L. C. N. De Vreede and M. S. Alavi, “A Millimeter-Wave Front-End for FD / FDD Transceivers Featuring an Embedded PA and an N-Path Filter Based Circulator Receiver,” 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, USA, 2022, pp. 11-14

[0005] However, in the conventional technology described in Non-Patent Document 1, the signal path to the capacitor for charging the signal voltage is controlled on and off by two switches, with two switches per signal path. This increases the parasitic capacitance from the switch as seen from the clock signal source, causing the clock signal to become dull. When the clock signal becomes dull, the on-time of the switch changes, which changes the voltage charged to the capacitor, resulting in performance degradation such as increased transmission loss.

[0006] The present disclosure is intended to solve the above-mentioned problem, and aims to provide a bandpass filter that can suppress distortion of a clock signal caused by a switch for switching a signal path.

[0007] The band-pass filter according to the present disclosure comprises an input terminal to which a high-frequency signal is input, an output terminal to which an output signal is output, a plurality of differential switches each consisting of two switches, each of which is arranged between the input terminal and the output terminal and in which a plurality of switches controlled by a clock signal are connected in a tournament configuration, and a plurality of capacitors each having one end connected to a connection point between the differential switches and the other end grounded.

[0008] According to the present disclosure, a band-pass filter according to the present disclosure includes a plurality of differential switches, each consisting of two switches, in which a plurality of switches controlled by a clock signal are connected in a tournament configuration, and a plurality of capacitors, one end of which is connected to a junction between the differential switches and the other end of which is grounded. As a result, the band-pass filter according to the present disclosure reduces the number of switches driven by the clock signal for each phase by one compared to the band-pass filter described in Non-Patent Document 1. In other words, the band-pass filter according to the present disclosure reduces the number of switches as viewed from the clock signal source by one, thereby suppressing distortion of the clock signal caused by the switches for switching the signal path.

[0009] 1 is a circuit diagram showing a configuration example of a band-pass filter according to a first embodiment; FIG. 2 is a diagram showing a clock signal source; FIG. 3 is a waveform diagram showing a waveform of a clock signal in the band-pass filter according to the first embodiment; FIG. 4 is a circuit diagram showing a configuration example of a band-pass filter according to a second embodiment; and FIG. 5 is a waveform diagram showing a waveform of a clock signal in the band-pass filter according to the second embodiment.

[0010] Embodiment 1. Fig. 1 is a circuit diagram showing an example configuration of a band-pass filter 1 according to embodiment 1. Fig. 2 is a diagram showing a clock signal source 3. In Fig. 1, band-pass filter 1 is an N-path filter that can suppress deterioration in the attenuation of unwanted waves and suppress attenuation of the gain of a desired wave. Band-pass filter 1 is a filter controlled by clock signals S1, S2, S3, and S4 generated by clock signal source 3 shown in Fig. 2, and includes an input terminal 2A, an output terminal 2B, differential switches 4 to 9, and capacitors 22 to 25.

[0011] The clock period is T ＬＯIn this case, the clock signal source 3 generates four clock signals S1, S2, S3, and S4, each with a 50% duty ratio and a phase delay of 90 degrees. Clock signal S1 is a first clock signal with a phase of 0 degrees. Clock signal S2 is a second clock signal with a phase of 90 degrees. Clock signal S3 is a third clock signal with a phase of 180 degrees. Clock signal S4 is a fourth clock signal with a phase of 270 degrees. The clock signal source 3 may also be configured with a differential amplifier circuit. Note that as long as the bandpass filter operates as a desired filter, the duty ratio does not have to be 50%, and other periodic waveforms, such as a sine wave, may be used.

[0012] Differential switches 4 to 9 are provided between input terminal 2A and output terminal 2B, and are configured by switches 10 to 21 connected in a tournament configuration, controlled by a clock signal generated by clock signal source 3. Each differential switch is composed of two switches. For example, each switch in one differential switch is controlled by a clock signal that is 180 degrees out of phase with the other switch. Each switch outputs a signal when the clock signal is at a high level.

[0013] The differential switch 4 is a first differential switch composed of a switch 10 and a switch 11 connected to the input terminal 2A. The switch 10 is the first switch that receives one of the two split signals from the input terminal 2A and is controlled by a clock signal S1. The switch 11 is the second switch that receives the other of the two split signals from the input terminal 2A and is controlled by a clock signal S3.

[0014] Differential switch 5 is a second differential switch composed of switch 12 and switch 13 connected to switch 10 constituting differential switch 4. Switch 12 is a third switch that receives a signal from switch 10 and is controlled by clock signal S4. Switch 13 is a fourth switch that receives a signal from switch 10 and is controlled by clock signal S2.

[0015] The differential switch 6 is a third differential switch composed of a switch 14 and a switch 15 connected to the switch 11 constituting the differential switch 4. The switch 14 is a fifth switch that receives a signal from the switch 11 and is controlled by a clock signal S2. The switch 15 is a sixth switch that receives a signal from the switch 11 and is controlled by a clock signal S4.

[0016] Differential switch 7 is a fourth differential switch composed of switch 16 connected to switch 12 constituting differential switch 5, and switch 17 connected to switch 13 constituting differential switch 5. Switch 16 is a seventh switch that receives a signal from switch 12 and is controlled by clock signal S3. Switch 17 is an eighth switch that receives a signal from switch 13 and is controlled by clock signal S1.

[0017] Differential switch 8 is a fifth differential switch composed of switch 18 connected to switch 14 constituting differential switch 6, and switch 19 connected to switch 15 constituting differential switch 6. Switch 18 is a ninth switch that receives a signal from switch 14 and is controlled by clock signal S1. Switch 19 is a tenth switch that receives a signal from switch 15 and is controlled by clock signal S3.

[0018] Differential switch 9 is a sixth differential switch composed of switch 20 connected to switch 16 and switch 17 constituting differential switch 7, and switch 21 connected to switch 18 and switch 19 constituting differential switch 8. Switch 20 is an eleventh switch that receives a signal from either or both of switch 16 and switch 17 and is controlled by clock signal S4. Switch 21 is a twelfth switch that receives a signal from either or both of switch 18 and switch 19 and is controlled by clock signal S2. The output signal output from output terminal 2B is a signal obtained by combining the outputs of switch 20 and switch 21.

[0019] Capacitors 22 to 25 are a plurality of capacitors each having one end connected to a junction between the differential switches and the other end grounded. Capacitor 22 is a first capacitor having one end connected to a junction between switch 12 of differential switch 5 and switch 16 of differential switch 7 and the other end grounded. Capacitor 23 is a second capacitor having one end connected to a junction between switch 13 of differential switch 5 and switch 17 of differential switch 7 and the other end grounded. Capacitor 24 is a third capacitor having one end connected to a junction between switch 14 of differential switch 6 and switch 18 of differential switch 8 and the other end grounded. Capacitor 25 is a fourth capacitor having one end connected to a junction between switch 15 of differential switch 6 and switch 19 of differential switch 8 and the other end grounded.

[0020] 3 is a waveform diagram showing the waveforms of clock signals S1, S2, S3 and S4 in the band-pass filter 1. The upper left and right diagrams in FIG. ＬＯ The waveforms of the four-phase clock signals S1, S2, S3 and S4 are shown in the figure. ＬＯ The diagram on the bottom left of Fig. 3 shows the waveform of the clock signal when the band-pass filter 1 down-converts. The diagram on the bottom right of Fig. 3 shows the waveform of the clock signal when the band-pass filter 1 up-converts.

[0021] In the lower left and right diagrams of Fig. 3, the time when clock signals S1 and S4 are on (high level) is defined as interval (1) shown in the lower left and right diagrams of Fig. 3. In the lower left and right diagrams of Fig. 3, the time when clock signals S1 and S2 are on is defined as interval (2) shown in the lower left and right diagrams of Fig. 3. In the lower left and right diagrams of Fig. 3, the time when clock signals S2 and S3 are on is defined as interval (3) shown in the lower left and right diagrams of Fig. 3. In the upper left and right diagrams of Fig. 3, the time when clock signals S3 and S4 are on is defined as interval (4) shown in the lower left and right diagrams of Fig. 3.

[0022] 3, in the band-pass filter 1, the switch 10 is turned on by the clock signal S1 only in the section (1), and the switch 12 is turned on by the clock signal S4 only in the section (1). At this time, the signal input from the input terminal 2A is down-converted at the clock frequency, and the voltage of the signal is charged to the capacitor 22.

[0023] 3, in the band-pass filter 1, the switch 16 is turned on by the clock signal S3 only in the section (4), and the switch 20 is turned on by the clock signal S4 only in the section (4). At this time, the signal charged in the section (1) is up-converted.

[0024] Similarly, in the band-pass filter 1, the switch 10 is turned on by the clock signal S1 only in the section (2), and the switch 13 is turned on by the clock signal S2 only in the section (2). At this time, the signal input from the input terminal 2A is down-converted at the clock frequency, and the voltage of the signal is charged to the capacitor 23.

[0025] 3, in the band-pass filter 1, the switch 17 is turned on by the clock signal S1 only in the section (1), and the switch 20 is turned on by the clock signal S4 only in the section (1). At this time, the signal charged in the section (2) is up-converted.

[0026] Similarly, in the band-pass filter 1, the switch 11 is turned on by the clock signal S3 only in the section (3), and the switch 14 is turned on by the clock signal S2 only in the section (3). At this time, the signal input from the input terminal 2A is down-converted at the clock frequency, and the voltage of the signal is charged to the capacitor 24.

[0027] 3, in the band-pass filter 1, the switch 18 is turned on by the clock signal S1 only in the section (2), and the switch 21 is turned on by the clock signal S2 only in the section (2). At this time, the signal charged in the section (3) is up-converted.

[0028] Similarly, in the band-pass filter 1, the switch 11 is turned on by the clock signal S3 only in the section (4), and the switch 15 is turned on by the clock signal S4 only in the section (4). At this time, the signal input from the input terminal 2A is down-converted at the clock frequency, and the voltage of the signal is charged to the capacitor 25.

[0029] 3, in the band-pass filter 1, the switch 19 is turned on by the clock signal S3 only in the section (3), and the switch 21 is turned on by the clock signal S2 only in the section (3). At this time, the signal charged in the section (4) is up-converted.

[0030] In band-pass filter 1, the up-converted signals are added together at specified timings by performing an operation in the signal path that charges each of capacitors 22, 23, 24, and 25 with a signal voltage, and the added signal is output from output terminal 2B. This operation generates a four-phase clock signal by taking the logical product of clock signals with a 50% duty cycle and phase differences of 90 degrees each, thereby achieving narrow-band band-pass filter characteristics centered on the clock signal frequency. However, because the signals down-converted in sections (1), (2), (3), and (4) are output in sections (4), (1), (2), and (3), respectively, the phase of the output signal lags 270 degrees behind the input signal.

[0031] Note that the switch drive timing described above may be different as long as the phase difference of the clock signals is consistent between the down-conversion and up-conversion sections in all signal paths, and the number of switches driven by each clock signal is consistent. For example, in band-pass filter 1, the phase difference of the clock signals is 180 degrees between the down-conversion in section (1) and the up-conversion in section (4). The number of switches driven by the clock signal is two, switches 10 and 12, for the down-conversion in section (1), and two, switches 16 and 20, for the up-conversion in section (4), so the number of switches driven in these sections is consistent. Note that if the number of switches driven by each clock signal does not match, differences in the degree of dullness of the clock waveform will occur, degrading high-frequency characteristics.

[0032] In band-pass filter 1, each differential switch is composed of two switches, and capacitors 22 to 25 that charge the signal voltage during down-conversion are connected to the junctions between the differential switches. As a result, the number of switches driven by clock signals of each phase in band-pass filter 1 is reduced by one compared to the band-pass filter described in Non-Patent Document 1. In other words, by reducing the number of switches by one as viewed from clock signal source 3, band-pass filter 1 is able to reduce the parasitic capacitance derived from the switches by 25%, improving the frequency at which the clock waveform becomes dull, and enabling high-frequency operation.

[0033] As described above, the band-pass filter 1 according to the first embodiment includes an input terminal 2A to which a high-frequency signal is input, an output terminal 2B to which an output signal is output, differential switches 4-9 arranged between the input terminal 2A and the output terminal 2B, each consisting of two switches, and multiple switches 10-21 connected in a tournament configuration and controlled by a clock signal, and capacitors 22-25 having one end connected to a junction between the differential switches and the other end grounded. This reduces the number of switches driven by clock signals for each phase in the band-pass filter 1 by one, compared to the band-pass filter described in Non-Patent Document 1. In other words, because the number of switches as viewed from the clock signal source 3 is reduced by one, the band-pass filter 1 can suppress distortion of the clock signal caused by the switches used to switch signal paths.

[0034] The band-pass filter 1 according to the first embodiment is controlled by clock signals S1, S2, S3, and S4, which are, for example, 90-degree phase-shifted and have a duty ratio of 50%. The band-pass filter 1 includes a differential switch 4 having switches 10 and 11 connected to an input terminal 2A, where switch 10 is controlled by the clock signal S1 and switch 11 is controlled by the clock signal S3, a differential switch 5 having switches 12 and 13 connected to switch 10, where switch 12 is controlled by the clock signal S4 and switch 13 is controlled by the clock signal S2, a differential switch 6 having switches 14 and 15 connected to switch 11, where switch 14 is controlled by the clock signal S2 and switch 15 is controlled by the clock signal S4, a differential switch 7 having switch 16 connected to switch 12 and controlled by the clock signal S3, and switch 17 connected to switch 13 and controlled by the clock signal S1, and a differential switch 18 connected to switch 14 and controlled by the clock signal S1. and a switch 19 connected to switch 15 and controlled by a clock signal S3, a capacitor 22 having one end connected to the junction of switch 12 and switch 16 and the other end grounded, a capacitor 23 having one end connected to the junction of switch 13 and switch 17 and the other end grounded, a capacitor 24 having one end connected to the junction of switch 14 and switch 18 and the other end grounded, a capacitor 25 having one end connected to the junction of switch 15 and switch 19 and the other end grounded, a differential switch 9 having a switch 20 connected to switch 16 and switch 17 and controlled by a clock signal S4, and a switch 21 connected to switch 18 and switch 19 and controlled by a clock signal S2. The output signal output from output terminal 2B is a signal obtained by combining the outputs of switch 20 and switch 21. This configuration allows the number of switches seen from the clock signal source 3 to be reduced by one, so that the band-pass filter 1 can suppress distortion of the clock signal caused by the switches for switching the signal path.

[0035] Second Embodiment. Fig. 4 is a circuit diagram showing an example configuration of a band-pass filter 1A according to a second embodiment. In Fig. 4, the band-pass filter 1A is a filter known as an N-path filter, which can suppress deterioration in the attenuation of unwanted waves and suppress attenuation of the gain of a desired wave. The band-pass filter 1A is a filter controlled by clock signals S1, S2, S3, and S4 generated by the clock signal source 3 shown in Fig. 2, and includes an input terminal 2A, an output terminal 2B, differential switches 4, 5A, 6A, 7A, 8A, and 9, and capacitors 22 to 25.

[0036] The clock period is T ＬＯ In this case, the clock signal source 3 generates four clock signals S1, S2, S3, and S4, each with a duty ratio of 50% and a phase delay of 90 degrees, as in FIG. 1 . Clock signal S1 is a first clock signal with a phase of 0 degrees. Clock signal S2 is a second clock signal with a phase of 90 degrees. Clock signal S3 is a third clock signal with a phase of 180 degrees. Clock signal S4 is a fourth clock signal with a phase of 270 degrees. The clock signal source 3 may also be configured with a differential amplifier circuit. Note that as long as the band-pass filter operates as a desired filter, the duty ratio does not have to be 50%, and other periodic waveforms, such as a sine wave, may be used.

[0037] Differential switches 4, 5A, 6A, 7A, 8A, and 9 are provided between input terminal 2A and output terminal 2B, and are configured by a plurality of switches connected in a tournament configuration, each controlled by a clock signal generated by clock signal source 3. Each differential switch is composed of two switches. For example, each switch in one differential switch is controlled by two clock signals that are 180 degrees out of phase with each other. Each switch outputs a signal when the clock signal is at a high level.

[0038] Similar to the band-pass filter 1, the differential switch 4 is a first differential switch composed of a switch 10 and a switch 11 connected to the input terminal 2A. The switch 10 is a first switch that receives one of the two split signals from the input terminal 2A and is controlled by a clock signal S1. The switch 11 is a second switch that receives the other of the two split signals from the input terminal 2A and is controlled by a clock signal S3.

[0039] Differential switch 5A is a second differential switch composed of switch 12A and switch 13A connected to switch 10 constituting differential switch 4. Switch 12A is a third switch that receives a signal from switch 10 and is controlled by clock signal S4. Switch 13A is a fourth switch that receives a signal from switch 10 and is controlled by clock signal S2.

[0040] Differential switch 6A is a third differential switch composed of switch 14A and switch 15A connected to switch 11 constituting differential switch 4. Switch 14A is a fifth switch that receives a signal from switch 11 and is controlled by clock signal S4. Switch 15A is a sixth switch that receives a signal from switch 11 and is controlled by clock signal S2.

[0041] The differential switch 7A is a fourth differential switch composed of a switch 16A connected to the switch 12A constituting the differential switch 5A and a switch 17A connected to the switch 14A constituting the differential switch 6A. The switch 16A is a seventh switch that receives an input of a signal from the switch 12A and is controlled by the clock signal S1. The switch 17A is an eighth switch that receives an input of a signal from the switch 14A and is controlled by the clock signal S3.

[0042] The differential switch 8A is a fifth differential switch composed of a switch 18A connected to the switch 13A constituting the differential switch 5A and a switch 19A connected to the switch 15A constituting the differential switch 6A. The switch 18A is a ninth switch that receives an input of a signal from the switch 13A and is controlled by the clock signal S1. The switch 19A is a tenth switch that receives an input of a signal from the switch 15A and is controlled by the clock signal S3.

[0043] Differential switch 9 is a sixth differential switch composed of switch 20 connected to switches 16A and 17A constituting differential switch 7A, and switch 21 connected to switches 18A and 19A constituting differential switch 8A. Switch 20 is an eleventh switch that receives a signal from either or both of switches 16A and 17A and is controlled by clock signal S4. Switch 21 is a twelfth switch that receives a signal from either or both of switches 18A and 19A and is controlled by clock signal S2. The output signal output from output terminal 2B is a signal obtained by combining the outputs of switches 20 and 21.

[0044] Capacitors 22A, 23A, 24A, and 25A are multiple capacitors having one end connected to the junction between the differential switches and the other end grounded. Capacitor 22A is a first capacitor having one end connected to the junction between switch 12A of differential switch 5A and switch 16A of differential switch 7A and the other end grounded. Capacitor 23A is a second capacitor having one end connected to the junction between switch 13A of differential switch 5A and switch 18A of differential switch 8A and the other end grounded. Capacitor 24A is a third capacitor having one end connected to the junction between switch 14A of differential switch 6A and switch 17A of differential switch 7A and the other end grounded. Capacitor 25A is a fourth capacitor having one end connected to the junction between switch 15A of differential switch 6A and switch 19A of differential switch 8A and the other end grounded.

[0045] 5 is a waveform diagram showing the waveforms of clock signals S1, S2, S3 and S4 in the band-pass filter 1A. The upper left and right diagrams in FIG. 5 show the waveforms of clock signals S1, S2, S3 and S4 from the clock signal source 3 with a period T ＬＯ The waveforms of the four-phase clock signals S1, S2, S3 and S4 are shown in the figure. ＬＯ The signal is shifted by 1 / 4. The diagram on the bottom left of Fig. 5 shows the waveform of the clock signal when the band-pass filter 1A down-converts. The diagram on the bottom right of Fig. 5 shows the waveform of the clock signal when the band-pass filter 1A up-converts.

[0046] In the lower left and right diagrams of Fig. 5, the time when clock signals S1 and S4 are on (high level) is defined as interval (1) shown in the lower left and right diagrams of Fig. 5. In the lower left and right diagrams of Fig. 5, the time when clock signals S1 and S2 are on is defined as interval (2) shown in the lower left and right diagrams of Fig. 5. In the lower left and right diagrams of Fig. 5, the time when clock signals S2 and S3 are on is defined as interval (3) shown in the lower left and upper right diagrams of Fig. 5. In the lower left and right diagrams of Fig. 5, the time when clock signals S3 and S4 are on is defined as interval (4) shown in the lower left and right diagrams of Fig. 5.

[0047] 5, in band-pass filter 1A, switch 10 is turned on by clock signal S1 only in section (1), and switch 12A is turned on by clock signal S4 only in section (1). At this time, the signal input from input terminal 2A is down-converted at the clock frequency, and the signal voltage is charged to capacitor 22A.

[0048] 5, in the band-pass filter 1A, the switch 16A is turned on by the clock signal S1 only in the section (1), and the switch 20 is turned on by the clock signal S4 only in the section (1). At this time, the signal charged in the section (1) is up-converted.

[0049] Similarly, in band-pass filter 1A, switch 10 is turned on by clock signal S1 only during section (2), and switch 13A is turned on by clock signal S2 only during section (2). At this time, the signal input from input terminal 2A is down-converted at the clock frequency, and the signal voltage is charged to capacitor 23A.

[0050] 5, in the band-pass filter 1A, the switch 18A is turned on by the clock signal S1 only in the section (2), and the switch 21 is turned on by the clock signal S2 only in the section (2). At this time, the signal charged in the section (2) is up-converted.

[0051] Similarly, in band-pass filter 1A, switch 11 is turned on by clock signal S3 only during section (4), and switch 14A is turned on by clock signal S4 only during section (4). At this time, the signal input from input terminal 2A is down-converted at the clock frequency, and the signal voltage is charged to capacitor 24A.

[0052] 5, in the band-pass filter 1A, switch 17A is turned on by clock signal S3 only in section (4), and switch 20 is turned on by clock signal S4 only in section (4). At this time, the signal charged in section (4) is up-converted.

[0053] Similarly, in band-pass filter 1A, switch 11 is turned on by clock signal S3 only during section (3), and switch 15A is turned on by clock signal S2 only during section (3). At this time, the signal input from input terminal 2A is down-converted at the clock frequency, and the signal voltage is charged to capacitor 25A.

[0054] 5, in the band-pass filter 1A, the switch 19A is turned on by the clock signal S3 only in the section (3), and the switch 21 is turned on by the clock signal S2 only in the section (3). At this time, the signal charged in the section (3) is up-converted.

[0055] Band-pass filter 1A performs a signal path operation that charges each of capacitors 22A, 23A, 24A, and 25A with a signal voltage at a specified timing, thereby adding up-converted signals and outputting the added signal from output terminal 2B. This operation generates a four-phase clock signal by performing a logical AND of clock signals with a 50% duty cycle and phase differences of 90 degrees each, thereby achieving narrow-band band-pass filter characteristics centered on the clock signal frequency. However, because the down-converted signals in sections (1), (2), (3), and (4) are output in sections (1), (2), (3), and (4), respectively, unwanted phase rotation can be suppressed, unlike band-pass filter 1.

[0056] Note that the switch drive timing described above may be different as long as the phase difference of the clock signals is consistent between the downconversion and upconversion sections in all signal paths, and the number of switches driven by each clock signal is consistent. For example, in bandpass filter 1A, the phase difference of the clock signals is 180 degrees between the downconversion in section (1) and the upconversion in section (1). The number of switches driven by the clock signal is two, switches 10 and 12A, for the downconversion in section (1), and two, switches 16A and 20A, for the upconversion in section (1), so the number of switches driven in these sections is consistent. Note that if the number of switches driven by each clock signal does not match, differences in the degree of dullness of the clock waveform will occur, degrading high-frequency characteristics.

[0057] In the band-pass filter 1A, each differential switch is composed of two switches, and capacitors 22A, 23A, 24A, and 25A that charge the signal voltage during down-conversion are connected to the junctions between the differential switches. As a result, the number of switches driven by clock signals of each phase in the band-pass filter 1A is reduced by one compared to the band-pass filter described in Non-Patent Document 1. In other words, by reducing the number of switches as viewed from the clock signal source 3, the band-pass filter 1A reduces the parasitic capacitance derived from the switches by 25%, improving the frequency at which the clock waveform becomes dull, and enabling high-frequency operation.

[0058] As described above, the band-pass filter 1A according to the second embodiment is controlled by the clock signals S1, S2, S3, and S4, which are sequentially different in phase by 90 degrees and have a duty ratio of 50%, for example. a differential switch 4 having switches 10 and 11 connected to input terminal 2A, where switch 11 is controlled by a clock signal S1 and switch 11 is controlled by a clock signal S3; a differential switch 5A having switches 12A and 13A connected to switch 10, where switch 12A is controlled by a clock signal S4 and switch 13A is controlled by a clock signal S2; a differential switch 6A having switches 14A and 15A connected to switch 11, where switch 14A is controlled by the clock signal S2 and switch 15A is controlled by the clock signal S4; a differential switch 7A having switch 16A connected to switch 12A and controlled by the clock signal S1 and switch 17A connected to switch 14A and controlled by the clock signal S3; and a switch 18A connected to switch 13A and controlled by the clock signal S1. The differential switch 9 includes a differential switch 8A having a switch 19A connected to the switch 15A and controlled by a clock signal S3, a capacitor 22A having one end connected to the junction of the switch 12A and the switch 16A and the other end grounded, a capacitor 23A having one end connected to the junction of the switch 13A and the switch 18A and the other end grounded, a capacitor 24A having one end connected to the junction of the switch 14A and the switch 17A and the other end grounded, a capacitor 25A having one end connected to the junction of the switch 15A and the switch 19A and the other end grounded, a differential switch 9 having a switch 20 connected to the switch 16A and the switch 17A and controlled by a clock signal S4, and a switch 21 connected to the switch 18A and the switch 19A and controlled by a clock signal S2. The output signal output from the output terminal 2B is a signal obtained by combining the outputs of the switch 20 and the switch 21. This configuration allows the number of switches seen from the clock signal source 3 to be reduced by one, so the band-pass filter 1A can suppress distortion of the clock signal caused by the switches for switching the signal path.

[0059] It is possible to combine the embodiments, modify any of the components of the embodiments, or omit any of the components of the embodiments.

[0060] The bandpass filter according to the present disclosure can be used in a variety of wireless communications.

[0061] 1, 1A band-pass filter, 2A input terminal, 2B output terminal, 3 clock signal source, 4, 5, 5A, 6, 6A, 7, 7A, 8, 8A, 9 differential switch, 10, 11, 12, 12A, 13, 13A, 14, 14A, 15, 15A, 16, 16A, 17, 17A, 18, 18A, 19, 19A, 20, 21 switch, 22, 22A, 23, 23A, 23A, 24, 24A, 25, 25A capacitor.

Claims

1. A bandpass filter comprising: an input terminal to which a high frequency signal is input; an output terminal to which an output signal is output; a plurality of differential switches, each consisting of two switches, connected in a tournament configuration and controlled by a clock signal, provided between the input terminal and the output terminal; and a plurality of capacitors, one end of which is connected to a connection point between the differential switches and the other end of which is grounded.

2. The plurality of differential switches are: a first differential switch having a first switch and a second switch connected to the input terminal; a second differential switch having a third switch and a fourth switch connected to the first switch; a third differential switch having a fifth switch and a sixth switch connected to the second switch; a fourth differential switch having a seventh switch connected to the third switch and an eighth switch connected to the fourth switch; a fifth differential switch having a ninth switch connected to the fifth switch and a tenth switch connected to the sixth switch; and a sixth differential switch having an eleventh switch connected to the seventh switch and the eighth switch and a twelfth switch connected to the ninth switch and the tenth switch; and the plurality of capacitors are: a first capacitor having one end connected to a connection point between the third switch and the seventh switch and the other end grounded; a second capacitor having one end connected to a connection point between the fourth switch and the eighth switch and the other end grounded; 2. The band-pass filter according to claim 1, further comprising: a third capacitor having one end connected to a connection point between the fifth switch and the ninth switch and the other end grounded; and a fourth capacitor having one end connected to a connection point between the sixth switch and the tenth switch and the other end grounded, wherein a signal obtained by combining the outputs of the eleventh switch and the twelfth switch is output from the output terminal.

3. The plurality of differential switches are: a first differential switch having a first switch and a second switch connected to the input terminal; a second differential switch having a third switch and a fourth switch connected to the first switch; a third differential switch having a fifth switch and a sixth switch connected to the second switch; a fourth differential switch having a seventh switch connected to the third switch and an eighth switch connected to the fifth switch; a fifth differential switch having a ninth switch connected to the fourth switch and a tenth switch connected to the sixth switch; and a sixth differential switch having an eleventh switch connected to the seventh switch and the eighth switch and a twelfth switch connected to the ninth switch and the tenth switch; and the plurality of capacitors are: a first capacitor having one end connected to a connection point between the third switch and the seventh switch and the other end grounded; a second capacitor having one end connected to a connection point between the fourth switch and the ninth switch and the other end grounded; 2. The band-pass filter according to claim 1, further comprising: a third capacitor having one end connected to a connection point between the fifth switch and the eighth switch and the other end grounded; and a fourth capacitor having one end connected to a connection point between the sixth switch and the tenth switch and the other end grounded, wherein a signal obtained by combining the outputs of the eleventh switch and the twelfth switch is output from the output terminal.

4. A band-pass filter according to any one of claims 1 to 3, characterized in that the clock signals have phases that differ by 90 degrees in succession and a duty ratio of 50%.

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