Low-output-ripple ultralow-offset-voltage operational amplifier and working method thereof

Abstract

The invention discloses a low-output-ripple ultralow-offset-voltage operational amplifier and a working method thereof. The low-output-ripple ultralow-offset-voltage operational amplifier comprises a first chopper circuit, a first-stage operational amplifier additionally provided with an offset voltage adjusting circuit, a second chopper circuit, a notch filter, a second-stage operational amplifier and a third-stage operational amplifier which are sequentially connected. The offset voltage adjusting circuit trims the input offset voltage of the first-stage operational amplifier to hundreds of microvolts and then outputs the offset voltage to the second chopper circuit; the first chopper circuit and the second chopper circuit are used for modulating the offset voltage of the first-stage operational amplifier to a chopping frequency, and then the ripple voltage at the chopping frequency is filtered by the notch filter; the first-stage operational amplifier is designed to be a high-gain amplifier so as to restrain input offset voltage errors caused by the second-stage operational amplifier and the third-stage operational amplifier. According to the invention, low output ripple voltage and ultralow input offset voltage can be realized only by using the wave trap with a small area.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier technology, specifically to a low-output-ripple, ultra-low-offset-voltage operational amplifier and its operating method. Background Technology

[0002] Operational amplifier input offset voltage and noise are critical parameters of concern to engineers. To minimize input offset voltage, a series of trimming methods have been developed, such as wafer-level fuse trim, wafer-level laser resistor trim, and post-packaging e-trim. In-process calibration or user-managed fine-tuning are obvious solutions for achieving low offset. However, even after offset trimming, CMOS amplifiers still exhibit offset voltage drift due to temperature and time variations. This offset voltage drift is a precision limitation, and engineers are using a new method to dynamically compensate for the offset voltage through additional on-chip dynamic adjustment modules. Because these techniques continuously compensate for the offset voltage during chip operation, slow changes in offset voltage are also compensated for, thus significantly reducing offset voltage variations over time and temperature. Typical methods include auto-zeroing and chopping techniques. Automatic zeroing technology achieves low offset voltage by storing and subtracting the amplifier's own offset. This requires ping-pong alternating operation, increasing chip noise and area. Furthermore, the alternating operation generates output ripple; the greater the offset voltage mismatch in the alternating amplifier, the larger the output ripple. Chopper technology modulates the input offset voltage to a high frequency, requiring a large notch filter to remove it; the larger the initial input offset voltage, the larger the output ripple. Therefore, compared to general-purpose operational amplifiers, precision amplifiers employing automatic zeroing and chopper technologies both suffer from large area and large ripple. Summary of the Invention

[0003] To address the issues of large area and high ripple associated with precision operational amplifiers employing automatic zeroing and chopping techniques, this invention designs a low-area, low-output-ripple, and ultra-low-input-off-voltage operational amplifier. This invention utilizes an input offset voltage adjustment circuit to reduce the amplifier's initial offset voltage to within the hundreds of µV range before chopping and notch filtering. Low output ripple voltage and ultra-low input offset voltage can be achieved using only a small notch filter.

[0004] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0005] In a first aspect, the present invention discloses a low-output ripple ultra-low offset voltage operational amplifier, wherein the low-output ripple ultra-low offset voltage operational amplifier comprises a first chopper circuit, a first-stage operational amplifier with an added offset voltage adjustment circuit, a second chopper circuit, a notch filter, a second-stage operational amplifier, and a third-stage operational amplifier connected in sequence.

[0006] The first-stage operational amplifier, the second-stage operational amplifier, and the third-stage operational amplifier constitute a three-stage high-gain operational amplifier. The offset voltage adjustment circuit adjusts the input offset voltage of the first-stage operational amplifier to several hundred microvolts before outputting it to the second chopper circuit. The first and second chopper circuits are used to modulate the offset voltage of the first-stage operational amplifier to the chopper frequency, and then the ripple voltage at the chopper frequency is filtered out by the notch filter. The first-stage amplifier is designed as a high-gain operational amplifier to suppress the input offset voltage error caused by the second-stage and third-stage operational amplifiers.

[0007] Furthermore, the first-stage operational amplifier with added offset voltage adjustment circuit is a folded common-source common-gate amplifier, including a first gain boost operational amplifier (GN), a second gain boost operational amplifier (GP), a first CMOS transistor (M1), a second CMOS transistor (M2), a third CMOS transistor (M3), a fourth CMOS transistor (M4), a fifth CMOS transistor (M5), a sixth CMOS transistor (M6), a seventh CMOS transistor (M7), an eighth CMOS transistor (M8), a ninth CMOS transistor (M9), a tenth CMOS transistor (M10), an eleventh CMOS transistor (M11), a twelfth CMOS transistor (M12), a thirteenth CMOS transistor (M13), a fourteenth CMOS transistor (M14), a fifteenth CMOS transistor (M15), a sixteenth CMOS transistor (M6), a first current source (I1), a second current source (I2), a third current source (I3), a fourth current source (I4), and a fifth current source (I5);

[0008] The sources of the first CMOS transistor (M1) and the second CMOS transistor (M2) are connected to the power supply voltage through the first current source (I1), the gates are connected to the positive and negative terminals of the input voltage Vin, respectively, and the drains are connected to the sources of the eighth CMOS transistor (M8) and the seventh CMOS transistor (M7), respectively; the second current source (I2) and the third current source (I3) are adjustable current sources, the input terminals of which are connected to the power supply voltage, and the output terminals of which are connected to the gates of the second CMOS transistor (M2) and the first CMOS transistor (M1), respectively;

[0009] The gates of the fifth CMOS transistor (M5) and the sixth CMOS transistor (M6) are interconnected, their sources are connected to the power supply voltage, and their drains are connected to the sources of the third CMOS transistor (M3) and the fourth CMOS transistor (M4), respectively. Their gates are connected to the third bias voltage Vb. The drains of the third CMOS transistor (M3) and the fourth CMOS transistor (M4) are connected to the drains of the seventh CMOS transistor (M7) and the eighth CMOS transistor (M8), respectively. The sources of the seventh CMOS transistor (M7) and the eighth CMOS transistor (M8) are connected to the drains of the ninth CMOS transistor (M9) and the tenth CMOS transistor (M10), respectively.

[0010] The sources of the thirteenth CMOS transistor (M13) and the fourteenth CMOS transistor (M14) are interconnected and connected to the power supply voltage through the fourth current source (I4). The drains of the thirteenth CMOS transistor (M13) and the fourteenth CMOS transistor (M14) are respectively connected to the drain of the twelfth CMOS transistor (M12) and the drain of the eleventh CMOS transistor (M11). The sources of the fifteenth CMOS transistor (M15) and the sixteenth CMOS transistor (M16) are interconnected and connected to the power supply voltage through the fifth current source (I5). The drain of transistor (M16) is connected to the drain of the eleventh CMOS transistor (M11) and the drain of the twelfth CMOS transistor (M12), respectively; the gate of the thirteenth CMOS transistor (M13) is connected to the drain of the fourth CMOS transistor (M4) and serves as the positive terminal of the output voltage Vout; the gates of the fourteenth CMOS transistor (M14) and the fifteenth CMOS transistor (M15) are interconnected and connected to the reference voltage VCM of the output common-mode voltage; the gate of the sixteenth CMOS transistor (M16) is connected to the drain of the third CMOS transistor (M3) and serves as the negative terminal of the output voltage Vout.

[0011] The gates of the ninth CMOS transistor (M9), the tenth CMOS transistor (M10), and the eleventh CMOS transistor (M11) are all connected to the drain of the eleventh CMOS transistor (M11); the gate of the twelfth CMOS transistor (M12) is connected to the drain of the twelfth CMOS transistor (M12); the sources of the ninth CMOS transistor (M9), the tenth CMOS transistor (M10), the eleventh CMOS transistor (M11), and the twelfth CMOS transistor (M12) are all grounded;

[0012] The input of the first gain boost operational amplifier (GN) is connected to a first bias voltage V1 to provide a DC bias point to the drains of the third CMOS transistor (M3), the fourth CMOS transistor (M4), the fifth CMOS transistor (M5), and the sixth CMOS transistor (M6); the input of the second gain boost operational amplifier (GP) is connected to a second bias voltage V2 to provide a DC bias point to the gates and sources of the seventh CMOS transistor (M7) and the eighth CMOS transistor (M8).

[0013] Furthermore, the second current source (I2) and the third current source (I3) have the same structure, including a fuse array, an adjustable current source, and a decoder;

[0014] The fuse array includes a thirteenth CMOS transistor (CM0), a fourteenth CMOS transistor (CM1), a fifteenth CMOS transistor (CM2), a sixteenth CMOS transistor (CM3), a first fuse, a second fuse, a third fuse, a fourth fuse, a first Schmitt trigger, a second Schmitt trigger, a third Schmitt trigger, and a fourth Schmitt trigger;

[0015] The gates of the thirteenth CMOS transistor (CM0), fourteenth CMOS transistor (CM1), fifteenth CMOS transistor (CM2), and sixteenth CMOS transistor (CM3) are all connected to the bias voltage VBIAS, and the sources of the thirteenth CMOS transistor (CM0), fourteenth CMOS transistor (CM1), fifteenth CMOS transistor (CM2), and sixteenth CMOS transistor (CM3) are all connected to the power supply voltage; the gates of the thirteenth CMOS transistor (CM0), fourteenth CMOS transistor (CM1), fifteenth CMOS transistor (CM2), and sixteenth CMOS transistor (CM3) are grounded through the first fuse, second fuse, third fuse, and fourth fuse, respectively; the first signal terminal (B0), second signal terminal (B1), third signal terminal (B2), and fourth signal terminal (B3) are connected to the ends of the first fuse, second fuse, third fuse, and fourth fuse away from ground through the first Schmitt trigger, second Schmitt trigger, third Schmitt trigger, and fourth Schmitt trigger, respectively.

[0016] The decoder receives signals generated by the second signal terminal (B1), the third signal terminal (B2), and the fourth signal terminal (B3), compiles and generates 6 signals, and outputs them to the fifth signal terminal (A1), the sixth signal terminal (A2), the seventh signal terminal (A3), the eighth signal terminal (A4), the ninth signal terminal (A5), and the tenth signal terminal (A6), respectively.

[0017] The adjustable current source includes a test PAD, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fifth current mirror, a sixth current mirror, a first switch (CM4), a second switch (CM5), a third switch (CM6), a fourth switch (CM7), a fifth switch (CM8), a sixth switch (CM9), a seventeenth CMOS transistor, an eighteenth CMOS transistor, an inverter, and an AND gate.

[0018] The first current mirror, the second current mirror, the third current mirror, the fourth current mirror, the fifth current mirror, and the sixth current mirror are connected in parallel. Their input terminals are all connected to the power supply voltage, and their output terminals are connected to the drains of the seventeenth CMOS transistor and the eighteenth CMOS transistor through the first switch (CM4), the second switch (CM5), the third switch (CM6), the fourth switch (CM7), the fifth switch (CM8), and the sixth switch (CM9), respectively.

[0019] The test PAD and the tenth signal terminal (A6) are respectively connected to the two input terminals of the AND gate, and the output terminal of the AND gate is connected to the sixth switch (CM9) to control the on / off state of the sixth current mirror; the fifth signal terminal (A1), the sixth signal terminal (A2), the seventh signal terminal (A3), the eighth signal terminal (A4), and the ninth signal terminal (A5) are respectively connected to the first switch (CM4), the second switch (CM5), the third switch (CM6), the fourth switch (CM7), the fifth switch (CM8), and the sixth switch (CM9) to control their on / off state;

[0020] The first signal terminal (B0) is directly connected to the gate of the seventeenth CMOS transistor (CM10) on one hand, and connected to the gate of the eighteenth CMOS transistor (CM11) through an inverter on the other hand; the sources of the seventeenth CMOS transistor (CM10) and the eighteenth CMOS transistor (CM11) serve as the offset voltage increase terminal and the offset voltage decrease terminal, respectively.

[0021] Secondly, the present invention discloses a method for operating a low-output-ripple, ultra-low-offset-voltage operational amplifier based on the aforementioned method, the method comprising the following steps:

[0022] The control oscillator generates a set of clock signals with a fixed frequency, including the control signal ФC1 of the first chopper circuit, the control signal ФC2 of the second chopper circuit, and the control signals Ф1 and Ф2 of the notch filter;

[0023] Add a control switch signal test to the first chopper circuit, the second chopper circuit, and the notch filter. Set the control switch signal test to 0 to turn off the first chopper circuit, the second chopper circuit, and the notch filter, so that the first-stage operational amplifier enters the adjustment mode. Test the magnitude of the offset voltage and record it as V0S0.

[0024] Set the test PAD to 0, test the magnitude of the offset voltage, and record it as V0S1;

[0025] The adjustment MSB is obtained by calculating the difference between V0S0 and V0S1. The adjustment LSB is calculated from the adjustment MSB. The fuse code required for adjustment is obtained from V0S0 / LSB.

[0026] The corresponding fuse is adjusted by laser according to the fuse adjustment code to obtain the bare die of the arithmetic amplifier with an offset voltage of several hundred microvolts;

[0027] The arithmetic unit amplifier die is packaged so that the test and offset voltage pre-adjustment test PADs are not visible from the outside;

[0028] When the chip is powered on, the offset voltage of several hundred microvolts is attenuated to low output ripple and ultra-low offset voltage through chopping and notch filtering.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] The low-output ripple ultra-low offset voltage operational amplifier and its operating method of the present invention employ an input offset voltage adjustment circuit to reduce the initial offset voltage of the amplifier to within the hundreds of μV range, and then perform chopping and notch filtering. Low output ripple voltage and ultra-low input offset voltage can be achieved using only a small notch filter. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall structure of a traditional operational amplifier;

[0032] Figure 2 The diagram shows the structure and timing of a notch filter, with the left diagram being the structure diagram and the right diagram being the timing diagram.

[0033] Figure 3 The block diagram of the first-stage operational amplifier with added offset voltage adjustment circuitry;

[0034] Figure 4 Diagram of an adjustable current source;

[0035] Figure 5 This is a diagram of a fuse array structure;

[0036] Figure 6 The diagram shows the switching structure of the first chopper circuit (left) and the circuit diagram for generating the switching control signal (right).

[0037] Figure 7 The diagram shows the structure of the second chopper circuit and the notch filter (left), as well as the corresponding circuit diagram for generating the switching control signal (right).

[0038] Figure 8This is a flowchart illustrating the operation method of the low-output ripple ultra-low offset voltage operational amplifier of the present invention.

[0039] Figure 9 The left image shows the output waveform of the chopper amplifier under existing technology, while the right image shows the output waveform of the amplifier proposed in this invention. Detailed Implementation

[0040] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0041] This invention discloses a low-output-ripple, ultra-low-offset-voltage operational amplifier.

[0042] The low-output ripple ultra-low offset voltage operational amplifier includes a first chopper circuit, a first-stage operational amplifier with an added offset voltage adjustment circuit, a second chopper circuit, a notch filter, a second-stage operational amplifier, and a third-stage operational amplifier connected in sequence.

[0043] The first-stage operational amplifier, the second-stage operational amplifier, and the third-stage operational amplifier constitute a three-stage high-gain operational amplifier. The offset voltage adjustment circuit adjusts the input offset voltage of the first-stage operational amplifier to several hundred microvolts before outputting it to the second chopper circuit. The first and second chopper circuits are used to modulate the offset voltage of the first-stage operational amplifier to the chopper frequency, and then the ripple voltage at the chopper frequency is filtered out by the notch filter. The first-stage amplifier is designed as a high-gain operational amplifier to suppress the input offset voltage error caused by the second-stage and third-stage operational amplifiers.

[0044] See Figure 1The operational amplifier used in this invention is a three-stage chopper operational amplifier. This operational amplifier topology can be viewed as a three-stage high-gain operational amplifier composed of GM1, GM2, and GM3. Its DC accuracy is determined by the high-gain path containing the input stage GM1. The three-stage high-gain amplifier effectively reduces amplifier offset voltage, offset voltage drift, and noise by employing a chopping method. Chopping only modulates the offset voltage of the input stage GM1 to the chopping frequency; a notch filter of a specific frequency is then used to filter out the ripple voltage at the chopping frequency, thus ensuring that no large ripple voltage appears at the output. This also avoids the drawback of traditional methods that use low-pass filters to filter out high-frequency signals along with the output. However, the larger the initial input offset voltage, the higher the requirements for the notch filter in order to obtain better DC performance. When the circuit is working normally, the oscillator generates a set of clock signals with a fixed frequency. Among them, ФC1 and ФC2 are the control signals of CHOP1 and CHOP2, and Ф1 and Ф2 are the control signals of the notch filter. The timing is shown in the figure above (ФC1 and ФC2 are control signals with opposite phases generated by the oscillator, and Ф1 and Ф2 are a set of notch filter control signals with opposite phases. Ф1 and Ф2 are one-quarter of a cycle different from ФC1 and ФC2 respectively. Ф1 controls the turn-off and turn-on of switches S5, S6, S11, and S12, and Ф2 controls switches S7, S8, S9, and S10). The larger the sample-and-hold capacitors used by the notch filter (CS1 and CS2 are the sampling capacitors, and Ch is the holding capacitor), the lower its AC characteristics will be, resulting in a longer power-on settling time and overload recovery time. Therefore, this invention adds an offset voltage adjustment circuit to first adjust the amplifier input offset voltage to a small value, about 100 μV, and then performs chopping and notch filtering. Low output ripple voltage and ultra-low input offset voltage can be achieved by using only a small notch filter.

[0045] To ensure DC accuracy meets design requirements, the open-loop gains Av1 of GM1 and Av2 of GM2 need to be sufficiently large. However, considering that the offset ripple caused by non-ideal switching and related timing factors in the notch filter is typically amplified by GM2, GM1 is designed as a high-gain input stage op-amp. High-gain op-amps are typically implemented as sleeve op-amps, folded cascode op-amps, and gain-boosted folded cascode op-amps. Sleeve op-amps and multilayer folded cascode op-amps are simple in structure and can achieve higher gains, but they consume too much voltage margin, limiting the output swing; therefore, these methods are not chosen here. Folded cascode amplifiers using gain-boosting technology increase gain without affecting the output swing; therefore, this invention selects a folded cascode amplifier using gain-boosting technology as the high-gain input stage op-amp. Figure 3As shown, the first-stage operational amplifier with added offset voltage adjustment circuit is a folded common-source common-gate amplifier, including a first gain boost operational amplifier, a second gain boost operational amplifier, a first CMOS transistor M1, a second CMOS transistor M2, a third CMOS transistor M3, a fourth CMOS transistor M4, a fifth CMOS transistor M5, a sixth CMOS transistor M6, a seventh CMOS transistor M7, an eighth CMOS transistor M8, a ninth CMOS transistor M9, a tenth CMOS transistor M10, an eleventh CMOS transistor M11, a twelfth CMOS transistor M12, a thirteenth CMOS transistor M13, a fourteenth CMOS transistor M14, a fifteenth CMOS transistor M15, a sixteenth CMOS transistor M16, a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, and a fifth current source I5;

[0046] The sources of the first CMOS transistor M1 and the second CMOS transistor M2 are connected to the power supply voltage through the first current source I1, and their gates are connected to the positive and negative terminals of the input voltage Vin, respectively. Their drains are connected to the sources of the eighth CMOS transistor M8 and the seventh CMOS transistor M7, respectively. The second current source I2 and the third current source I3 are adjustable current sources. Their input terminals are connected to the power supply voltage, and their output terminals are connected to the gates of the second CMOS transistor M2 and the first CMOS transistor M1, respectively.

[0047] The gates of the fifth CMOS transistor M5 and the sixth CMOS transistor M6 are interconnected, their sources are connected to the power supply voltage, and their drains are connected to the sources of the third CMOS transistor M3 and the fourth CMOS transistor M4, respectively. Their gates are connected to the third bias voltage Vb. The drains of the third CMOS transistor M3 and the fourth CMOS transistor M4 are connected to the drains of the seventh CMOS transistor M7 and the eighth CMOS transistor M8, respectively. The sources of the seventh CMOS transistor M7 and the eighth CMOS transistor M8 are connected to the drains of the ninth CMOS transistor M9 and the tenth CMOS transistor M0, respectively.

[0048] The sources of the thirteenth CMOS transistor M13 and the fourteenth CMOS transistor M4 are interconnected and connected to the power supply voltage through the fourth current source I4. The drains of the thirteenth CMOS transistor M13 and the fourteenth CMOS transistor M14 are connected to the drains of the twelfth CMOS transistor M12 and the eleventh CMOS transistor M11, respectively. The sources of the fifteenth CMOS transistor M15 and the sixteenth CMOS transistor M16 are interconnected and connected to the power supply voltage through the fifth current source I5. The drains of the fifteenth CMOS transistor M15 and the sixteenth CMOS transistor M16 are connected to the drains of the eleventh CMOS transistor M11 and the twelfth CMOS transistor M12, respectively. The gate of the thirteenth CMOS transistor M13 is connected to the drain of the fourth CMOS transistor M4 and serves as the positive terminal of the output voltage Vout. The gates of the fourteenth CMOS transistor M14 and the fifteenth CMOS transistor M15 are interconnected and connected to the reference voltage VCM of the output common-mode voltage. The gate of the sixteenth CMOS transistor M16 is connected to the drain of the third CMOS transistor M3 and serves as the negative terminal of the output voltage Vout.

[0049] The gates of the ninth CMOS transistor M9, the tenth CMOS transistor M10, and the eleventh CMOS transistor M11 are all connected to the drain of the eleventh CMOS transistor M11; the gate of the twelfth CMOS transistor M12 is connected to the drain of the twelfth CMOS transistor M12; the sources of the ninth CMOS transistor M9, the tenth CMOS transistor M10, the eleventh CMOS transistor M11, and the twelfth CMOS transistor M12 are all grounded.

[0050] The input of the first gain-boosting operational amplifier GN is connected to a first bias voltage V1, providing a DC bias point to the drains of the third CMOS transistor M3, the fourth CMOS transistor M4, the fifth CMOS transistor M5, and the sixth CMOS transistor M6. The input of the second gain-boosting operational amplifier GP is connected to a second bias voltage V2, providing a DC bias point to the gates and sources of the seventh CMOS transistor M7 and the eighth CMOS transistor M8. GN and GP are important components of the first-stage operational amplifier GM1, used to achieve a high-gain first-stage operational amplifier and suppress the input offset voltage error of the second and third stages. V1, V2, and Vb are bias voltages used to provide the DC bias point and ensure the normal operation of the amplifier. VCM is the reference voltage for the output common-mode voltage, which is determined by the common-mode feedback circuit composed of devices M11, M12, M13, M14, M15, M16, and I4 and I5.

[0051] The high gain of the first-stage operational amplifier GM1 can suppress the input offset voltage error caused by the second-stage operational amplifier GM2 / the third-stage operational amplifier GM3. GM2vos_RTI=GM2vos / A v1 ,GM3vos_RTI=GM3vos / Av1 A v2 Typically, a folded cascode amplifier using gain boosting technology has an open-loop gain greater than 140dB, which can reduce the 5mV input offset voltage of GM2 to less than 0.5uV. Therefore, only the input offset voltage of the first stage needs to be pre-adjusted, and the input offset voltage error caused by GM2 / GM3 can be suppressed by the circuit's own performance. The initial equivalent input offset voltage of GM1 is adjusted by adjustable current sources I2 and I3.

[0052] The second current source I2 and the third current source I3 have the same structure, including a fuse array, an adjustable current source and a decoder. In this embodiment, a 3-8 decoder is used, which includes three input terminals and eight output terminals, but two of the output signals are not used.

[0053] Fuse arrays such as Figure 5 As shown, the fuse array includes a thirteenth CMOS transistor CM0, a fourteenth CMOS transistor CM1, a fifteenth CMOS transistor CM2, a sixteenth CMOS transistor CM3, a first fuse, a second fuse, a third fuse, a fourth fuse, a first Schmitt trigger, a second Schmitt trigger, a third Schmitt trigger, and a fourth Schmitt trigger; the gates of the thirteenth CMOS transistor CM0, the fourteenth CMOS transistor CM1, the fifteenth CMOS transistor CM2, and the sixteenth CMOS transistor CM3 are all connected to a bias voltage VBIAS. The sources of MOSFET CM2 and the sixteenth CMOS transistor CM3 are both connected to the power supply voltage; the gates of the thirteenth CMOS transistor CM0, the fourteenth CMOS transistor CM1, the fifteenth CMOS transistor CM2, and the sixteenth CMOS transistor CM3 are grounded through the first fuse, the second fuse, the third fuse, and the fourth fuse, respectively; the first signal terminal B0, the second signal terminal B1, the third signal terminal B2, and the fourth signal terminal B3 are connected to the ends of the first fuse, the second fuse, the third fuse, and the fourth fuse away from ground through the first Schmitt trigger, the second Schmitt trigger, the third Schmitt trigger, and the fourth Schmitt trigger, respectively.

[0054] The decoder receives signals generated by the second signal terminal B1, the third signal terminal B2, and the fourth signal terminal B3, compiles and generates 6 signals (actually 8 signals are compiled and generated, of which 2 are unused), and outputs them to the fifth signal terminal A1, the sixth signal terminal A2, the seventh signal terminal A3, the eighth signal terminal A4, the ninth signal terminal A5, and the tenth signal terminal A6 respectively to control the adjustable current source.

[0055] Figure 4 The structure diagram of the adjustable current source is as follows: Figure 4As shown, the adjustable current source includes a test PAD, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fifth current mirror, a sixth current mirror, a first switch CM4, a second switch CM5, a third switch CM6, a fourth switch CM7, a fifth switch CM8, a sixth switch CM9, a seventeenth CMOS transistor, an eighteenth CMOS transistor, an inverter, and an AND gate.

[0056] The first, second, third, fourth, fifth, and sixth current mirrors are connected in parallel. Their inputs are all connected to the power supply voltage, and their outputs are connected to the drains of the seventeenth and eighteenth CMOS transistors via switches CM4, CM5, CM6, CM7, CM8, and CM9, respectively. The test PAD and the tenth signal terminal A6 are connected to the two inputs of an AND gate, and the output of the AND gate is connected to the sixth switch CM9 to control the on / off state of the sixth current mirror. The fifth signal terminal A1 and the sixth... Signal terminals A2, A3, A4, and A5 are respectively connected to the first switch CM4, the second switch CM5, the third switch CM6, the fourth switch CM7, the fifth switch CM8, and the sixth switch CM9 to control their on / off states; the first signal terminal B0 is directly connected to the gate of the seventeenth CMOS transistor CM10 on one hand, and to the gate of the eighteenth CMOS transistor CM11 on the other hand through an inverter; the sources of the seventeenth CMOS transistor CM10 and the eighteenth CMOS transistor CM11 serve as the offset voltage increase terminal and the offset voltage decrease terminal, respectively.

[0057] Figure 4 This is a diagram of an adjustable current source structure, with a fuse array as shown. Figure 5 Before the fuse blows, the B0 / B1 / B2 / B3 signals are at a logic high level by default, as are the A1 / A2 / A3 signals. A decoder converts the 3-bit control signals into more control signals. B0 controls whether the offset voltage changes in the direction of increase or decrease, i.e., the adjustable current source I2 / I3. The logic high or low of the A1 / A2 / A3 signals controls the opening and closing of the upper current mirror. The test PAD is used for pre-adjustment. The maximum adjustable value of the MSB is connected to the circuit to calculate the adjustable value of each LSB.

[0058] During normal operation, the circuit generates a set of fixed-frequency clock signals by the oscillator. ФC1 and ФC2 are the control signals for CHOP1 and CHOP2, and Ф1 and Ф2 are the control signals for the notch filter. The timing diagram is shown above. After chopping and filtering, the output offset voltage is significantly reduced. To accurately reflect the true offset voltage value of the operational amplifier before chopping and filtering, the chopper and filter need to be turned off while maintaining a complete signal path. Therefore, a trimming mode is designed, adding a test signal to the circuit. This signal is input through a CP_PAD in the layout, as shown above. Figure 6 As shown, ФC1 and ФC21 pass through Figure 7 The combinational logic is implemented as follows: When the test signal is 0, the system enters adjustment mode, ФC11 is constantly 0, ФC21 is constantly 1, switches S1 / S4 are closed, and switches S2 / S3 are open, ensuring that the input signal can enter the input stage amplifier normally. The test signal is set to a default value of 1 by the internal pull-up circuit, ensuring that ФC11 and ФC1 have the same timing, and ФC21 and ФC2 have the same timing. Ф11, Ф21, Ф22, and Ф12 are... Figure 8 Implement the combinational logic on the right.

[0059] When the test signal is 0, the system enters the tuning mode. Ф11 and Ф21 are always 0, and Ф22 and Ф12 are always 1, ensuring that the input signal can enter the subsequent amplifier normally. The test signal is set to 1 by the internal pull-up circuit, ensuring that Ф11 and Ф12 have the same timing as Ф1, and Ф21 and Ф22 have the same timing as Ф2.

[0060] See Figure 8 This invention discloses a method for operating the aforementioned low-output-ripple, ultra-low-offset-voltage operational amplifier, the method comprising the following steps:

[0061] The control oscillator generates a set of clock signals with a fixed frequency, including the control signal ФC1 of the first chopper circuit, the control signal ФC2 of the second chopper circuit, and the control signals Ф1 and Ф2 of the notch filter;

[0062] Add a control switch signal test to the first chopper circuit, the second chopper circuit, and the notch filter. Set the control switch signal test to 0 to turn off the first chopper circuit, the second chopper circuit, and the notch filter, so that the first-stage operational amplifier enters the adjustment mode. Test the magnitude of the offset voltage and record it as V0S0.

[0063] Set the test PAD to 0, test the magnitude of the offset voltage, and record it as V0S1;

[0064] The adjustment MSB is obtained by calculating the difference between V0S0 and V0S1. The adjustment LSB is calculated from the adjustment MSB. The fuse code required for adjustment is obtained from V0S0 / LSB.

[0065] The corresponding fuse is adjusted by laser according to the fuse adjustment code to obtain the bare die of the arithmetic amplifier with an offset voltage of several hundred microvolts;

[0066] The arithmetic unit amplifier die is packaged so that the test and offset voltage pre-adjustment test PADs are not visible from the outside;

[0067] When the chip is powered on, the offset voltage of several hundred microvolts is attenuated to low output ripple and ultra-low offset voltage through chopping and notch filtering.

[0068] Figure 9 For comparison, the left image shows the output waveform of a chopper amplifier using existing technology, with an output ripple of 100µV and an offset voltage of 10µV; the right image shows the output waveform of the amplifier proposed in this invention, with an output ripple of 10µV and an offset voltage of 2µV. By employing an input offset voltage adjustment circuit, the initial offset voltage of the amplifier is reduced to within the hundreds ofµV range before chopping and notch filtering are performed. Low output ripple voltage and ultra-low input offset voltage are achieved using only a small notch filter.

[0069] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0070] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A low-output-ripple, ultra-low-offset-voltage operational amplifier, characterized in that, The low-output ripple ultra-low offset voltage operational amplifier includes a first chopper circuit, a first-stage operational amplifier with an added offset voltage adjustment circuit, a second chopper circuit, a notch filter, a second-stage operational amplifier, and a third-stage operational amplifier connected in sequence. The first-stage operational amplifier, the second-stage operational amplifier, and the third-stage operational amplifier constitute a three-stage high-gain operational amplifier. The offset voltage adjustment circuit adjusts the input offset voltage of the first-stage operational amplifier to several hundred microvolts before outputting it to the second chopper circuit. The first and second chopper circuits are used to modulate the offset voltage of the first-stage operational amplifier to the chopper frequency, and then the ripple voltage at the chopper frequency is filtered out by the notch filter. The first-stage amplifier is designed as a high-gain operational amplifier to suppress the input offset voltage error caused by the second-stage and third-stage operational amplifiers.

2. The low output ripple ultra-low offset voltage operational amplifier according to claim 1, characterized in that, The first-stage operational amplifier with added offset voltage adjustment circuit is a folded common-source common-gate amplifier, including a first gain boost operational amplifier (GN), a second gain boost operational amplifier (GP), a first CMOS transistor (M1), a second CMOS transistor (M2), a third CMOS transistor (M3), a fourth CMOS transistor (M4), a fifth CMOS transistor (M5), a sixth CMOS transistor (M6), a seventh CMOS transistor (M7), an eighth CMOS transistor (M8), a ninth CMOS transistor (M9), a tenth CMOS transistor (M10), an eleventh CMOS transistor (M11), a twelfth CMOS transistor (M12), a thirteenth CMOS transistor (M13), a fourteenth CMOS transistor (M14), a fifteenth CMOS transistor (M15), a sixteenth CMOS transistor (M6), a first current source (I1), a second current source (I2), a third current source (I3), a fourth current source (I4), and a fifth current source (I5); The sources of the first CMOS transistor (M1) and the second CMOS transistor (M2) are connected to the power supply voltage through the first current source (I1), the gates are connected to the positive and negative terminals of the input voltage Vin, respectively, and the drains are connected to the sources of the eighth CMOS transistor (M8) and the seventh CMOS transistor (M7), respectively; the second current source (I2) and the third current source (I3) are adjustable current sources, the input terminals of which are connected to the power supply voltage, and the output terminals of which are connected to the gates of the second CMOS transistor (M2) and the first CMOS transistor (M1), respectively; The gates of the fifth CMOS transistor (M5) and the sixth CMOS transistor (M6) are interconnected, their sources are connected to the power supply voltage, and their drains are connected to the sources of the third CMOS transistor (M3) and the fourth CMOS transistor (M4), respectively. Their gates are connected to the third bias voltage Vb. The drains of the third CMOS transistor (M3) and the fourth CMOS transistor (M4) are connected to the drains of the seventh CMOS transistor (M7) and the eighth CMOS transistor (M8), respectively. The sources of the seventh CMOS transistor (M7) and the eighth CMOS transistor (M8) are connected to the drains of the ninth CMOS transistor (M9) and the tenth CMOS transistor (M10), respectively. The sources of the thirteenth CMOS transistor (M13) and the fourteenth CMOS transistor (M14) are interconnected and connected to the power supply voltage through the fourth current source (I4). The drains of the thirteenth CMOS transistor (M13) and the fourteenth CMOS transistor (M14) are respectively connected to the drain of the twelfth CMOS transistor (M12) and the drain of the eleventh CMOS transistor (M11). The sources of the fifteenth CMOS transistor (M15) and the sixteenth CMOS transistor (M16) are interconnected and connected to the power supply voltage through the fifth current source (I5). The drain of transistor (M16) is connected to the drain of the eleventh CMOS transistor (M11) and the drain of the twelfth CMOS transistor (M12), respectively; the gate of the thirteenth CMOS transistor (M13) is connected to the drain of the fourth CMOS transistor (M4) and serves as the positive terminal of the output voltage Vout; the gates of the fourteenth CMOS transistor (M14) and the fifteenth CMOS transistor (M15) are interconnected and connected to the reference voltage VCM of the output common-mode voltage; the gate of the sixteenth CMOS transistor (M16) is connected to the drain of the third CMOS transistor (M3) and serves as the negative terminal of the output voltage Vout. The gates of the ninth CMOS transistor (M9), the tenth CMOS transistor (M10), and the eleventh CMOS transistor (M11) are all connected to the drain of the eleventh CMOS transistor (M11); the gate of the twelfth CMOS transistor (M12) is connected to the drain of the twelfth CMOS transistor (M12); the sources of the ninth CMOS transistor (M9), the tenth CMOS transistor (M10), the eleventh CMOS transistor (M11), and the twelfth CMOS transistor (M12) are all grounded; The input of the first gain boost operational amplifier (GN) is connected to a first bias voltage V1 to provide a DC bias point to the drains of the third CMOS transistor (M3), the fourth CMOS transistor (M4), the fifth CMOS transistor (M5), and the sixth CMOS transistor (M6); the input of the second gain boost operational amplifier (GP) is connected to a second bias voltage V2 to provide a DC bias point to the gates and sources of the seventh CMOS transistor (M7) and the eighth CMOS transistor (M8).

3. The low output ripple ultra-low offset voltage operational amplifier according to claim 1, characterized in that, The second current source (I2) and the third current source (I3) have the same structure, including a fuse array, an adjustable current source and a decoder; The fuse array includes a thirteenth CMOS transistor (CM0), a fourteenth CMOS transistor (CM1), a fifteenth CMOS transistor (CM2), a sixteenth CMOS transistor (CM3), a first fuse, a second fuse, a third fuse, a fourth fuse, a first Schmitt trigger, a second Schmitt trigger, a third Schmitt trigger, and a fourth Schmitt trigger; The gates of the thirteenth CMOS transistor (CM0), fourteenth CMOS transistor (CM1), fifteenth CMOS transistor (CM2), and sixteenth CMOS transistor (CM3) are all connected to the bias voltage VBIAS, and the sources of the thirteenth CMOS transistor (CM0), fourteenth CMOS transistor (CM1), fifteenth CMOS transistor (CM2), and sixteenth CMOS transistor (CM3) are all connected to the power supply voltage; the gates of the thirteenth CMOS transistor (CM0), fourteenth CMOS transistor (CM1), fifteenth CMOS transistor (CM2), and sixteenth CMOS transistor (CM3) are grounded through the first fuse, second fuse, third fuse, and fourth fuse, respectively; the first signal terminal (B0), second signal terminal (B1), third signal terminal (B2), and fourth signal terminal (B3) are connected to the ends of the first fuse, second fuse, third fuse, and fourth fuse away from ground through the first Schmitt trigger, second Schmitt trigger, third Schmitt trigger, and fourth Schmitt trigger, respectively. The decoder receives signals generated by the second signal terminal (B1), the third signal terminal (B2), and the fourth signal terminal (B3), compiles and generates 6 signals, and outputs them to the fifth signal terminal (A1), the sixth signal terminal (A2), the seventh signal terminal (A3), the eighth signal terminal (A4), the ninth signal terminal (A5), and the tenth signal terminal (A6), respectively. The adjustable current source includes a test PAD, a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fifth current mirror, a sixth current mirror, a first switch (CM4), a second switch (CM5), a third switch (CM6), a fourth switch (CM7), a fifth switch (CM8), a sixth switch (CM9), a seventeenth CMOS transistor, an eighteenth CMOS transistor, an inverter, and an AND gate. The first current mirror, the second current mirror, the third current mirror, the fourth current mirror, the fifth current mirror, and the sixth current mirror are connected in parallel. Their input terminals are all connected to the power supply voltage, and their output terminals are connected to the drains of the seventeenth CMOS transistor and the eighteenth CMOS transistor through the first switch (CM4), the second switch (CM5), the third switch (CM6), the fourth switch (CM7), the fifth switch (CM8), and the sixth switch (CM9), respectively. The test PAD and the tenth signal terminal (A6) are respectively connected to the two input terminals of the AND gate, and the output terminal of the AND gate is connected to the sixth switch (CM9) to control the on / off state of the sixth current mirror; the fifth signal terminal (A1), the sixth signal terminal (A2), the seventh signal terminal (A3), the eighth signal terminal (A4), and the ninth signal terminal (A5) are respectively connected to the first switch (CM4), the second switch (CM5), the third switch (CM6), the fourth switch (CM7), the fifth switch (CM8), and the sixth switch (CM9) to control their on / off state; The first signal terminal (B0) is directly connected to the gate of the seventeenth CMOS transistor (CM10) on one hand, and connected to the gate of the eighteenth CMOS transistor (CM11) through an inverter on the other hand; the sources of the seventeenth CMOS transistor (CM10) and the eighteenth CMOS transistor (CM11) serve as the offset voltage increase terminal and the offset voltage decrease terminal, respectively.

4. A method for operating a low-output-ripple, ultra-low-offset-voltage operational amplifier according to any one of claims 1-3, characterized in that, The working method includes the following steps: The control oscillator generates a set of clock signals with a fixed frequency, including the control signal ФC1 of the first chopper circuit, the control signal ФC2 of the second chopper circuit, and the control signals Ф1 and Ф2 of the notch filter; Add a control switch signal test to the first chopper circuit, the second chopper circuit, and the notch filter. Set the control switch signal test to 0 to turn off the first chopper circuit, the second chopper circuit, and the notch filter, so that the first-stage operational amplifier enters the adjustment mode. Test the magnitude of the offset voltage and record it as V0S0. Set the test PAD to 0, test the magnitude of the offset voltage, and record it as V0S1; The adjustment MSB is obtained by calculating the difference between V0S0 and V0S1. The adjustment LSB is calculated from the adjustment MSB. The fuse code required for adjustment is obtained from V0S0 / LSB. The corresponding fuse is adjusted by laser according to the fuse adjustment code to obtain the bare die of the arithmetic amplifier with an offset voltage of several hundred microvolts; The arithmetic unit amplifier die is packaged so that the test and offset voltage pre-adjustment test PADs are not visible from the outside; When the chip is powered on, the offset voltage of several hundred microvolts is attenuated to low output ripple and ultra-low offset voltage through chopping and notch filtering.

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