Broadband current mode low pass filter circuit

Abstract

Methods and apparatus for filtering a signal using a current mode filter circuit that enables source degradation. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled with the input node; a second transistor including a drain coupled with the output node and including a gate coupled with a gate of the first transistor; a capacitive element coupled between a drain of the first transistor and the power supply node; a first resistive element coupled between the drain electrode and the gate electrode of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

Description

Cross - Reference to Related Applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 068,837, filed on December 20, 2022, which is assigned to the assignee of this application and is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes. Technical Field

[0002] Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to filter circuits. Background Art

[0003] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasting, and the like. Such wireless communication devices may transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile Communications (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RAT (e.g., WiFi), etc.

[0004] A wireless communication network may include multiple base stations capable of supporting communication for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, while the uplink (or reverse link) refers to the communication link from the mobile station to the base station. The base station may send data and control information to the mobile station on the downlink and / or may receive data and control information from the mobile station on the uplink. The base station and / or the mobile station may include a transmit digital - to - analog converter (TX DAC), which may be used, for example, to convert a digital signal into an analog signal for signal processing (e.g., filtering, up - conversion, and amplification) before transmission by one or more antennas. The filtering may be done by a baseband filter, which may be implemented as a low - pass filter. Summary of the Invention

[0005] The systems, methods, and devices of the present disclosure each have several aspects, none of which alone is responsible for its desirable characteristics. Without limiting the scope of the present disclosure as expressed by the appended claims, some features will now be briefly discussed. After considering this discussion and particularly after reading the section entitled "Detailed Description," it will be understood how the features of the present disclosure provide the following advantages: including higher image frequency rejection, lower signal attenuation, reduced area, lower power consumption, greater residual sideband (RSB) suppression, and / or higher signal-to-noise ratio (SNR).

[0006] Certain aspects of the present disclosure provide a filter circuit. The filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled to the input node; a second transistor including a drain coupled to the output node and including a gate coupled to the gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between the source of the first transistor and the power supply node; and a second source degeneration element coupled between the source of the second transistor and the power supply node.

[0007] Certain aspects of the present disclosure provide a filter circuit. The filter circuit generally includes an input node; an output node; a power supply node; a first capacitive element coupled between the input node and the power supply node; a first transistor; a second transistor including a drain coupled to the output node and including a gate coupled to the gate and the drain of the first transistor; a third transistor including a drain coupled to the drain of the first transistor and including a source coupled to the input node; a second capacitive element coupled between the source and the gate of the third transistor; a first resistive element coupled between the gate of the third transistor and a bias node of the filter circuit; a first source degeneration element coupled between the source of the first transistor and the power supply node; and a second source degeneration element coupled between the source of the second transistor and the power supply node.

[0008] Certain aspects of the present disclosure provide a transmitter circuit. The transmitter circuit generally includes a filter circuit as described herein, a digital-to-analog converter including an output coupled to the input node of the filter circuit, and a mixer including an input coupled to the output node of the filter circuit.

[0009] Certain aspects of the present disclosure provide a method for filtering a signal. The method generally includes receiving an input signal at a first branch of a current-mode filter circuit; and filtering the received input signal using the current-mode filter circuit to generate an output signal at a second branch of the current-mode filter circuit, wherein the first branch includes a first source degeneration element, and wherein the second branch includes a second source degeneration element.

[0010] To achieve the foregoing and related purposes, one or more aspects include the features described comprehensively below and particularly pointed out in the claims. The following description and the drawings set forth in detail some illustrative features of one or more aspects. However, these features are only indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To enable a more particular understanding of the manner in which the above-recited features of the present disclosure can be obtained, a more specific description, briefly summarized above, may be had by reference to the aspects, some of which are illustrated in the drawings. It is to be noted, however, that the drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, as the specification may admit other equally effective aspects.

[0012] Figure 1 is a diagram of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0013] Figure 2 is a block diagram conceptually illustrating the design of an example base station (BS) and user equipment (UE) in which aspects of the present disclosure may be practiced.

[0014] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0015] Figure 4A is a circuit diagram of a portion of an example transmit path in accordance with certain aspects of the present disclosure, illustrating a digital-to-analog converter (DAC) and a current-mode low-pass filter circuit having a switching circuit.

[0016] Figure 4B is illustrative of Figure 4A a variant of the filter circuit in accordance with certain aspects of the present disclosure, which variant uses transistors for degeneration.

[0017] Figure 5A is a circuit diagram of another example current-mode low-pass filter circuit in accordance with certain aspects of the present disclosure.

[0018] Figure 5BIt is a circuit diagram of another exemplary current-mode low-pass filter circuit according to certain aspects of the present disclosure.

[0019] Figure 6 It is a flowchart of an exemplary operation for filtering a signal according to certain aspects of the present disclosure.

[0020] For ease of understanding, the same reference numerals have been used, where possible, to denote the same elements common to the drawings. It is contemplated that elements disclosed in one aspect may be beneficially used in other aspects without specific recitation. Detailed Description

[0021] Certain aspects of the present disclosure relate to a current-mode low-pass filter circuit with source degeneration. Such a filter circuit can be used, for example, as a baseband filter circuit in a wireless transmit path or as a filter in a high-speed transmitter. For certain aspects, the filter circuit is implemented as a current mirror, and in such a case, may include a gate resistance element coupled between the transistor gates in the current mirror branches. The filter circuits described herein may provide several advantages over at least some methods, such as higher digital-to-analog converter (DAC) image frequency rejection, lower signal attenuation, reduced area, lower power consumption, greater residual sideband (RSB) suppression, and / or higher signal-to-noise ratio (SNR).

[0022] Aspects of the present disclosure are described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently or in combination with any other aspect of the present disclosure. For example, any number of the aspects set forth herein may be used to implement a device or practice a method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or a combination of structures and functionality in addition to or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present invention.

[0023] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0024] As used herein, the term "coupled to" in various tenses of the verb "couple" can mean that element A is directly coupled to element B or that other elements can be coupled between element A and element B (i.e., element A is indirectly coupled to element B). In the case of an electronic assembly, the term "coupled to" can also be used herein to mean that a wire, trace, or other conductive material is used to electrically couple element A and element B (and any components electrically connected therebetween).

[0025] As used herein, the term "power node" generally refers to a power rail of a given circuit (such as VDD or VSS, common nomenclature in a field effect transistor (FET) circuit), or a reference potential node (e.g., electrical ground).

[0026] Example wireless system

[0027] Figure 1 An example wireless communication network 100 is illustrated in which aspects of the present disclosure may be practiced. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured to communicate according to an IEEE standard such as one or more of the 802.11 standards.

[0028] As Figure 1 Illustrated, the wireless communication network 100 may include several base stations (BSs) 110a through 110z (each also referred to herein individually as BS 110 or collectively as BS 110) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other term.

[0029] The BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or may move depending on the location of the mobile BS. In some examples, the BS 110 may use any suitable transport network to interconnect with each other and / or connect to one or more other BSs or network nodes (not shown) in the wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.). In Figure 1In the example shown, BS 110a, 110b, and 110c can be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS110x can be a pico BS for pico cell 102x. BS 110y and 110z can be femto BSs for femto cells 102y and 102z, respectively. A BS can support one or more cells.

[0030] BS 110 communicates with one or more user equipments (UEs) 120a to 120y in wireless communication network 100 (each also referred to herein individually as UE 120 or collectively as UE 120). A UE can be fixed or mobile and can also be referred to as a user terminal (UT), mobile station (MS), access terminal, station (STA), client, wireless device, mobile device, or some other term. A user terminal can be a wireless device such as a cellular phone, smart phone, personal digital assistant (PDA), handheld device, wearable device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0031] BS 110 is considered a transmitting entity for the downlink and a receiving entity for the uplink. UE 120 is considered a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operating device or equipment capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operating device or equipment capable of receiving data via a frequency channel. In the following description, the subscript "dn" represents the downlink and the subscript "up" represents the uplink. N up UEs can be selected for simultaneous transmission on the uplink, and N dn UEs can be selected for simultaneous transmission on the downlink. N up can be equal to or can be not equal to N dn and N up and N dn can be static values or can change for each scheduling interval. Beam control or some other spatial processing techniques can be used at BS 110 and UE 120.

[0032] UEs 120 (e.g., 120x, 120y, etc.) can be scattered throughout wireless communication network 100, and each UE120 can be stationary or mobile. Wireless communication network 100 can also include a relay station (e.g., relay station 110r) (also referred to as a repeater, etc.), which receives the transmission of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmits the transmission of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relays transmissions between UEs 120 to facilitate communication between devices.

[0033] BS 110 can communicate with one or more UEs 120 on the downlink and uplink at any given moment. The downlink (i.e., the forward link) is the communication link from the BS 110 to the UE 120, and the uplink (i.e., the reverse link) is the communication link from the UE 120 to the BS 110. The UE 120 can also perform peer-to-peer communication with another UE 120.

[0034] The wireless communication network 100 can use multiple transmit antennas and multiple receive antennas to send data on the downlink and uplink. The BS 110 can be equipped with several (N ap ) antennas to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A group (N u ) of UEs 120 can receive downlink transmissions and send uplink transmissions. Each UE 120 can send user-specific data to the BS 110 and / or receive user-specific data from the BS. Generally, each UE 120 can be equipped with one or more antennas. N u UEs 120 can have the same or different numbers of antennas.

[0035] The wireless communication network 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each UE 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., when additional cost can be supported).

[0036] The network controller 130 (sometimes also referred to as the "system controller") can communicate with a group of BS 110s and provide coordination and control for these BS 110s (e.g., via the backhaul). In some cases (e.g., in a 5G NR system), the network controller 130 can include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 can communicate with the core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane function, policy control function, authentication server function, unified data management, application function, network exposure function, network repository function, network slice selection function, etc.

[0037] In certain aspects of the present disclosure, the BS 110 and / or the UE 120 may include a baseband filter in the transmit path. The baseband filter may be implemented by a filter circuit as described herein (e.g., a current-mode low-pass filter circuit).

[0038] Figure 2 Examples of the BS 110a and the UE 120a (e.g., from Figure 1 the wireless communication network 100) in which aspects of the present disclosure may be implemented are illustrated.

[0039] On the downlink, at the BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, the control information may be designated for the physical broadcast channel (PBCH), the physical control format indicator channel (PCFICH), the physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), the physical downlink control channel (PDCCH), the group common PDCCH (GC PDCCH), etc. The data may be designated for the physical downlink shared channel (PDSCH), etc. The media access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. The MAC-CE may be carried in a shared channel such as the PDSCH, the physical uplink shared channel (PUSCH), or the physical sidelink shared channel (PSSCH).

[0040] The processor 220 may process (e.g., encode and symbol map) the data and the control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for the primary synchronization signal (PSS), the secondary synchronization signal (SSS), the PBCH demodulation reference signal (DMRS), and the channel state information reference signal (CSI-RS).

[0041] A transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on data symbols, control symbols, and / or reference symbols when applicable, and may provide the output symbol stream to a modulator (MOD) in transceivers 232a - 232t. Each modulator 232a - 232t in the transceivers may process its respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each transceiver in transceivers 232a - 232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from transceivers 232a - 232t may be transmitted via antennas 234a - 234t, respectively.

[0042] At the UE 120a, antennas 252a - 252r may receive downlink signals from the BS 110a and may provide the received signals to transceivers 254a - 254r, respectively. The transceivers 254a - 254r may condition (e.g., filter, amplify, down-convert, and digitize) the respective received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a - 232t may further process the input samples (e.g., for OFDM, etc.) to obtain the received symbols. A MIMO detector 256 may obtain the received symbols from all the demodulators in transceivers 254a - 254r, perform MIMO detection on the received symbols when applicable, and provide detected symbols. A receive processor 258 may process (e.g., demodulate, de-interleave, and decode) the detected symbols, provide the decoded data for the UE 120a to a data sink 260, and provide the decoded control information to a controller / processor 280.

[0043] On the uplink, at the UE 120a, the transmit processor 264 may receive and process data (e.g., for the Physical Uplink Shared Channel (PUSCH)) from the data source 262, and receive and process control information (e.g., for the Physical Uplink Control Channel (PUCCH)) from the controller / processor 280. The transmit processor 264 may also generate reference symbols for reference signals (e.g., for the Sounding Reference Signal (SRS)). Symbols from the transmit processor 264 may be pre-coded by the TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in the transceivers 254a to 254r (e.g., for Single Carrier Frequency Division Multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At the BS 110a, the uplink signal from the UE 120a may be received by the antenna 234, processed by a demodulator in the transceivers 232a - 232t, detected by the MIMO detector 236 (if applicable), and further processed by the receive processor 238 to obtain the decoded data and control information transmitted by the UE 120a. The receive processor 238 may provide the decoded data to the data sink 239, and the decoded control information to the controller / processor 240.

[0044] The memories 242 and 282 may store data and program codes for the BS 110a and the UE 120a, respectively. The memories 242 and 282 may also interface with the controller / processor 240 and 280, respectively. The scheduler 244 may schedule the UE for data transmission on the downlink and / or uplink.

[0045] The antenna 252, processors 258, 264, 266, and / or the controller / processor 280 of the UE 120a and / or the antenna 234, processors 220, 230, 238, and / or the controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0046] In certain aspects of the present disclosure, the transceiver 232 and / or the transceiver 254 may include a transmit path having a baseband filter. The baseband filter may be implemented by a filter circuit as described herein (e.g., a current-mode low-pass filter circuit).

[0047] Example RF transceiver

[0048] Figure 3FIG. 0 is a block diagram of an example radio frequency (RF) transceiver circuit 300 in accordance with certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via the antenna 306. When the TX path 302 and the RX path 304 share the antenna 306, these paths may be connected to the antenna via an interface 308, which may include any one of various suitable RF devices such as switches, duplexers, diplexers, multiplexers, etc.

[0049] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0050] The DAC 310 may be implemented by any high-speed DAC topology of various suitable high-speed DAC topologies such as a current-steering DAC. The BBF 312 may be implemented by a filter circuit as described herein (e.g., a current-mode low-pass filter circuit).

[0051] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-converting from baseband to radio frequency). This frequency conversion process produces a sum frequency and a difference frequency between the LO frequency and the frequency of the baseband signal of interest. The sum frequency and the difference frequency are referred to as “beat frequencies”. The beat frequencies are typically in the RF range such that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, a plurality of mixers may be used to up-convert the filtered baseband signal to one or more intermediate frequencies and then up-convert the intermediate frequency (IF) signal to a frequency for transmission.

[0052] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC including the TX path components or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0053] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by the amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by the amplifier 334 before being mixed with the RF signal in the mixer 326. For some aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In some aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0054] The controller 336 (e.g., Figure 2 the controller / processor 280 in Figure 2 may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via the TX path 302 and / or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The memory 338 (e.g.,

[0055] While Figures 1 to 3Wireless communication is provided as an example application, where certain aspects of the present disclosure can be implemented for ease of understanding, but certain aspects described herein can be used for filtering in any of a variety of other suitable systems (e.g., high-speed transmitters).

[0056] Example filter circuit

[0057] Digital-to-analog converters (DACs), such as those used in the transmit chain of wireless applications (e.g., DAC 310) and in the transmit chain of other applications, generate unwanted image frequencies around multiple harmonics of the sampling frequency ( ), where is a positive integer, and is the frequency of the signal generated by the DAC (e.g., the baseband signal). Various wireless communication standards impose limits on power emission, which require significant attenuation of such image frequencies, especially the first image frequency ( ). In broadband applications (e.g., 5G), the broadband baseband signal and the sampling frequency limited by technology (e.g., low

[0058]

[0059] Some methods for image frequency rejection are designed to be complex, may consume a large amount of power, and / or may occupy a large amount of chip area, such as using an auxiliary DAC with a clock frequency of for interleaving with the main DAC. Other methods for image frequency rejection include using high-order filters. However, for example, compared to a simple current mirror filter circuit, some such high-order filters may have a reduced signal-to-noise ratio (SNR) and reduced residual sideband (RSB) rejection. In such embodiments, especially for broadband signals, it may be challenging to achieve a balance between low signal attenuation and high image frequency rejection. Certain aspects of the present disclosure provide a broadband current-mode low-pass filter circuit with a current mirror topology using source degeneration, e.g., to increase the signal-to-noise ratio (SNR), reduce mismatches in transistors and other components, reduce the drift of the direct current (DC) offset with temperature, and enhance the residual sideband (RSB) rejection. Certain aspects of the present disclosure can also use gate resistance elements between the current mirror branches to provide a peak near the cut-off frequency (e.g., at the edge of the frequency band), thereby reducing signal attenuation without reducing the image frequency rejection. Certain aspects of the present disclosure can also provide a low input impedance (Zin) and a low common-mode voltage (VCM ).

[0060] Figure 4A is a circuit diagram that is part of an example transmit path 400 (e.g., similar to Figure 3 the TX path 302) in accordance with certain aspects of the present disclosure. This portion of the transmit path 400 includes a digital-to-analog converter (DAC) 402 (e.g., similar to DAC 310) that has an output coupled to an input of a current-mode low-pass filter (LPF) circuit 401 (e.g., implementing BBF 312).

[0061] The current-mode LPF circuit 401 has a current mirror topology that has a first branch 406 and a second branch 408. The first branch 406 includes an n-type transistor Mn1, which may be implemented by an n-type metal-oxide semiconductor (NMOS) transistor as shown. The drain of the transistor Mn1 is coupled to an input node of the current-mode LPF circuit 401. The second branch 408 of the current mirror type filter circuit includes an n-type transistor Mn2, which may also be implemented by an NMOS transistor as shown. The drain of the transistor Mn2 is coupled to an output node (labeled "Iout") of the LPF circuit 401, which may be coupled to an input of a mixer (e.g., mixer 314) in a wireless application. The transistor size ratio between the transistors Mn1 and Mn2 may be 1:N, where N is a positive number (e.g., N = 3).

[0062] To achieve its low-pass frequency response, the LPF circuit 401 includes a capacitive element C1 and a resistive element Rgate1. The shunt capacitive element C1 is coupled between an input node of the circuit (and the drain of the transistor Mn1) and a reference potential node (e.g., electrical ground, power rail VSS, or another power node). For some aspects, the capacitive element C1 has a variable capacitance and may be implemented by an adjustable capacitor, a switched network of capacitors, or a combination thereof. A first terminal of the resistive element Rgate1 may be coupled to the drain of the transistor Mn1, and a second terminal of the resistive element Rgate1 is coupled to the gate of the transistor Mn2. For some aspects, the resistive element Rgate1 has a variable resistance and may be implemented by an adjustable resistor, a switched network of resistors, or a combination thereof. The capacitive element C1 and the resistive element Rgate1 may be used to control the bandwidth of the LPF circuit 401, where higher capacitance and / or higher resistance results in lower bandwidth (e.g., lower cut-off frequency).

[0063] The LPF circuit 401 can strive to increase the SNR by utilizing source degeneration in branches 406, 408 of a current mirror topology, reduce mismatch in transistors Mn1 and Mn2 (and other components), reduce the drift of DC offset with temperature, and enhance the RSB suppression of the filter circuit. Accordingly, a first source degeneration element (e.g., resistor element Rdeg1) can be coupled between the source of transistor Mn1 and a reference potential node, and a second source degeneration element (e.g., resistor element Rdeg2) can be coupled between the source of transistor Mn2 and the reference potential node, as Figure 4A illustrated.

[0064] For some aspects, the LPF circuit further includes a resistor element Rgate2 coupled between the gate of transistor Mn1 and the gate of transistor Mn2, wherein the terminal of resistor element Rgate2 coupled to transistor Mn2 is also coupled to the terminal of resistor element Rgate1 coupled to transistor Mn2, as shown. For some aspects, resistor element Rgate2 has a variable resistance and can be implemented by an adjustable resistor, a switched network of resistors, or a combination thereof. Resistor element Rgate2 can be used to provide a peak at the edge of the filter bandwidth (e.g., at the "band edge"), thereby reducing signal attenuation without degrading the image frequency rejection.

[0065] Although Figure 4A the exemplary LPF circuit (and other aspects presented herein) includes n-type transistors Mn1 and Mn2, the reader should understand that the LPF circuits presented herein can alternatively be implemented using p-type transistors as complementary filter circuits. In such complementary filter circuits, the capacitor elements C1 and the source degeneration elements can be coupled to a power supply rail, such as VDD, rather than to a reference potential node. For example, a first source degeneration element (e.g., resistor element Rdeg1) can be coupled between the source of transistor Mn1 (now a p-type transistor in this complementary implementation example) and the power supply rail, and a second source degeneration element (e.g., resistor element Rdeg2) can be coupled between the source of transistor Mn2 (now a p-type transistor in this example) and the power supply rail.

[0066] For some aspects, as Figure 4A shown, this portion of the transmit path 400 can further include a switching circuit 403 (e.g., in the case where the output of the DAC 402 is coupled to more than one circuit, such as to different TX paths or test paths) coupled between the output of the DAC 402 and the input of the filter circuit. The switching circuit 403 can include a switch 404 and a switch driver 405 (labeled "Sw-drv") having an output coupled to the control input of the switch 404. In some cases, the switch 404 can be implemented by a transistor (e.g., an n-type transistor, such asFigure 4A (illustrated) or transmit gate implementations. For some aspects, the switch circuit 403 may also include a resistive element Rsw coupled between the output of the switch driver 405 and the control input (e.g., the gate of a transistor) of the switch 404. Although the output of the DAC 402 and the switch 404 are depicted in a single-ended implementation in Figure 4A , it should be understood that the DAC 402 may have a differential output, and in such a case, the switch 404 may be implemented differentially, where each switch in the differential switch pair is equipped with a resistive element Rsw.

[0067] The switch 404 may have parasitic capacitances that affect the frequency response of the LPF circuit 401. For example, the transistors implementing the switch 404 may have gate-drain capacitance (Cgd) and gate-source capacitance (Cgs), which at higher frequencies can shunt the DAC output signal to the low impedance of the switch driver output. The resistive element Rsw can reduce the effect of these capacitances in the switch 404 by presenting a higher impedance path for the DAC output signal, thereby preventing the DAC output signal from flowing to the switch driver output and forcing the DAC output signal to be transmitted from the output of the DAC 402 to the input of the LPF circuit 401. The higher the resistance of the resistive element Rsw, the less attenuation of the band-edge signal of the combined frequency response of this part of the transmit path 400 typically results, and the higher the bandwidth.

[0068] According to some aspects, this part of the transmit path 400 may also include a routing 407 (e.g., a trace) coupled between the output of the DAC 402 (or the output of the switch 404, when present) and the input of the filter circuit. When the switch 404 is closed, the analog signal output by the DAC 402 can be transmitted (through the routing 407) to the input of the current-mode LPF circuit 401.

[0069] By adding the above components (e.g., degeneration elements), the combined switch circuit system 403 and LPF circuit 401 may have a higher input impedance (Zin) than some other methods, but the common-mode voltage (V CM ) can remain relatively low, such that the DAC linearity remains within the desired limits. Compared to some other embodiments, Figure 4A this part of the transmit path 400 also provides lower complexity and occupies less area.

[0070] Figure 4B is a circuit diagram of another example filter circuit 420 according to some aspects of the present disclosure, and this example filter circuit is Figure 4AVariant of the filter circuit 401 in []. The filter circuit 420 uses n-type transistors Mdeg1 and Mdeg2 as source degeneration elements instead of using resistor elements for source degeneration. The transistors Mdeg1 and Mdeg2 can have a transistor size ratio that matches the transistor size ratio (1:N) of the transistors Mn1 and Mn2.

[0071] As Figure 4B illustrated, the drain of the transistor Mdeg1 is coupled to the source of the transistor Mn1, the source of the transistor Mdeg1 is coupled to the reference potential node (e.g., electrical ground or another power supply node) of the filter circuit 420, and the gate of the transistor Mdeg1 is coupled to the gate of the transistor Mdeg2. The drain of the transistor Mdeg2 is coupled to the source of the transistor Mn2, and the source of the transistor Mdeg2 is coupled to the reference potential node. For some aspects, as Figure 4B shown, the transistors Mdeg1 and Mdeg2 can be biased by coupling the gates of the transistors Mdeg1 and Mdeg2 to the gate of the transistor Mn2. For other aspects, the transistors Mdeg1 and Mdeg2 can be biased by coupling the gates of the transistors Mdeg1 and Mdeg2 to another bias source (not shown), which uses a bias level that biases the transistors in the linear region.

[0072] By replacing the resistor elements Rdeg1 and Rdeg2 with the transistors Mdeg1 and Mdeg2 respectively, the filter circuit 420 can have an improved frequency response. For example, compared with the frequency response of the filter circuit 401, the frequency response of the filter circuit 420 can exhibit less signal attenuation and / or greater attenuation, with other component values of the filter circuit being the same. Therefore, compared with the filter circuit 401, the filter circuit 420 can provide a better trade-off between signal attenuation and image frequency rejection.

[0073] Figure 5A is a circuit diagram of another example current-mode low-pass filter circuit 500 according to certain aspects of the present disclosure. The filter circuit 500 adds a gain-enhanced p-type common-gate buffer and source degeneration elements to a current-mirror type low-pass filter circuit. For example, in addition to the n-type transistors Mn1 and Mn2 and the capacitive element C1, the filter circuit 500 further includes p-type transistors Mp1 and Mp2, capacitive element Cgs, resistor elements Rgs and Rextra, current source I1, and source degeneration elements (e.g., resistor elements Rdeg1 and Rdeg2 or transistors Mdeg1 and Meg2).

[0074] The input node Iin of the filter circuit 500 is coupled to a reference potential node via a shunt capacitor element C1. The first branch 406 of the current mirror in the filter circuit 500 includes a resistor element Rextra, transistors Mp2 and Mn1, and a first source degeneration element (e.g., a resistor element Rdeg1). The drain of transistor Mp2 is coupled to the drain of transistor Mn1, and the source of transistor Mp2 is coupled to the resistor element Rextra. The current mirror in the filter circuit 500 is formed by transistors Mn1 and Mn2, where the drain and gate of transistor Mn1 are coupled (e.g., shorted) together and coupled to the gate of transistor Mn2. The second branch 408 of the current mirror in the filter circuit 500 includes transistor Mn2 and a second source degeneration element (e.g., a resistor element Rdeg2).

[0075] The gain-enhanced common-gate buffer is implemented by transistors Mp2, a capacitor element Cgs, a resistor element Rgs, transistor Mp1, and a current source I1. The capacitor element Cgs and / or the resistor element Rgs can be variable. The source of transistor Mp2 is coupled to the gate of transistor Mp1, and the capacitor element Cgs is coupled between the gate and source of transistor Mp2. The source of transistor Mp1 is coupled to a bias node (labeled "Vbias"), and the drain of transistor Mp1 is coupled to the reference potential node via the current source I1. The resistor element Rgs is coupled between the gate of transistor Mp2 and the drain of transistor Mp1. In the topology of the filter circuit 500, transistor Mp1 provides transconductance (gm) enhancement for transistor Mp2 at low frequencies, and the enhancement effect weakens as the frequency increases, thereby synthesizing an inductor element for a low-pass filter (to provide an active inductor).

[0076] The degeneration elements in the filter circuit 500 can provide at least some of the advantages described above, such as increased SNR and higher RSB suppression, while also reducing mismatch and the drift of the DC offset with temperature. However, compared with the filter circuits 401 and 420, the filter circuit 500 may have reduced headroom (attributed to the cascode transistors Mp2 and Mn1) and higher noise (e.g., attributed to the high-frequency noise peaks caused by the additional transistors Mp1 and Mp2). The filter circuit 500 may also have a higher common-mode voltage (V CM ) than the filter circuits 401 and 420, but has a low enough Zin such that the DAC linearity of the filter circuit 500 is acceptable.

[0077] Figure 5BFIG. 0 is a circuit diagram of another example current-mode low-pass filter circuit 520 in accordance with certain aspects of the present disclosure. Filter circuit 520 is a simplified component implementation of filter circuit 500, and thus, most of the description of filter circuit 500 above also applies to filter circuit 520. Filter circuit 520 removes transistor Mp1, current source I1, and resistor element Rextra from filter circuit 500, and couples resistor element Rgs between the gate of transistor Mp2 and a bias node (labeled "Vbias"). Figure 5B The bias node of Figure 5A may be at a different voltage level than the bias node of

[0078] By removing resistor element Rextra, input node Iin is coupled to the source of transistor Mp2 in filter circuit 520. Since the above components are removed, filter circuit 520 may have lower power consumption and occupy less area than filter circuit 500. Elements Cgs and Rgs can be used to impart a certain amount of effective inductance to the input impedance (Zin) of the common-gate buffer. Compared to filter circuit 500, filter circuit 520 may exhibit reduced image frequency rejection and increased signal attenuation. Filter circuit 520 may have a common-mode voltage similar to that of filter circuit 500, but with a higher Zin, and thus the DAC linearity of filter circuit 520 may be slightly inferior to that of filter circuit 500.

[0079] Example filtering operation

[0080] Figure 6 FIG. 14 is a flow chart of an example operation 600 for filtering a signal in accordance with certain aspects of the present disclosure. Operation 600 can be performed by a current-mode filter circuit, such as Figures 4A to 5B filter circuits 401, 420, 500, and 520 as illustrated.

[0081] Operation 600 can begin at block 602, where a current-mode filter circuit receives an input signal at a first branch of the filter circuit (e.g., first branch 406). At block 604, the current-mode filter circuit can filter the received input signal to generate an output signal at a second branch of the filter circuit (e.g., second branch 408). The first branch includes a first source degeneration element (e.g., transistor Mdeg1 or resistor element Rdeg1), and the second branch includes a second source degeneration element (e.g., transistor Mdeg2 or resistor element Rdeg2). For some aspects, the first source degeneration element includes a first transistor (e.g., transistor Mdeg1), and the second source degeneration element includes a second transistor (e.g., transistor Mdeg2).

[0082] According to some aspects, the first branch further includes a first transistor (e.g., transistor Mn1) having a source coupled to a first source degeneration element, and the second branch further includes a second transistor (e.g., transistor Mn2) having a source coupled to a second source degeneration element. In this case, a first resistor element (e.g., resistor element Rgate1) may be coupled between the gate and the drain of the first transistor, and a capacitor element (e.g., capacitor element C1) may be coupled to the drain of the first transistor. For some aspects, the current mode filter circuit further includes a second resistor element (e.g., resistor element Rgate2), a first terminal of the second resistor element to which the gate of the first transistor is coupled, and a second terminal of the second resistor element is coupled to the gate of the second transistor. In this case, the first resistor element may have a first terminal coupled to the drain of the first transistor, and a second terminal coupled to the second terminal of the second resistor element and the gate of the second transistor. For some aspects, operation 600 may further involve adjusting the resistance of at least one of the first resistor element or the second resistor element. For some aspects, operation 600 may further include driving a control input of a switch (e.g., switch 404) using a switch driver (e.g., switch driver 405). In this case, the switch may be coupled in series with the first branch of the current mode filter circuit. For some aspects, a third resistor element (e.g., resistor element Rsw) is coupled between the output of the switch driver and the control input of the switch.

[0083] According to certain aspects, the first branch further includes a first transistor (e.g., transistor Mn1) having a source coupled to a first source degeneration element and a gate coupled to the drain of the first transistor, and the second branch further includes a second transistor (e.g., transistor Mn2) having a source coupled to a second source degeneration element. In this case, the first branch may further include a third transistor (e.g., transistor Mp2) including a drain coupled to the drain of the first transistor. For certain aspects, the current mode filter circuit further includes a first capacitive element (e.g., capacitive element C1) coupled in parallel with the first branch, a second capacitive element (e.g., capacitive element Cgs) coupled between the source and the gate of the third transistor, and a first resistive element (e.g., resistive element Rgs) coupled to the gate of the third transistor. For certain aspects, operation 600 also involves adjusting at least one of the capacitance of the first capacitive element, the capacitance of the second capacitive element, or the resistance of the first resistive element. For certain aspects, the current mode filter circuit further includes: a fourth transistor (e.g., transistor Mp1) having a drain coupled to the first resistive element and a gate coupled to the source of the third transistor; a current source (e.g., current source I1) coupled to the drain of the fourth transistor; and a second resistive element (e.g., resistive element Rextra) coupled between the first capacitive element and the source of the third transistor.

[0084] Example aspect

[0085] In addition to the various aspects described above, specific combinations of aspects are also within the scope of the present disclosure, some details of which are as follows:

[0086] Aspect 1: A filter circuit, the filter circuit including: an input node; an output node; a power supply node; a first transistor including a drain coupled to the input node; a second transistor including a drain coupled to the output node and a gate coupled to the gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between the source of the first transistor and the power supply node; and a second source degeneration element coupled between the source of the second transistor and the power supply node.

[0087] Aspect 2: The filter circuit according to Aspect 1, wherein the filter circuit further includes a second resistor element, the second resistor element including a first terminal coupled to the gate of the first transistor and including a second terminal coupled to the gate of the second transistor, wherein the first resistor element includes a first terminal coupled to the drain of the first transistor and including a second terminal coupled to the second terminal of the second resistor element and the gate of the second transistor.

[0088] Aspect 3: The filter circuit according to Aspect 2, wherein the filter circuit further includes: a switch coupled between the input node and the drain of the first transistor; a switch driver; and a third resistor element coupled between a control input of the switch and an output of the switch driver.

[0089] Aspect 4: The filter circuit according to Aspect 2 or 3, wherein at least one of the first resistor element or the second resistor element is adjustable to provide a variable resistance.

[0090] Aspect 5: The filter circuit according to Aspect 1, wherein the filter circuit further includes: a switch coupled between the input node and the drain of the first transistor; a switch driver; and a second resistor element coupled between a control input of the switch and an output of the switch driver.

[0091] Aspect 6: The filter circuit according to Aspect 1, wherein the first source degeneration element includes a second resistor element, and wherein the second source degeneration element includes a third resistor element.

[0092] Aspect 7: The filter circuit according to any one of the preceding aspects, wherein: the first source degeneration element includes a third transistor, the third transistor including a drain coupled to the source of the first transistor and including a source coupled to the power supply node; and the second source degeneration element includes a fourth transistor, the fourth transistor including a drain coupled to the source of the second transistor and including a source coupled to the power supply node.

[0093] Aspect 8: The filter circuit according to Aspect 7, wherein the third transistor includes a gate coupled to the gate of the fourth transistor and the gate of the second transistor.

[0094] Aspect 9: A transmitter circuit, the transmitter circuit including the filter circuit of any one of the foregoing aspects, the transmitter circuit further including: a digital-to-analog converter including an output coupled to the input node of the filter circuit; and a mixer including an input coupled to the output node of the filter circuit.

[0095] Aspect 10: A filter circuit, the filter circuit including: an input node; an output node; a power supply node; a first capacitive element coupled between the input node and the power supply node; a first transistor; a second transistor including a drain coupled to the output node and including a gate coupled to the gates and drains of the first transistor; a third transistor including a drain coupled to the drain of the first transistor and including a source coupled to the input node; a second capacitive element coupled between the source and the gate of the third transistor; a first resistive element coupled between the gate of the third transistor and a bias node of the filter circuit; a first source degeneration element coupled between the source of the first transistor and the power supply node; and a second source degeneration element coupled between the source of the second transistor and the power supply node.

[0096] Aspect 11: The filter circuit according to aspect 10, wherein at least one of the second capacitive element or the first resistive element is adjustable.

[0097] Aspect 12: The filter circuit according to aspect 10 or 11, wherein the first source degeneration element includes a second resistive element, and wherein the second source degeneration element includes a third resistive element.

[0098] Aspect 13: The filter circuit according to any one of aspects 10 to 12, wherein: the first source degeneration element includes a fourth transistor including a drain coupled to the source of the first transistor and including a source coupled to the power supply node; and the second source degeneration element includes a fifth transistor including a drain coupled to the source of the second transistor and including a source coupled to the power supply node.

[0099] Aspect 14: The filter circuit according to aspect 13, wherein the fifth transistor includes a gate coupled to the gates of the fourth transistor and the second transistor.

[0100] Aspect 15: The filter circuit according to any one of Aspects 10 to 14, the filter circuit further comprising: a switch coupled between the input node and the source of the third transistor; a switch driver; and a second resistor element coupled between the control input of the switch and the output of the switch driver.

[0101] Aspect 16: The filter circuit according to Aspect 10 or 11, the filter circuit further comprising: a fourth transistor having a source coupled to the bias node, a drain coupled to the first resistor element, and a gate coupled to the source of the third transistor; a current source coupled between the drain of the fourth transistor and the power supply node; and a second resistor element coupled between the input node and the source of the third transistor.

[0102] Aspect 17: A transmitter circuit, the transmitter circuit comprising the filter circuit according to any one of Aspects 10 to 16, the transmitter circuit further comprising: a digital-to-analog converter having an output coupled to the input node of the filter circuit; and a mixer having an input coupled to the output node of the filter circuit.

[0103] Aspect 18: A filtering method, the method comprising: receiving an input signal at a first branch of a current-mode filter circuit; and filtering the received input signal using the current-mode filter circuit to generate an output signal at a second branch of the current-mode filter circuit, wherein the first branch includes a first source degeneration element, and wherein the second branch includes a second source degeneration element.

[0104] Aspect 19: The method according to Aspect 18, wherein the first source degeneration element includes a first transistor, and wherein the second source degeneration element includes a second transistor.

[0105] Aspect 20: The method according to Aspect 18 or 19, wherein: the first branch further includes a first transistor having a source coupled to the first source degeneration element; a first resistor element is coupled between the gate and the drain of the first transistor; a capacitor element is coupled to the drain of the first transistor; and the second branch further includes a second transistor having a source coupled to the second source degeneration element.

[0106] Aspect 21: The method according to aspect 20, wherein: the current mode filter circuit further includes a second resistor element; the gate of the first transistor is coupled to a first terminal of the second resistor element; a second terminal of the second resistor element is coupled to the gate of the second transistor; and the first resistor element includes a first terminal coupled to the drain of the first transistor and includes a second terminal coupled to the second terminal of the second resistor element and the gate of the second transistor.

[0107] Aspect 22: The method according to aspect 21, the method further includes: adjusting the resistance of at least one of the first resistor element or the second resistor element.

[0108] Aspect 23: The method according to aspect 21 or 22, the method further includes: driving a control input of a switch using a switch driver, wherein the switch is coupled in series with the first branch of the current mode filter circuit, and wherein a third resistor element is coupled between an output of the switch driver and the control input of the switch.

[0109] Aspect 24: The method according to aspect 18, wherein: the first branch further includes a first transistor, the first transistor includes a source coupled to the first source degeneration element and includes a gate coupled to the drain of the first transistor; the second branch further includes a second transistor, the second transistor includes a source coupled to the second source degeneration element; the first branch further includes a third transistor, the third transistor includes a drain coupled to the drain of the first transistor; and the current mode filter circuit further includes: a first capacitor element, the first capacitor element is coupled in parallel with the first branch; a second capacitor element, the second capacitor element is coupled between the source and the gate of the third transistor; and a first resistor element, the first resistor element is coupled to the gate of the third transistor.

[0110] Aspect 25: The method according to aspect 24, the method further includes adjusting at least one of the capacitance of the first capacitor element, the capacitance of the second capacitor element, or the resistance of the first resistor element.

[0111] Aspect 26: The method according to aspect 24 or 25, wherein the current mode filter circuit further includes: a fourth transistor, the fourth transistor includes a drain coupled to the first resistor element and includes a gate coupled to the source of the third transistor; a current source, the current source is coupled to the drain of the fourth transistor; and a second resistor element, the second resistor element is coupled between the first capacitor element and the source of the third transistor.

[0112] Additional considerations

[0113] The foregoing description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the functionality and arrangement of the elements discussed without departing from the scope of the present disclosure. Various examples may omit, substitute, or add various processes or components as appropriate. For example, the methods described may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described relative to some examples may be combined in some other examples. For instance, any number of the aspects set forth herein may be used to implement an apparatus or practice a method. Further, the scope of the present disclosure is intended to cover such apparatus or methods practiced using other structures, functional features, or a combination of structures and functional features in addition to or different from the various aspects of the present disclosure given herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the present invention. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0114] The various operations of the above-described method may be performed by any suitable component capable of performing the corresponding functions. The component may include various hardware and / or software components and / or modules, including but not limited to circuitry, an application specific integrated circuit (ASIC), or a processor. Generally, where there are operations illustrated in the figures, these operations may have corresponding component-plus-function components.

[0115] As used herein, the phrase referring to a list of items "at least one of" refers to any combination of those items (which includes a single member). For example, "at least one of a, b, or c" is intended to cover: a, b, c, a - b, a - c, b - c, and a - b - c, as well as any combination having multiple identical elements (e.g., a - a, a - a - a, a - a - b, a - a - c, a - b - b, a - c - c, b - b, b - b - b, b - b - c, c - c, and c - c - c or any other ordering of a, b, and c).

[0116] The methods disclosed herein include one or more steps or acts for implementing the described methods. The steps and / or acts of the method may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of the steps or acts is specified, the order and / or use of specific steps and / or acts may be modified without departing from the scope of the claims.

[0117] It should be understood that the claims are not limited to the exact configurations and components illustrated above. Various modifications, variations, and alterations can be made to the arrangements, operations, and details of the methods and apparatuses described above without departing from the scope of the claims.

Claims

1. A filter circuit, the filter circuit comprising: An input node; An output node; A power supply node; A first transistor, the first transistor comprising a drain coupled to the input node; A second transistor, the second transistor comprising a drain coupled to the output node and comprising a gate coupled to the gate of the first transistor; A capacitive element, the capacitive element being coupled between the drain of the first transistor and the power supply node; A first resistive element, the first resistive element being coupled between the drain and the gate of the first transistor; A first source degeneration element, the first source degeneration element being coupled between the source of the first transistor and the power supply node; And A second source degeneration element, the second source degeneration element being coupled between the source of the second transistor and the power supply node.

2. The filter circuit according to claim 1, the filter circuit further comprising a second resistive element, the second resistive element comprising a first terminal coupled to the gate of the first transistor and comprising a second terminal coupled to the gate of the second transistor, wherein the first resistive element comprises a first terminal coupled to the drain of the first transistor and comprises a second terminal coupled to the second terminal of the second resistive element and to the gate of the second transistor.

3. The filter circuit according to claim 2, the filter circuit further comprising: A switch, the switch being coupled between the input node and the drain of the first transistor; A switch driver; And A third resistive element, the third resistive element being coupled between the control input of the switch and the output of the switch driver.

4. The filter circuit according to claim 2, wherein at least one of the first resistive element or the second resistive element is adjustable to provide a variable resistance.

5. The filter circuit according to claim 1, the filter circuit further comprising: A switch, the switch being coupled between the input node and the drain of the first transistor; A switch driver; And A second resistive element, the second resistive element being coupled between the control input of the switch and the output of the switch driver.

6. The filter circuit according to claim 1, wherein the first source degeneration element comprises a second resistive element, and wherein the second source degeneration element comprises a third resistive element.

7. The filter circuit according to claim 1, wherein: The first source degeneration element comprises a third transistor, the third transistor comprising a drain coupled to the source of the first transistor and comprising a source coupled to the power supply node; and The second source degeneration element comprises a fourth transistor, the fourth transistor comprising a drain coupled to the source of the second transistor and comprising a source coupled to the power supply node.

8. The filter circuit according to claim 7, wherein the third transistor comprises a gate coupled to the gate of the fourth transistor and to the gate of the second transistor.

9. A transmitter circuit, the transmitter circuit comprising the filter circuit of claim 1, the transmitter circuit further comprising: A digital-to-analog converter, the digital-to-analog converter comprising an output coupled to the input node of the filter circuit; And A mixer, the mixer comprising an input coupled to the output node of the filter circuit.

10. A filter circuit, the filter circuit comprising: An input node; An output node; A power supply node; A first capacitive element, the first capacitive element being coupled between the input node and the power supply node; A first transistor; A second transistor, the second transistor comprising a drain coupled to the output node and comprising a gate coupled to the gates and drains of the first transistor; A third transistor, the third transistor comprising a drain coupled to the drain of the first transistor and comprising a source coupled to the input node; A second capacitive element, the second capacitive element being coupled between the source and the gate of the third transistor; A first resistive element, the first resistive element being coupled between the gate of the third transistor and the bias node of the filter circuit; A first source degeneration element, the first source degeneration element being coupled between the source of the first transistor and the power supply node; And A second source degeneration element, the second source degeneration element being coupled between the source of the second transistor and the power supply node.

11. The filter circuit according to claim 10, wherein at least one of the second capacitive element or the first resistive element is adjustable.

12. The filter circuit according to claim 10, wherein the first source degeneration element comprises a second resistive element, and wherein the second source degeneration element comprises a third resistive element.

13. The filter circuit according to claim 10, wherein: The first source degeneration element comprises a fourth transistor, the fourth transistor comprising a drain coupled to the source of the first transistor and comprising a source coupled to the power supply node; and The second source degeneration element comprises a fifth transistor, the fifth transistor comprising a drain coupled to the source of the second transistor and comprising a source coupled to the power supply node.

14. The filter circuit according to claim 13, wherein the fifth transistor comprises a gate coupled to the gate of the fourth transistor and to the gate of the second transistor.

15. The filter circuit according to claim 10, the filter circuit further comprising: A switch, the switch being coupled between the input node and the source of the third transistor; A switch driver; And A second resistive element, the second resistive element being coupled between the control input of the switch and the output of the switch driver.

16. The filter circuit according to claim 10, the filter circuit further comprising: A fourth transistor, the fourth transistor comprising a source coupled to the bias node, comprising a drain coupled to the first resistive element and comprising a gate coupled to the source of the third transistor; A current source, the current source being coupled between the drain of the fourth transistor and the power supply node; and A second resistor element, the second resistor element being coupled between the input node and the source of the third transistor.

17. A transmitter circuit, the transmitter circuit comprising the filter circuit of claim 10, the transmitter circuit further comprising: A digital-to-analog converter, the digital-to-analog converter including an output coupled to the input node of the filter circuit; and A mixer, the mixer including an input coupled to the output node of the filter circuit.

18. A filtering method, the method comprising: Receiving an input signal at a first branch of a current-mode filter circuit; and Filtering the received input signal using the current-mode filter circuit to generate an output signal at a second branch of the current-mode filter circuit, wherein the first branch includes a first source degeneration element, and wherein the second branch includes a second source degeneration element.

19. The method according to claim 18, wherein the first source degeneration element includes a first transistor, and wherein the second source degeneration element includes a second transistor.

20. The method according to claim 18, wherein: The first branch further includes a first transistor, the first transistor including a source coupled to the first source degeneration element; A first resistor element is coupled between the gate and the drain of the first transistor; A capacitive element is coupled to the drain of the first transistor; and The second branch further includes a second transistor, the second transistor including a source coupled to the second source degeneration element.

21. The method according to claim 20, wherein: The current-mode filter circuit further includes a second resistor element; The gate of the first transistor is coupled to a first terminal of the second resistor element; A second terminal of the second resistor element is coupled to the gate of the second transistor; and The first resistor element includes a first terminal coupled to the drain of the first transistor and includes a second terminal coupled to the second terminal of the second resistor element and to the gate of the second transistor.

22. The method according to claim 21, the method further comprising: Adjusting the resistance of at least one of the first resistor element or the second resistor element.

23. The method according to claim 21, the method further comprising: Driving a control input of a switch using a switch driver, wherein the switch is serially coupled to the first branch of the current-mode filter circuit, and wherein a third resistor element is coupled between an output of the switch driver and the control input of the switch.

24. The method according to claim 18, wherein: The first branch further includes a first transistor, the first transistor including a source coupled to the first source degeneration element and including a gate coupled to the drain of the first transistor; The second branch further includes a second transistor, the second transistor including a source coupled to the second source degeneration element; The first branch further includes a third transistor, the third transistor including a drain coupled to the drain of the first transistor; and The current mode filter circuit further comprises: a first capacitive element, the first capacitive element being coupled in parallel with the first branch; a second capacitive element, the second capacitive element being coupled between the source and the gate of the third transistor; and a first resistive element, the first resistive element being coupled to the gate of the third transistor.

25. The method according to claim 24, the method further comprising adjusting at least one of a capacitance of the first capacitive element, a capacitance of the second capacitive element, or a resistance of the first resistive element.

26. The method according to claim 24, wherein the current mode filter circuit further comprises: a fourth transistor, the fourth transistor comprising a drain coupled to the first resistive element and comprising a gate coupled to the source of the third transistor; a current source, the current source being coupled to the drain of the fourth transistor; and a second resistive element, the second resistive element being coupled between the first capacitive element and the source of the third transistor.

Images