Split switch structure, radio frequency switch, electronic product, and base station

Abstract

The present invention provides a split switch structure, a radio frequency switch, an electronic product, and a base station. The split switch structure comprises a single-pole N-throw switch, wherein N is a natural number greater than or equal to 1. The single-pole N-throw switch comprises N switch paths; each switch path is opened and closed by turning on and off a switch transistor; and devices in the single-pole N-throw switch are arranged on at least two chips. Pads corresponding to contacts of the single-pole N-throw switch meet the isolation requirement in terms of distance. According to the split switch structure and the electronic product of the present invention, splitting devices of a single-pole multi-throw switch onto at least two chips reduces chip area and cost, and isolation is improved by means of flexible spatial arrangement, thereby achieving both high isolation and low cost. Therefore, the split switch structure and the electronic product are suitable for large-scale production and application.

Description

Split switch structure, radio frequency switch, electronic product and base station Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a split switch structure, a radio frequency switch, an electronic product and a base station. Background Art

[0002] Single-pole multi-throw (SPNT) switches are one of the most commonly used devices in the circuit field, and are particularly widely used in communications, radar, electronic countermeasures, and other fields. SPNT switches can be used to switch between different paths.

[0003] Existing single-pole multi-throw switches are set on a chip. To improve isolation, the pads (PADs) of the SPMT switch need to be as far apart as possible. This results in a larger chip size for manufacturing the SPMT switch and correspondingly increased costs. Conversely, to reduce costs, the chip area is reduced, resulting in insufficient isolation between the signals.

[0004] Therefore, how to propose a single-pole multi-throw switch that takes into account both high isolation and low cost has become one of the problems that need to be solved urgently by those skilled in the art.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art.

[0006] Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a split switch structure, a radio frequency switch, an electronic product and a base station, which are used to solve the problem that the single-pole multi-throw switch in the prior art is difficult to achieve both high isolation and low cost.

[0008] To achieve the above-mentioned and other related objectives, the present invention provides a split switch structure, comprising:

[0009] A single-pole N-throw switch, where N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch includes N switch paths, each switch path is switched by turning on and off a switch tube, and the components in the single-pole N-throw switch are arranged on at least two chips.

[0010] Optionally, the split switch structure further includes a packaging shell, the single-pole N-throw switch is disposed in the packaging shell, and each pad of the single-pole N-throw switch is electrically connected to a corresponding pin on the packaging shell.

[0011] Optionally, each switching path includes M levels of switching tubes and m levels of pull-down modules, where M is a natural number greater than or equal to 1, and m is a natural number greater than or equal to 0 and less than or equal to M+1; when the number M of switching tubes in a switching path is greater than or equal to 2, the switching tubes at each level are cascaded in sequence; one end of each pull-down module is connected to one end of the corresponding switching tube, and the other end is grounded or connected to a specific impedance; the number M of switching tubes and the number m of pull-down modules in each switching path are the same or different.

[0012] More optionally, the pull-down module includes P-level transistors, P is a natural number greater than or equal to 1, and when P is greater than or equal to 2, transistors of each level are connected in series in sequence; the number P of transistors in each pull-down module is the same or different.

[0013] More optionally, the switch tube is an NMOS tube, and the transistor in the pull-down module is an NMOS tube.

[0014] More optionally, when N is greater than or equal to 2, the N switch paths are provided on at least two chips, and the same switch path is located on the same chip.

[0015] More optionally, the n1 switch path in the single-pole N-throw switch is provided on the first chip, and the n2 switch path is provided on the second chip; n1+n2=N, and n1 is a natural number greater than or equal to 1 and less than N.

[0016] More optionally, when n2 is greater than or equal to 2, the number of the second chips is set to n2, and taking a switch path as a unit, n2 switch paths are respectively provided on the n2 second chips in a one-to-one correspondence.

[0017] More optionally, at least one of the N switch paths is split into at least two parts, and the parts of the same switch path are located on different chips.

[0018] More optionally, the n3 switch paths in the single-pole N-throw switch are arranged on the first chip; the n4 switch paths are divided into a first section and a second section, wherein the first section of each switch path is arranged on the first chip, and the second section of each switch path is arranged on the second chip; n3+n4=N, where n4 is a natural number greater than or equal to 1 and less than or equal to N.

[0019] More optionally, the first section and the second section of each switch path are connected in series, and one ends of the N switch paths on the first chip are connected together.

[0020] More optionally, when N and n4 are both greater than or equal to 2, the number of the second chips is set to n4, and taking a switch path as a unit, the n4 switch paths are respectively provided on the n4 second chips in a one-to-one correspondence.

[0021] More optionally, the circuit structures on each second chip are the same.

[0022] More optionally, the pins on the packaging shell include 1 antenna pin and N radio frequency pins.

[0023] To achieve the above-mentioned and other related objectives, the present invention provides a split switch structure, comprising:

[0024] A single-pole N-throw switch, where N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch includes N switch paths;

[0025] Wherein, at least one of the switch paths is located on at least two chips.

[0026] More optionally, at least one of the switch paths is located on the same chip.

[0027] More optionally, each of the switch paths is located on a different chip.

[0028] More optionally, the switch path includes a first chip and a second chip, and the circuit structures of the first chips of different switch paths are the same.

[0029] More optionally, the switch path includes a first chip and a second chip, and the circuit structures of the second chips of different switch paths are the same.

[0030] More optionally, the circuit structure of each of the switch paths is the same.

[0031] More optionally, the N switch paths include a first switch path and a second switch path, and the circuit structures of the first switch path and the second switch path are different.

[0032] More optionally, each chip includes: at least two pads, and the pads are used to electrically connect the chip (current chip) with another chip (target chip) or a packaging shell.

[0033] More optionally, it further includes: a packaging shell, used to package the single-pole N-throw switch in the packaging shell.

[0034] More optionally, the packaging shell includes: 1 antenna pin and N radio frequency pins;

[0035] wherein the antenna pins are all electrically connected to one end of all the N-way switch paths;

[0036] The N radio frequency pins are electrically connected to the other ends of the N switch paths in a one-to-one correspondence.

[0037] More optionally, it further includes: metal leads or substrates for electrically connecting different chips.

[0038] More optionally, each of the switch paths includes: M switch tubes; when the number M of the switch tubes in a switch path is greater than or equal to 2, the switch tubes are cascaded in sequence, and M is a natural number greater than or equal to 1.

[0039] More optionally, the switch path further includes: m pull-down modules, where m is a natural number greater than or equal to 0 and less than or equal to M-1; one end of each pull-down module is connected to one end of the corresponding switch tube, and the other end is grounded or connected to a specific impedance.

[0040] More optionally, the pull-down module includes P transistors, where P is a natural number greater than or equal to 1, and when P is greater than or equal to 2, the transistors are connected in series in sequence.

[0041] More optionally, the switch tube is an NMOS tube, and the transistor in the pull-down module is an NMOS tube.

[0042] In another aspect, the present invention provides a radio frequency switch, which at least includes: the split switch structure as described above.

[0043] On the other hand, the present invention provides an electronic product, which includes at least: a data receiving component and a data sending component, and the data receiving component and the data sending component both include: the radio frequency switch as described above.

[0044] On the other hand, the present invention provides a base station, wherein the base station is provided with a radio frequency switch unit, and the radio frequency switch unit includes the radio frequency switch as described above.

[0045] As described above, the split switch structure, radio frequency switch, electronic product, and base station of the present invention have the following beneficial effects:

[0046] The split switch structure of the present invention splits the original large single-pole, N-throw switch chip into at least two chips. Because the two chips are spaced apart, the overall isolation of the switch is higher. Furthermore, the spacing between the two pads in a single switch path does not need to be considered during manufacturing. By reducing the spacing between the two pads in a single switch path, the total chip area is relatively smaller. This reduction in overall chip area also reduces chip manufacturing costs. Furthermore, the smaller chip size makes it easier to place the chip in a suitable location. Electrical connections between the chips are achieved through metal leads or a substrate, significantly increasing flexibility and further contributing to the optimization of isolation and other indicators. (Once the chip sizes are determined, the distance between the chips can be increased as needed to achieve higher isolation.)

[0047] The cost and isolation requirements of the split switch structure of the present invention are not mutually restricted, and high isolation can be achieved while taking low cost into account, and is suitable for large-scale production and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a schematic diagram showing the structure of a single-pole triple-throw switch chip.

[0049] FIG2 is a schematic diagram showing the circuit structure of a single-pole N-throw switch according to the present invention.

[0050] FIG3 is a schematic diagram showing a splitting method of a single-pole N-throw switch according to the present invention.

[0051] FIG4 is a schematic diagram showing a split switch structure corresponding to the splitting method of FIG3 .

[0052] FIG5 is a schematic diagram showing another splitting method of the single-pole N-throw switch of the present invention.

[0053] FIG6 is a schematic diagram showing the split switch structure corresponding to the splitting method of FIG5 .

[0054] FIG. 7 is a schematic diagram showing another disassembly method of the single-pole N-throw switch of the present invention.

[0055] FIG8 is a schematic diagram showing another disassembly method of the single-pole N-throw switch of the present invention.

[0056] FIG9 is a schematic diagram showing the split switch structure corresponding to the splitting method of FIG7 and FIG8.

[0057] Component Reference Numbers 1 SP3T switch chip 10 Package housing 101, 102, 103, 104 Pins 11 Chip 12, 13, 14, 15 Pads 2 Split switch structure 20 Package housing 21 SP3T switch 211 Switch tube 212 Pull-down module 21a First switch path 21b Second switch path 21c Third switch path 21d Fourth switch path 22 First chip 23, 23a, 23b, 23c Second chip DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please refer to Figures 1 to 9. It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concepts of the present invention. Therefore, the diagrams only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of the components can be varied arbitrarily, and the component layout can be more complex. As shown in Figure 1, a single-pole, triple-throw switch chip 1 is shown. The switch is fabricated on a chip 11 within a housing 10. The four pads 12, 13, 14, and 15 of the switch are connected to pins 101, 102, 103, and 104, respectively. The distance between the pads must meet isolation requirements. In this solution, high isolation results in a larger chip area; a smaller chip area results in poor isolation; these two factors are mutually restrictive. To balance isolation and cost, the distance between the pads can be set to just meet the isolation requirement to minimize chip size. However, this results in poor isolation and cost performance, making it impossible to achieve both high isolation and low cost.

[0060] In order to achieve low cost and high isolation, the present invention proposes a split switch structure 2, which includes:

[0061] A single-pole N-throw switch 21, where N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch 21 includes N switch paths, each switch path is switched on and off by a switch tube; the components of the single-pole N-throw switch 21 are arranged on at least two chips; and the distance between the pads corresponding to the contacts of the single-pole N-throw switch meets the isolation requirement.

[0062] Specifically, the single-pole N-throw switch 21 can be configured as a single-pole single-throw switch, a single-pole double-throw switch, a single-pole triple-throw switch, or a single-pole multi-throw switch that provides more paths as needed.

[0063] Specifically, in one example, each chip of the single-pole N-throw switch 21 can be used as an independent individual in the circuit, that is, each pad of the single-pole N-throw switch 21 is directly electrically connected to other devices without connecting to the package pins (that is, the RF pins or antenna pins). In another example, each chip of the single-pole N-throw switch 21 is packaged in a package shell 20 and used as a whole in the circuit. In this case, the split switch structure 2 also includes a package shell 20, the single-pole N-throw switch 21 is arranged in the package shell 20, and each pad of the single-pole N-throw switch 21 is electrically connected to the corresponding pins on the package shell 20; in this embodiment, the pins on the package shell 20 include an antenna pin ANT and N RF pins RF1, RF2...RFN, that is, N RF channels share one antenna through time division multiplexing; each pin is electrically connected to the corresponding pad through a packaging method such as a metal lead or a substrate. In actual use, the application of the split switch structure 2 can be set according to needs, and the definition of each pin can be configured, which is not limited to this embodiment.

[0064] Specifically, as shown in Figure 2, in this embodiment, each switch path includes M-level switches 211 and m-level pull-down modules 212, where M is a natural number greater than or equal to 1, and m is a natural number greater than or equal to 0 and less than or equal to M+1. When the number M of switches 211 in a switch path is greater than or equal to 2, the switch paths 211 are connected in cascade. The number M of switches 211 is determined based on design requirements. One end of each pull-down module 212 is connected to the connection node of the corresponding switch 211 (the pull-down module can be provided at the input and / or output of each switch), and the other end is connected to ground or a specific impedance (the impedance value is set as required). The pull-down modules 212 are used to improve isolation between switch paths (when the current switch path is off, the connection node between the switch paths is configured to a preset potential). The number m of pull-down modules 212 is determined based on design requirements; a larger m value indicates higher isolation between channels. The number M of switch tubes 211 in each switch path can be configured to be the same or different. Similarly, the number m of pull-down modules 212 in each switch path can be configured to be the same or different, depending on actual needs. In this embodiment, the structure and number of components of each switch path are the same.

[0065] More specifically, as an example, the switch transistor 211 is configured as an NMOS transistor, wherein each NMOS transistor is connected in series, the drain of the preceding NMOS transistor is connected to the source of the succeeding NMOS transistor, the source of the first-stage NMOS transistor is connected to the antenna pin ANT (moving contact), and the source of the last-stage NMOS transistor is connected to the corresponding RF pin (static contact). The pull-down module 212 includes a P-stage NMOS transistor, where P is a natural number greater than or equal to 1. When P is greater than or equal to 2, each stage of the NMOS transistor is connected in series, wherein each NMOS transistor is connected in series, the source of the preceding NMOS transistor is connected to the drain of the succeeding NMOS transistor, the drain of the first-stage NMOS transistor is connected to the connection node of the two adjacent switching transistors, and the source of the last-stage NMOS transistor is grounded. The number P of cascaded NMOS transistors in the pull-down module 212 is determined according to design requirements; the number P of NMOS transistors in each pull-down module 212 can be configured to be the same or different. In this example, the number P of NMOS transistors in each pull-down module 212 is the same.

[0066] It is understandable that the device may be the aforementioned switch tube 211 and / or the NMOS tube in each pull-down module 212 .

[0067] It should be noted that in actual use, the structure and device type of each switch path can be set as needed. Any circuit structure that can realize switching operation and meet signal transmission requirements is applicable to the present invention and is not limited to this embodiment.

[0068] The single-pole, N-throw (SPN-T) switch of the present invention is split into at least two parts, each of which is fabricated on a different chip. The splitting pattern can be configured based on actual needs, including but not limited to: when N is greater than or equal to 2, N switching paths are provided on at least two chips, with the same switching path located on the same chip; at least one of the N switching paths is split into at least two parts, with each part of the same switching path located on a different chip. The switching control signals for each switching path are controlled by a control module, which can be provided on any chip or chips on which the SPN-throw switch is provided, or on another chip.

[0069] Several specific implementations of the split switch structure 2 are listed below and described.

[0070] As shown in Figures 3 to 6, in this embodiment, the n1 switch path in the single-pole N-throw switch 21 is set on the first chip, and the n2 switch path is set on the second chip; n1+n2=N, n1 is a natural number greater than or equal to 1 and less than N, that is, each switch path is split as a whole, with one part set on the first chip and the other part set on the second chip.

[0071] Specifically, when n2 is greater than or equal to 2, the switch path set on the second chip can be further split into switch path units, that is, the second chip includes at least two; as an example, the number of second chips is set to n2, and in switch path units, n2 switch paths are respectively set one-to-one on n2 second chips.

[0072] As shown in Figures 3 and 5, in this embodiment, N is set to 4, n1 is set to 2, and n2 is set to 2. The single-pole N-throw switch 21 is a single-pole four-throw switch, including a first switch path 21a, a second switch path 21b, a third switch path 21c, and a fourth switch path 21d. Each switch path has the same structure, including five switching transistors and four pull-down modules. The switching transistors at each stage are cascaded, and the pull-down modules at each stage are located between two adjacent switching transistors. Each pull-down module includes two cascaded NMOS transistors.

[0073] As an example, as shown in Figure 3, the chip for setting the single-pole four-throw switch includes (one) a first chip 22 and (one) a second chip 23; the first switch path 21a and the second switch path 21b are set on the first chip 22, and the third switch path 21c and the fourth switch path 21d are set on the second chip 23; as shown in Figure 4, the moving contact of the single-pole four-throw switch is split into two, located on the first chip 22 and the second chip 23 respectively. The two moving contacts can be electrically connected through metal leads or substrates, or directly electrically connected to corresponding pins through metal leads or substrates. Since the four-way switch paths are split onto two chips, the position arrangement between the pads is more flexible while meeting the isolation requirements. The sum of the sizes of the first chip 22 and the second chip 23 is smaller than the size of the chip when the four-way switch paths are set on the same chip, meeting the requirements of reducing costs and ensuring isolation.

[0074] As another example, as shown in FIG5 , the chip for setting the single-pole four-throw switch includes (one) first chip 22 and (two) second chips 23a and 23b; the first switch path 21a and the second switch path 21b are set on the first chip 22, the third switch path 21c is set on the second chip 23a, and the fourth switch path 21d is set on the second chip 23b; as shown in FIG6 , the moving contacts of the single-pole four-throw switch are split into three, which are respectively located on the first chip 22, the second chip 23a and 23b. The three moving contacts can be electrically connected through metal leads or substrates, or directly electrically connected to corresponding pins through metal leads or substrates. The four switch paths are split on three chips, which can achieve low cost and high isolation requirements.

[0075] It should be noted that in the examples shown in Figures 3 and 4, if the structures of the switch paths on the first chip 22 and the second chip 23 are the same (the number of devices and the connection relationship are the same), then the first chip and the second chip are the same chip, which can simplify the preparation process (only one chip needs to be prepared) and reduce the pressure of stocking inventory. Similarly, in the examples shown in Figures 5 and 6, the switch paths on the second chips 23a and 23b can also be configured with the same structure. In actual use, the structure of each switch path and the switch path structure on each chip can be set as needed; in addition, based on this embodiment, each switch path can also be further divided into at least two sections, and each section is set on a different chip (for example, the third chip, the fourth chip...), further improving flexibility and reducing costs, which will not be described in detail here.

[0076] Based on the above embodiments, in one embodiment of the present specification, as shown in Figures 7 to 9, the n3 switch paths in the single-pole N-throw switch 21 are arranged on the first chip; the n4 switch paths are divided into a first part (including at least one device) and a second part (including at least one device), wherein the first part of each switch path is arranged on the first chip, and the second part of each switch path is arranged on the second chip; n3+n4=N, n4 is a natural number greater than or equal to 1 and less than or equal to N (when N=1, n3=0, n4=1); that is, at least one switch path is split into two parts, and the two parts are arranged on different chips.

[0077] Specifically, in this embodiment, each switch path is divided into a first section and a second section (two parts). Both the first section and the second section are continuous circuit structures. The first section and the second section of each switch path are connected in series. One end of the N switch paths on the first chip is connected together; that is, a switch path is divided into two continuous sections, and the first section and the second section are connected in series to form a complete switch path. In actual use, the first and second sections can be configured as discontinuous circuit structures. For example, a switch path can be divided into three sections in a cascade order, with the first section belonging to the first section, the middle section belonging to the second section, and the last section belonging to the first section. In this case, additional pads and metal leads are required to achieve electrical connection of the switch paths, while still achieving low cost and high isolation.

[0078] Specifically, when N and n4 are both greater than or equal to 2, the switch paths provided on the second chip can be further split into switch path units, that is, the second chip includes at least two; the number of second chips is set to n4, and in switch path units, the n4 switch paths are respectively provided on the n4 second chips in a one-to-one correspondence.

[0079] As shown in Figures 7 and 8, in this embodiment, N is set to 3, n3 is set to 0, and n4 is set to 3. The single-pole, N-throw switch 21 is a single-pole, three-throw switch, comprising a first switch path 21a, a second switch path 21b, and a third switch path 21c. Each switch path has the same structure, including five switching transistors and four pull-down modules. Each switching transistor is cascaded, and each pull-down module is located between two adjacent switching transistors. Each pull-down module comprises two cascaded NMOS transistors.

[0080] As an example, as shown in Figure 7, the chip used to configure the single-pole, triple-throw switch includes one first chip 22 and three second chips 23a, 23b, and 23c. The first switch path 21a, the second switch path 21b, and the third switch path 23c are each divided into a first portion and a second portion. The first portion includes two-stage switching transistors and a two-stage pull-down module, while the second portion includes three-stage switching transistors and a two-stage pull-down module. The first portion of each switch path is configured on the first chip 22, the second portion of the first switch path 21a is configured on the second chip 23a, the second portion of the second switch path 21b is configured on the second chip 23b, and the second portion of the third switch path 21c is configured on the second chip 23c. Since the second portions of each second portion have the same structure, the second chips are identical.

[0081] As another example, as shown in FIG8 , the chip for configuring the single-pole, triple-throw switch includes (one) first chip 22 and (three) second chips 23a, 23b, and 23c. The first switch path 21a, the second switch path 21b, and the third switch path 23c are each divided into a first portion and a second portion. The first portion of the first switch path 21a includes a first-stage switch transistor and a first-stage pull-down module, while the second portion includes a fourth-stage switch transistor and a third-stage pull-down module. The first portion of the second switch path 21b includes a second-stage switch transistor and a second-stage pull-down module, while the second portion includes a third-stage switch transistor and a second-stage pull-down module. The first portion of the third switch path 21c includes a third-stage switch transistor and a third-stage pull-down module, while the second portion includes a second-stage switch transistor and a first-stage pull-down module. The first portion of each switch path is configured on the first chip 22, the second portion of the first switch path 21a is configured on the second chip 23a, the second portion of the second switch path 21b is configured on the second chip 23b, and the second portion of the third switch path 21c is configured on the second chip 23c. In this example, each second chip is a different chip.

[0082] As shown in Figure 9, one end of the first part of each switch path on the first chip 22 is connected together as a moving contact, and the other end is connected to one end of the corresponding second part on each second chip. The other end of the second part on each second chip serves as a static contact. The electrical connection between the chips is achieved through metal leads or substrates. The size of the first chip is greatly reduced, and the position of each second chip can be set as needed. Therefore, low cost and high isolation can be effectively taken into account.

[0083] It should be noted that the second part of each switch path can be set on a second chip; the circuit structure of the first part of each switch path can be set to be different, and the circuit structure of the second part of each switch path can also be set to be different; of course, each switch path can also be divided into three or more parts, each part is set on a different chip (for example, the third chip, the fourth chip...), and the complete switch path is obtained in sequence through the first chip, the second chip, the third chip...; I will not go into details here.

[0084] In summary, the present invention can meet the isolation requirements of each pad by placing each chip position, and each chip is electrically connected through a metal lead or substrate to realize the circuit structure of the single-pole N-throw switch 21. At the same time, the area of ​​the chip can be greatly reduced. In one scheme, when the circuit structure is exactly the same, compared with the single-pole multi-throw switch in Figure 1, the total area of ​​the chip in the split switch structure of the present invention is reduced to 40% of the scheme in Figure 1. The splitting method of the single-pole N-throw switch of the present invention needs to be determined in combination with the application scenario, performance requirements, packaging requirements, cost, etc. There is no absolute limit on the number and form. Any scheme of splitting the single-pole N-throw switch 21 and setting it on different chips falls within the scope of protection of the present invention and will not be described in detail here.

[0085] The present invention further provides an electronic product, which at least comprises: the split switch structure 2 of the present invention. The electronic product includes but is not limited to electronic switches and communication equipment, which are not described in detail here.

[0086] The present invention further provides a base station, wherein the base station is provided with a radio frequency switch unit, wherein the radio frequency switch unit includes the radio frequency switch described above. The radio frequency switch unit includes but is not limited to a radio frequency switch, a data receiving and transmitting subunit, etc., which are not described in detail here.

[0087] In summary, the present invention provides a split switch structure, a radio frequency switch, an electronic product and a base station, comprising: a single-pole N-throw switch, where N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch comprises N switch paths, each switch path realizes switching by turning on and off a switch tube, and the components in the single-pole N-throw switch are arranged on at least two chips; the pads corresponding to the contacts of the single-pole N-throw switch meet the isolation requirements in terms of distance. The split switch structure and electronic product of the present invention split the components of the single-pole multi-throw switch onto at least two chips, thereby reducing the chip area and cost, improving the isolation through flexible spatial placement, and thus taking into account both high isolation and low cost, and are suitable for large-scale production and application. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A split switch structure, characterized in that: The split switch structure comprises: A single-pole N-throw switch, wherein N is a natural number greater than or equal to 1; wherein the single-pole N-throw switch includes N switch paths, each switch path is switched by turning on and off a switch tube, and the devices in the single-pole N-throw switch are arranged on at least two chips.

2. The split switch structure according to claim 1, characterized in that: in, At least one of the switch paths is located on at least two chips.

3. The split switch structure according to claim 1, characterized in that: Each chip comprises: at least two pads, and the pads are used to electrically connect the chip to another chip or a packaging shell.

4. The split switch structure according to claim 1, characterized in that: The split switch structure further includes a packaging shell, the single-pole N-throw switch is arranged in the packaging shell, and each pad of the single-pole N-throw switch is electrically connected to a corresponding pin on the packaging shell.

5. The split switch structure according to claim 1, characterized in that: Each switch path includes M-level switch tubes, where M is a natural number greater than or equal to 1; in a switch path where the number of switch tubes M is greater than or equal to 2, the switch tubes at each level are cascaded in sequence.

6. The split switch structure according to claim 5, characterized in that: Each switch path also includes: m-level pull-down modules, m is a natural number greater than or equal to 0 and less than or equal to M+1, one end of each pull-down module is connected to one end of the corresponding switch tube, and the other end is grounded or connected to a specific impedance; the number M of switch tubes and the number m of pull-down modules in each switch path are the same or different.

7. The split switch structure according to claim 6, characterized in that: Each of the pull-down modules includes a P-level transistor, where P is a natural number greater than or equal to 1. In a pull-down module where the number of transistors P is greater than or equal to 2, the transistors at each level are connected in series in sequence; the number of transistors P in each pull-down module is the same or different.

8. The split switch structure according to claim 7, characterized in that: The switch tube is an NMOS tube, and the transistor in the pull-down module is an NMOS tube.

9. The split switch structure according to any one of claims 1 to 8, characterized in that: N is greater than or equal to 2, N switch paths are arranged on at least two chips, and the same switch path is located on the same chip.

10. The split switch structure according to claim 9, characterized in that: In the single-pole N-throw switch, n1 switch paths are arranged on the first chip, and n2 switch paths are arranged on the second chip; n1+n2=N, and n1 is a natural number greater than or equal to 1 and less than N.

11. The split switch structure according to claim 10, characterized in that: n2 is greater than or equal to 2, the number of the second chips is n2, and taking a switch path as a unit, n2 switch paths are respectively arranged on n2 second chips in a one-to-one correspondence.

12. The split switch structure according to any one of claims 1 to 8, characterized in that: At least one of the N switch paths is divided into at least two parts, and each part of the at least two parts is located on a different chip.

13. The split switch structure according to claim 12, characterized in that: The n3 switch paths in the single-pole N-throw switch are arranged on the first chip; the n4 switch paths are divided into a first section and a second section, wherein the first section of each switch path in the n4 switch paths is arranged on the first chip, and the second section of each switch path is arranged on the second chip; n3+n4=N, n4 is a natural number greater than or equal to 1 and less than or equal to N.

14. The split switch structure according to claim 13, characterized in that: The first section and the second section of each switch path are connected in series, and one ends of the N switch paths on the first chip are connected together.

15. The split switch structure according to claim 14, characterized in that: N and n4 are both greater than or equal to 2, the number of the second chips is n4, and taking the switch path as a unit, the n4 switch paths are respectively arranged on the n4 second chips in a one-to-one correspondence.

16. The split switch structure according to claim 10 or 14, characterized in that: The circuit structures on each second chip are the same.

17. The split switch structure according to claim 1, characterized in that: Also includes: Metal leads or substrates are used to electrically connect different chips.

18. The split switch structure according to any one of claims 1 to 8, characterized in that: The pins on the packaging shell include 1 antenna pin and N radio frequency pins.

19. A radio frequency switch, characterized in that: The radio frequency switch at least includes: a split switch structure as described in any one of claims 1-18.

20. An electronic product, characterized in that: The electronic product at least includes: a data receiving component and a data sending component, and the data receiving component and the sending component both include: the radio frequency switch according to claim 19.

21. A base station, characterized in that: The base station is provided with a radio frequency switch unit, and the radio frequency switch unit at least includes the radio frequency switch according to claim 19.

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