Verification method and apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application relate to the technical field of computers, and provide a verification method and apparatus, an electronic device, and a readable storage medium. The method comprises: downloading software design into a processing system of a programmable logic chip, and burning hardware design corresponding to the software design into a programmable logic area of the programmable logic chip; synchronously operating the hardware design and the software design in the programmable logic chip, and monitoring first operation data of the hardware design and second operation data of the software design; when the first operation data and the second operation data are not matched, taking a hardware snapshot of the programmable logic chip to store state information of the programmable logic chip; and importing the state information into simulation software for simulation, so as to debug the hardware design.

Description

Verification method, device, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 17, 2023, with application number 202311345112.6 and titled “A Verification Method, Device, Electronic Device and Readable Storage Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a verification method, device, electronic device, and readable storage medium. Background Art

[0004] In related technologies, verification of High-Level Synthesis (HLS) designs usually uses software simulation. Compared with hardware simulation methods such as FPGA prototype verification and FPGA simulation, hardware-based simulation usually runs at speeds of tens or hundreds of megahertz, while software simulation is often slower, in units of tens or hundreds of kilohertz. Debugging options such as waveform dump or debug information display will further reduce the simulation speed, resulting in lower overall verification efficiency.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a verification method, device, electronic device, and readable storage medium, which can solve the problem of low verification efficiency of hardware design in related technologies.

[0007] In one aspect, an embodiment of the present application discloses a verification method, the method comprising:

[0008] Downloading the software design into a processing system of a programmable logic chip, and burning the hardware design corresponding to the software design into a programmable logic area of ​​the programmable logic chip;

[0009] Synchronously running the hardware design and the software design in the programmable logic chip, and monitoring first operating data of the hardware design and second operating data of the software design;

[0010] When the first operating data and the second operating data do not match, taking a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip;

[0011] The state information is imported into simulation software for simulation to debug the hardware design.

[0012] On the other hand, an embodiment of the present application discloses a verification device, comprising:

[0013] A pre-processing module, configured to download the software design into a processing system of a programmable logic chip and burn the hardware design corresponding to the software design into a programmable logic area of ​​the programmable logic chip;

[0014] a monitoring module, configured to synchronously run the hardware design and the software design in the programmable logic chip, and monitor first operating data of the hardware design and second operating data of the software design;

[0015] a first snapshot module, configured to take a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip when the first operating data and the second operating data do not match;

[0016] The transmission module is used to import the state information into the simulation software for simulation so as to debug the hardware design.

[0017] On the other hand, an embodiment of the present application further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned verification method.

[0018] An embodiment of the present application further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the aforementioned verification method.

[0019] The embodiments of the present application include the following advantages:

[0020] An embodiment of the present application provides a verification method that loads a hardware design onto an FPGA chip for execution, utilizing FPGA acceleration to improve verification efficiency. Furthermore, in the event that the first running data of the hardware design does not match the second running data of the software design, the error can be quickly and accurately located through a hardware snapshot, and the state information saved in the snapshot can be imported into the simulation software, allowing the hardware design to be debugged in a more fine-grained manner using the simulation software, thereby ensuring the freedom of simulation and debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] FIG1 is a flowchart of a verification method embodiment of the present application;

[0023] FIG2 is a schematic diagram of the architecture of a verification framework of the present application;

[0024] FIG3 is a structural block diagram of a verification device of the present application;

[0025] FIG4 is a structural block diagram of an electronic device for verification provided by an example of this application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0028] Method Example

[0029] The embodiment of the present application provides a verification method that can combine FPGA acceleration with software simulation to improve verification efficiency while ensuring freedom and debugging efficiency.

[0030] To facilitate understanding of the embodiments provided in this application, the following points are explained:

[0031] 1. High-Level Synthesis (HLS): High-level synthesis is a hardware design method that allows developers to use high-level languages ​​(such as C, C++, or SystemC) to describe hardware functions and behaviors, and then use high-level synthesis tools to convert these high-level language descriptions into RTL (Register Transfer Level) descriptions of hardware circuits. This method eliminates the need to manually write hardware description languages ​​(such as Verilog and VHDL) in traditional hardware design, making the hardware design process simpler and more efficient, speeding up hardware design development, lowering the hardware design threshold, and allowing more software developers to focus on functional design. However, HLS also has its limitations. For example, in some complex hardware design scenarios, manually writing RTL code may still be more efficient than the circuit obtained by automatic synthesis.

[0032] Different companies and research institutions have developed a variety of HLS tools. Some of the current mainstream HLS tools include:

[0033] i. Vitis HLS (Xilinx): Vitis HLS is an HLS tool developed by Xilinx and is a component of the Xilinx Vivado Design Suite. The primary goal of Vitis HLS is to allow hardware designers to describe hardware functionality using high-level programming languages ​​such as C / C++ and OpenCL, and then automatically convert this into optimized RTL (Register Transfer Level) code for efficient hardware acceleration on Xilinx FPGA and SoC platforms.

[0034] ii. Intel HLS Compiler (Intel FPGA): Intel HLS Compiler is an HLS tool provided by Intel FPGA (formerly Altera). It supports high-level synthesis using C / C++ and can generate optimized RTL code for Intel FPGA devices.

[0035] iii. LegUp HLS: LegUp HLS is an open source HLS tool that supports converting C code into hardware circuits on FPGA.

[0036] 2. IP (IP Core): An IP core is a pre-designed and verified hardware functional unit that can be reused in different hardware systems. It is a reusable hardware module, similar to a code library in software development. On-chip IP can include a variety of different functions, from simple logic gates and registers to complex processors, communication interfaces, graphics processing units, and more.

[0037] 3. RTL circuit: RTL (Register-Transfer Level) circuit is a common hardware description level. RTL circuit describes the behavior and structure of digital circuits and is represented using the abstraction level of the register transfer level. RTL circuit descriptions are usually written in a hardware description language (HDL), such as VHDL (VHSIC Hardware Description Language), Verilog HDL, and SystemVerilog HDL. Designers can use RTL-level descriptions to define and implement the required digital circuit functions, and then use synthesis tools to convert the RTL-level descriptions into physical implementations in the FPGA. In the field of FPGA and chip design and verification, RTL-level descriptions are very important for design, verification, and debugging. It provides a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and use appropriate tools for simulation, verification, and synthesis, ultimately generating a bitstream file that can be configured into the FPGA chip to implement specific digital circuit functions.

[0038] 4. FPGA: An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit chip with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs, adapting them to different applications and functions. FPGAs consist of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, and can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form the desired circuit structure. With FPGAs, designers can describe the desired circuit functionality using a hardware description language and, using programming tools, convert this into a bitstream compatible with the FPGA chip. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. They allow designers to implement customized functions and algorithms at the hardware level without the traditional custom integrated circuit design and manufacturing process. This makes FPGAs very useful for prototyping and rapid design iteration.

[0039] 5. Dynamic Partial Reconfiguration (DPR) of FPGA refers to the ability to reconfigure part of the circuit while the FPGA is running. In traditional FPGA design, the entire circuit usually needs to be reprogrammed and reloaded into the FPGA to change its function. However, DPR technology allows only part of the circuit to be reconfigured while the FPGA is running without affecting other running circuits. The main advantages of dynamic partial reconfiguration are its flexibility and improved resource utilization. By using DPR, multiple functional modules can be implemented in the FPGA, and each module can be independently reconfigured as needed without reloading the entire design. This flexibility enables the FPGA to adapt to a variety of application requirements, while reducing the time for reprogramming and reloading, and speeding up design iterations.

[0040] 6. FIFO: FIFO stands for "First In, First Out," and is a common queue data structure management method. In a FIFO, the first element to enter the queue is the first to be removed, and the last element to enter is the last to be removed, much like the person at the front of the queue leaves first. This data structure can be used to simulate various real-world scenarios, such as queuing and request processing. FIFO queues are often used for managing shared resources, processing tasks, and managing caches.

[0041] 1 , a flowchart of an embodiment of a verification method of the present application is shown. The method may specifically include the following steps:

[0042] Step 101: Download the software design into the processing system of the programmable logic chip, and burn the hardware design corresponding to the software design into the programmable logic area of ​​the programmable logic chip.

[0043] Step 102: synchronously run the hardware design and the software design in the programmable logic chip, and monitor first operating data of the hardware design and second operating data of the software design.

[0044] Step 103 : When the first operating data and the second operating data do not match, perform a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip.

[0045] Step 104: Import the state information into simulation software for simulation to debug the hardware design.

[0046] It should be noted that the programmable logic chip, that is, the FPGA chip (or FPGA system on chip), not only includes a programmable gate array circuit, but also includes one or more on-chip processors. Among them, the programmable gate array circuit is usually called programmable logic (PL); the on-chip processor is usually an ARM processor, called a processing system (PS). In the embodiment of the present application, the hardware design is burned on the PL end of the FPGA chip, and the software design runs on the PS end of the FPGA chip. The hardware design in this application mainly refers to the HLS design, and the software design mainly refers to the C / C++ design corresponding to the HLS design. The software design is used to achieve the same function as the hardware design.

[0047] In an embodiment of the present application, the hardware design that needs to be verified is first burned to the PL end of the FPGA chip, the software design is downloaded to the PS end of the FPGA chip, and the hardware design and software design are run synchronously on the FPGA chip. Exemplary, if a specific function verification is to be performed on the hardware design, the corresponding benchmark test program can be downloaded to the external storage device of the FPGA, for example, Double Data Rate Synchronous Dynamic Random Access Memory (DDR). Then, the FPGA chip is run, and the benchmark test program is executed synchronously by the hardware design and software design. The benchmark test program includes a series of programs for testing the performance or correctness of the design to be tested. In the actual verification process, different benchmark test programs can be generated according to different verification requirements.

[0048] If the first operating data of the hardware design and the second operating data of the software design do not match, it can be determined that the hardware design is wrong. In this case, a hardware snapshot can be taken of the entire FPGA chip to save the state information of the FPGA chip. Finally, the saved state information is imported into the simulation software for simulation, thereby debugging the design to be tested. Among them, the state information of the FPGA may include the state information of the fly-drag, on-chip memory, DSP, external devices, etc. The external device in the embodiment of the present application refers to a device mounted on the FPGA chip that belongs neither to the PL end nor to the PS end, such as an external storage device such as DDR.

[0049] With reference to Figure 2, there is shown a schematic diagram of the architecture of a verification framework provided by an embodiment of the present application. As shown in Figure 2, the verification framework includes an FPGA chip and simulation software, and the simulation software is installed in a personal computer (PC). Among them, the PL end of the FPGA chip is equipped with a hardware design and verification module, and the verification module is used to collect the operating data of the hardware design and software design and compare the two sets of data to determine whether the hardware design is wrong. The software design runs on the PS end of the FPGA chip. The external device in Figure 2 refers to a device that is installed on the FPGA chip and does not belong to the PL end or the PS end, such as an external storage device such as DDR.

[0050] Traditionally, FPGA prototyping methods only check whether the module output matches the expected results. However, if any errors are found, visibility of internal signals and intermediate results is critical for debugging. Using FPGA vendor's debugging tools (such as SignalTap and ILA) to change the analyzed signals requires recompilation, and storing more data introduces more overhead. In an embodiment of the present application, additional code can be added to the C / C++ model of the original HLS matrix multiplication to sample the internal signals of the hardware design and software design, so that the internal signals can be directly compared later. Specifically, the embodiment of the present application configures a buffer for the hardware design and software design respectively. During operation, the hardware design writes its operation data, including intermediate results and final output results, into the hardware buffer; the software design writes its operation data into the software buffer.

[0051] The verification module reads the first hardware design running data from the hardware buffer and the second software design running data from the software buffer. The module compares the first and second data sets. If the two sets of data do not match, the module determines that the hardware design has an error, interrupts the execution of the hardware and software designs, and takes a hardware snapshot of the FPGA chip, saving the FPGA chip's status information. The verification module interacts with the PC and imports the saved status information into the simulation software, which then debugs and repairs the hardware design.

[0052] The embodiment of the present application maps the hardware design and software design to the same FPGA chip for execution, and significantly improves the simulation speed by utilizing FPGA hardware acceleration. Moreover, in the event of a hardware design error, the embodiment of the present application can import the status information of the FPGA chip into the simulation software for simulation, thereby ensuring the freedom of simulation and debugging efficiency through software simulation.

[0053] Optionally, the programmable logic chip is also equipped with an external device, and the programmable logic area also includes a verification module, which is used to verify the hardware design; during operation, the hardware design interacts with the external device and / or the verification module through an on-chip bus.

[0054] In an embodiment of the present application, system-level verification of the hardware design can be implemented on the FPGA chip, that is, the hardware design can interact with other modules on the FPGA chip, such as the verification module, external devices such as DDR, etc. during operation and generate operation data. By comparing the operation data of the hardware design and the software design, it is determined whether there are errors in the hardware design.

[0055] Optionally, the programmable logic chip further includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

[0056] The embodiment of the present application can also implement unit-level verification of the hardware design on the FPGA chip, that is, only the correctness of the hardware design itself is verified, and no attention is paid to the interaction process between the hardware design and other modules, such as the verification module, external devices, etc.

[0057] Optionally, when the first operating data and the second operating data do not match, before taking a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip, the method further includes:

[0058] When all result signals of the hardware design are generated in the same iterative operation, first operation data of the hardware design is written into a hardware buffer; the first operation data includes all result signals in the iterative operation.

[0059] On the PL side, you can sample the intermediate results of each iteration of the hardware design. Because the internal result signals in the HLS-generated hardware may not be generated in the same clock cycle, the results of the same iteration in the hardware design can be synchronized before being written to the hardware buffer. In other words, when all the result signals in the same iteration are generated, all the result signals in the iteration are synchronously written to the hardware buffer.

[0060] For example, in the HLS hardware design for implementing merge sort, the output signals may include address signals and data signals. Since the output timing of the address and data signals differs, the address and data signals can be synchronized and written into the hardware buffer in the form of "address + data".

[0061] On the PS side, no additional synchronization is required because the intermediate calculation results of the software design have been identified and executed sequentially within the same iteration.

[0062] In an optional embodiment of the present application, the method further includes:

[0063] Step S11: determining a sampling condition of a first signal in the hardware design; the first signal is any signal in the hardware design;

[0064] Step S12: When the first signal satisfies the sampling condition, interrupt the operation of the hardware design, and take a hardware snapshot of the hardware design to save state information of the hardware design.

[0065] In an embodiment of the present application, a first signal of interest in the hardware design can be sampled to verify the correctness of the HLS design itself. The first signal can be any signal generated during the operation of the hardware design. During the verification process, the sampling conditions of the first signal can be pre-set. When it is determined that the sampling conditions are met, the operation of the hardware design is interrupted and a hardware snapshot of the hardware design is taken.

[0066] Exemplarily, the PL end of the FPGA chip also includes an interrupt module. During the verification process, the sampling conditions of the first signal can be set in the interrupt module. When the interrupt module determines that the sampling conditions are met, it sends an interrupt signal to the hardware design. After receiving the interrupt signal, the hardware design suspends operation. After the hardware design is safely suspended, the interrupt module only takes a hardware snapshot of the design module (including the hardware design and the functional units corresponding to the hardware design) and saves the status information of the design module. For example, the sampling conditions "signal A == x && signal B == x || signal C > x" can be set for signals signal A, signal B, and signal C. When the sampling conditions are met, the hardware design is interrupted and the status information of the design module is snapshot saved.

[0067] Furthermore, the status information of the hardware design can be imported into the simulation software for simulation, thereby realizing unit-level verification of the hardware design, that is, only the correctness of the hardware design itself is verified, without paying attention to the interaction process between the hardware design and other modules, such as verification modules, external devices, etc.

[0068] In an optional embodiment of the present application, the method further includes:

[0069] Step S21: Determine the breakpoint logic of the second signal in the hardware design; the correct value of the second signal is any value in the target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal;

[0070] Step S22: When the current value of the second signal does not conform to the breakpoint logic, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip.

[0071] It is understandable that the values ​​of some intermediate signals are correct within a certain range, and this situation cannot be directly compared with the signal values ​​in the PS end software design. In an embodiment of the present application, breakpoint logic judgments can be added for these signals. Specifically, if the current value of the second signal is any value within the target interval, no processing is performed and the hardware design is run. If the current value of the second signal does not belong to any value within the target interval, that is, the current value of the signal does not meet the breakpoint logic, in this case, the operation of the hardware design can be interrupted, and the state information of the FPGA chip can be saved by a hardware snapshot.

[0072] Furthermore, the saved state information can be imported into simulation software for simulation, thereby performing more fine-grained analysis and debugging on the second signal.

[0073] In an optional embodiment of the present application, the programmable logic area of ​​the programmable logic chip further includes a verification module, the verification module being configured to compare the first operating data and the second operating data; and when the first operating data and the second operating data do not match, performing a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip includes:

[0074] Step S31: When the amount of the first operating data and / or the second operating data is greater than or equal to a preset threshold, compress the first operating data and the second operating data to obtain first compressed data and second compressed data;

[0075] Step S32: Send the first compressed data and the second compressed data to the verification module, and compare the first compressed data and the second compressed data by the verification module;

[0076] Step S33: When the first compressed data and the second compressed data do not match, a hardware snapshot is performed on the programmable logic chip to save state information of the programmable logic chip.

[0077] If the hardware design and software design generate a large amount of operating data during operation, and the communication bandwidth of the on-chip bus is limited, it will take a long time to transmit this data, affecting the verification efficiency. Therefore, in an embodiment of the present application, if the data volume of the first operating data of the hardware design is greater than or equal to a preset threshold, and / or the data volume of the first operating data of the software design is greater than or equal to a preset threshold, a compression algorithm can be used to compress the first operating data of the hardware design and the second operating data of the software design, and then the compressed first compressed data and the second compressed data are sent to the verification module, thereby reducing the delay and resource overhead caused by data transmission.

[0078] As an example, corresponding buffers can be allocated in the FPGA chip for hardware design and software design to record operating data. Typically, the hardware buffer for recording the operating data of the hardware design and the software buffer for recording the operating data of the software design are both set at the PL end, generally in the verification module. When the amount of data is large, the hardware design and software design can first use a compression algorithm to compress the operating data separately, and then write the compressed data into the corresponding buffer. Among them, the compression algorithm may include but is not limited to algorithms such as XOR-folding, checksum, and cyclic redundancy check (CRC). Selecting the appropriate compression granularity can balance the compression rate and accuracy to quickly detect potential problems. In practical applications, the compression algorithm can be selected based on the compression granularity and compression accuracy.

[0079] In summary, the embodiment of the present application provides a verification method, which loads the hardware design onto an FPGA chip for execution, and utilizes FPGA acceleration to improve verification efficiency; and, in the case where the first running data of the hardware design does not match the second running data of the software design, the error can be quickly and accurately located through a hardware snapshot, and the state information saved in the snapshot can be imported into the simulation software, and the hardware design can be debugged in a more fine-grained manner using the simulation software, thereby ensuring the freedom of simulation and debugging efficiency.

[0080] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0081] Device embodiment

[0082] 3 , a structural block diagram of a verification device of the present application is shown. The device may specifically include:

[0083] A pre-processing module 301 is configured to download the software design into a processing system of a programmable logic chip and burn the hardware design corresponding to the software design into a programmable logic area of ​​the programmable logic chip;

[0084] A monitoring module 302 is configured to synchronously run the hardware design and the software design in the programmable logic chip, and monitor first operating data of the hardware design and second operating data of the software design;

[0085] A first snapshot module 303 is configured to take a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip when the first operating data and the second operating data do not match;

[0086] The transmission module 304 is used to import the state information into the simulation software for simulation so as to debug the hardware design.

[0087] Optionally, the programmable logic chip is also equipped with an external device, and the programmable logic area also includes a verification module, which is used to verify the hardware design; during operation, the hardware design interacts with the external device and / or the verification module through an on-chip bus.

[0088] Optionally, the programmable logic chip further includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

[0089] Optionally, the device further comprises:

[0090] The data writing module is used to write the first operation data of the hardware design into the hardware buffer when all the result signals of the hardware design in the same iterative operation are generated; the first operation data includes all the result signals in the iterative operation.

[0091] Optionally, the device further comprises:

[0092] A first determining module is configured to determine a sampling condition of a first signal in the hardware design; the first signal is any signal in the hardware design;

[0093] The second snapshot module is configured to interrupt the operation of the hardware design and take a hardware snapshot of the hardware design to save state information of the hardware design when the first signal meets the sampling condition.

[0094] Optionally, the device further comprises:

[0095] a second determination module, configured to determine a breakpoint logic of a second signal in the hardware design; a correct value of the second signal being any value within a target interval, and the breakpoint logic being configured to indicate the target interval corresponding to the second signal;

[0096] The third snapshot module is used to interrupt the operation of the hardware design and the software design when the current value of the second signal does not comply with the breakpoint logic, and to take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip.

[0097] Optionally, the programmable logic area of ​​the programmable logic chip further includes a verification module, the verification module being configured to compare the first operating data with the second operating data; and the first snapshot module including:

[0098] a compression submodule, configured to compress the first operating data and the second operating data respectively to obtain first compressed data and second compressed data when the amount of the first operating data and / or the second operating data is greater than or equal to a preset threshold;

[0099] a sending submodule, configured to send the first compressed data and the second compressed data to the verification module, and compare the first compressed data and the second compressed data by the verification module;

[0100] The snapshot submodule is configured to take a hardware snapshot of the programmable logic chip when the first compressed data and the second compressed data do not match, so as to save state information of the programmable logic chip.

[0101] In summary, the embodiment of the present application provides a verification device that loads the hardware design onto an FPGA chip for execution, and utilizes FPGA acceleration to improve verification efficiency; and, in the case where the first running data of the hardware design does not match the second running data of the software design, the error can be quickly and accurately located through a hardware snapshot, and the state information saved in the snapshot can be imported into the simulation software, and the hardware design can be debugged in a more fine-grained manner using the simulation software, thereby ensuring the freedom of simulation and debugging efficiency.

[0102] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0103] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0105] Referring to Figure 4, there is a block diagram of a structure of an electronic device for verification provided in an embodiment of the present application. As shown in Figure 4, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method of the aforementioned embodiment.

[0106] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0107] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG4 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0108] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0109] An embodiment of the present application also provides a non-temporary computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute the verification method shown in Figure 1.

[0110] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0111] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0112] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0113] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0114] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0115] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0116] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0117] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0118] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0120] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] It is understood that the embodiments described in the present disclosure may be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the modules, units, and subunits may be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, or other electronic units or combinations thereof for performing the functions described in the present disclosure.

[0122] For software implementation, the techniques described in the embodiments of the present disclosure can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of the present disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0123] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0124] The above is a detailed introduction to a verification method, device, electronic device and readable storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A verification method, the method comprising: Downloading the software design into a processing system of a programmable logic chip, and burning the hardware design corresponding to the software design into a programmable logic area of ​​the programmable logic chip; Synchronously running the hardware design and the software design in the programmable logic chip, and monitoring first operation data of the hardware design and second operation data of the software design; When the first operation data and the second operation data do not match, taking a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip; The state information is imported into simulation software for simulation to debug the hardware design.

2. The method according to claim 1, wherein: The programmable logic chip is also equipped with external devices, and the programmable logic area also includes a verification module, which is used to verify the hardware design; during the operation of the hardware design, the hardware design interacts with the external device and / or the verification module through the on-chip bus.

3. The method according to claim 1, wherein: The programmable logic chip also includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

4. The method according to claim 1, wherein: In the case where the first operation data and the second operation data do not match, before taking a hardware snapshot of the programmable logic chip to save the state information of the programmable logic chip, the method further includes: When all result signals of the hardware design in the same iterative operation are generated, first operation data of the hardware design is written into a hardware buffer; the first operation data includes all result signals in the iterative operation.

5. The method according to claim 1, wherein: The method further comprises: Determine a sampling condition of a first signal in the hardware design; the first signal is any signal in the hardware design; When the first signal meets the sampling condition, the operation of the hardware design is interrupted, and a hardware snapshot is taken of the hardware design to save state information of the hardware design.

6. The method according to claim 1, wherein: The method further comprises: Determining a breakpoint logic of a second signal in the hardware design; a correct value of the second signal is any value in a target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal; When the current value of the second signal does not conform to the breakpoint logic, the operation of the hardware design and the software design is interrupted, and a hardware snapshot is taken of the programmable logic chip to save the state information of the programmable logic chip.

7. The method according to claim 1, wherein: The programmable logic area of ​​the programmable logic chip also includes a verification module, the verification module is used to compare the first operation data and the second operation data; when the first operation data and the second operation data do not match, taking a hardware snapshot of the programmable logic chip to save the state information of the programmable logic chip, including: When the amount of the first operating data and / or the second operating data is greater than or equal to a preset threshold, compressing the first operating data and the second operating data respectively to obtain first compressed data and second compressed data; Sending the first compressed data and the second compressed data to the verification module, and comparing the first compressed data and the second compressed data by the verification module; In the case that the first compressed data and the second compressed data do not match, a hardware snapshot is performed on the programmable logic chip to save state information of the programmable logic chip.

8. The method according to claim 2, wherein: The hardware design writes the first running data into the hardware buffer; The software design writes the second operation data into the software buffer; the method also includes: The verification module reads the first operation data from the hardware buffer, reads the second operation data from the software buffer, and compares the first operation data with the second operation data.

9. The method according to claim 1, characterized in that: The status information includes status information of at least one of the programmable logic chip's on-the-fly, on-chip memory, and external devices. The external device is a device mounted on the programmable logic chip that belongs neither to the programmable logic area nor to the processing system.

10. A verification device, comprising: A preprocessing module, used to download the software design into the processing system of the programmable logic chip, and burn the hardware design corresponding to the software design into the programmable logic area of ​​the programmable logic chip; A monitoring module, configured to synchronously run the hardware design and the software design in the programmable logic chip, and monitor first operation data of the hardware design and second operation data of the software design; A first snapshot module, configured to take a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip when the first operation data and the second operation data do not match; The transmission module is used to import the state information into the simulation software for simulation so as to debug the hardware design.

11. The device according to claim 10, wherein: The programmable logic chip is also equipped with external devices, and the programmable logic area also includes a verification module, which is used to verify the hardware design; during the operation of the hardware design, the hardware design interacts with the external device and / or the verification module through the on-chip bus.

12. The device according to claim 10, wherein: The programmable logic chip also includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

13. The device according to claim 10, wherein: The device also includes: The data writing module is used to write the first operation data of the hardware design into the hardware buffer when all the result signals of the hardware design in the same iterative operation are generated; the first operation data includes all the result signals in the iterative operation.

14. The device according to claim 10, wherein: The device also includes: A first determination module is used to determine a sampling condition of a first signal in the hardware design; the first signal is any signal in the hardware design; The second snapshot module is used to interrupt the operation of the hardware design and take a hardware snapshot of the hardware design to save the state information of the hardware design when the first signal meets the sampling condition.

15. The device according to claim 10, wherein: The device also includes: A second determination module is used to determine the breakpoint logic of the second signal in the hardware design; the correct value of the second signal is any value in the target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal; The third snapshot module is used to interrupt the operation of the hardware design and the software design when the current value of the second signal does not conform to the breakpoint logic, and to take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip.

16. The device according to claim 10, wherein: The programmable logic area of ​​the programmable logic chip also includes a verification module, and the verification module is used to compare the first operation data and the second operation data; The first snapshot module includes: a compression submodule, configured to compress the first operation data and the second operation data respectively to obtain first compressed data and second compressed data when the amount of the first operation data and / or the second operation data is greater than or equal to a preset threshold; a sending submodule, configured to send the first compressed data and the second compressed data to the verification module, and compare the first compressed data and the second compressed data through the verification module; The snapshot submodule is used to take a hardware snapshot of the programmable logic chip when the first compressed data and the second compressed data do not match, so as to save the state information of the programmable logic chip.

17. The device according to claim 10, wherein: The hardware design writes the first operating data into the hardware buffer; the software design writes the second operating data into the software buffer; the verification module is used to read the first operating data from the hardware buffer, read the second operating data from the software buffer, and compare the first operating data with the second operating data.

18. An electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method as described in any one of claims 1 to 9.

19. A readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the verification method according to any one of claims 1 to 9.

20. A verification apparatus / device, comprising the apparatus / device (configured to) be used to perform the verification method according to any one of claims 1 to 9.

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