Verification method and system, chip, electronic device, and readable storage medium

Abstract

Embodiments of the present application relate to the technical field of computers, and provide a verification method and system, a chip, an electronic device, and a readable storage medium. The method comprises: a hardware design writes first operation data into a hardware buffer area in an operation process, and a software design writes second operation data into a software buffer area in the operation process; and a verification module reads the first operation data from the hardware buffer area, reads the second operation data from the software buffer area, compares the first operation data with the second operation data, and in the case that the first operation data and the second operation data do not match, interrupts the operation of the hardware design and the software design, captures a hardware snapshot of a programmable logic chip so as to store state information of the programmable logic chip, and imports the state information into simulation software for simulation so as to debug the hardware design.

Description

Verification method, chip, system, electronic device and readable storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 17, 2023, with application number 202311340379.6 and titled “A Verification Method, Chip, System, Electronic Device and Readable Storage Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a verification method, chip, system, electronic device, and readable storage medium. Background Art

[0004] In related technologies, verification of High-Level Synthesis (HLS) designs usually uses software simulation. Compared with hardware simulation methods such as FPGA prototype verification and FPGA simulation, hardware-based simulation usually runs at speeds of tens or hundreds of megahertz, while software simulation is often slower, in units of tens or hundreds of kilohertz. Debugging options such as waveform dump or debug information display will further reduce the simulation speed, resulting in lower overall verification efficiency.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a verification method, chip, system, electronic device and readable storage medium, which can solve the problem of low efficiency of hardware design verification in related technologies.

[0007] In one aspect, an embodiment of the present application discloses a verification method applied to a programmable logic chip, wherein a programmable logic region of the programmable logic chip includes a design module, a simulation module, and an onboard module, wherein the design module includes a hardware design and a functional unit corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; a software design corresponding to the hardware design runs in a processing system of the programmable logic chip, the software design being configured to implement the same functions as the hardware design; the method comprising:

[0008] The hardware design writes the first operation data into the hardware buffer during operation, and the software design writes the second operation data into the software buffer during operation;

[0009] The verification module reads the first operating data from the hardware buffer, reads the second operating data from the software buffer, and compares the first operating data with the second operating data;

[0010] In a case where the first operating data and the second operating data do not match, the verification module interrupts the operation of the hardware design and the software design, and performs a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip;

[0011] The verification module imports the status information into simulation software for simulation to debug the hardware design.

[0012] On the other hand, an embodiment of the present application discloses a programmable logic chip, wherein a programmable logic area of ​​the programmable logic chip includes a design module, a simulation module, and an onboard module, wherein the design module includes a hardware design and a functional unit corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; a processing system of the programmable logic chip runs a software design corresponding to the hardware design, wherein the software design is used to implement the same function as the hardware design;

[0013] The hardware is designed to write the first operation data into the hardware buffer during operation;

[0014] The software is designed to write the second operation data into the software buffer during operation;

[0015] The verification module is used to read the first operating data from the hardware buffer, read the second operating data from the software buffer, and compare the first operating data with the second operating data; if the first operating data and the second operating data do not match, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip; import the status information into simulation software for simulation to debug the hardware design.

[0016] In another aspect, an embodiment of the present application further discloses a verification system, comprising a programmable logic chip and a personal computer, wherein the personal computer is equipped with simulation software; a programmable logic area of ​​the programmable logic chip includes a design module, a simulation module, and an onboard module, wherein the design module includes a hardware design and a functional unit corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; a software design corresponding to the hardware design runs in a processing system of the programmable logic chip, wherein the software design is configured to implement the same functions as the hardware design;

[0017] The hardware is designed to write the first operation data into the hardware buffer during operation;

[0018] The software is designed to write the second operation data into the software buffer during operation;

[0019] The verification module is used to read the first operating data from the hardware buffer, read the second operating data from the software buffer, and compare the first operating data with the second operating data; if the first operating data and the second operating data do not match, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip; import the status information into simulation software for simulation to debug the hardware design.

[0020] On the other hand, an embodiment of the present application further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned verification method.

[0021] An embodiment of the present application further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the aforementioned verification method.

[0022] The embodiments of the present application include the following advantages:

[0023] An embodiment of the present application provides a verification method that loads a hardware design onto an FPGA chip for execution, utilizing FPGA acceleration to improve verification efficiency. Furthermore, in the event that the first running data of the hardware design does not match the second running data of the software design, the error can be quickly and accurately located through a hardware snapshot, and the state information saved in the snapshot can be imported into the simulation software, allowing the hardware design to be debugged in a more fine-grained manner using the simulation software, thereby ensuring the freedom of simulation and debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] FIG1 is a flowchart of a verification method embodiment of the present application;

[0026] FIG2 is a schematic diagram of the structure of a verification system of the present application;

[0027] FIG3 is a schematic diagram of the structure of a programmable logic chip of the present application;

[0028] FIG4 is a structural block diagram of an electronic device for verification provided by an example of this application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0031] Method Example

[0032] The embodiment of the present application provides a verification method that can combine FPGA acceleration with software simulation to improve verification efficiency while ensuring freedom and debugging efficiency.

[0033] To facilitate understanding of the embodiments provided in this application, the following points are explained:

[0034] 1. High-Level Synthesis (HLS): High-level synthesis is a hardware design method that allows developers to use high-level languages ​​(such as C, C++, or SystemC) to describe hardware functions and behaviors, and then use high-level synthesis tools to convert these high-level language descriptions into RTL (Register Transfer Level) descriptions of hardware circuits. This method eliminates the need to manually write hardware description languages ​​(such as Verilog and VHDL) in traditional hardware design, making the hardware design process simpler and more efficient, speeding up hardware design development, lowering the hardware design threshold, and allowing more software developers to focus on functional design. However, HLS also has its limitations. For example, in some complex hardware design scenarios, manually writing RTL code may still be more efficient than the circuit obtained by automatic synthesis.

[0035] Different companies and research institutions have developed a variety of HLS tools. Some of the current mainstream HLS tools include:

[0036] i. Vitis HLS (Xilinx): Vitis HLS is an HLS tool developed by Xilinx and is a component of the Xilinx Vivado Design Suite. The primary goal of Vitis HLS is to allow hardware designers to describe hardware functionality using high-level programming languages ​​such as C / C++ and OpenCL, and then automatically convert this into optimized RTL (Register Transfer Level) code for efficient hardware acceleration on Xilinx FPGA and SoC platforms.

[0037] ii. Intel HLS Compiler (Intel FPGA): Intel HLS Compiler is an HLS tool provided by Intel FPGA (formerly Altera). It supports high-level synthesis using C / C++ and can generate optimized RTL code for Intel FPGA devices.

[0038] iii. LegUp HLS: LegUp HLS is an open source HLS tool that supports converting C code into hardware circuits on FPGA.

[0039] 2. IP (IP Core): An IP core is a pre-designed and verified hardware functional unit that can be reused in different hardware systems. It is a reusable hardware module, similar to a code library in software development. On-chip IP can include a variety of different functions, from simple logic gates and registers to complex processors, communication interfaces, graphics processing units, and more.

[0040] 3. RTL circuit: RTL (Register-Transfer Level) circuit is a common hardware description level. RTL circuit describes the behavior and structure of digital circuits and is represented using the abstraction level of the register transfer level. RTL circuit descriptions are usually written in a hardware description language (HDL), such as VHDL (VHSIC Hardware Description Language), Verilog HDL, and SystemVerilog HDL. Designers can use RTL-level descriptions to define and implement the required digital circuit functions, and then use synthesis tools to convert the RTL-level descriptions into physical implementations in the FPGA. In the field of FPGA and chip design and verification, RTL-level descriptions are very important for design, verification, and debugging. It provides a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and use appropriate tools for simulation, verification, and synthesis, ultimately generating a bitstream file that can be configured into the FPGA chip to implement specific digital circuit functions.

[0041] 4. FPGA: An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit chip with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs, adapting them to different applications and functions. FPGAs consist of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, and can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form the desired circuit structure. With FPGAs, designers can describe the desired circuit functionality using a hardware description language and, using programming tools, convert this into a bitstream compatible with the FPGA chip. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. They allow designers to implement customized functions and algorithms at the hardware level without the traditional custom integrated circuit design and manufacturing process. This makes FPGAs very useful for prototyping and rapid design iteration.

[0042] 5. FPGA dynamic partial reconfiguration (DPR) refers to the ability to reconfigure part of the circuit while the FPGA is running. In traditional FPGA design, the entire circuit usually needs to be reprogrammed and reloaded into the FPGA to change its function. However, DPR technology allows only part of the circuit to be reconfigured while the FPGA is running without affecting other running circuits. The main advantages of dynamic partial reconfiguration are its flexibility and improved resource utilization. By using DPR, multiple functional modules can be implemented in the FPGA, and each module can be independently reconfigured as needed without reloading the entire design. This flexibility enables the FPGA to adapt to a variety of application requirements, while reducing reprogramming and reloading time and accelerating design iterations.

[0043] 6. FIFO: FIFO stands for "First In, First Out," and is a common queue data structure management method. In a FIFO, the first element to enter the queue is the first to be removed, and the last element to enter is the last to be removed, much like the person at the front of the queue leaves first. This data structure can be used to simulate various real-world scenarios, such as queuing and request processing. FIFO queues are often used for managing shared resources, processing tasks, and managing caches.

[0044] 1 , a flowchart of an embodiment of a verification method of the present application is shown. The method may specifically include the following steps:

[0045] Step 101: The hardware design writes first operation data into the hardware buffer during operation, and the software design writes second operation data into the software buffer during operation.

[0046] Step 102: The verification module reads the first operating data from the hardware buffer, reads the second operating data from the software buffer, and compares the first operating data with the second operating data.

[0047] Step 103: When the first operating data and the second operating data do not match, the verification module interrupts the operation of the hardware design and the software design, and takes a hardware snapshot of the programmable logic chip to save status information of the programmable logic chip.

[0048] Step 104: The verification module imports the status information into simulation software for simulation to debug the hardware design.

[0049] The verification method provided in the embodiment of the present application can be applied to a programmable logic chip, that is, an FPGA chip. Referring to Figure 2, a structural diagram of a verification system provided in the embodiment of the present application is shown. As shown in Figure 2, the verification system includes an FPGA chip and a personal computer (PC), and the PC is equipped with simulation software. The programmable logic area of ​​the FPGA chip includes a design module, a simulation module and an onboard module, the design module includes a hardware design and a functional unit corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; the software design corresponding to the hardware design runs in the processing system of the programmable logic chip, and the software design is used to implement the same function as the hardware design.

[0050] It should be noted that an FPGA chip (or FPGA system-on-chip) contains not only programmable gate array circuits, but also one or more on-chip processors. The programmable gate array circuit is usually called programmable logic (PL); the on-chip processor is usually an ARM processor, called a processing system (PS). In the embodiment of the present application, the design module, simulation module, and onboard module are all burned into the PL side of the FPGA chip, and the software design runs on the PS side of the FPGA chip.

[0051] The hardware design in this application mainly refers to the HLS design, and the software design mainly refers to the C / C++ design corresponding to the HLS design. For example, the HLS tool can be used to generate HLS from the C code. Taking the merge sort algorithm as an example, the C code can be co-simulated with C / RTL to obtain the corresponding HLS design. By adding externally required modules or IPs to the HLS design, the design module (Design Module) in this application can be obtained. For example, a BRAM module is added to the HLS design to store the data required for the merge sort algorithm, including the input data before sorting and the output data after sorting.

[0052] The simulation module mainly adds an interrupt module on the basis of the design module. The interrupt module is used to perform interrupt control on the hardware design.

[0053] The onboard module mainly adds a verification module on the basis of the simulation module. The verification module can compare the operation of the hardware design and the software design to determine whether there is an error in the hardware design.

[0054] Traditionally, FPGA prototyping methods only check whether the module output matches the expected results. However, if any errors are found, visibility of internal signals and intermediate results is critical for debugging. Using FPGA vendor's debugging tools (such as SignalTap and ILA) to change the analyzed signals requires recompilation, and storing more data introduces more overhead. In an embodiment of the present application, additional code can be added to the C / C++ model of the original HLS matrix multiplication to sample the internal signals of the hardware design and software design, so that the internal signals can be directly compared later. Specifically, the embodiment of the present application configures a buffer for the hardware design and software design respectively. During operation, the hardware design writes its operation data, including intermediate results and final output results, into the hardware buffer; the software design writes its operation data into the software buffer.

[0055] The verification module can read the first operating data of the hardware design from the hardware buffer, read the second operating data of the software design from the software buffer, and compare the read first operating data and the second operating data. If the two sets of data do not match, it can be determined that there is an error in the hardware design, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the FPGA chip to save the status information of the FPGA chip, such as the status information of the fly-by, on-chip memory, DSP, external devices, etc. It should be noted that the external device in the embodiment of the present application refers to a device mounted on the FPGA chip that belongs neither to the PL end nor to the PS end, such as an external storage device such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0056] The verification module interacts with the PC and imports the saved status information into the simulation software, which then debugs and repairs the hardware design.

[0057] The embodiment of the present application maps the hardware design and software design to the same FPGA chip for execution, and significantly improves the simulation speed by utilizing FPGA hardware acceleration. Moreover, in the event of a hardware design error, the embodiment of the present application can import the status information of the FPGA chip into the simulation software for simulation, thereby ensuring the freedom of simulation and debugging efficiency through software simulation.

[0058] Optionally, the functional unit includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

[0059] Based on the three-layer structure provided by the present application, unit-level verification of the hardware design can be implemented on the FPGA chip, that is, only the correctness of the hardware design itself is verified, without paying attention to the interaction process between the hardware design and other modules, such as the verification module, external devices, etc.

[0060] Optionally, the programmable logic chip is also equipped with an external device; during operation, the hardware design interacts with any one of the external device, the functional unit, the interrupt module and the verification module through an on-chip bus.

[0061] Based on the three-layer structure provided by the present application, system-level verification of the hardware design can also be implemented on the FPGA chip. That is, during operation, the hardware design can interact with other modules on the FPGA chip, such as the verification module and external devices such as DDR, and generate operation data. By comparing the operation data of the hardware design and the software design, it can be determined whether there are errors in the hardware design.

[0062] Optionally, the hardware design writes the first operation data into the hardware buffer during operation, including:

[0063] The hardware design writes first operation data into a hardware buffer when all result signals in the same iterative operation are generated; the first operation data includes all result signals in the iterative operation.

[0064] On the PL side, you can sample the intermediate results of each iteration of the hardware design. Because the internal result signals in the HLS-generated hardware may not be generated in the same clock cycle, the results of the same iteration in the hardware design can be synchronized before being written to the hardware buffer. In other words, when all the result signals in the same iteration are generated, all the result signals in the iteration are synchronously written to the hardware buffer.

[0065] For example, in the HLS hardware design for implementing merge sort, the output signals may include address signals and data signals. Since the output timing of the address and data signals differs, the address and data signals can be synchronized and written into the hardware buffer in the form of "address + data".

[0066] On the PS side, no additional synchronization is required because the intermediate calculation results of the software design have been identified and executed sequentially within the same iteration.

[0067] In an optional embodiment of the present application, the method further includes:

[0068] Step S11: the interrupt module determines a sampling condition of a first signal; the first signal is any signal in the hardware design;

[0069] Step S12: When the first signal meets the sampling condition, the interrupt module sends an interrupt signal to the hardware design to interrupt the operation of the hardware design;

[0070] Step S13: The interrupt module takes a hardware snapshot of the design module to save status information of the design module.

[0071] In an embodiment of the present application, the first signal of interest can be sampled by the interrupt module to verify the correctness of the HLS design itself. The first signal can be any signal generated during the operation of the hardware design. During the verification process, the sampling condition of the first signal can be set in the interrupt module. When the interrupt module determines that the sampling condition is met, it sends an interrupt signal to the hardware design. After receiving the interrupt signal, the hardware design suspends operation. After the hardware design is safely suspended, the interrupt module only takes a hardware snapshot of the design module (including the hardware design and the functional unit corresponding to the hardware design) and saves the status information of the design module. For example, the sampling condition "signal A == x && signal B == x || signal C>x" can be set for signals signal A, signal B and signal C. When the sampling condition is met, the hardware design is interrupted and the status information of the design module is snapshot saved.

[0072] Furthermore, the status information of the design module can be imported into the simulation software for simulation, thereby realizing unit-level verification of the hardware design, that is, only the correctness of the hardware design itself is verified, without paying attention to the interaction process between the hardware design and other modules, such as verification modules, external devices, etc.

[0073] In an optional embodiment of the present application, the method further includes:

[0074] Step S21: The interrupt module determines the breakpoint logic of the second signal; the correct value of the second signal is any value in the target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal;

[0075] Step S22: When the current value of the second signal does not conform to the breakpoint logic, the interrupt module interrupts the operation of the hardware design and the software design, and takes a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip.

[0076] It is understandable that the values ​​of some intermediate signals are correct within a certain range, and this situation cannot be directly compared with the signal values ​​in the PS end software design. In an embodiment of the present application, breakpoint logic judgment can be added to these signals in the interrupt module. Specifically, if the current value of the second signal is any value within the target interval, the interrupt module does not perform any processing, and the hardware design runs. If the current value of the second signal does not belong to any value within the target interval, that is, the current value of the signal does not meet the breakpoint logic, in this case, the interrupt module can interrupt the operation of the hardware design and save the status information of the FPGA chip through a hardware snapshot.

[0077] Furthermore, the saved state information can be imported into simulation software for simulation, thereby performing more fine-grained analysis and debugging on the second signal.

[0078] In an optional embodiment of the present application, the hardware design writes the first operation data into the hardware buffer during operation, and the software design writes the second operation data into the software buffer during operation, including:

[0079] Step S31: If the data volume of the first running result of the hardware design is greater than or equal to a preset threshold, and / or the data volume of the second running result of the software design is greater than or equal to a preset threshold, the hardware design compresses the first running result to obtain first running data, and writes the first running data into the hardware buffer;

[0080] Step S32: The software is designed to compress the second operation result to obtain second operation data, and write the second operation data into a software buffer.

[0081] Typically, both the hardware and software buffers are set up on the PL side, typically within the verification module. If the hardware and software designs generate a large amount of operational data during operation, and the communication bandwidth of the on-chip bus is limited, transmitting this data will take a long time, affecting verification efficiency.

[0082] Therefore, when the amount of operating data of the hardware design and the software design is large, that is, the amount of data of the first operating result of the hardware design is greater than or equal to the preset threshold, and / or the amount of data of the second operating result of the software design is greater than or equal to the preset threshold, a compression algorithm can be used to compress the first operating result and the second operating result, and then the compressed data can be written into the corresponding buffer, thereby reducing the delay and resource overhead caused by data transmission.

[0083] As an example, compression algorithms may include, but are not limited to, XOR-folding, checksum, and cyclic redundancy check (CRC) algorithms. Selecting an appropriate compression granularity can balance compression rate and accuracy to quickly detect potential problems. In practical applications, a compression algorithm can be selected based on compression granularity and compression accuracy.

[0084] For compression granularity, a compression granularity option, Gc, can be introduced to group the signal into Gc-bit words. Assuming the collected data is ultimately compressed to 128 bits, compression is required when N Gc-bit words need to be compared, and N > 128 / Gc. Each Gc-bit word is compressed to Bc bits using the compression algorithm mentioned above, where Bc is given by formula (1).

[0085] A larger Gc value can make the compression algorithm perform better, but it will also make it more difficult to accurately locate errors.

[0086] For the selection of compression algorithms, the compression granularity Gc can be adjusted from 64 to 512 for each algorithm, and the accuracy, delay, and area consumption corresponding to each compression granularity can be measured. By generating a data stream containing random data, compression is performed using different Gc values. Furthermore, errors can be inserted at random intervals in the original data stream and compressed again. Finally, the data before and after compression are compared to determine the compression accuracy. For example, the compression accuracy rate Rca indicator can be introduced to quantify the compression accuracy of the compression algorithm, as shown in formula (2).

[0087] Ndb and Nab represent the number of errors detected after compression and the actual number of errors before compression, respectively. A higher Rca indicates that the compression algorithm and configuration will miss fewer potential errors. In practical applications, compression algorithms with high compression accuracy can be selected to compress the results of hardware and software designs.

[0088] Optionally, the method further includes:

[0089] When an interrupt condition is met, the interrupt module interrupts the operation of the hardware design.

[0090] The interruption condition includes at least one of the following:

[0091] The hardware design runs to a preset breakpoint;

[0092] The operating result of the hardware design is an error;

[0093] The hardware buffer of the hardware design is full;

[0094] The software buffer designed by the software is empty.

[0095] It should be noted that the preset breakpoints can be one or more time points customized by the tester. When the hardware design runs to the preset breakpoints, the interrupt module can interrupt the operation of the hardware design.

[0096] The operating results of the hardware design are erroneous, including the error situations mentioned in the aforementioned embodiments, such as the first operating data of the hardware design does not match the second operating data of the software design, the current value of the second signal does not meet the breakpoint logic, etc.

[0097] If the hardware buffer corresponding to the hardware design is full, it is no longer possible to write the running data of the design under test into the hardware buffer. Therefore, it is necessary to interrupt the hardware design and wait for the hardware buffer to release the recorded data.

[0098] If the software buffer corresponding to the software design is empty, the execution results of the hardware design and the software design cannot be compared at this time. The hardware design needs to be interrupted and the software design needs to wait for the running data to be written into the software buffer.

[0099] In an embodiment of the present application, the interrupt module can automatically determine when to stop the hardware design based on the interrupt condition.

[0100] In summary, the embodiment of the present application provides a verification method, which loads the hardware design onto an FPGA chip for execution, and utilizes FPGA acceleration to improve verification efficiency; and, in the case where the first running data of the hardware design does not match the second running data of the software design, the error can be quickly and accurately located through a hardware snapshot, and the state information saved in the snapshot can be imported into the simulation software, and the hardware design can be debugged in a more fine-grained manner using the simulation software, thereby ensuring the freedom of simulation and debugging efficiency.

[0101] It should be noted that for the method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0102] Device embodiment

[0103] 3 , a schematic diagram of the structure of a programmable logic chip of the present application is shown. The programmable logic area of ​​the programmable logic chip includes a design module, a simulation module, and an onboard module. The design module includes a hardware design and functional units corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; a software design corresponding to the hardware design runs in the processing system of the programmable logic chip, and the software design is used to implement the same functions as the hardware design.

[0104] The hardware is designed to write the first operation data into the hardware buffer during operation;

[0105] The software is designed to write the second operation data into the software buffer during operation;

[0106] The verification module is used to read the first operating data from the hardware buffer, read the second operating data from the software buffer, and compare the first operating data with the second operating data; if the first operating data and the second operating data do not match, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip; import the status information into simulation software for simulation to debug the hardware design.

[0107] Optionally, the hardware design is specifically used for:

[0108] When all result signals in the same iterative operation are generated, first operation data is written into the hardware buffer; the first operation data includes all result signals in the iterative operation.

[0109] Optionally, the interrupt module is used to:

[0110] Determining a sampling condition of a first signal; the first signal is any signal in the hardware design;

[0111] When the first signal satisfies the sampling condition, sending an interrupt signal to the hardware design to interrupt the operation of the hardware design;

[0112] A hardware snapshot is taken of the design module to save state information of the design module.

[0113] Optionally, the interrupt module is further configured to:

[0114] Determining a breakpoint logic of a second signal; the correct value of the second signal is any value in a target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal;

[0115] When the current value of the second signal does not conform to the breakpoint logic, the operation of the hardware design and the software design is interrupted, and a hardware snapshot of the programmable logic chip is taken to save state information of the programmable logic chip.

[0116] Optionally, the hardware design is specifically used for:

[0117] When the data volume of the first running result of the hardware design is greater than or equal to a preset threshold, and / or the data volume of the second running result of the software design is greater than or equal to a preset threshold, compressing the first running result to obtain first running data, and writing the first running data into the hardware buffer;

[0118] The software is specifically designed to:

[0119] The second operation result is compressed to obtain second operation data, and the second operation data is written into a software buffer.

[0120] Optionally, the interrupt module is further configured to:

[0121] When an interruption condition is met, interrupting the operation of the hardware design;

[0122] The interruption condition includes at least one of the following:

[0123] The hardware design runs to a preset breakpoint;

[0124] The operating result of the hardware design is an error;

[0125] The hardware buffer of the hardware design is full;

[0126] The software buffer designed by the software is empty.

[0127] Optionally, the programmable logic chip is also equipped with an external device; during operation, the hardware design interacts with any one of the external device, the functional unit, the interrupt module and the verification module through an on-chip bus.

[0128] Optionally, the functional unit includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

[0129] 2 , a schematic diagram of the structure of a verification system provided by an embodiment of the present application is shown. As shown in FIG2 , the system includes a programmable logic chip and a personal computer, wherein the personal computer is equipped with simulation software; the programmable logic area of ​​the programmable logic chip includes a design module, a simulation module, and an onboard module, wherein the design module includes a hardware design and functional units corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; the processing system of the programmable logic chip runs a software design corresponding to the hardware design, wherein the software design is used to implement the same functions as the hardware design;

[0130] The hardware is designed to write the first operation data into the hardware buffer during operation;

[0131] The software is designed to write the second operation data into the software buffer during operation;

[0132] The verification module is used to read the first operating data from the hardware buffer, read the second operating data from the software buffer, and compare the first operating data with the second operating data; if the first operating data and the second operating data do not match, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the status information of the programmable logic chip; import the status information into simulation software for simulation to debug the hardware design.

[0133] Optionally, the hardware design is specifically used for:

[0134] When all result signals in the same iterative operation are generated, first operation data is written into the hardware buffer; the first operation data includes all result signals in the iterative operation.

[0135] Optionally, the interrupt module is used to:

[0136] Determining a sampling condition of a first signal; the first signal is any signal in the hardware design;

[0137] When the first signal satisfies the sampling condition, sending an interrupt signal to the hardware design to interrupt the operation of the hardware design;

[0138] A hardware snapshot is taken of the design module to save state information of the design module.

[0139] Optionally, the interrupt module is further configured to:

[0140] Determining a breakpoint logic of a second signal; the correct value of the second signal is any value in a target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal;

[0141] When the current value of the second signal does not conform to the breakpoint logic, the operation of the hardware design and the software design is interrupted, and a hardware snapshot of the programmable logic chip is taken to save state information of the programmable logic chip.

[0142] Optionally, the hardware design is specifically used for:

[0143] When the data volume of the first running result of the hardware design is greater than or equal to a preset threshold, and / or the data volume of the second running result of the software design is greater than or equal to a preset threshold, compressing the first running result to obtain first running data, and writing the first running data into the hardware buffer;

[0144] The software is specifically designed to:

[0145] The second operation result is compressed to obtain second operation data, and the second operation data is written into a software buffer.

[0146] Optionally, the interrupt module is further configured to:

[0147] When an interruption condition is met, interrupting the operation of the hardware design;

[0148] The interruption condition includes at least one of the following:

[0149] The hardware design runs to a preset breakpoint;

[0150] The operating result of the hardware design is an error;

[0151] The hardware buffer of the hardware design is full;

[0152] The software buffer designed by the software is empty.

[0153] Optionally, the programmable logic chip is also equipped with an external device; during operation, the hardware design interacts with any one of the external device, the functional unit, the interrupt module and the verification module through an on-chip bus.

[0154] Optionally, the functional unit includes a data storage device, which is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

[0155] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0156] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0157] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0158] Referring to Figure 4, there is a block diagram of a structure of an electronic device for verification provided in an embodiment of the present application. As shown in Figure 4, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method of the aforementioned embodiment.

[0159] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0160] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG4 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0161] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0162] An embodiment of the present application also provides a non-temporary computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute the verification method shown in Figure 1.

[0163] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0164] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0165] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0166] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0168] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0169] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0170] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0171] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0172] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0173] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0174] It is understood that the embodiments described in the present disclosure may be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the modules, units, and subunits may be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, or other electronic units or combinations thereof for performing the functions described in the present disclosure.

[0175] For software implementation, the techniques described in the embodiments of the present disclosure can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of the present disclosure. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0176] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0177] The above is a detailed introduction to a verification method, chip, system, electronic device and readable storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A verification method, applied to a programmable logic chip, wherein a programmable logic area of ​​the programmable logic chip includes a design module, a simulation module and an onboard module, wherein the design module includes a hardware design and a functional unit corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; a software design corresponding to the hardware design runs in a processing system of the programmable logic chip, and the software design is used to implement the same function as the hardware design; the method comprises: The hardware design writes the first operation data into the hardware buffer during operation, and the software design writes the second operation data into the software buffer during operation; The verification module reads the first operation data from the hardware buffer, reads the second operation data from the software buffer, and compares the first operation data with the second operation data; In the case where the first operation data and the second operation data do not match, the verification module interrupts the operation of the hardware design and the software design, and performs a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip; The verification module imports the status information into simulation software for simulation to debug the hardware design.

2. The method according to claim 1, wherein: The hardware design writes the first operation data into the hardware buffer during the operation, including: The hardware design writes first operation data into a hardware buffer when all result signals in the same iterative operation are generated; the first operation data includes all result signals in the iterative operation.

3. The method according to claim 1, wherein: The method further comprises: The interrupt module determines a sampling condition of a first signal; the first signal is any signal in the hardware design; When the first signal satisfies the sampling condition, the interrupt module sends an interrupt signal to the hardware design to interrupt the operation of the hardware design; The interrupt module takes a hardware snapshot of the design module to save the status information of the design module.

4. The method according to claim 1, wherein: The method further comprises: The interrupt module determines the breakpoint logic of the second signal; the correct value of the second signal is any value in the target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal; When the current value of the second signal does not conform to the breakpoint logic, the interrupt module interrupts the operation of the hardware design and the software design, and takes a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip.

5. The method according to claim 1, wherein: The hardware design writes the first operation data into the hardware buffer during operation, and the software design writes the second operation data into the software buffer during operation, including: The data volume of the first running result of the hardware design is greater than or equal to a preset threshold, and / or the software design When the data amount of the second operation result is greater than or equal to a preset threshold, the hardware design compresses the first operation result to obtain first operation data, and writes the first operation data into the hardware buffer; The software is designed to compress the second operation result to obtain second operation data, and write the second operation data into a software buffer.

6. The method according to claim 1, wherein: The method further comprises: When an interrupt condition is met, the interrupt module interrupts the operation of the hardware design; The interruption condition includes at least one of the following: The hardware design runs to a preset breakpoint; The operation result of the hardware design is wrong; The hardware buffer of the hardware design is full; The software buffer designed by the software is empty.

7. The method according to claim 1, wherein: The programmable logic chip is also equipped with an external device; during operation, the hardware design interacts with any one of the external device, the functional unit, the interrupt module and the verification module through an on-chip bus.

8. The method according to claim 1, wherein: The functional unit includes a data storage device, and the data storage device is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

9. A programmable logic chip, wherein the programmable logic area of ​​the programmable logic chip includes a design module, a simulation module and an onboard module, the design module includes a hardware design and a functional unit corresponding to the hardware design; the simulation module includes the design module and an interrupt module; the onboard module includes the simulation module and a verification module; a software design corresponding to the hardware design runs in the processing system of the programmable logic chip, and the software design is used to implement the same function as the hardware design; The hardware is designed to write the first operation data into the hardware buffer during operation; The software is designed to write the second operation data into the software buffer during operation; The verification module is configured to read the first operation data from the hardware buffer, read the second operation data from the software buffer, and compare the first operation data with the second operation data; if the first operation data and the second operation data do not match, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the state information of the programmable logic chip; The state information is imported into simulation software for simulation to debug the hardware design.

10. The programmable logic chip according to claim 9, wherein: The hardware design is specifically used for: When all result signals in the same iterative operation are generated, first operation data are written into the hardware buffer; the first operation data includes all result signals in the iterative operation.

11. The programmable logic chip according to claim 9, wherein: The interrupt module is used for: Determine a sampling condition of a first signal; the first signal is any signal in the hardware design; When the first signal satisfies the sampling condition, sending an interrupt signal to the hardware design to interrupt the operation of the hardware design; A hardware snapshot is taken of the design module to save state information of the design module.

12. The programmable logic chip according to claim 9, wherein: The interrupt module is also used for: Determine a breakpoint logic of the second signal; the correct value of the second signal is any value in the target interval, and the breakpoint logic is used to indicate the target interval corresponding to the second signal; When the current value of the second signal does not conform to the breakpoint logic, the operation of the hardware design and the software design is interrupted, and a hardware snapshot is taken of the programmable logic chip to save the state information of the programmable logic chip.

13. The programmable logic chip according to claim 9, wherein: The hardware design is specifically used for: When the data volume of the first operation result of the hardware design is greater than or equal to a preset threshold, and / or the data volume of the second operation result of the software design is greater than or equal to a preset threshold, compressing the first operation result to obtain first operation data, and writing the first operation data into the hardware buffer; The software is specifically designed to: The second operation result is compressed to obtain second operation data, and the second operation data is written into a software buffer.

14. The programmable logic chip according to claim 9, wherein: The interrupt module is also used for: When an interruption condition is met, interrupting the operation of the hardware design; The interruption condition includes at least one of the following: The hardware design runs to a preset breakpoint; The operation result of the hardware design is wrong; The hardware buffer of the hardware design is full; The software buffer designed by the software is empty.

15. The programmable logic chip according to claim 9, wherein: The programmable logic chip is also equipped with an external device; during operation, the hardware design interacts with any one of the external device, the functional unit, the interrupt module and the verification module through an on-chip bus.

16. The programmable logic chip according to claim 9, wherein: The functional unit includes a data storage device, and the data storage device is used to store input data corresponding to the hardware design. During operation, the hardware design reads the input data from the data storage device and processes the operation data.

17. A verification system, the system comprising a programmable logic chip and a personal computer, the personal computer being equipped with simulation software; the programmable logic area of ​​the programmable logic chip comprising a design module, a simulation module and an onboard module, the design module comprising a hardware design and a functional unit corresponding to the hardware design; the simulation module comprising the design module and an interrupt module; the onboard module comprising the simulation module and a verification module; the processing system of the programmable logic chip running a software design corresponding to the hardware design, the software design being used to implement the same function as the hardware design; The hardware is designed to write the first operation data into the hardware buffer during operation; The software is designed to write the second operation data into the software buffer during operation; The verification module is configured to read the first operation data from the hardware buffer, read the second operation data from the software buffer, and compare the first operation data with the second operation data; if the first operation data and the second operation data do not match, interrupt the operation of the hardware design and the software design, and take a hardware snapshot of the programmable logic chip to save the state information of the programmable logic chip; The state information is imported into simulation software for simulation to debug the hardware design.

18. An electronic device, comprising a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method as described in any one of claims 1 to 8.

19. A readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the verification method according to any one of claims 1 to 8.

20. A verification apparatus / device, comprising: the apparatus / device being configured to execute the verification method according to any one of claims 1 to 8.

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