Epitaxial wafer and method of producing same

Abstract

The present invention relates to a method of producing an epitaxial wafer, the method comprising the steps of: forming a first layer on a growth substrate wafer; depositing a material layer on the first layer; and patterning the material layer to form a plurality of protrusions spaced apart from each other at predetermined intervals. According to the present invention, crystalline defects are hardly generated in regions having protrusions, and crystalline defects such as threading dislocations and the like are only generated on surfaces between the protrusions in conjunction with the growth of materials such as GaN, AlGaN, AlN, etc. Therefore, the crystallinity of epitaxial growth on a GaN-on-Si epitaxial wafer can be greatly improved. Accordingly, the performance and reliability of a HEMT power device and an LED optical device can be improved.

Description

Epitaxial wafer and method for manufacturing the same

[0001] The present invention relates to an epitaxy wafer and a method for manufacturing the same, and more particularly, to a GaN-on-Si epitaxy wafer and a method for manufacturing the same, which can grow high-quality GaN epitaxy with reduced crystal defects through a plurality of SiO2 protrusions patterned on a Si growth substrate wafer having a (111) crystal plane.

[0002] Figure 1 illustrates the structure of a conventional GaN-on-Si epitaxy wafer.

[0003] As illustrated in FIG. 1, a structure of a GaN-on-Si epitaxy wafer (10) for fabricating a conventional HEMT device includes a growth substrate wafer (11) formed of Si, a nucleation layer (12) formed of AlN on the growth substrate wafer, a transition layer (13) grown of AlGaN on the nucleation layer, a buffer layer (14) grown of GaN on the transition layer, a channel layer (15) grown of GaN on the buffer layer, and a barrier layer (16) formed of AlGaN on the channel layer.

[0004] Here, the nucleation layer (12) is formed with a thickness of 200 to 400 nm to suppress the melt-back etching phenomenon due to the Si-Ga Eutectic Reaction and to act as a seed when forming a high-quality group III nitride (AlN, AlGaN, GaN, InGaN, InN, AlInN) epitaxy, and the transition layer (13) plays a role in alleviating the lattice constant difference between the AlN (nucleation layer) material and the GaN (buffer layer, channel layer) material and gradually controlling (gradual control) the wafer bowing (convex bow occurring during GaN growth) during epitaxy growth. In addition, the buffer layer (14) has a role of reducing leakage current in the vertical direction by imparting high resistance through C (Carbon) doping, and the channel layer (15) and barrier layer (16) have a role of forming a HEMT element by generating 2DEG (Two-Dimensional Electron Gas) at the AlGaN / GaN heterojunction.

[0005] However, the crystallinity of a conventional GaN-on-Si epitaxy wafer (10) based on a Si growth substrate wafer grown to have such a structure (e.g., XRD values ​​of 500 arcsec and 900 arcsec for the (002) crystal plane and (102) crystal plane, respectively) is significantly lower than that of a GaN-on-Sapphire epitaxy wafer based on a conventional sapphire growth substrate wafer (e.g., XRD values ​​of 300 arcsec and 400 arcsec for the (002) crystal plane and (102) crystal plane, respectively).

[0006] In this way, since the crystallinity of the conventional GaN-on-Si epitaxy wafer (10) is not good, problems with electrical characteristics or reliability may occur, and therefore, improvement of crystallinity is absolutely necessary to improve this.

[0007] Meanwhile, as one of the methods for improving the crystallinity of epitaxy grown on a growth substrate wafer (11), there is a PSS (Patterned Sapphire Substrates) technique that performs patterning to form protrusions on a sapphire growth substrate wafer. When this PSS technique is applied to an LED epitaxy wafer process, it has the effect of improving the crystallinity of the epitaxy and increasing the light extraction efficiency of the LED.

[0008] FIG. 2 illustrates the formation of protrusions on a conventional Si growth substrate wafer. However, as illustrated in FIG. 2, when applying the PSS technology to a Si growth substrate wafer (11), unlike sapphire, a rough surface is generated due to surface damage (Damaged Surface) caused by a rapid etching rate on the bottom surface where epitaxy will grow, and when GaN epitaxy is grown on this rough surface, abnormal growth occurs, similar to growth on an amorphous crystal plane. In addition, when applying the PSS technology to a Si growth substrate wafer (11), there is a disadvantage in that it is impossible to create patterns of various shapes due to the rapid etching rate of the Si material and the crystal plane singularity of the cubic system.

[0009] The purpose of the present invention is to solve the above-described conventional problems, and to provide a GaN-on-Si epitaxy wafer and a manufacturing method thereof capable of growing high-quality GaN epitaxy with reduced crystal defects through a plurality of SiO2 protrusions patterned on a Si growth substrate wafer of a (111) crystal plane.

[0010] The above object is achieved by a method for manufacturing an epitaxial wafer, comprising the steps of: depositing a first layer on a Si growth substrate wafer; depositing a material layer on the first layer; and patterning the material layer to form a plurality of protrusions spaced at predetermined intervals.

[0011] In addition, the present invention may further include a step of depositing a second layer on the first layer and a plurality of the protrusions; and a step of growing a transfer layer on the second layer.

[0012] Additionally, the first layer and the second layer may be formed of AlN.

[0013] Additionally, the material layer may be formed of SiO2.

[0014] Additionally, in the step of forming the transfer layer, the transfer layer can be grown in a vertical growth mode on the second layer, and then the transfer layer can be grown in a horizontal growth mode.

[0015] Additionally, the shape of the cross-section of the protrusion may include a semicircle, a trapezoid, a triangle, or a square.

[0016] The above object is achieved by an epitaxy wafer comprising, according to the present invention, a growth substrate wafer; a first layer formed on the growth substrate wafer; and a plurality of protrusions formed at predetermined intervals on the first layer.

[0017] According to the present invention, crystal defects such as threading dislocations occur only on the surface between the protrusions, while crystal defects such as threading dislocations occur only on the surface between the protrusions along with the growth of materials such as GaN, AlGaN, and AlN. Therefore, the crystallinity of the epitaxy grown on the GaN-on-Si epitaxy wafer can be significantly improved, and accordingly, the performance and reliability characteristics of HEMT power devices and LED optical devices can be improved.

[0018] In addition, according to the present invention, the contact surface between the GaN epitaxy region and the growth substrate wafer can be reduced compared to the existing structure, so there is an effect of alleviating the stress between the epitaxy region and the growth substrate wafer.

[0019] In addition, according to the present invention, in the case of GaN power semiconductors, since the epitaxy can be grown thicker, there is an effect of improving the breakdown voltage by strengthening the insulation breakdown field.

[0020] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0021] Figure 1 illustrates the structure of a conventional GaN HEMT-on-Si epitaxy wafer.

[0022] Figure 2 illustrates the formation of protrusions on a conventional Si growth substrate wafer.

[0023] Figure 3 is a flowchart of a method for manufacturing an epitaxy wafer according to one embodiment of the present invention.

[0024] FIG. 4 illustrates a process of manufacturing an epitaxy wafer according to a method for manufacturing an epitaxy wafer according to one embodiment of the present invention.

[0025] FIG. 5 illustrates examples of various shapes of protrusions in a method for manufacturing an epitaxy wafer according to one embodiment of the present invention.

[0026] FIG. 6 illustrates the change in reflectance according to the growth time during the growth of the transfer layer in the method for manufacturing an epitaxy wafer according to one embodiment of the present invention.

[0027] FIG. 7 illustrates the surface shape according to the growth time during the growth of the transfer layer in the method for manufacturing an epitaxy wafer according to one embodiment of the present invention.

[0028] FIG. 8 illustrates an epitaxy wafer manufactured according to a method for manufacturing an epitaxy wafer according to one embodiment of the present invention.

[0029] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0030] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0031] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0032]

[0033] From now on, with reference to the attached drawings, a method for manufacturing an epitaxy wafer (S100) according to one embodiment of the present invention will be described in detail.

[0034] FIG. 3 is a flowchart of a method for manufacturing an epitaxy wafer (S100) according to an embodiment of the present invention, FIG. 4 illustrates a process of manufacturing an epitaxy wafer according to a method for manufacturing an epitaxy wafer (S100) according to an embodiment of the present invention, FIG. 5 illustrates examples of various shapes of protrusions (130) of a method for manufacturing an epitaxy wafer (S100) according to an embodiment of the present invention, FIG. 6 illustrates a change in reflectance according to a growth time during growth of a transfer layer (150) in a method for manufacturing an epitaxy wafer (S100) according to an embodiment of the present invention, and FIG. 7 illustrates a surface shape according to a growth time during growth of a transfer layer (150) in a method for manufacturing an epitaxy wafer (S100) according to an embodiment of the present invention.

[0035] As illustrated in FIGS. 3 and 4, a method for manufacturing an epitaxy wafer (S100) according to an embodiment of the present invention includes a step of depositing a first layer (120) on a growth substrate wafer (110) (step S110), a step of depositing a material layer (M) on the first layer (120) (step S120), a step of patterning the material layer (M) to form a plurality of protrusions (130) spaced at preset intervals (step S130), a step of depositing a second layer (140) on the first layer (120) and the plurality of protrusions (130) (step S140), a step of growing a transfer layer (150) on the second layer (140) (step S150), and a step of forming a device layer (160) on the transfer layer (150).

[0036] Step S110 is a step of forming a first layer (120) on a growth substrate wafer (110).

[0037] Here, the growth substrate wafer (110) may be prepared as a Si growth substrate wafer (110), and preferably, may be prepared as a Si growth substrate wafer (110) having a (111) crystal plane. Meanwhile, in cases where high heat dissipation specifications are required for the device, the growth substrate wafer (110) may be prepared as a SiC growth substrate wafer (110).

[0038] In step S110, a first layer (120) is formed on the growth substrate wafer (110). At this time, the first layer (120) can be formed of an AlN material and serves as a nucleation layer for growing a group III nitride semiconductor layer such as AlN, AlGaN, or GaN on the Si growth substrate wafer (110).

[0039] At the same time, in the step described later, after depositing a SiO2 material layer (M) on a Si growth substrate wafer (110), dry etching is performed during patterning to form a plurality of protrusions (130), and the first layer (120) serves to prevent surface damage that may occur on the Si growth substrate wafer (110) during such dry etching.

[0040] This AlN first layer (120) can be formed into a film with a thickness ranging from 10 to 500 nm using MOCVD or PVD (Sputter, PLD), and when grown using MOCVD, the growth temperature can be 800 to 1200°C, the growth pressure can be 35 to 100 torr, and the VIII element ratio can be grown under the conditions of 50 to 150.

[0041] At this time, if the thickness of the first layer (120) is formed to be 10 nm or less, there is a problem that nuclei are not easily generated during GaN growth and surface damage occurring on the surface of the Si growth substrate wafer (110) is not properly prevented. In addition, if the thickness of the first layer (120) exceeds 500 nm, strong tensile stress is induced, which causes severe wafer warpage (concave shape) and causes microcracks to occur or break, and due to wafer warpage, the thicknesses of the layers grown in subsequent processes become uneven, which causes a problem that the characteristics and quality of the manufactured device are seriously deteriorated.

[0042] Step S120 is a step of depositing a material layer (M) on the first layer (120).

[0043] This material layer (M) is a layer for forming a pattern with various dimensions on a Si growth substrate wafer (110), and can be formed of SiO2, etc., and can be formed with a thickness in the range of 0.5 to 3 ㎛, preferably in the range of 2 to 3 ㎛, using CVD, etc.

[0044] Step S130 is a step of patterning the material layer (M) to form a plurality of protrusions (130) spaced at preset intervals.

[0045] In step S130, a plurality of SiO2 protrusions (130) are formed on the first layer (120) by patterning the material layer (M) by etching it in a preset pattern through a dry etching process. In this way, in the present invention, the quality of epitaxy can be significantly improved without causing damage to the surface of the Si growth substrate wafer (110) due to the presence of the first layer (120) and the separate SiO2 protrusions (130).

[0046] At this time, as shown in FIG. 5, the shape, height, length, etc. of the SiO2 protrusion (130) may have various forms depending on the type of device being manufactured and the type of growth substrate wafer (110).

[0047] For example, the protrusion (130) may have various shapes, such as a case where the shape when viewed from the side (i.e., the shape of the side cross-section) is semicircular and the shape when viewed from the top is circular, a case where the shape when viewed from the side is trapezoidal and the shape when viewed from the top is hexagonal, a case where the shape when viewed from the side is triangular and the shape when viewed from the top is circular, square, or hexagonal, and a case where both the shape when viewed from the side and the shape when viewed from the top are square.

[0048] According to these multiple protrusions (130), the region where the protrusions (130) are present has almost no crystal defects, and crystal defects such as threading dislocations occur only on the surface between the protrusions (130) along with the growth of materials such as GaN, AlGaN, and AlN, so that the crystallinity of the epitaxy grown on the GaN-on-Si epitaxy wafer can be significantly improved.

[0049] In addition, since the contact surface between the GaN epitaxy region and the growth substrate wafer (110) can be reduced by a plurality of protrusions (130) compared to the existing structure, the stress between the epitaxy region and the growth substrate wafer (110) can be effectively relieved.

[0050] Step S140 is a step of forming a second layer (140) on the first layer (120) and a plurality of protrusions (130).

[0051] Here, the second layer (140) is formed of AlN in the same manner as the first layer (120), but can be formed relatively thinner than the first layer (120), and is formed on the surface of the protrusion (130) and the first layer (120) between the plurality of protrusions (130) to serve as a seed layer for growing an AlGaN or GaN semiconductor layer. At this time, the thickness of the second layer (140) formed on the surface of the protrusion (130) can be formed thinner than the thickness of the second layer (140) formed between the plurality of protrusions (130).

[0052] This second AlN layer (140) is formed relatively much thinner than the first layer (120) with a thickness ranging from 0.1 to 50 nm using MOCVD or PVD (Sputter, PLD), and can be grown using MOCVD at a growth temperature of 800 to 1200°C, a growth pressure of 35 to 100 torr, and a VIII element ratio of 50 to 150.

[0053] At this time, the reason why the thickness of the second layer (140) must be formed to be 50 nm or less is to properly perform the function of the seed layer for the growth of the transition layer (150). More specifically, the AlN second layer (140) between the plurality of protrusions (130) has a single-crystalline crystallinity, whereas the AlN second layer (140) covering the surface (including the top and side surfaces) of the protrusions (130) has a poly-crystalline or amorphous crystallinity, and is formed relatively much thinner than the second layer (140) between the plurality of protrusions (130). Due to this, it becomes difficult to grow the transition layer (140) material on the upper and side surfaces of the SiO2 protrusions (130), and the growth of the transition layer (150) begins only on the upper portion of the second layer (140) between the plurality of protrusions (130), so that radial ELOG (Epitaxial Lateral Overgrowth) can proceed around the plurality of protrusions (130).

[0054] Step S150 is a step of growing a transition layer (150) on the second layer (140), and the transition layer (150) can be grown in a Radial ELOG (Epitaxial Lateral Overgrowth) manner.

[0055] In the conventional GaN-on-Si epitaxy wafer manufacturing process, an AlGaN transition layer is formed flatly in a 2D horizontal growth mode on an AlN nucleation layer having a flat surface. However, this method is very likely to cause stress at the interface due to the difference in lattice constant and thermal expansion coefficient between the AlN nucleation layer and the AlGaN transition layer, which may cause cracks and deteriorate the quality of the device. In contrast, in the present invention, since 3D vertical growth proceeds first due to the presence of a plurality of SiO2 protrusions (130), 2D horizontal growth can proceed in a radial structure depending on the shape and size of the structure, stress can be sufficiently relieved, thereby enabling growth of a high-quality transition layer (150).

[0056] Specifically, as shown in FIGS. 6 and 7, in step S150, Al is grown in a 3D vertical growth mode at relatively high pressure on the second layer (140) between SiO2 protrusions (130) using MOCVD. x Ga 1-x After growing N(0≤x≤0.99), Al is applied to cover multiple SiO2 protrusions (130) in a 2D horizontal growth mode at relatively low pressure. x Ga 1-x A transition layer (150) can be formed by growing N (0≤x≤0.99). Thereafter, in the S150 step, the surface of the transition layer (150) can be planarized for the growth of a high-quality element layer (160), and can also be planarized through subsequent GaN growth.

[0057] As shown in Fig. 6, in the reflectance signal that can confirm the growth rate and flatness of the thin film in the MOCVD device, it can be confirmed that the amplitude is elongated in the 3D vertical growth mode, and when flatness is reached through the 2D horizontal growth mode, the amplitude of the reflectance signal is evenly distributed. Fig. 7 shows the shape of this growth process.

[0058] At this time, Al grown in 3D vertical growth mode x Ga 1-x The growth temperature of N(0≤x≤0.99) is 950 to 1100℃, the growth pressure is 200 to 500 torr, and the VIII element ratio can be grown under the conditions within the range of 700 to 3000, and the grown thickness can vary depending on the thickness of the formed SiO2 protrusion (130). In addition, Al grown in 2D horizontal growth mode x Ga 1-x The growth temperature of N(0≤x≤0.99) is 1050 to 1200℃, the growth pressure is 100 to 300 torr, and the VⅢ element ratio can be grown under the conditions within the range of 700 to 1500, and the thickness grown can vary depending on the epitaxy structure design. At this time, in the present invention, Al x Ga 1-x The N(0≤x≤0.99) transition layer (150) may have a multilayer structure in which the Al composition gradually decreases to more effectively relieve stress.

[0059] Meanwhile, in the present invention, the stress between the epitaxy region and the growth substrate wafer (110) can be effectively relieved through a plurality of SiO2 protrusions (130), so the transfer layer (150) is made of Al. x Ga 1-x Instead of being formed with N(0≤x≤0.99), it can be formed only with GaN, and after a GaN layer is partially grown (e.g., approximately 200 nm), Al is added on top of it. xGa 1-x It may have a structure in which the N(0≤x≤0.99) layer is grown (for example, approximately 50 nm), and further, the transition layer is a GaN layer and an Al x Ga 1-x It may have a superlattice structure in which N(0≤x≤0.99) layers are alternately stacked. According to this, the quality of the element layer (160) grown on the transition layer (150) can be further improved.

[0060] Step S160 is a step of forming a device layer (160) on a flattened transfer layer (150).

[0061] At this time, the device layer (160) may be a power semiconductor device such as a HEMT or a light-emitting device such as an LED, and when the device layer (160) is formed with a HEMT power semiconductor device structure, it may include a buffer layer (161, Buffer Layer), a channel layer (162, Channel Layer), and a barrier layer (163, Barrier Layer).

[0062] At this time, the buffer layer (161) forms an electrically high resistance layer through carbon (C) or iron (Fe) doping to reduce leakage current, and the channel layer (162) and barrier layer (163) play a role in generating a 2DEG (Two-Dimensional Electron Gas) quantum well structure in the AlGaN / GaN heterojunction.

[0063]

[0064] From now on, with reference to the attached drawings, an epitaxy wafer (100) according to one embodiment of the present invention will be described in detail.

[0065] FIG. 8 illustrates an epitaxy wafer (100) manufactured according to a method for manufacturing an epitaxy wafer (S100) according to one embodiment of the present invention.

[0066] As illustrated in FIG. 8, an epitaxy wafer (100) according to one embodiment of the present invention includes a growth substrate wafer (110), a first layer (120) formed on the growth substrate wafer (110), a plurality of SiO2 protrusions (130) formed at predetermined intervals on the first layer (120), a second layer (140) formed on the first layer (120) and the plurality of SiO2 protrusions (130), a transfer layer (150) grown on the second layer (140), and a device layer (160) grown on the transfer layer (150).

[0067] Meanwhile, since each configuration has been described above in the method for manufacturing an epitaxy wafer (S100) according to one embodiment of the present invention, a duplicate description will be omitted.

[0068]

[0069] According to the epitaxy wafer and the manufacturing method thereof according to an embodiment of the present invention as described above, crystal defects hardly occur in the region where the protrusions are present, and crystal defects such as threading dislocations occur only on the surface between the protrusions along with the growth of materials such as GaN, AlGaN, and AlN, so that the crystallinity of epitaxy grown in the GaN-on-Si epitaxy wafer can be significantly improved, and accordingly, the performance and reliability characteristics of HEMT power devices and LED optical devices can be further improved.

[0070] In addition, according to the present invention, compared to a conventional structure formed through a general Si growth substrate wafer, the contact surface between the GaN epitaxy region and the growth substrate wafer can be reduced, so that there is an effect of alleviating the stress between the epitaxy region and the growth substrate wafer.

[0071] In addition, according to the present invention, in the case of GaN power semiconductors, since the epitaxy can be grown thicker, there is an effect of improving the breakdown voltage by strengthening the insulation breakdown field.

[0072]

[0073] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0074] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0075] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0076] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted based on the claims below, and all technical concepts within the scope equivalent thereto should be interpreted as being included within the scope of the rights of the present invention.

Claims

1. A step of forming a first layer on a Si growth substrate wafer; A step of depositing a material layer on the first layer; and A method for manufacturing an epitaxy wafer, comprising a step of patterning the material layer to form a plurality of protrusions spaced at preset intervals.

2. In claim 1, A step of depositing a second layer on the first layer and a plurality of the protrusions; and A method for manufacturing an epitaxial wafer, further comprising the step of growing a transfer layer on the second layer.

3. In claim 2, The first layer and the second layer, A method for manufacturing an epitaxial wafer formed of AlN.

4. In claim 1, The above material layer is, A method for manufacturing an epitaxial wafer formed of SiO2.

5. In claim 2, In the step of forming the above transition layer, A method for manufacturing an epitaxial wafer, wherein the transfer layer is grown in a vertical growth mode on the second layer, and then the transfer layer is grown in a horizontal growth mode.

6. In claim 1, The shape of the cross-section of the above protrusion is: A method for manufacturing an epitaxial wafer, comprising a semicircular, trapezoidal, triangular or rectangular shape.

7. Growth substrate wafer; A first layer formed on the growth substrate wafer; and An epitaxial wafer comprising a plurality of protrusions formed at preset intervals on the first layer.

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