Low roughness thin-film transistors (TFTS) and method of mitigating charge carrier scattering with low roughness gate electrodes and high permittivity gate insulators

Abstract

Embodiments of the invention provide a method comprising generating a first electric field strength at a first point at a first interface between a gate insulator and a semiconductor layer of a thin film transistor having an amorphous metal gate; generating a second electric field strength at a second point at the first interface; and minimizing the difference between the first electric field strength and the second electric field strength by: forming a first surface roughness value at a first surface of the amorphous metal gate; and forming a second surface roughness value at a second surface of the gate insulator, the first and second surface roughness values being less than 10% different from each other.

Description

LOW ROUGHNESS THIN-FILM TRANSISTORS (TFTS) AND METHOD OF MITIGATING CHARGE CARRIER SCATTERING WITH LOW ROUGHNESS GATE ELECTRODES AND HIGH PERMITTIVITY GATE INSULATORSBACKGROUNDTechnical Field

[0001] Section 1 : The present disclosure relates to thin-film transistors, and, more specifically, to reducing charge carrier (electron (negative) or hole (positive)) scattering (e.g., surface roughness electron / hole scattering or remote surface roughness electron / hole scattering) occurring within a semiconductor layer of a transistor, which may be a thin-film transistor (TFT).

[0002] Section 2: The present disclosure relates to thin-film transistors, and, more specifically, to reducing charge carrier scattering (e.g., surface roughness scattering or remote surface roughness scattering) occurring within a semiconductor layer of a transistor, which may be a thin-film transistor (TFT), metal semiconductor junction field-effect transistor (MESFET) or a junction field-effect transistor (JFET).Description of the Related Art

[0003] Section 1 : Thin film-transistors for the display industry are typically formed on non-conducting substrates. Thin-film transistors (TFTs) may be formed utilizing processes that are different than traditional CMOS (z.e., complementary metal oxide semiconductor) processes. As thin-film transistors are not bound by some process constraints of traditional CMOS transistors, thin-film transistors can be utilized in various application in which it may be difficult to utilize traditional CMOS transistors. These applications can include OLED (z.e., organic light-emitting-diode) displays and other types of displays. In spite of various advantages of thin- film transistors, it can still be difficult to achieve desired transistor conduction characteristics within film transistors.

[0004] A respective thin film-transistor may include a gate metal layer, a gate insulator layer, and a semiconductor layer that are stacked on one another to form the respective thin-film transistor. In an ideal world, electrons would flow or pass through the semiconductor layer from between a source and drain directly without being disrupted, disturbed, or interrupted. However, in the real world, as the electrons flow or pass through the semiconductor layer, the electrons directional flow through the semiconductor layer may be disrupted, disturbed, or interrupted byelectrons bumping into each other, being exposed to other types of charges, being exposed to physical impurities within the semiconductor layer, being exposed to a surface roughness at an interface between a gate insulator and the semiconductor layer, or being exposed to nonuniformities within an electrical field causing the flow of electrons through the semiconductor layer to be disrupted, disturbed, or interrupted decreasing the overall performance of the thin- film transistor.

[0005] Section 2: TFTs for the display industry are typically formed on nonconducting glass substrates. TFTs may be formed utilizing processes that are different than traditional CMOS (i.e., complementary metal oxide semiconductor) processes. As TFTs are not bound by some process constraints of traditional CMOS transistors, TFTs can be utilized in various application in which it may be difficult to utilize traditional CMOS transistors. These applications can include OLED (i.e., organic light-emitting-diode) displays and other types of displays. Despite various advantages of thin-film transistors, it can still be difficult to achieve desired transistor current- voltage characteristics within TFTs.

[0006] A respective TFT may include a gate metal layer, a gate insulator layer, a semiconductor layer, a source layer and a drain layer that are stacked on one another to form the respective TFT device. Electronic conduction in a transistor occurs via electrons for an n-type semiconductor layer and via holes for a p-type semiconductor layer. Electrons and holes are referred to as charge carriers in either case. The present disclosure is directed at electrons in n-type oxide semiconductors without loss of generality. Ideally, when an external voltage is applied across the source and drain electrodes in a transistor, charge carriers would move along directions which are parallel (applies to holes) or antiparallel (applies to electrons) to the electric field lines established within the semiconductor by the external voltage. The motion of the charge carriers would be regarded as ballistic, since the acceleration of charge carriers is unbound, limited only by the electric field. Realistically, charge carriers experience frequent collisions — referred to as scattering or scattering events — which may result in an alteration of the energy or momentum of a charge carrier, despite moving in a direction which — on average — is determined by the electric field established by the applied voltages. The efficiency in which charge carriers move is measured by their mobility, which considers all possible scattering processes. These may include, but are not limited to, scattering by lattice vibrations (i.e., phonons), charged or neutral impurities, or surfaces (i.e., surface roughness scattering) — In TFTs, scattering from surfaces is more important since charge carriers are confined to within the finite thickness ofthe semiconductor, which is typically much smaller than that used in traditional CMOS transistors. In any transistor, the relevant mobility is referred to as field-effect mobility, which is used to benchmark transistor performance and understanding factors influencing transistor performance. Factors influencing mobility may be introduced by a particular layer stack (i.e., device structure) and / or processing sequence. Importantly, an increase in scattering (of any type) leads to a reduction in field-effect mobility and, therefore, transistor performance.BRIEF SUMMARY

[0007] Section 1 : The present disclosure is directed to providing embodiments of thin film transistors (TFT) that reduce charge carrier (electron / hole) scattering due to surface roughness at the gate insulator and semiconductor interface, as well as scattering due to remote surface roughness. Reducing these scattering effects within the semiconductor layer of the TFTs improves a flow of electrons through the semiconductor layer increasing the drain current of the TFTs. Furthermore, the present disclosure is directed to methods of reducing or managing these scattering effects.

[0008] Increases in a root mean square (RMS) of a surface roughness (e.g., 0.5 nanometers (nm) to 4.5 nanometers (nm)) of certain metallic gate electrodes (e.g., TiAk such as TiAk, Mo, AlNdo.02, and Ti) is related to a reduction in field effect mobility. In some situations, this field effect mobility may be substantially equal to 65 cm2 / Vs. In some situations, this field effect mobility may be greater than 65 cm2 / Vs. In some situations, this field effect mobility may be less than 65 cm2 / Vs. In some situations, this field effect mobility may be within the range of 65 to 37 cm2 / Vs, or may be equal to the upper and lower ends of this range. In other words, when there is an increase in the RMS of the surface roughness of a metallic gate electrode of a thin-film transistor (TFT), electron / hole scattering within a semiconductor layer of the TFT is increased reducing overall performance of the TFT. For example, in a respective bottom-gate, top-contact amorphous metal oxide TFT having a sputtered gate insulator between an amorphous metal gate and a semiconductor layer of the TFT, atomic force microscopy (AFM) indicates that a surface topography of the gate insulator is practically identical to that of a surface topography of the underlying gate electrode. The gate insulator is generally a high-k dielectric insulator such as a high-k dielectric oxide insulator.

[0009] In at least one embodiment, the top-contact amorphous TFT is a top-contact amorphous IGZO (InGaZnCh) TFT. In alternative embodiments, the top-contact amorphous TFT is some other type of top-contact amorphous TFT.

[0010] In at least one embodiment, the gate insulator is an AhOx gate insulator such as AI2O3 gate insulator. In alternative embodiments, the gate insulator is some other type of gate insulator.

[0011] This relationship between the surface roughness or topographies of the gate insulator and the underlying gate electrodes remains the same regardless of a thickness of the gate insulator, which may range from 5 nm to 75 nm. Any change in difference between the surface topographies of the gate insulator and the underlying gate electrode as a result of a smaller thickness (e.g., 5 nm) or a larger thickness (e.g., 75 nm) is negligible. This relationship between the surface topographies of the gate insulator and the underlying gate electrode suggests a strong templating effect on the underlying gate electrode. Effectively, the surface roughness or topography of the underlying gate electrode is transferred to a gate insulator and semiconductor interface at which the gate insulator abuts the semiconductor layer. As the surface roughness at the gate insulator and semiconductor interface increases, surface scattering at the gate insulator and semiconductor interface increases.

[0012] The relationship between the surface roughness of the gate electrode and the uniformity of the electric field formed across the high-k oxide gate insulator is such that reducing gate electrode roughness increases gate electric field uniformity. This increase in uniformity directly results in an increase in field-effect mobility.

[0013] These various embodiments of the present disclosure include field-effect mobility within a relaxation time approximation, considering electron / hole scattering (i.e., surface roughness scattering and remote surface roughness scattering) caused by surface roughness, charged impurities, and phonons. Furthermore, for surface roughness related scattering (i.e., surface roughness scattering and remote surface roughness scattering), a comparison was made using gaussian, exponential and intermediate gaussian-exponential surface models with excellent agreement with respect to collected data. These results support the use of smooth gate metals (e.g., amorphous metals) for realizing high mobility amorphous metal oxide semiconductor TFTs, and, for example, IGZO TFTs.

[0014] Section 2: The present disclosure is directed to providing embodiments of TFTs that reduce charge carrier scattering and increase mobility within the semiconductor by reducing the surface roughness at the interface between the gate insulator andsemiconductor and the interface between the gate and gate insulator. Reducing these charge carrier scattering effects within the semiconductor layer of the TFTs improves charge carrier conduction through the semiconductor layer increasing field-effect mobility and the overall performance of the TFTs. Furthermore, the present disclosure is directed to methods of reducing or managing these charge carrier scattering effects by using gate metals having different surface roughness.

[0015] Increases in a root mean square (RMS) surface roughness (e.g., 0.5 nanometers (nm) to 4.5 nanometers (nm)) of certain metallic gate electrodes (e.g., TAF, Mo, AlNdo.02, and Ti) is related to a reduction in field-effect mobility. In some situations, this field-effect mobility may be substantially equal to 65 cm2 / Vs. In some situations, this fieldeffect mobility may be greater than 65 cm2 / Vs. In some situations, this field-effect mobility may be less than 65 cm2 / Vs. In some situations, this field-effect mobility may be within the range of 65 to 37 cm2 / Vs or may be equal to the upper and lower ends of this range. In other words, when there is an increase in the RMS of the surface roughness of a metallic gate electrode of a thin-film transistor (TFT), charge carrier scattering within a semiconductor layer of the TFT is increased, reducing overall performance of the TFT. For example, in a respective bottom-gate, top-contact amorphous IGZO (InGaZnCh) TFT having a sputtered AI2O3 gate insulator between an amorphous metal gate and a semiconductor layer of the TFT, atomic force microscopy (AFM) indicates that a surface topography of the AI2O3 gate insulator is practically identical to that of a surface topography of the underlying gate electrode. In other words, the roughness of the gate determines the roughness at the interface between the gate insulator and semiconductor, resulting in the ability to mitigate surface scattering through the selection of metallic gate electrodes having lower roughness. The result is to increase field-effect mobility and overall TFT performance.

[0016] This relationship between the surface roughness or surface topographies of the AI2O3 gate insulator and the underlying gate electrodes remains the same regardless of a thickness of the AI2O3, which may range from 5 nm to 75 nm. Any change in the difference between the surface topographies of the AI2O3 gate insulator and the underlying gate electrode because of a smaller thickness (e.g., 5 nm) or a larger thickness (e.g., 75 nm) is negligible. This relationship between the surface topographies of the AI2O3 gate insulator and the underlying gate electrode suggests a strong templating effect on the underlying gate electrode. Effectively, the surface roughness or topography of the underlying gate electrode is transferred to an upper surface of the AI2O3 gate insulator which is also the interfacebetween gate insulator and semiconductor where a significant portion of charge carrier conduction occurs. As the surface roughness at the gate insulator and semiconductor interface increases, charge carrier scattering at the gate insulator and semiconductor interface increases. As the surface roughness of the underlying gate electrode increases, remote surface roughness scattering increases.

[0017] These various embodiments of the present disclosure include field-effect mobility calculated within a relaxation time approximation, considering charge carrier scattering caused by surface roughness (i.e., surface roughness scattering and remote surface roughness scattering), charged impurities, and phonons. Furthermore, for surface roughness related charge carrier scattering (i.e., surface roughness scattering and remote surface roughness scattering), a comparison was made using gaussian, exponential and intermediate gaussian-exponential surface models with excellent agreement with respect to collected data. These results support the use of smooth gate metals (e.g., amorphous metals) for realizing high mobility amorphous metal oxide semiconductor TFTs, such as, for example, IGZO TFTs.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0018] The detailed description is described with reference to the accompanying figures. The sizes and relative positions of elements in the figures are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale and some of these elements are enlarged and positioned to improve figure legibility. As is understood by one of skill in the art, the shape of a particular element may be modified (e.g., rounded, thinned, elongated, etc.) to suit a particular application.

[0019] Section 1: Figures 1.1 -1.4 are cross-sectional views of at various stages of formation of a thin-film-transistor (TFT), according to one embodiment.

[0020] Figure 1.5 is a top view of the microelectronic device of Figure 1.4, according to one embodiment.

[0021] Figure 1.6 is a cross-sectional view of a microelectronic device including a thin- film transistor, according to one embodiment.

[0022] Figure 1.7 is a top view of the microelectronic device of Figure 1.6, according to one embodiment.

[0023] Figure 1.8 is a cross-sectional view of a microelectronic device including a thin- film transistor, according to one embodiment.

[0024] Figure 1.9 is a top view of the microelectronic device of Figurel .8, according to one embodiment.

[0025] Figure 1.10 is a cross-sectional view of a microelectronic device including a thin- film transistor, according to one embodiment.

[0026] Figure 1.11 is a top view of the microelectronic device of Figure 1.10, according to one embodiment.

[0027] Figure 1.12 is a cross-sectional view of a thin-film transistor of a microelectronic device illustrating surface roughness scattering, in accordance to one embodiment.

[0028] Figure 1.13 is a cross-sectional view of the microelectronic device including the thin-film transistor (TFT) as shown in Figure 1.12 illustrating surface roughness scattering, in accordance to one embodiment.

[0029] Figure 1.14 is a cross-sectional view of a thin-film transistor of a microelectronic device illustrating remote surface roughness scattering, in accordance to one embodiment.

[0030] Figure 1.15 is a cross-sectional view of the microelectronic device including the thin-film transistor (TFT) as shown in Figure 1.14 illustrating remote surface roughness scattering, in accordance to one embodiment.

[0031] Figure 1.16 is a plurality of atomic force microscopy (AFM) images of respective surface topographies of respective gate insulator on respective gate metals having respective thicknesses, in accordance to one embodiment.

[0032] Figure 1.17 is a graph of data collected with respect to respective surface roughnesses or topographies of gate insulators formed on respective gate metals having respective thicknesses.

[0033] Figure 1.18 is a graph of data collected with respect to respective surface roughnesses or topographies of gate insulators formed on respective gate metals having respective thicknesses.

[0034] Figure 1.19 is a graph of field effect transistor (FET) mobility of respective semiconductor layers relative to respective surface roughnesses of respective gate metals.

[0035] Figure 1.20 is a graph of a IGZO (InGaZnCh) thin-film transistor (TFT) model of impact of scattering on field effect mobility as a gate electric field energy is increased, which is based on actual IGZO TFT device performance.

[0036] Section 2: Figures 2.1-2.9 are cross-sectional views of a thin-film transistor at various stages of formation of a thin-film transistor, according to one embodiment.

[0037] Figure 2.9 is a cross-sectional view of a thin-film transistor in bottom-gate bottom-contact configuration, according to one embodiment.

[0038] Figure 2.10 is a top view of the microelectronic device of Figure 2.9, according to one embodiment.

[0039] Figure 2.11 is a cross-sectional view of a thin-film transistor in bottom-gate top-contact configuration, according to one embodiment.

[0040] Figure 2.12 is a top view of the microelectronic device of Figure 2.11, according to one embodiment.

[0041] Figure 2.13 is a cross-sectional view of a thin-film transistor in double-gate bottom-contact configuration, according to one embodiment.

[0042] Figure 2.14 is atop view of the microelectronic device of Figure 2.13, according to one embodiment.

[0043] Figure 2.15 is a cross-sectional view of a thin-film transistor in double-gate top-contact configuration, according to one embodiment.

[0044] Figure 2.16 is atop view of the microelectronic device of Figure 2.15, according to one embodiment.

[0045] Figure 2.17 is a cross-sectional view of the gate electrode, gate insulator and semiconductor layers within a thin-film transistor, illustrating two types of surface roughness scattering mechanisms, in accordance to one embodiment.

[0046] Figure 2.18 is a cross-sectional view of the gate electrode, gate insulator and semiconductor layers within a thin-film transistor, illustrating surface roughness scattering, according to one embodiment.

[0047] Figure 2.19 is a cross-sectional view of the gate electrode, gate insulator and semiconductor layers within a thin-film transistor, illustrating remote surface roughness scattering, according to one embodiment.

[0048] Figure 2.20 is a plurality of atomic force microscopy (AFM) images of respective surface topographies of respective gate insulator on respective gate metals having respective thicknesses, according to one embodiment.

[0049] Figure 2.21 is a graph of data collected with respect to respective surface roughness values of gate insulators formed on respective gate metals having respective thicknesses, according to one embodiment.

[0050] Figure 2.22 is a graph of data collected with respect to respective surface roughness values of gate insulators formed on respective gate metals having respective thicknesses, according to one embodiment.

[0051] Figure 2.23 is a graph comparing theoretical and measured field-effect mobility of respective IGZO thin film transistors relative to respective RMS surface roughness values of respective gate metals, according to one embodiment.

[0052] Figure 2.24 is a graph showingthe impact of gate insulator material, gate insulator thickness and gate electrode on field-effect mobility of an IGZO TFT, according to one embodiment.DETAILED DESCRIPTION

[0053] It will be appreciated that, although specific embodiments of the present disclosure are described for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure.

[0054] In this description, certain specific details are set forth to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well- known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.

[0055] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

[0056] Section 1 : Many aspects of our lives are benefited by utilizing ever smaller electronic devices. These include televisions, mobile electronic devices, like cellular phones, smart phones, tablet computers, and wearable electronics, like smart watches and pedometers. The transistors built on semiconductor substrates are limited by the materials used to form these circuits, z.e., silicon or other semiconductor wafers. With flexible transistors, the potential uses of electronic devices can be further expanded and improved, such as lighter and faster displays,wearable displays, mobile or easily movable displays, integrated into intemet-of-things applications, or be integrated into medical devices. However, as these devices become ever smaller, thicknesses of various layers of TFTs are further reduced to accommodate the available spaced in the ever smaller devices.

[0057] The present disclosure is directed to providing embodiments of TFTs that reduce surface roughness charge carrier (electron / hole) scattering at a gate insulator and semiconductor interface caused by surface roughness or topography of the gate insulator at this respective interface, and reduce remote surface roughness electron / hole scattering caused by the surface roughness or topography of a gate metal at a gate insulator and gate metal interface. Reducing these scattering effects (z.e., surface roughness scattering and remote surface roughness scattering) improves a flow of charge carriers through the semiconductor layer increasing the drain current of the TFTs. Furthermore, the present disclosure is directed to methods of reducing or managing these scattering effects that occur within the semiconductor layer.

[0058] These various embodiments of the present disclosure include field-effect mobility within a relaxation time approximation, considering electron / hole scattering (z.e., surface roughness scattering and remote surface roughness scattering) caused by surface roughness or topography, charged impurities, and phonons. Furthermore, for surface roughness or topography related scattering (z.e., surface roughness scattering and remote surface roughness scattering), a comparison was made using gaussian, exponential and intermediate gaussian-exponential surface models with excellent agreement with respect to collected data. These results support the use of smooth gate metals (e.g., amorphous metals) for realizing high mobility amorphous metal oxide semiconductor TFTs, such as, for example, IGZO TFTs.

[0059] Any metal oxide transistor can be viewed as conducting electric charge carriers in proportion to the energy stored in a gate capacitance. Increasing energy stored in the gate capacitance therefore increases an amount of charge conducted through a semiconductor layer of the metal oxide transistor. A typical thin-film metal oxide transistor structure includes a substrate, a gate layer on the substrate (e.g., a gate electrode), a gate insulator layer on the gate layer, a semiconductor layer on the gate insulator layer and spaced apart from the gate layer by the gate insulator layer, a source layer on the semiconductor layer (e.g., a source electrode), and a drain layer on the semiconductor layer (e.g, a drain electrode). A rate of conduction is ultimately limited by a charge carrier mobility, which may be lowered due to any number of collisions, which may be referred to as “electron or hole scattering,” that alter momentum orenergy of the charge carrier. Reducing an amount of the electron / hole scattering generally improves an efficiency and performance of a thin-film transistor (TFT).

[0060] In view of the above discussion and for example, increases in a root mean square (RMS) of a surface roughness (e.g., 0.5 nanometers (nm) to 4.5 nanometers (nm)) of certain metallic gate electrodes (e.g., TiAk such as TiAh, Mo, AlNdo.02, and Ti) is related to a reduction in field effect mobility. In some situations, this field effect mobility may be substantially equal to 65 cm2 / Vs. In some situations, this field effect mobility may be greater than 65 cm2 / Vs. In some situations, this field effect mobility may be less than 65 cm2 / Vs. In some situations, this field effect mobility may be substantially equal to 65 cm2 / Vs. In some situations, this field effect mobility may be greater than 65 cm2 / V s. In some situations, this field effect mobility may be less than 65 cm2 / V s. In some situations, this field effect mobility may be within the range of 37 to 65 cm2 / Vs, or may be equal to the upper and lower ends of this range. In other words, when there is an increase in the RMS of the surface roughness of a metallic gate electrode of a TFT, scattering within a semiconductor layer of the TFT is increased reducing overall performance of the TFT. For example, in a respective bottom-gate, top-contact amorphous IGZO (InGaZnCh) TFT having a sputtered AhOx such as AI2O3 gate insulator between an amorphous metal gate and a semiconductor layer of the TFT, atomic force microscopy (AFM) indicates that a surface topography or roughness of the AhOx such as AI2O3 gate insulator is practically identical to that of a surface topography or roughness of the underlying gate electrode. This relationship between the surface topographies of the AhOx such as AI2O3 gate insulator and the underlying gate electrodes remains the same regardless of a thickness of the AhOx such as AI2O3, which may range from 5 nm to 75 nm. Any change in difference between the surface topographies or roughnesses of the AhOx such as AI2O3 gate insulator and the underlying gate electrode as a result of a smaller thickness (e.g., 5 nm) or a larger thickness (e.g., 75 nm) is negligible. This relationship between the surface topographies or roughnesses of the AhOx such as AI2O3 gate insulator and the underlying gate electrode suggests a strong templating effect on the underlying gate electrode. Effectively, the surface roughness or topography of the underlying gate electrode is transferred to a gate insulator and semiconductor interface at which the AhOx such as AI2O3 gate insulator abuts the semiconductor layer. As the surface roughness at the gate insulator and semiconductor interface increases, surface electron / hole scattering at the gate insulator and semiconductor interface increases. As the surface roughness of the underlying gate electrode increases, remote surface roughness scattering increases.

[0061] There are six primary mechanisms for scattering of charge carriers in an oxide semiconductor, which have been provided in no particular order as follows herein: (1) surface roughness at a semiconductor-gate insulator interface (z.e., surface roughness scattering), (2) remote surface roughness that generates distortions, fluctuations, or non-uniformities in a gate electric field caused by a surface roughness of the gate (z.e., remote surface roughness scattering), (3) polar optical phonon collisions, (4) acoustic-deformation potential, (5) optical deformation potential, and (6) charged impurity collisions. The main focus of the following discussion herein will be with respect to preventing, mitigating, or reducing the effects of items (1) (z.e., surface roughness scattering) and (2) (z.e., remote surface roughness scattering) as set forth above.

[0062] A dominant mechanism for charge scattering in a field effect transistor (FET) with a large gate field (e.g., high energy storage) is surface roughness charge carrier scattering. Furthermore, remote surface roughness scattering can also be limiting at large gate fields if a gate insulator has a thickness that is small (e.g., less than 10 nanometers (nm)).

[0063] With respect to remote surface roughness scattering, the roughness of a gate metal is known to translate directly to a roughness of a semiconductor-gate interface, which impacts field effect mobility through enhanced surface roughness scattering. The roughness of the gate metal is known to create distortions, fluctuations, or non-uniformities in an electromagnetic field crated by energy stored in a gate capacitance. These distortions, fluctuations, or non- uniformities cause surface remote charge scattering impacting a mean free path of charges when the electromagnetic field is applied to control a flow of electrons through a semiconductor layer of a TFT.

[0064] The use of an amorphous gate metal to replace the typical crystalline gate metal reduces gate metal surface roughness. This reduction in gate metal surface roughness directly results in a reduction in semiconductor-gate insulator interface surface roughness. This overall decrease in surface roughness at the semiconductor-gate insulator interface increases the mean free path of charges in the semiconductor, and reduces distortions, fluctuations, or non- uniformities in the electromagnetic field created by the energy stored in the gate capacitance, increasing mean free path of charges in the semiconductor layer. The use of an amorphous metal gate in a metal oxide transistor therefore increases field effect mobility performance of the transistor - independent of the structure of the transistor (single-gate, top-gate, dual-gate).

[0065] Figure 1.1 is a cross-sectional view of a thin-film electronic device 100 (e.g., a thin-film transistor (TFT)) and an intermediate stage of processing, according to oneembodiment. The thin-film electronic device 100 includes a substrate 102. The substrate 102 corresponds to a support substrate on which a thin-film transistor will be formed. The thin-film transistor may include many materials and structures that are nontraditional with respect to traditional complimentary metal-oxide-semiconductor (CMOS) transistors. Accordingly, the substrate 102 may include nontraditional materials and characteristics with respect to CMOS transistors. For example, traditional CMOS transistors typically performed on a monocrystalline semiconductor substrate. However, the substrate 102 may include materials other than monocrystalline semiconductors, though monocrystalline semiconductors can be used in some embodiments. The ability to use materials other than monocrystalline semiconductors can greatly simplify the manufacturing process and reduce the manufacturing cost.

[0066] The substrate 102 can include a substantially nonconductive material. The substrate can be glass, a polymer, plastic, or other materials. In some embodiments, the substrate is glass, a polymer, plastic, or other material. In other embodiments, the substrate is a rubber. As used herein, “rubber” includes polymers of isoprene as well as forms of polyisoprene. In some such embodiments, the substrate is a plastic. Any suitable plastic may be used. In some embodiments, the plastic is a polyimide, an arylamide, acrylamide, polybenzimidazole (PBI), polyetherimide, polyetherketoneketone (PEKK), polyether ether ketone (PEEK), polyamide, polyimide, polyamide-imides, polystyrene (PS), polyphenylene oxide (PPO), polyphthalamide (PPA), polyvinyl alcohol (PVA), acrylonitrile butadiene styrene (ABS), polycarbonate (PC), thermoset, PBI-PEEK, urea, epoxies, polyurethanes, or any combination thereof. In some embodiments, the plastic is a polyethylene. In particular embodiments, the plastic is a high density polyethylene.

[0067] In further embodiments, the flexible substrate can be deformed (e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 5 degrees. In some embodiments, the flexible substrate can be deformed e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 10 degrees. Unless otherwise specified, the central angle is measured for a curve in relation to an apex of the curve.

[0068] The materials of the support substrate can be selected by the manufacturer based on the end application of the transistor structure and the ultimate device being manufactured. For example, if the transistor structure is incorporated with an array of transistor structures, the array could be implemented within a liquid crystal display. Other end applications include wearable electronics. The support substrate can be transparent or non-transparent, such as those that can be used in some reflective displays.

[0069] Manufacturing on non-conducting flexible support substrates can reduce manufacturing costs significantly. Such substrates can enable roll-to-roll manufacturing of transistors. Such manufacturing changes can redefine the electronic supply chain.

[0070] The thin-film electronic device 100 includes a layer of conductive material 104 positioned on the substrate 102. The layer of conductive material 104 can include a crystalline material, a polycrystalline material, or an amorphous material, according to various embodiments. The layer of conductive material 104 can include a metal or other types of conductive materials. As will be described in greater detail with respect to Figures 1.2 and 1.3, the layer of conductive material 104 has a smooth upper surface.

[0071] In one embodiment, the layer of conductive material 104 includes titanium aluminum. In particular, the layer of conductive material 104 can include TiAk. In at least one embodiment, the layer of conductive material 104 is TiAk. The thickness of the TiAk such as TiAk is between 80 nm and 100 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The TiAk such as TiAk can have an amorphous structure. The TiAk such as TiAk can be deposited with a physical vapor deposition (PVD) process. The PVD process can include sputtering, evaporation, or other PVD processes. The TiAk such as TiAk has a roughness less than 1 nm.

[0072] In one embodiment, the layer of conductive material 104 includes titanium. The thickness of the titanium is between 80 nm and 100 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The titanium can have a crystalline structure. The titanium can be deposited with a PVD process. The PVD process can include sputtering, evaporation, or other PVD processes. The titanium has a roughness less than 2 nm.

[0073] In one embodiment, the layer of conductive material 104 includes molybdenum. The thickness of the molybdenum is between 40 nm and 60 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The molybdenum can have an amorphous structure. The molybdenum can be deposited with a PVD process. The PVD process can include sputtering, evaporation, or other PVD processes. The molybdenum has a roughness less than 2 nm.

[0074] In one embodiment, the layer of conductive material 104 includes copper, aluminum or any other suitable metal or conductive material. The thickness of the material 104 is between 15 nm and 35 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The copper or other conductive material can have a crystallinestructure. If copper is utilized, the copper can be deposited with an atomic layer deposition (ALD) process. The copper has a roughness less than 2 nm.

[0075] Figure 1.2 is a cross-sectional view of the thin-film electronic device 100 and an intermediate stage of processing, according to one embodiment. In Figure 1.2, the layer of conductive material 104 has been patterned to form a gate electrode 106. The gate electrode can be formed from the layer of conductive material 104 by a photolithography process. The photolithography process can include patterning a mask on the layer of conductive material 104 and etching the layer of conductive material 104 in the presence of the mask. The etching process can include a wet etch or dry etch. The resulting gate electrode 106 has a shape corresponding to the shape of the mask.

[0076] The gate electrode 106 has a top surface 108. The roughness of the top surface 108 can affect the performance of the thin-film transistor in which the gate electrode 106 will be part. As will be set forth in more detail in subsequent figures, gate insulator and semiconductor materials will be formed above the gate electrode 106. The roughness of the top surface 108 of the gate electrode 106 influences the roughness of subsequent gate insulator and semiconductor layers. If the top surface 108 of the gate electrode 106 is rough, the top surface of the subsequent gate insulator and semiconductor layers may likewise be rough. If the top surface of the gate electrode 106 is smooth, the top surface of the subsequent gate insulator and semiconductor layers may likewise be smooth.

[0077] The smoothness of the top and bottom surfaces a semiconductor layer of a thin- film transistor can affect the performance of the thin-film transistor. Rougher top and bottom surfaces of a semiconductor layer can result in trap states that can trap charge carriers, such as electrons, and prevent them from transitioning across the bandgap from a valence band to a conduction band. While trap states can exist anywhere within a semiconductor material, trap states are much more likely to occur at rough surfaces of a semiconductor material. The more charge carriers that are trapped in trap states at the surfaces of the semiconductor layer, the lower the conductivity of the semiconductor layer. Low conductivity in the semiconductor layer may correspond to poor performance of the thin-film transistor.

[0078] As the roughness of the surfaces of the semiconductor layer is influenced by the roughness of the gate electrode 106, embodiments of the present disclosure provide a gate electrode 106 having a top surface 108 with low roughness. In one embodiment, the top surface 108 of the gate electrode 106 has a roughness less than 2 nm. Based on the material of the deposition process of the layer of conductive material 104, the top surface 108 of the gateelectrode 106 may have a roughness less than 1 nm. For example, a gate electrode 106 of crystalline titanium may have a roughness of about 0.5 nm. A gate electrode 106 of amorphous TiAk such as amorphous TiAh may have a roughness of about 0.2 nm.

[0079] Unless stated otherwise, as used herein, roughness values are given as root mean square (RMS) roughness values, though other types of roughness values can be used. For example, roughness can be given as the arithmetical mean deviation of an assessed surface profile, as a maximum valley depth of the assessed surface profile, the maximum peak height of the assessed surface profile, the skewness of the assessed surface profile, the kurtosis of the assessed surface profile, or the average distance between the highest peak and lowest valley in each sampling length. Those of skill in the art will recognize, in light of the present disclosure, that while RMS roughness is used herein, various other surface roughness assessments can be utilized without departing from the scope of the present disclosure.

[0080] Figure 1.3 is an enlarged cross-sectional view of a portion of the top surface 108 of the gate electrode 106 of Figure 1.2, according to one embodiment. The view of Figure 1.3 illustrates that the top surface 108 includes various peaks and valleys. The heights and depths of the peaks and valleys as shown in Figure 1.3 may not correspond to an accurate representation of the top surface 108 of the gate electrode 106. However, the view of Figure 1.3 is helpful in illustrating the principle of surface roughness and, in particular, RMS roughness.

[0081] In Figure 1.3, a mean line ML is illustrated. The mean line ML corresponds to the mean height of the top surface 108 when all peaks and valleys are taken into account along the sampling length L. Accordingly, the mean line ML is at a height between the highest peak and the lowest valley of the top surface 108 of the gate electrode 106.

[0082] The RMS roughness is represented by the line RQ in Figure 1.3. The RMS roughness RQ is calculated by taking a number of height measurement samples relative to the mean line ML. Heights that are greater than the mean line ML have a positive value. Heights that are lower than the mean line ML have a negative value. Each of the individual height measurements is squared. The squares of all the height measurements are summed and divided by the number of samples. The square root of this value is the RMS roughness RQ and has units of distance. Accordingly, and RMS roughness of 2 nm means that the line RQ is 2 nm above the mean line ML. A larger RMS roughness value indicates a rougher surface. Unless specified otherwise, roughness values provided herein correspond to RMS roughness values.

[0083] Materials, deposition processes, and etching processes for forming the gate electrode 106 are selected to provide a top surface 108 having a roughness less than 2 nm. Inparticular embodiments, the roughness may be less than 1 nm or less than 0.5 nm. Such low roughness values of the top surface 108 can promote subsequently deposited layers having similarly low roughness values.

[0084] With reference again to Figure 1.1, after deposition of the layer of conductive material 104, one or more planarization processes may be performed on the layer of conductive material 104. For example, a chemical mechanical planarization (CMP) process may be performed on the layer of conductive material 104. The CMP process utilizes chemical and mechanical polishing processes to reduce the roughness of the top surface of the layer of conductive material 104. This can result in the gate electrode 106 having a top surface 108 with low roughness.

[0085] With reference again to Figure 1.2, after patterning the conductive material 104 to form the gate electrode 106, one or more planarization processes may be performed on the gate electrode 106. For example, a CMP process may be performed on the gate electrode 106 to further reduce the roughness of the top surface 108 of the gate electrode 106.

[0086] The gate electrode 106 can be formed in ways other than those described above. For example, the gate electrode 106 can be formed by depositing the gate electrode metal in trench or gap formed in a dielectric layer formed on the substrate 102. This can be followed by a planarization process, such as a CMP process to remove excess metal and to reduce the roughness of the top surface 108 of the gate electrode 106.

[0087] Figure 1.4 is a cross-sectional view of the thin-film electronic device 100, according to one embodiment.

[0088] As shown in Figure 1.4, a gate insulator 112 is on the top surface 108 of the gate electrode 106 and on portions of the substrate 102. The gate insulator 112 has a material and thickness selected to enable the gate insulator 112 to electrically insulate the gate electrode 106 from a semiconductor material 124 on the gate insulator 112, which may be at a semiconductor channel region.

[0089] The gate insulator 112 can have a thickness between 5 nm and 25 nm. The inventors have found that such a relatively low thickness can result in a top surface 114 of the gate insulator 112 having a relatively low roughness. In particular, when the gate insulator 112 has a thickness less than 25 nm and is formed on a gate electrode 106 having a top surface 108 with a roughness less than 2 nm, the gate insulator 112 has a top surface 114 with a low roughness. In one example, the roughness of the top surface 114 of the gate insulator 112 is lessthan 2 nm. The low surface roughness of the top surface 114 of the gate insulator 112 can promote low surface roughness in a subsequently deposited semiconductor layer.

[0090] The gate insulator 112 can include AkO3 such as AI2O3, AkOy, or some other high-k dielectric material, for example, some other type of high-k dielectric oxide material. For example, while the following discussion will be directed to the gate insulator 112 including AhOx such as AI2O3, it will be readily appreciated that another type of suitable high-k dielectric material is used in alternative embodiments. The thickness and deposition process utilized for forming the gate insulator 112 can be selected based on the material and thickness of the gate electrode 106. The gate insulator 112 can be deposited by a PVD process, a CVD process, such as PECVD, or an ALD process. In an example in which the gate electrode 106 includes TiAk such as TiAk with a thickness between 80 nm and 100 nm and a surface roughness less than 1 nm, the AhOx such as AI2O3 gate insulator 112 can be deposited with a PVD process. The thickness of the AI2O3 gate insulator 112 can be about 15 nm. In an example in which the gate electrode 106 includes Ti with a thickness between 80 and 100 nm and the surface roughness less than 2 nm, the AkOx such as AI2O3 gate insulator 112 can be deposited with a PVD process and have a thickness of about 15 nm. In an example in which the gate electrode 106 includes molybdenum with a thickness between 40 nm and 60 nm and a surface roughness less than 2 nm, the AhOx such as AI2O3 gate insulator 112 can be deposited with an ALD process and can have a thickness between 5 nm and 15 nm. In an example in which the gate electrode 106 includes copper with a thickness between 20 nm and 30 nm in the surface roughness less than 2 nm, the AhOx such as AI2O3 gate insulator 112 can be deposited with an ALD process and have a thickness between 3 nm and 8 nm. In an example in which the gate electrode includes titanium with a thickness between 20 nm and 30 nm in the surface roughness less than 2 nm, the gate AhOx such as AI2O3 insulator 112 can be deposited with a PVD process and can have a thickness between 5 nm and 15 nm.

[0091] The gate insulator 112 can include materials other than AhOx such as AI2O3 such as other types of high-k dielectric materials, for example, other types of high-k dielectric oxide materials. For example, the gate insulator 112 can include one or more of silicon oxide, silicon nitride, a metal oxide, hafnium oxide, etc. In embodiments, the gate insulator 112 insulator is a metal oxide or metal nitride that can be formed in a very thin layer. In some embodiments, portions of the gate insulator layer 112 between the source / drain electrodes and the gate electrode 106 may be thinner than other portions.

[0092] A source electrode 120 and a drain electrode 122 are on the gate insulator 112. The source electrode 120 and the drain electrode 122 can have a thickness between 50 nm and 100 nm. The source electrode 120 and the drain electrode 122 include a metal, and the metal can include one or more of copper, aluminum, titanium, tungsten, or other suitable metals. The source electrode 120 and the drain electrode 122 may have been formed utilizing PVD, chemical vapor deposition (CVD), ALD, or other suitable deposition processes.

[0093] A semiconductor material 124 is on the source electrode 120, the drain electrode 122, and the exposed portion of the gate insulator 112 that is not covered by the source electrode 120 and the drain electrode 122. The semiconductor material 124 can have a thickness between 15 nm and 55 nm. The semiconductor material 124 may have been formed with a deposition process including PVD, plasma enhanced CVD (PECVD), and PECVD with Excimer laser annealing (ELA).

[0094] The semiconductor material 124 can include one or more of IGZO (compositions of In, Ga, Zn, and O), low temperature poly crystalline silicon (LTPS), amorphous silicon, or other suitable semiconducting materials such as other types of metal oxide semiconductors or semiconductor materials. In other words, any suitable semiconductor materials is capable of being utilized for the semiconductor material 124. For example, while the following discussion will be directed to the semiconductor material 124 including IGZO, it will be readily appreciated that another type of suitable semiconducting material is used in alternative embodiments. In an example in which the gate insulator 112 includes AhOx such as AI2O3 between 10 nm and 20 nm in thickness, the semiconductor material 124 can include IGZO between 30 nm and 50 nm in thickness, formed with a PVD process. In an example in which the gate insulator 112 includes AhOx such as AI2O3 between 5 nm and 15 nm in thickness and the gate electrode 106 includes molybdenum, the semiconductor material 124 can include LTPS between 40 nm and 60 nm in thickness, formed with a PECVD process followed by an ELA process. In an example in which the gate insulator 112 includes AhOx such as AI2O3 between 3 nm and 8 nm in thickness, the semiconductor material 124 can include amorphous silicon between 40 nm and 60 nm in thickness, formed with a PECVD process. In an example in which the gate insulator 112 includes AhOx such as AI2O3 between 5 nm and 15 nm in thickness and the gate electrode 106 includes titanium, the semiconductor material 124 can include IGZO between 15 nm and 25 nm in thickness, formed with a PVD process followed by an ELA process. These embodiments can result in a semiconductor material 124 having a bottom surface 126 and a top surface 128 withrelatively low roughness. Accordingly, the semiconductor material 124 can have a low number of trap states at the bottom and top surfaces 126, 128, and correspondingly high conductivity.

[0095] In some embodiments, IGZO may correspond to amorphous In-Ga-Zn-0 compositions, also referred to as a-IGZO. In other embodiments, IGZO may include crystalline materials. Crystalline IGZO materials may include, for example, InGaZnO4, InGaO3(ZnO)s, or In2Ga2ZnO?. IGZO may also include InwGaxZnyOz in which w, x, y, and z are numbers that collectively sum to 1 and individually represent the proportion, by mass, of the material made up by the corresponding element. The values of w, x, y, and z can vary based on the deposition process. In one example, w = 0.486, x = 0.267, y = 0.99, and z = 0.148. Other values of w, x, y, and z can be utilized without departing from the scope of the present disclosure.

[0096] The semiconductor material 124 terminates on the source electrode 120 and the drain electrode 122. The semiconductor material 124 terminates on the source electrode 120 and the drain electrode 122 as the semiconductor material 124 may have been previously patterned and etched with photolithographic masking process followed by a wet or a dry etch to form the semiconductor material as shown in Figure 1.4.

[0097] A passivation layer 131 is on the semiconductor material 124 and portions of the source electrode 120 and drain electrode 122 not covered by the semiconductor material 124. The passivation layer 131 can include a dielectric material with a thickness between 50 nm and 500 nm. The passivation layer 131 can include one or more of silicon dioxide, silicon nitride, or other dielectric materials.

[0098] As shown in Figure 1.4, the thin-film transistor 132 is fully formed and complete. The thin-film transistor 132 includes the gate electrode 106, the gate insulator 112, the source electrode 120, the drain electrode 122, and the semiconductor material 124. The semiconductor material 124 includes a channel region 130. The channel region 130 corresponds to the portion of the semiconductor material 124 between the source and drain electrodes 120, 122 and the above the gate electrode 106. The gate insulator 112 separates the channel region 130 of the semiconductor material 124 from the gate electrode 106.

[0099] The thin-film transistor 132 can operate by selectively applying voltages to the gate electrode 106, the source electrode 120, and the drain electrode 122. In one example, thin- film transistor 132 is turned on by applying a gate to source voltage and a drain to source voltage of about 4 V. The thin-film transistor 132 can be turned off by applying a gate to source voltage of 0 V. Other voltages can be utilized without departing from the scope of the present disclosure.

[0100] Figure 1.5 is a top view of the thin-film transistor 132 of Figure 1.4. The gate insulator 112 and the passivation layer 131 are hidden for visibility of the semiconductor layer 124, the source electrode 120, the drain electrode 122, and the gate electrode 106. Figures 1.4 and 1.5 illustrate that the semiconductor material 124 is positioned over portions of the gate electrode 106, the source electrode 120, and the drain electrode 122. The various components of the thin-film transistor 132 can have other shapes and arrangements without departing from the scope of the present disclosure.

[0101] While the description of Figures 1.1-1.5 has primarily described a thin film transistor 132 including a gate electrode 106 having a top surface 108 with low roughness, principles of the present disclosure can extend to other structures formed in the thin-film electronic device 100. For example, a layer of conductive material can be patterned to form various types of metal structures on the substrate 102 in addition to the gate electrode 106. These other metal structures will also have top surfaces with the low roughness of the top surface 108. Accordingly, these other metal structures, and the structures formed over them, may also benefit from the low roughness top surface. The other metal structures can include metal lines, contacts, plugs, or types of metal structures that may be formed with the metal of the gate electrode 106.

[0102] Figure 1.6 is a cross-sectional view of a thin-film electronic device 200 including a thin-film transistor 232, according to one embodiment. The transistor 232 includes a gate electrode 206 positioned on a substrate 202. The gate insulator 212 is positioned on the gate electrode 206 and the substrate 202. A semiconductor material 224 is positioned on the gate insulator 212. A source electrode 220 and the drain electrode 222 are positioned on the semiconductor material 224. A passivation layer 231 is positioned on the source electrode 220, the drain electrode 222, and the semiconductor material 224. Accordingly, the thin-film transistor 232 of Figure 1.6 is substantially similar to the thin-film transistor 132 of Figures 1.4 and 1.5, except that the source and drain electrodes 220, 222 are formed after formation of the semiconductor material 224. The various components of the thin-film transistor 232 can be formed with the same processes, dimensions, and materials as described previously in relation to Figures 1.1-1.5.

[0103] The gate electrode 206 has surface roughness characteristics as described in relation to the gate electrode 106 of Figure 1.1 -1.5. This results in the semiconductor material 224 having bottom surface 226 and top surface 228 with low roughness like the semiconductor material 124 of Figure 1.4. Accordingly, although the order of deposition of some of thecomponents of the thin-film transistor 232 is different than the order of deposition of some of the components of the thin-film transistor 132, the thin-film transistor 232 has the same beneficial low surface roughness characteristics as the thin-film transistor 132.

[0104] Figure 1.7 is a top view of the thin-film transistor 232 of Figure 1.6. The top view of the thin-film transistor 232 illustrates that the source electrode 220 and the drain electrode 222 are positioned on the semiconductor material 224. The semiconductor material 224 is positioned over the gate electrode 206. The passivation layer 231 is hidden for visibility of the source electrode 220, the drain electrode 222, the semiconductor material 224, and the gate electrode 206.

[0105] Figure 1.8 is a cross-sectional view of a thin-film electronic device 300 including a thin-film transistor 332, according to one embodiment. The thin-film transistor 332 includes a substrate 302, a gate electrode 306 positioned on the substrate 302, a gate insulator 312 positioned on the gate electrode 306 and substrate 302, source and drain electrodes 320, 322 positioned on the gate insulator 312, and a semiconductor material 324 positioned on the source electrode 320, the drain electrode 322, and the gate insulator 312. These components of the thin- film transistor 332 can be formed with the same processes, materials, and thicknesses described for the thin-film transistor 132 in relation to Figures 1.1-1.5. The thin-film transistor 332 is substantially similar to the thin-film transistor 132 of Figure 1.4, except that a second gate insulator 333 is positioned on the semiconductor material 324 and a second gate electrode 334 is positioned on the second gate insulator 333. The second gate insulator 333 can be of the same material and thickness as the gate insulator 312. The second gate electrode 334 can have a same material and thickness as the gate electrode 306. Control of currents in the channel region 330 can be enhanced by applying the same voltages to the second gate electrode 334 as are applied to the first gate electrode 306. Though not shown in Figure 1.8, a passivation layer, similar to the passivation layer 131, can be deposited on the thin-film transistor 332. In the example of Figure 1.8, gate electrode 306 can be considered a first gate electrode.

[0106] The gate electrode 306 has surface roughness characteristics as described in relation to the gate electrode 106 of Figure 1.1 -1.5. This results in the semiconductor material 324 having bottom surface 326 and top surface 328 with low roughness like the semiconductor material 124 of Figure 1.4. Accordingly, although the order of deposition of some of the components of the thin-film transistor 332 is different than the order of deposition of some of the components of the thin-film transistor 132, the thin-film transistor 332 has the same beneficial low surface roughness characteristics as the thin-film transistor 132.

[0107] The thin-film transistor 332 will include contacts or other electrical connections through the second gate insulator 333 to the source and drain electrodes 320, 322. These contacts are in openings formed in the second gate insulator 333, which are not shown in Figure 1.8. The contacts may be formed in a same processing step as the second gate electrode 334 such that they are formed from the same layer, but are electrically isolated from each other.

[0108] Figure 1.9 is a top view of the thin-film transistor 332 of Figure 1.8. The top view of the thin-film transistor 332 illustrates that the second gate electrode 334 is positioned over the semiconductor material 324. The semiconductor material 324 is positioned over the source and drain electrodes 320, 322 and the gate electrode 306.

[0109] Figure 1.10 is a cross-sectional view of a thin-film electronic device 400 including a thin-film transistor 432, according to one embodiment. The thin-film transistor 432 includes a substrate 402, a gate electrode 406 positioned on the substrate 402, a gate insulator 412 positioned on the gate electrode 406 and substrate 402, source and drain electrodes 420, 422 positioned on the gate insulator 412, and a semiconductor material 424 positioned on the source electrode 420, the drain electrode 422, and the gate insulator 412. These components of the thin- film transistor 432 can be formed with the same processes, materials, and thicknesses described for the thin-film transistor 132 in relation to Figures 1.1-1.5. The thin-film transistor 432 is substantially similar to the thin-film transistor 132 of Figure 1.4, except that a second gate insulator 433 is positioned on the semiconductor material 424 and a second gate electrode 434 is positioned on the second gate insulator 433. The second gate insulator 433 can be of the same material and thickness as the gate insulator 412. The second gate electrode 434 can have a same material and thickness as the gate electrode 406. Control of currents in the channel region 430 can be enhanced by applying the same voltages to the second gate electrode 434 as are applied to the first gate electrode 406. Though not shown in Figure 1.10, a passivation layer, similar to the passivation layer 131, can be deposited on the thin-film transistor 432. In the example of Figure 1.10, the gate electrode 406 can be considered a first gate electrode.

[0110] The gate electrode 406 has surface roughness characteristics as described in relation to the gate electrode 106 of Figure 1.1 -1.5. This results in the semiconductor material 424 having bottom surface 426 and top surface 428 with low roughness like the semiconductor material 124 of Figure 1.4. Accordingly, although the order of deposition of some of the components of the thin-film transistor 432 is different than the order of deposition of some of the components of the thin-film transistor 132, the thin-film transistor 432 has the same beneficial low surface roughness characteristics as the thin-film transistor 132.

[0111] Figure 1.11 is a top view of the thin-film transistor 432 of Figure 1.10. The top view of the thin-film transistor 432 illustrates that the second gate electrode 434 is positioned over the semiconductor material 424. The source and drain electrodes 420, 422 are positioned over the semiconductor material 424. The semiconductor material 424 is positioned over the gate electrode 406.

[0112] In view of the above embodiments of the thin-film electronic devices 100, 200, 300, 400 as described with respect to Figures 1.1-1.5, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11, when powered, electrons travel through the respective semiconductor materials 124, 224, 324, 424. The electrons travel through the semiconductor materials 124, 224, 324, 424 directed from the respective source electrode towards the respective drain electrode, which in the embodiments of the thin-film electronic devices 100, 200, 300, 400 are directed from left-to-right. As these electrons move left-to-right along the semiconductor materials 124, 224, 234, 424 based on the orientation of the thin-film devices 100, 200, 300, 40 as shown in Figures 1.1-1.5, 1.6, 1.7, 1.8, 1.9, 1.10, and 1.11, the electrons may be exposed to various types of disruption, interruptions, or disturbances that cause at least some of the electrons to scatter, which as set forth earlier here in generally referred to as “scattering.” These disturbances may include electrons bumping into each other, electrons being exposed to other types of charges, electrons being exposed to physical impurities within the semiconductor layer, electrons being exposed to a surface roughness or topography at a gate insulator and semiconductor interface (z.e., surface roughness scattering), or electrons being exposed to distortions, fluctuations, or non-uniformities within an electrical field causing the flow of electrons through the semiconductor layer (z.e., remote surface roughness scattering).

[0113] Electron / hole scattering caused by the surface roughness or topography at the gate insulator and semiconductor interface (e.g., where the respective gate insulators 112, 212, 312, 412 meet the respective semiconductor materials 124, 224, 324, 424) may be referred to as surface roughness scattering. This type of surface roughness scattering may also occur at an interface between the second gate insulator 333 and the semiconductor material 334 as shown in Figure 1.8 or at an interface between the second gate insulator 433 and the semiconductor material 424 as shown in Figure 1.10.

[0114] Figure 1.12 is a cross-sectional view of a thin-film transistor of a microelectronic device illustrating surface roughness scattering. It will be readily appreciated that this discussion of surface roughness scattering may apply to the various embodiments of the thin-film electronic devices 100, 200, 300, 400 as discussed earlier herein.

[0115] As shown in Figure 1.12, a surface roughness at a semiconductor interface between a gate insulator and a semiconductor material results in peaks and valleys being present at the semiconductor interface. As electrons move as shown in Figure 1.12, at least some of the electrons that are traveling through the semiconductor material in close proximity to the semiconductor interface bump into the peaks resulting in surface roughness scattering, which means these electrons no longer move ideally from right to left as shown in Figure 1.12. This causes noise within an electrical signal passing through the semiconductor material by the movement of the electrons from right to left as shown in Figure 1.12. The surface roughness or topography at the semiconductor interface is affected by the surface roughness or topography of gate electrode at the gate interface as shown in Figure 1.12. In other words, when the gate insulator is formed on the gate electrode, the surface roughness or topography of the gate electrode is transferred to a surface of the gate insulator at the semiconductor interface. This was found and determined by data collection by the inventors as will become readily apparent in view of the discussion that follows herein with respect to Figures 1.16-1.18. Furthermore, it was found by the inventors that the surface roughness or topography of the surface of the gate electrode at the gate interface is transferred to the surface of the gate insulator at the semiconductor interface regardless of the thickness of the gate insulator.

[0116] Figure 1.13 is a cross-sectional view of a thin-film transistor of a microelectronic device, in which the gate electrode surface is flat and the surface of the gate insulator has some surface roughness or topography at the semiconductor interface for the purposes of further illustrating surface roughness scattering. A dotted line represents an average gate insulator thickness (z.e., thickness between the surface of the gate electrode at the gate interface to an imaginary surface of the gate insulator if it were perfectly flat, which is determined by taking an average of the thickness along various points of the surface of the gate insulator at the semiconductor interface). As will be readily appreciated, as the electrons as shown in Figure 1.13 get closer and closer to the surface of the gate insulator along the z-direction, a likelihood of these electrons scattering due to the surface roughness scattering effect is increased, which increases noise within an electrical signal as the electrical signal passes or flows through the semiconductor material.

[0117] Charge carrier scattering caused by distortions, fluctuations, or non-uniformities within the electrical field causing the flow of electrons through the respective semiconductor materials 124, 224, 324, 424 may be referred to as a remote surface roughness scattering. The distortions, fluctuations, and non-uniformities within the electrical field are caused by the surfaceroughness or topography at respective top surfaces 108, 208, 308, 408 of the respective gate electrodes 106, 206, 306, 406 as a distance between the respective top surfaces 108, 208, 308, 408 from the respective semiconductor materials 124, 224, 324, 424 varies as one moves along the respective top surfaces 106, 206, 306, 406. For example, peaks of the surface roughnesses or topographies of the respective top surfaces 106, 206, 306, 406 are closer to the respective semiconductor materials 124, 224, 324, 424 generally as compared to valleys of the surface roughnesses or topographies of the respective top surfaces 106, 206, 306, 406. These differences in distances results in the electrical field applied to the respective semiconductor materials 124, 224, 324, 424 being different at various points along the respective top surfaces 108, 208, 308, 408. This type of remote surface roughness scattering may occur similarly with respect to the second gate electrode 434 and the semiconductor material 424 as shown in Figure 1.10. In at least some embodiments, the surface roughness or topography at the respective top surfaces 108, 208, 308, 408 of the respective gate electrodes 106, 206, 306, 406 is less than 10% different from the corresponding surface roughnesses of the corresponding one of the respective top surfaces of the corresponding ate insulators 112, 212, 312, 412.

[0118] Figure 1.14 is a cross-sectional view of a thin-film transistor of a microelectronic device illustrating remote surface roughness scattering. It will be readily appreciated that this discussion of the remote surface roughness scattering may apply with respect to the various embodiments of the thin-film electronic devices 100, 200, 300, 400 as discussed earlier herein.

[0119] As shown in Figure 1.14, a surface roughness at a semiconductor interface between a gate insulator and a semiconductor material results in peaks and valleys being present at the semiconductor interface, and a surface roughness at a gate interface between a gate electrode and a gate interface results in peaks and valleys being present at the gate interface. As electrons move as shown in Figure 1.14, the electrons that are traveling through the semiconductor material are moving due to being exposed to a gate electrical field and a semiconductor electric field as represented by arrows extending vertically through the gate insulator and the semiconductor material based on the orientation as shown in Figure 1.14. The various widths of the arrows represent differences in strengths in the gate and semiconductor electric fields caused by the surface roughnesses or topographies at the semiconductor interface and the gate interface. The semiconductor field is essentially a mirror of the gate electric field. While the electrons ideally move right to left as shown in Figure 1.14, distortions, fluctuations, and non-uniformities in the gate and semiconductor electric fields result in an increased likelihood of scattering of these electrons or holes, which means these charge carriers no longermove ideally from right to left as shown in Figure 1.14. This type of scattering is referred to as remote surface roughness scattering as the gate electric field being generated at the gate interface is spaced apart from the semiconductor interface due to the peaks and valley at the gate interface. The peaks and valleys at the semiconductor interface may also affect the non-uniformities within the gate electric field as well because as one moves along the semiconductor interface and the gate interface a distance between them does not remain the same and instead fluctuates. These distortions, fluctuations, or non-uniformities in the gate electrical field causes the electrons to be exposed to different strengths of the semiconductor electrical field resulting in at least some of the electrons scattering due to this remote surface roughness scattering effect causing noise within an electrical signal passing through the semiconductor material. In other words, in view of the above discussions, when the surface roughness or topography at the gate interface is relatively high, the gate electric field has greater distortions, fluctuations, or non-uniform ties along the semiconductor interface generating greater distortions, fluctuations, or non- uniformities in the semiconductor electrical field increasing the remote surface roughness scattering. This was found and determined by the inventors as will become readily apparent in view of the discussion that follows herein with respect to Figures 1.16-1.18. Furthermore, it was found by the inventors that the surface roughness or topography of the surface of the gate electrode at the gate interface is transferred to the surface of the gate insulator at the semiconductor interface.

[0120] Figure 1.15 is a cross-sectional view of a thin-film transistor of a microelectronic device, in which the gate insulator surface is flat and the surface of the gate electrode has some surface roughness or topography at the gate interface. A dotted line represents an average gate insulator thickness (z.e., thickness between the surface of the gate insulator at the semiconductor interface to an imaginary surface of the gate electrode if it were perfectly flat, which is determined by taking an average of the thickness along various points of the surface of the gate electrode at the gate interface). As will be readily appreciated as the electron as shown in Figure 1.13 moves from left to right, a distance between the electron and the surface of the gate electrode resulting in the electron being exposed to electrical fields with different strengths as the electron travels through the semiconductor material. In other words, as the surface roughness or topography of the surface of the gate electrode increases, a likelihood of this scattering due to the remote surface roughness scattering effect is increased, which increases noise within an electrical signal as the electrical signal passes or flows through the semiconductor material.

[0121] In view of above discussion, the inventors have determined that the surface roughness or topography of the gate electrode at the gate interface is directly proportional to an amount of distortion, fluctuation, or non-uniformity within the gate electrical field that results in the remote surface roughness scattering effect as discussed herein. Furthermore, a high roughness (e.g., high surface roughness) at the surface of the gate electrode at the gate interface will have a negative impact on performance regardless of a bottom gate configuration or a top gate configuration of a thin-film transistor. In other words, the position of the gate does not appear to matter as much as the smoothness (e.g., low surface roughness) of the surface of the gate electrode at the gate interface.

[0122] In view of the above discussion, preventing or mitigating the effects of surface roughness scattering and remote surface roughness scattering would reduce noise present within the electrical signal passing through the semiconductor material. The inventors have found that by utilizing an amorphous metal for the respective gate electrode 106, 206, 306, 406 in the various embodiments as set forth above generates a smooth surface roughness or topography of the respective top surfaces 108, 208, 308, 408 (e.g., the RMS of the surface roughness or topography of the respective top surfaces 108, 208, 308, 408 is low meaning that the top surfaces 108, 208, 308, 408 are smooth as compared to when utilizing other types of poly crystalline metals are utilized). Reducing the surface roughness of the respective top surfaces 108, 208, 308, 408 in turn reduces the surface roughness or topography of the surface of the respective gate insulator 112, 212, 312, 412 at the respective gate insulator and semiconductor interface since the surface roughness or topography of the respective gate insulators 112, 212, 312, 412 mimics that of the surface roughness or topography of the respective gate electrode 106, 206, 306, 406, which will become more readily apparent in view of the following discussion herein with respect to Figures 1.16-1.18. The surface roughness of the gate insulators 112, 212, 312, 412 mimics that of the surface roughness of the gate electrode 106, 206, 306, 406 as the gate insulator 112, 212, 312, 412 is formed on the gate electrode 106, 206, 306, 406. This reduction in the surface roughness or topography of the top surfaces 108, 208, 308, 408 and this reduction in the surface roughness or topography at the respective surfaces of the respective gate insulators 112, 212, 312, 412 at the respective gate insulator and semiconductor material interfaces mitigates or reduces the surface roughness scattering and the remote surface roughness scattering effects as discussed earlier herein. This reduction in the effects of the surface roughness scattering and the remote surface roughness scattering mitigates or reduces noise within respective electrical signals passing through the semiconductor materials 124, 224, 324, 424.

[0123] Figure 1.16 is a plurality of images of various respective surfaces of gate electrodes (e.g., top most row) and a plurality of images of various respective surfaces of gate insulators formed on the gate electrodes with different thickness (e.g., 5 lower rows). These images are atomic force microscopy (AFM) images and illustrate the surface roughness or topography of these various surfaces.

[0124] Figure 1.16 is directed to atomic force microscopy images of metallic gate electrodes (a-TiAk such as a-TiA13, Mo, AlNd0.02 and Ti) with a thickness of 200 nm, and AhOx such as AI2O3 gate insulator surfaces for different gate insulator thicknesses ranging from 5 nm to 75 nm formed on these various metallic gate electrodes. The surface topography of the gate insulator strongly resembles that of the underlying gate electrode and is not particularly influenced by the thickness of the gate insulator.

[0125] In view of the above discussion, the top-most row of Figure 1.16 is directed to respective surfaces of gate electrodes made of various gate metals. For example, the image in the upper left-hand corner of Figure 1.16 is directed to the surface roughness or topography of a gate electrode made of TiAk such as TiAk, which is an amorphous metal. The uppermost centerleft image of Figure 1.16 is directed to the surface roughness or topography of a gate electrode made of Mo, which is a polycrystalline metal. The uppermost center-right image of Figure 1.16 is directed to the surface roughness or topography of a gate electrode made of AlNdo.02, which is a polycrystalline metal. The image at the upper-right hand comer of Figure 1.16 is directed to the surface roughness or topography of a gate electrode made of Ti, which is a polycrystalline metal. As shown in these images in the top-most row, the TiAk such as TiAk, which is an amorphous metal, is much smoother (e.g., lower surface roughness) as compared to the other materials, which are polycrystalline metals. These various gate electrodes made of various metal materials have a thickness of 200 nanometers (nm).

[0126] The lower five most rows are directed to various gate insulators (e.g., some types of gate oxides or other types of materials suitable for a gate insulator) formed on the various gate electrodes of different materials. For example, the left-most column and the five lower rows are directed to the various gate insulators (made of AkOx such as AI2O3) formed on the surface of TiAk such as TiAk, the left-center column and the five lower rows are directed to the various gate insulators (made of AhOx such as AI2O3) formed on the surface of Mo, the right-center column and the five lower rows are directed to various gate insulators (made of AkOx such as AI2O3) formed on the surface of AlNdo.02, and the right most column and the five lower rows are directed to various gate insulators (made of AkOx such as AI2O3) formed on the surface of Ti.The thicknesses of the gate insulators increases as you move downward along the lower five rows (e.g., 5 nm, 10 nm, 15 nm, 20 nm, and 75nm).

[0127] As shown in these images in Figure 1.16, the respective surfaces of the gate insulators have a surface roughness or topography very similar to or nearly identical to a surface roughness or topography of the gate electrode on which they are formed regardless of the thickness of the gate insulator. In other words, regardless of how thick the gate insulator is formed on the surface of the gate electrode, the surface roughness of the gate insulator and the surface roughness of the gate electrode will be very similar or mimic each other. Furthermore, as shown in Figure 1.16, since the TiAk such as TiAk has a surface with a surface roughness that is smoother as compared to the surfaces of Mo, AlNdo.02, and Ti, the gate insulators formed on the TiAk such as TiAk, which is an amorphous metal, have a smoother surface as compared to those gate insulators formed on the Mo, AlNdo.02, and Ti, which are polycrystalline metals. In view of this discussion, utilizing the amorphous metal of TiAk such as TiAk means that the surface of the gate electrode and the surface of the gate insulator formed on the surface of the gate electrode are smoother relative to respective surfaces of gate insulators formed on the gate electrodes made of Mo, AlNdo.02, and Ti. In view of this discussion, utilizing the TiAk such as TiAk, which is an amorphous metal, to form the gate electrode further mitigates or reduces the effects of surface roughness scattering and remote surface roughness scattering as compared to when the gate electrodes are made of Mo, AlNdo.02, and Ti, which are poly crystalline metals.

[0128] Figure 1.17 is a graph illustrating data collected with respect to the surface roughnesses and topographies of the various images as shown in Figure 1.16. The points in the graph are representative of root mean squares (RMS) measurements of surface roughness or topography of the gate insulators when formed with different thicknesses (e.g., 0 nm, 5 nm, 10 nm, 15 nm, 20 nm, and 75 nm). As may be readily appreciated the measurements of the surface roughness when the gate insulator has a thickness of 0 nm is actually the surface roughness or topography measurement for the surface of the gate electrode itself. As shown in Figure 1.16, the RMS of the surfaces of the various gate insulators formed on the various gate electrodes made of the various gate metals essentially remains the same regardless of the thickness of the gate insulator. Furthermore, the RMS of the surfaces of the various gate insulators is essentially the same of the RMS of the surfaces of the gate electrodes on which they are formed. Additionally, the RMS surfaces of the gate insulators are the smallest when formed on the TiAk such as TiAk, which is an amorphous metal, as compared to when formed on the Mo, AlNdo.02, and Ti, which are polycrystalline metals.

[0129] Figure 1.18 is a graph illustrating the data collected and depicted in the graph as shown in Figure 1.16 in another format. The circles represent averages of the data points collected with respect to the various thickness of the gate insulator formed on the gate electrode made of various metals. The dotted lines represent a linear relationship representative of the surface roughness of the gate insulators as formed with varying thickness on the various gate electrodes made of various gate metals. As shown in Figure 1.18, one can readily appreciate that the gate insulators formed on the smoother surface of the TiAk such as TiAk, which is an amorphous metal, are smoother and have a lower RMS as when compared to the gate insulators formed on the gate electrodes made of Mo, AlNdo.02, and Ti, which are poly crystalline metals.

[0130] Figure 1.18 is directed to RMS roughness of the gate insulator as a function of gate insulator thickness, for different gate metals. Evidently, based on the linear relationships as shown in Figure 1.18, the surface roughness or topography of the gate electrode is a strongly related to the surface roughness or topography of gate insulator regardless of the thickness of the gate insulator formed on the gate electrode.

[0131] Figure 1.19 is a graph illustrating the mobility of electrons through a semiconductor layer formed on the gate insulators as shown in Figure 1.16 and as discussed with respect to Figures 1.17 and 1.18. As shown in Figure 1.19, when the gate electrode is made of the TiAk such as TiAk, which is an amorphous metal, the electron mobility is greater than electron mobilities when the gate electrode is made of Mo, AlNdo.02, and Ti, which are polycrystalline metals. In view of this discussion, forming the gate electrode from TiAk such as TiAk, which is an amorphous metal, instead of Mo, AlNdo.02, and Ti, which are polycryalline metals, more readily mitigates or reduces the effects of both surface roughness scattering and remote surface roughness scattering as the surfaces of the gate insulators formed on the gate electrode made of TiAk such as TiAk are smoother as compared to gate insulators formed on surfaces of the Mo, AfNck, and Ti.

[0132] Figure 1.19 is directed to Field-effect mobility versus RMS roughness for IGZO TFTs with different gate electrodes at T = 300 K. The surface roughness of the gate insulator results from the underlying gate electrode, causing a reduction in field-effect mobility.

[0133] Furthermore, as one reduces the thickness of the TiAk such as TiAk gate electrode the mobility of the electrons essentially remains the same. In view of this, the thin-film transistors can be made even thinner by reducing the thickness of the TiAk such as TiAk while at the same time mitigating or reducing the effects of surface roughness scattering and remote surface roughness scattering.

[0134] In view of the above discussion with respect to Figures 1.16-1.18 and 1.19, we begin by discussing the surface characteristics of the gate electrode and gate insulator measured using atomic force microscopy (AFM). The surface of the AhOx such as AI2O3 gate insulator is effectively identical to the underlying gate electrode. AFM images (e.g., see, Figure 1.16) of the surfaces of each of the four metallic gates (a-TiAk such as a-TiA13, Mo, AlNd0.02 and Ti) are shown in the first row of Figure 1.16. Also shown in the remaining rows of Figure 1.16 are the surfaces of the AhOx such as AI2O3 gate insulator (with thickness ranging from 5 to 75 nm) deposited on top of each gate electrode. We note that the film thickness of each gate metal is the same (200 nm), and all metals are polycrystalline except for a-TiAk such as a-TiA13 which is amorphous. Evidently, the surface topography of the AhOx such as AI2O3 gate insulator strongly resembles that of the underlying gate electrode and is not particularly influenced by the thickness of the gate insulator.

[0135] The RMS roughness of the gate insulator is correlated to the thickness of the gate insulator, but strongly correlated to the gate electrode. Figure 1.18 shows the RMS roughness of the gate insulator, computed over the entire scan area from the data in Figure 1.16, as a function of gate insulator thickness for each of the gate electrodes. The measured RMS roughness ranges from approximately 0.35 nm (a-TiAk such as a-TiA13) to 4.5 nm (Ti) over the range of gate insulator thickness (5 nm to 75 nm).

[0136] The transfer of the gate electrode’s surface structure onto the surface of the gate insulator can be explained based on a low surface mobility of AhOx such as AI2O3 clusters, due to the large melting point of AhOx such as AI2O3 and the low substrate temperature during deposition.

[0137] In view of the above discussion with respect to the graphs as shown in Figures 1.17 and 1.18, it will be readily appreciated that the effects of the surface roughness scattering and the remote surface roughness scattering may be mitigated or reduced when utilizing TiAk such as TiAh, which is an amorphous metal, for the gate electrode as compared to when utilizing Mo, AlNdo.02, or Ti, which are polycrystalline metals.

[0138] The increase in roughness of the gate insulator can degrade field-effect mobility through increased charge carrier scattering (e.g., surface roughness scattering and remove surface roughness scattering). The field-effect mobility is shown as function of RMS roughness in Figure 1.19, for IGZO BGTC TFTs having a gate insulator thickness of 75 nm. As shown, the fieldeffect mobility reduces with increasing surface roughness. This result is consistent with thecarrier mobility being limited by scattering (e.g., surface roughness scattering and remote electron surface roughness scattering).

[0139] To investigate this further, the field-effect mobility includes using the relaxation time approximation (RTA), in which we take into consideration scattering by ionized impurities, acoustic phonons, optical phonons (polar and nonpolar), surface roughness and remote surface roughness scattering.

[0140] In view of the above discussion herein, in a perfect world, the gate and drain electric fields formed as the result of V(GS) (e.g., voltage between gate and source) and V(DS) (e.g., voltage between drain and source) would cause current to conduct in a straight line through the semiconductor material (e.g., right to left as shown in Figures 1.12 and 1.14 of the present disclosure). In that “perfect world”, TFTs would operate at the theoretical maximum of their field effect mobility with high reliability.

[0141] That “perfect world” includes a perfectly smooth gate insulator-semiconductor interface and a perfectly uniform gate electric field. In actual reality and practice (e.g., a nonperfect world), thin film electronic devices live in a world nowhere near “perfect”. Charges influence each other and are influenced by both the roughness of the gate insulatorsemiconductor interface (electrostatic scattering, which may be surface roughness scattering) and non-uniformities in the surface potential induced in the semiconductor by the gate electric field (electromagnetic scattering, which may be remote surface roughness scattering).

[0142] Electrostatic surface charge scattering is fairly well understood as a mechanism for both limiting field effect mobility and increasing leakage current in IGZO TFTs (see, e.g.. Figure 1.13 of the present disclosure). However, electromagnetic charge scattering (see, e.g.. Figure 1, 15 of the present disclosure) is less well understood in thin film transistors and, therefore, is rarely considered in the analysis of charge scattering in IGZO. One of the reasons: the display industry rarely varies the gate insulator from 200nm silicon dioxide or silicon nitride.

[0143] As Figures 1.13 and 1.15 show, gate metal roughness is a major source of both electrostatic (e.g., surface roughness scattering) and electromagnetic charge scattering (e.g., remote surface roughness scattering) in the semiconductor. Data as collected indicates, at least some of which is provided herein, the surface roughness of both amorphous and crystalline gate metals transfers directly to the surface of gate insulators ranging from 5nm (nanometers) to 75nm (nanometers) thickness. An amorphous gate metal irrefutably represents a path to minimizing charge scattering (e.g., surface roughness scattering and remote surface roughness scattering) in IGZO TFTs.

[0144] An amount of impact an amorphous gate metal has on field effect mobility may be seen as shown in a graph as shown in Figure 1.20 of the present disclosure. Figure 1.20 shows the results of simulations of amorphous and crystalline gate metals using silicon dioxide (“low-k”) and aluminum oxide "(“high-k”) gate insulators varying from 10-100nm (nanometers) thickness.

[0145] From Figure 1.20, the simulation results are clear: the increase in gate electric field strength from using a high-k dielectric oxide gate insulator significantly increases field effect mobility over low-k silicon dioxide; an amorphous gate metal minimizes the impact of charge scattering as gate electric field strength is increased (through reducing gate insulator thickness and moving to a high-k gate insulator); and a crystalline metal contributes to increased charge scattering as gate electric field energy increases.

[0146] IGZO AMeTFT (z.e., amorphous metal thin film transistor) simplifies TFT design considerations. By using an amorphous gate electrode, the IGZO and gate insulator thickness can be optimized towards ideal electrostatic and electromagnetic charge scattering behavior in bulk accumulation. Bulk accumulation allows greater utilization of the IGZO thickness for a given gate capacitance. The combination of improvements to electrostatic and electromagnetic charge scattering are why IGZO AMeTFT have field-effect mobility comparable to LTPS (e.g., low temperature polycrystalline silicon), all while reducing capex by 67% with respect to LTPO (low temperature polycrystalline oxide) for a new backplane fab line and increasing the output capacity of existing fab lines.

[0147] Throughout this disclosure, charge carrier scattering is intended to cover electron scattering and hole scattering as most relevant for the end use case. Section l is a first set of embodiments of the present disclosure and section 2 is a second set of embodiments.

[0148] Section 2: Many aspects of our lives are benefited by utilizing ever smaller electronic devices. These include televisions, mobile electronic devices, like cellular phones, smart phones, tablet computers, and wearable electronics, like smart watches and pedometers. Traditional CMOS transistors built on semiconductor substrates are limited by the materials used to form these circuits, i.e., silicon or other semiconductor wafers. With TFTs, the potential uses of electronic devices can be further expanded to include flexible transistors, and improvements such as: lighter and faster displays; wearable displays; or portable displays; each of which can be integrated into existing applications such as medical devices or emerging applications such as the intemet-of-things. However, as these devices become ever smaller, thicknesses of various layers of TFTs are further reduced toaccommodate the available spaced in the ever smaller devices. A higher field-effect mobility enables more aggressive width- and thickness-scaling of the semiconductor, reducing material cost and increasing transistor density.

[0149] The present disclosure is directed to providing embodiments of TFTs that reduce surface roughness scattering at a gate insulator and semiconductor interface caused by surface roughness associated with a topography of a gate insulator at this respective interface, and reduce remote surface roughness scattering caused by the surface roughness associated with a topography of a gate metal at a gate insulator and gate metal interface. Reducing these charge carrier scattering effects (i.e., surface roughness scattering and remote surface roughness scattering) improves electron transport throughout the semiconductor layer, increasing field-effect mobility and the overall performance of the TFTs. Furthermore, the present disclosure is directed to methods of reducing or managing these charge carrier scattering effects that occur within the semiconductor layer.

[0150] These various embodiments of the present disclosure include field-effect mobility calculated within a relaxation time approximation, considering charge carrier scattering caused by surface roughness (i.e., surface roughness scattering and remote surface roughness scattering), charged impurities, and phonons. Furthermore, for surface roughness related charge carrier scattering (i.e., surface roughness scattering and remote surface roughness scattering) associated with a topography of a gate insulator at a gate insulator and semiconductor interface or associated with a topography of a gate metal at a gate insulator and gate metal interface, a comparison was made using gaussian, exponential and intermediate gaussian- exponential surface models with excellent agreement with respect to collected data. These results support the use of smooth gate metals (e.g., amorphous metals) for realizing high mobility amorphous metal oxide semiconductor TFTs, such as, for example, IGZO TFTs.

[0151] A respective TFT may include a gate metal layer, a gate insulator layer, a semiconductor layer, a source layer and a drain layer that are stacked on one another to form the respective TFT device. Electronic conduction in a transistor occurs via electrons for an n-type semiconductor layer and via holes for a p-type semiconductor layer. Electrons and holes are referred to as charge carriers in either case. Ideally, when an external voltage is applied across the source and drain electrodes in a transistor, charge carriers would move along directions which are parallel (applies to holes) or antiparallel (applies to electrons) to the electric field lines established within the semiconductor by the external voltage. Themotion of the charge carriers would be regarded as ballistic, since the acceleration of charge carriers is unbound, limited only by the electric field. Realistically, charge carriers experience frequent collisions — referred to as scattering or scattering events — which may result in an alteration of the energy or momentum of a charge carrier, despite moving in a direction which — on average — is determined by the electric field established by the applied voltages. The efficiency in which charge carriers move is measured by their mobility, which considers all possible scattering processes. These may include, but are not limited to, scattering by lattice vibrations (i.e., phonons), charged or neutral impurities, or surfaces (i.e., surface roughness scattering) — In TFTs, scattering from surfaces is more important since charge carriers are confined to within the finite thickness of the semiconductor, which is typically much smaller than that used in traditional CMOS transistors. In any transistor, the relevant mobility is referred to as field-effect mobility, which is used to benchmark transistor performance and understanding factors influencing transistor performance. Factors influencing mobility may be introduced by a particular layer stack (i.e., device structure) and / or processing sequence. Importantly, an increase in scattering (of any type) leads to a reduction in field-effect mobility and, therefore, transistor performance.

[0152] In view of the above discussion and for example, increases in a root mean square (RMS) surface roughness (e.g., 0.5 nanometers (nm) to 4.5 nanometers (nm)) of certain metallic gate electrodes (e.g., TiAlx, such asTi Ali, Mo, AlNdo.02, and Ti) is related to a reduction in field-effect mobility. In some situations, this field-effect mobility may be substantially equal to 65 cm2 / Vs. In some situations, this field-effect mobility may be greater than 65 cm2 / Vs. In some situations, this field-effect mobility may be less than 65 cm2 / Vs. In some situations, this field-effect mobility may be within the range of 65 to 37 cm2 / Vs or may be equal to the upper and lower ends of this range. In other words, when there is an increase in the RMS of the surface roughness of a metallic gate electrode of a thin-film transistor (TFT), charge carrier scattering within a semiconductor layer of the TFT is increased, reducing overall performance of the TFT. For example, in a respective bottomgate, top-contact amorphous IGZO (InGaZnCh) TFT having a sputtered AI2O3 gate insulator between an amorphous metal gate and a semiconductor layer of the TFT, atomic force microscopy (AFM) indicates that a surface topography of the AI2O3 gate insulator is practically identical to that of a surface topography of the underlying gate electrode. This relationship between the surface topographies of the AI2O3 gate insulator and the underlying gate electrodes remains the same regardless of a thickness of the AI2O3, which may rangefrom 5 nm to 75 nm. Any change in difference between the surface topographies or roughness of the AI2O3 gate insulator and the underlying gate electrode because of a smaller thickness (e.g., 5 nm) or a larger thickness (e.g., 75 nm) is negligible. Effectively, the surface roughness or topography of the underlying gate electrode is transferred to a gate insulator and semiconductor interface above it. As the surface roughness at the gate insulator and semiconductor interface increases, surface charge carrier scattering at the gate insulator and semiconductor interface increases. As the surface roughness of the underlying gate electrode increases, remote surface roughness scattering increases. In other words, the roughness of the gate determines the roughness at the interface between the gate insulator and semiconductor, resulting in the ability to mitigate surface scattering through the selection of metallic gate electrodes having lower roughness. The result is to increase fieldeffect mobility and overall TFT performance.

[0153] There are six primary mechanisms for scattering of charge carriers in an oxide semiconductor, which have been provided in no particular order as follows herein: (1) surface roughness at a semiconductor-gate insulator interface (i.e., surface roughness scattering), (2) remote surface roughness that generates spatial distortions, fluctuations, or non-uniformities in a transverse electric field — extending outwards from the gate electrode towards charge-carriers in the semiconductor — caused by a surface roughness of the gate at the interface between the gate and gate-insulator (i.e., remote surface roughness scattering), (3) polar optical phonon collisions, (4) acoustic-deformation potential, (5) optical deformation potential, and (6) charged impurity collisions. The primary focus of the following discussion herein will be with respect to preventing, mitigating, or reducing the effects of items (1) (i.e., surface roughness scattering) and (2) (i.e., remote surface roughness scattering) as set forth above.

[0154] A dominant mechanism for charge scattering in a field-effect transistor (FET) with a large gate field (e.g., high energy storage) is surface roughness scattering. Furthermore, remote surface roughness scattering can also be limiting at large gate fields, particularly if a gate insulator has a thickness that is small (e.g., less than 10 nanometers (nm)).

[0155] With respect to remote surface roughness scattering, the roughness of a metallic gate electrode is shown to translate directly to a roughness of a semiconductor-gate interface, which directly impacts field-effect mobility through enhanced surface roughness scattering. The roughness of the gate metal is shown to create spatial distortions, fluctuations, or non-uniformities in an electromagnetic field crated by energy stored in a gate capacitance. These spatial distortions, fluctuations, or non-uniformities impact a mean free path of charge carriers when the electric field within the semiconductor layer is established due to the external voltages applied to the gate, source and drain of the TFT to establish a certain level of conduction through a semiconductor layer of a TFT.

[0156] The use of an amorphous gate metal to replace the typical crystalline gate metal reduces gate metal surface roughness. This reduction in surface roughness of the metallic gate electrode directly results in a reduction in the surface roughness of the gateinsulator at a semiconductor-gate insulator interface. This overall decrease in surface roughness at the semiconductor-gate insulator interface increases the mean free path of charge carriers in the semiconductor, and reduces the effect of distortions, fluctuations, or non-uniformities in the electric field, leading to an increase in field-effect mobility. The use of an amorphous metal gate in a metal oxide transistor therefore increases overall performance of the transistor — independent of the structure of the transistor (e.g., singlegate, top-gate, dual-gate) defined by the relative positions of the various layers and the order in which they are processed.

[0157] Figure 2.1 is a cross-sectional view of athin-film electronic device 2100 (e.g., athin-film transistor (TFT)) and an intermediate stage of processing, according to one embodiment. The thin-film electronic device 2100 includes a substrate 2102. The substrate 2102 corresponds to a support substrate on which a TFT will be formed. The TFT may include many materials and structures that are nontraditional with respect to traditional CMOS transistors. Accordingly, the substrate 2102 may include nontraditional materials and characteristics with respect to CMOS transistors. For example, traditional CMOS transistors are typically prepared on a monocrystalline semiconductor substrate. However, the substrate 2102 may include materials other than monocrystalline semiconductors, though monocrystalline semiconductors can be used in some embodiments. The ability to use materials other than monocrystalline semiconductors can greatly simplify the manufacturing process, reduce the manufacturing cost, and enable new applications (e.g., flexible electronics).

[0158] The substrate 2102 can include a substantially nonconductive material. The substrate can be glass, a polymer, plastic, or other materials. In some embodiments, the substrate is glass, a polymer, plastic, or other material. In other embodiments, the substrate is a rubber. As used herein, "rubber" includes polymers of isoprene as well as forms ofpolyisoprene. In some such embodiments, the substrate is a plastic. Any suitable plastic may be used. In some embodiments, the plastic is a polyimide, an arylamide, acrylamide, polybenzimidazole (PBI), polyetherimide, poly etherketoneketone (PEKK), polyether ether ketone (PEEK), polyamide, polyimide, polyamide- imides, polystyrene (PS), polyphenylene oxide (PPO), polyphthalamide (PPA), polyvinyl alcohol (PVA), acrylonitrile butadiene styrene (ABS), polycarbonate (PC), thermoset, PBI-PEEK, urea, epoxies, polyurethanes, or any combination thereof. In some embodiments, the plastic is a polyethylene. In some embodiments, the plastic is a high-density polyethylene.

[0159] In further embodiments, the flexible substrate can be deformed (e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 5 degrees. In some embodiments, the flexible substrate can be deformed (e.g., bowed, rolled, etc.) to form a curve having a central angle of at least about 10 degrees. Unless otherwise specified, the central angle is measured for a curve in relation to an apex of the curve.

[0160] The materials of the support substrate can be selected by the manufacturer based on the end application of the transistor structure and the ultimate device being manufactured. For example, if the transistor structure is incorporated with an array of transistor structures, the array could be implemented within an OLED or LCD backplane. Other end applications include wearable electronics. The support substrate can be transparent or non-transparent, such as those that can be used in some reflective displays.

[0161] Manufacturing on non-conducting flexible support substrates can reduce manufacturing costs significantly. Such substrates can enable roll-to-roll manufacturing of transistors, and enable new applications (e.g., flexible electronics).

[0162] The thin-film electronic device 2100 includes a layer of conductive material 2104 positioned on the substrate 2102. The layer of conductive material 2104 can include a crystalline material, a polycrystalline material, or an amorphous material, according to various embodiments. The layer of conductive material 2104 can include a metal or other types of conductive materials. As will be described in greater detail with respect to Figures 2.2 and 2.3, the layer of conductive material 2104 has a smooth upper surface indicated by a sufficiently low root mean square surface roughness.

[0163] In one embodiment, the layer of conductive material 2104 includes titanium aluminum. In particular, the layer of conductive material 2104 can include TiAh or a titaniumaluminum alloy of varied composition. The thickness of the TiAh is typically between 60 nm and 200 nm, though other thicknesses can be used without departing from the scope of thepresent disclosure. The TiAh can have an amorphous structure. The TiAh can be deposited with a physical vapor deposition (PVD) process. The PVD process can include sputtering, evaporation, or other PVD processes. The TiAh has an RMS roughness of less than 1 nm.

[0164] In one embodiment, the layer of conductive material 2104 includes titanium. The thickness of the titanium is between 60 nm and 200 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The titanium can have a crystalline structure. The titanium can be deposited with a PVD process. The PVD process can include sputtering, evaporation, or other PVD processes. The titanium has a roughness less than 2 nm.

[0165] In one embodiment, the layer of conductive material 2104 includes molybdenum. The thickness of the molybdenum is between 60 nm and 200 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The molybdenum can have a crystalline structure. The molybdenum can be deposited with a PVD process. The PVD process can include sputtering, evaporation, or other PVD processes. The molybdenum has a roughness less than 2 nm.

[0166] In one embodiment, the layer of conductive material 2104 includes a conductive material. In some situations, the conductive material may include any suitable metal or material containing metal, and may include copper. The thickness is between 15 nm and 35 nm, though other thicknesses can be used without departing from the scope of the present disclosure. The conductive material can have a crystalline structure. The conductive material can be deposited with an atomic layer deposition (ALD) process and having a roughness less than 2 nm.

[0167] Figure 2.2 is a cross-sectional view of the thin-film electronic device 2100 and an intermediate stage of processing, according to one embodiment. In Figure 2.2, the layer of conductive material 2104 has been patterned to form a gate electrode 2106. The gate electrode can be formed from the layer of conductive material 2104 by a photolithography process. The photolithography process can include patterning a mask on the layer of conductive material 2104 and etching the layer of conductive material 2104 in the presence of the mask. The etching process can include a wet etch or dry etch. The resulting gate electrode 2106 has a shape corresponding to the shape of the mask.

[0168] The gate electrode 2106 has a top surface 2108. The roughness of the top surface 2108 can affect the performance of the thin-film transistor in which the gate electrode 2106 will be part. As will be set forth in more detail in subsequent figures, gate insulator and semiconductor materials will be formed above the gate electrode 2106. The roughness of the top surface 2108 of the gate electrode 2106 influences the roughness of subsequent gateinsulator and semiconductor layers. If the top surface 2108 of the gate electrode 2106 is rough, the surfaces of the subsequently deposited gate insulator and semiconductor layers may likewise be rough. If the top surface of the gate electrode 2106 is smooth, the surfaces of the subsequently deposited gate insulator and semiconductor layers may likewise be smooth.

[0169] The smoothness of the top and bottom surfaces a semiconductor layer of a thin-film transistor can affect the performance of the thin-film transistor. An increased RMS roughness of either surface leads to an increase in surface roughness scattering and a reduction in charge carrier mobility. In a transistor, this also results in a reduction in fieldeffect mobility and, therefore, overall transistor performance.

[0170] As the roughness of the surfaces of the semiconductor layer is influenced by the roughness of the gate electrode 2106, embodiments of the present disclosure provide a gate electrode 2106 having a top surface 2108 with low roughness. In one embodiment, the top surface 2108 of the gate electrode 2106 has a roughness less than 2 nm. Based on the material of the deposition process of the layer of conductive material 2104, the top surface 2108 of the gate electrode 2106 may have a roughness less than 1 nm. For example, a gate electrode 2106 of crystalline titanium may have a roughness between 4 nm and 5 nm. A gate electrode 2106 of amorphous TiAh may have a roughness between 0.2 nm and 0.5 nm.

[0171] Roughness may refer to any number of statistical quantities representing the deviation in the height of a surface from an idealized smooth plane. Unless stated otherwise, as used herein, roughness values are given as root mean square (RMS) roughness values, though other types of roughness values can be used without loss of generality (e.g., average roughness). RMS roughness can be given as the arithmetical mean deviation of the surface height of an assessed surface profile, as a maximum valley depth of the assessed surface profile, the maximum peak height of the assessed surface profile, the skewness of the assessed surface profile, the kurtosis of the assessed surface profile, spatial correlation length of the assessed surface profile, or the average distance between the highest peak and lowest valley in each sampling length. Those of skill in the art will recognize, considering the present disclosure, that while RMS roughness is used herein, various other surface roughness assessments can be utilized without departing from the scope of the present disclosure.

[0172] Figure 2.3 is an enlarged cross-sectional view of a portion of the top surface 2108 of the gate electrode 2106 of Figure 2.2, according to one embodiment. The view of Figure 2.3 illustrates that the top surface 2108 includes various peaks and valleys. The heights and depths ofthe peaks and valleys as shown in Figure 2.3 may not correspond to an accurate representation of the top surface 2108 of the gate electrode 2106. However, the view of Figure 2.3 is helpful in illustrating the concept of surface roughness and, particularly, RMS roughness.

[0173] In Figure 2.3, a mean line ML is illustrated along one dimension. The mean line ML corresponds to the average height of the top surface I 08 when all data points representing the surface height — including peak and valley extrema — are considered along the sampling length L, here shown along one dimension. Accordingly, the mean line ML is at a height between the highest peak and the lowest valley of the top surface 2108 of the gate electrode 2106. Those of skill in the art will recognize, considering the present disclosure, that while RMS roughness is depicted here in one dimension, a two-dimensional measure of surface roughness can be used without departing from the scope of the present disclosure.

[0174] The RMS roughness is represented by the line RQ in Figure 2.3. The RMS roughness RQ is calculated by taking several height measurement samples relative to the mean line ML. Heights that are greater than the mean line ML have a positive value. Heights that are lower than the mean line ML have a negative value. Each of the individual height measurements is squared. The squares of all the height measurements are summed and divided by the number of samples. The square root of this value is the RMS roughness RQ and has units of distance. For example, and RMS roughness of 2 nm means that the line RQ is 2 nm above the mean line ML. When used to compare surfaces, a larger RMS roughness value of one surface indicates that the surface exhibits larger deviations from its measured mean surface height relative to the other. Unless specified otherwise, roughness values provided herein correspond to RMS roughness values.

[0175] Materials, deposition processes, and etching processes for forming the gate electrode 106 are selected to provide a top surface 108 having a roughness less than 2 nm. In particular embodiments, the roughness may be less than 1 nm or less than 0.5 nm. Such low roughness values of the top surface 108 can promote subsequently deposited layers having similarly low roughness values.

[0176] With reference again to Figure 2.1, after deposition of the layer of conductive material 2104, one or more planarization processes may be performed on the layer of conductive material 2104. For example, a chemical mechanical planarization (CMP) process may be performed on the layer of conductive material 2104. The CMP process utilizes chemical and mechanical polishing processes to reduce the roughness of the top surface of thelayer of conductive material 2104. This can result in the gate electrode 2106 having atop surface 2108 with low roughness.

[0177] With reference again to Figure 2.2, after patterning the conductive material 2104 to form the gate electrode 2106, one or more planarization processes may be performed on the gate electrode 2106. For example, a CMP process may be performed on the gate electrode 2106 to further reduce the roughness of the top surface 2108 of the gate electrode 2106.

[0178] The gate electrode 2106 can be formed in ways other than those described above. For example, the gate electrode 2106 can be formed by depositing the gate electrode metal in a trench, gap or via formed in a dielectric layer formed on the substrate 2102. This can be followed by a planarization process, such as a CMP process to remove excess metal and to reduce the roughness of the top surface 2108 of the gate electrode 2106.

[0179] Figure 2.9 is a cross-sectional view of the thin-film electronic device 2100, according to one embodiment.

[0180] As shown in Figure 2.9, a gate insulator 2112 is on the top surface 2108 of the gate electrode 2106 and on portions of the substrate 2102. The gate insulator 2112 is an electrically insulating material with certain properties (e.g., thickness) selected to enable the gate insulator 2112 to electrically isolate the gate electrode 2106 from a semiconductor material 2124 on the gate insulator 2112, which may be at a semiconductor channel region.

[0181] The gate insulator 2112 can have a thickness between 5 nm and 75 nm. The inventors have found that such a relatively low thickness can result in a top surface 2114 of the gate insulator 2112 having a relatively low roughness. In particular, when the gate insulator 2112 has a thickness less than 75 nm and is formed on a gate electrode 2106 having a top surface 2108 with a roughness less than 1 nm, the gate insulator 2112 has a top surface 2114 with a low roughness. In one example, the roughness of the top surface 2114 of the gate insulator 2112 is less than 1 nm. The low surface roughness of the top surface 2114 of the gate insulator 2112 can promote low surface roughness in a subsequently deposited semiconductor layer and a higher charge carrier mobility.

[0182] The gate insulator 2112 can include AI2O3 or other high permittivity insulating materials of varied composition. The thickness and deposition process utilized for forming the gate insulator 2112 can be selected based on the material and thickness of the gate electrode 2106. The gate insulator 2112 can be deposited by aPVD process, a CVD process, such as PECVD, or an ALD process. In an example in which the gate electrode 2106 includes TiAh with a thickness between 60 nm and 200 nm and a surface roughness less than 1 nm, the AI2O3 gateinsulator 2112 can be deposited with a PVD process. The thickness of the AI2O3 gate insulator 2112 can be vary between 5 nm and 200 nm. In an example in which the gate electrode 2106 includes Ti with a thickness between 190 and 210 nm and the surface roughness less than 2 nm, the AI2O3 gate insulator 2112 can be deposited with a PVD process and have a thickness of about 15 nm. In an example in which the gate electrode 2106 includes molybdenum with a thickness between 190 nm and 210 nm and a surface roughness less than 2 nm, the AI2O3 gate insulator 2112 can be deposited with an ALD process and can have a thickness between 1 nm and 15 nm. In an example in which the gate electrode 2106 includes a conductive material, which in some situations may be a metal, with a thickness between 20 nm and 30 nm in the surface roughness less than 2 nm, the AI2O3 gate insulator 2112 can be deposited with an ALD process and have a thickness between 3 nm and 8 nm. In an example in which the gate electrode includes titanium with a thickness between 190 nm and 200 nm in the surface roughness less than 4 nm, the gate AI2O3 insulator 2112 can be deposited with a PVD process and can have a thickness between 5 nm and 15 nm.

[0183] The gate insulator 2112 can include materials other than AI2O3. For example, the gate insulator 2112 can include one or more of silicon oxide, silicon nitride, a metal oxide, hafnium oxide, etc. In embodiments, the gate insulator 2112 insulator is a metal oxide or metal nitride that can be formed in a very thin layer. In some embodiments, portions of the gate insulator layer 2112 between the source and drain electrodes and the gate electrode 2106 may be thinner than other portions.

[0184] A source electrode 2120 and a drain electrode 2122 are in contact with the gate insulator 2112. The source electrode 2120 and the drain electrode 2122 can have a thickness between 50 nm and 200 nm. The source electrode 2120 and the drain electrode 2122 include a metal, and the metal can include one or more of copper, aluminum, titanium, tungsten, or other suitable metals or be deposited as a multi-layer stack to promote adhesion or facilitate an improved electronic interface with the semiconductor layer. The source electrode 2120 and the drain electrode 2122 may have been formed utilizing PVD, chemical vapor deposition (CVD), ALD, or other suitable deposition processes.

[0185] A semiconductor material 2124 is on the source electrode 2120, the drain electrode 2122, and the exposed portion of the gate insulator 2112 that is not covered by the source electrode 2120 and the drain electrode 2122. The semiconductor material 2124 can have a thickness between 1 nm and 100 nm. The semiconductor material 2124 may have been formedwith a deposition process including PVD, plasma enhanced CVD (PECVD), and PECVD with Excimer laser annealing (ELA).

[0186] The semiconductor material 2124 can include one or more of IGZO (compositions of In, Ga, Zn, and O), low temperature poly crystalline silicon (LTPS), amorphous silicon, or other suitable semiconducting materials. In an example in which the gate insulator 2112 includes AI2O3 between 10 nm and 20 nm in thickness, the semiconductor material 2124 can include IGZO between 30 nm and 50 nm in thickness, formed with a PVD process. In an example in which the gate insulator 2112 includes AI2O3 between 5 nm and 15 nm in thickness and the gate electrode 2106 includes molybdenum, the semiconductor material 2124 can include LTPS between 40 nm and 60 nm in thickness, formed with a PECVD process followed by an ELA process. In an example in which the gate insulator 2112 includes AI2O3 between 3 nm and 8 nm in thickness, the semiconductor material 2124 can include amorphous silicon between 40 nm and 60 nm in thickness, formed with a PECVD process. In an example in which the gate insulator 2112 includes AI2O3 between 5 nm and 15 nm in thickness and the gate electrode 2106 includes titanium, the semiconductor material 2124 can include IGZO between 15 nm and 25 nm in thickness, formed with a PVD process followed by an ELA process. These embodiments can result in a semiconductor material 2124 having a bottom surface 2126 and a top surface 2128 with relatively low roughness. Accordingly, the semiconductor material 2124 can have a low number of trap states at the bottom and top surfaces 2126, 2128, and correspondingly high conductivity.

[0187] In some embodiments, IGZO may correspond to amorphous In-Ga-Zn-0 compositions, also referred to as a-IGZO. In other embodiments, IGZO may include crystalline materials. Crystalline IGZO materials may include, for example, InGaZnO4, InGaOsZnO, or In2Ga2ZnO?. IGZO may also include InwGaxZnyOz in which w, x, y, and z are numbers representing mole fraction and individually represent the proportion of the material made up by the corresponding element. The values of w, x, y, and z can vary based on the deposition process. In one example corresponding to InGaZnO4, w = x = y = 0.143, and z = 0.571. Other values of w, x, y, and z can be utilized without departing from the scope of the present disclosure.

[0188] The semiconductor material 2124 terminates on the source electrode 2120 and the drain electrode 2122. The semiconductor material 2124 terminates on the source electrode 2120 and the drain electrode 2122 as the semiconductor material 2124 may have been previouslypatterned and etched with photolithographic masking process followed by a wet or a dry etch to form the semiconductor material as shown in Figure 2.9.

[0189] A passivation layer 2131 is on the semiconductor material 2124 and portions of the source electrode 2120 and drain electrode 2122 not covered by the semiconductor material 2124. The passivation layer 2131 can include a dielectric material with a thickness between 50 nm and 500 nm. The passivation layer 2131 can include one or more of silicon dioxide, silicon nitride, or other dielectric materials.

[0190] As shown in Figure 2.9, the thin-film transistor 2132 is fully formed and complete. The thin-film transistor 2132 includes the gate electrode 2106, the gate insulator 2112, the source electrode 2120, the drain electrode 2122, and the semiconductor material 2124. The semiconductor material 2124 includes a channel region 2130. The channel region 2130 corresponds to the portion of the semiconductor material 2124 between the source and drain electrodes 2120, 2122 and the above the gate electrode 2106. The gate insulator 2112 separates the channel region 2130 of the semiconductor material 2124 from the gate electrode 2106.

[0191] The thin-film transistor 2132 can operate by selectively applying voltages to the gate electrode 2106, the source electrode 2120, and the drain electrode 2122. In one example, thin-film transistor 2132 is turned on by applying a gate to source voltage and a drain to source voltage of about 4V. The thin-film transistor 2132 can be turned off by applying a gate to source voltage of 0 V. Other voltages can be utilized without departing from the scope of the present disclosure.

[0192] Figure 2.10 is a top view of the thin-film transistor 2132 of Figure 2.9. The gate insulator 2112 and the passivation layer 2131 are hidden for visibility of the semiconductor layer 2124, the source electrode 2120, the drain electrode 2122, and the gate electrode 2106. Figure 2.10 illustrates that the semiconductor material 2124 is positioned over portions of the gate electrode 2106, the source electrode 2120, and the drain electrode 2122. The various components of the thin-film transistor 2132 can have other shapes and arrangements without departing from the scope of the present disclosure.

[0193] While the description of Figures 2.1-2.9 has primarily described a thin film transistor 2132 including a gate electrode 2106 having a top surface 2108 with low roughness, principles of the present disclosure can extend to other structures formed in the thin-film electronic device 2100. For example, a layer of conductive material can be patterned to form various types of metal structures on the substrate 2102 in addition to the gateelectrode 2106. These other metal structures will also have top surfaces with the low roughness of the top surface 2108. Accordingly, these other metal structures, and the structures formed over them, may also benefit from the low roughness top surface. The other metal structures can include metal lines, contacts, plugs, or types of metal structures that may be formed with the metal of the gate electrode 2106.

[0194] Figure 2.11 is a cross-sectional view of a thin-film electronic device 2200 including a thin-film transistor 2232, according to one embodiment. The transistor 2232 includes a gate electrode 2206 positioned on a substrate 2202. The gate insulator 2212 is positioned on the gate electrode 2206 and the substrate 2202. A semiconductor material 2224 is positioned on the gate insulator 2212. A source electrode 2220 and the drain electrode 2222 are positioned on the semiconductor material 2224. A passivation layer 2231 is positioned on the source electrode 2220, the drain electrode 2222, and the semiconductor material 2224. Accordingly, the thin-film transistor 2232 of Figure 2.11 is substantially similar to the thin-film transistor 2132 of Figure 2.9, except that the source and drain electrodes 2220, 2222 are formed after formation of the semiconductor material 2224. The various components of the thin-film transistor 2232 can be formed with the same processes, dimensions, and materials as described previously in relation to Figures 2.1-2.9.

[0195] The gate electrode 2206 has surface roughness characteristics as described in relation to the gate electrode 2106 of Figure 2.1-2.9. This results in the semiconductor material 2224 having bottom surface 2226 and top surface 2228 with low roughness like the semiconductor material 2124 of Figure 2.9. Accordingly, although the order of deposition of some of the components of the thin- film transistor 2232 is different than the order of deposition of some of the components of the thin- film transistor 2132, the thin-film transistor 2232 has the same beneficial low surface roughness characteristics as the thin-film transistor 2132.

[0196] Figure 2.12 is a top view of the thin-film transistor 2232 of Figure 2.11. The top view of the thin-film transistor 2232 illustrates that the source electrode 2220 and the drain electrode 2222 are positioned on the semiconductor material 2224. The semiconductor material 2224 is positioned over the gate electrode 2206. The passivation layer 2231 is hidden for visibility of the source electrode 2220, the drain electrode 2222, the semiconductor material 2224, and the gate electrode 2206.

[0197] Figure 2.13 is a cross-sectional view of a thin-film electronic device 2300 including a thin-film transistor 2332, according to one embodiment. The thin-film transistor2332 includes a substrate 2302, a gate electrode 2306 positioned on the substrate 2302, a gate insulator 2312 positioned on the gate electrode 2306 and substrate 2302, source and drain electrodes 2320, 2322 positioned on the gate insulator 2312, and a semiconductor material 2324 positioned on the source electrode 2320, the drain electrode 2322, and the gate insulator 2312. These components of the thin-film transistor 2332 can be formed with the same processes, materials, and thicknesses described for the thin-film transistor 2132 in relation to Figures 2.1-2.9. The thin-film transistor 2332 is substantially similar to the thin- film transistor 2132 of Figure 2.9, except that a second gate insulator 2333 is positioned on the semiconductor material 2324 and a second gate electrode 2334 is positioned on the second gate insulator 2333. The second gate insulator 2333 can be of the same material and thickness as the gate insulator 2312. The second gate electrode 2334 can have a same material and thickness as the gate electrode 2306. Control of currents in the channel region 2330 can be enhanced by applying the same voltages to the second gate electrode 2334 as are applied to the first gate electrode 2306. Though not shown in Figure 2.13, a passivation layer, similar to the passivation layer 2131, can be deposited on the thin-film transistor 2332. In the example of Figure 2.13, gate electrode 2306 can be considered a first gate electrode.

[0198] The gate electrode 2306 has surface roughness characteristics as described in relation to the gate electrode 2106 of Figure 2.1-2.9. This results in the semiconductor material 2324 having bottom surface 2326 and top surface 2328 with low roughness like the semiconductor material 2124 of Figure 2.9. Accordingly, although the order of deposition of some of the components of the thin- film transistor 2332 is different than the order of deposition of some of the components of the thin- film transistor 2132, the thin-film transistor 2332 has the same beneficial low surface roughness characteristics as the thin-film transistor 2132.

[0199] The thin-film transistor 2332 will include contacts or other electrical connections through the second gate insulator 2333 to the source and drain electrodes 2320, 2322. These contacts are in openings formed in the second gate insulator 2333, which are not shown in Figure 2.13. The contacts may be formed in a same processing step as the second gate electrode 2334 such that they are formed from the same layer, but are electrically isolated from each other.

[0200] Figure 2.14 is atop view of the thin-film transistor 2332 of Figure 2.13. The top view of the thin-film transistor 2332 illustrates that the second gate electrode 2334 ispositioned over the semiconductor material 2324. The semiconductor material 2324 is positioned over the source and drain electrodes 2320, 2322 and the gate electrode 2306.

[0201] Figure 2.15 is a cross-sectional view of a thin-film electronic device 2400 including a thin-film transistor 2432, according to one embodiment. The thin-film transistor 2432 includes a substrate 2402, a gate electrode 2406 positioned on the substrate 2402, a gate insulator 2412 positioned on the gate electrode 2406 and substrate 2402, source and drain electrodes 2420, 2422 positioned on the gate insulator 2412, and a semiconductor material 2424 positioned on the source electrode 2420, the drain electrode 2422, and the gate insulator 2412. These components of the thin-film transistor 2432 can be formed with the same processes, materials, and thicknesses described for the thin-film transistor 2132 in relation to Figures 2.1-2.9. The thin-film transistor 2432 is substantially similar to the thin- film transistor 2132 of Figure 2.9, except that a second gate insulator 2433 is positioned on the semiconductor material 2424 and a second gate electrode 2434 is positioned on the second gate insulator 2433. The second gate insulator 2433 can be of the same material and thickness as the gate insulator 2412. The second gate electrode 2434 can have a same material and thickness as the gate electrode 2406. Control of currents in the channel region 2430 can be enhanced by applying the same voltages to the second gate electrode 2434 as are applied to the first gate electrode 2406. Though not shown in Figure 2.15, a passivation layer, similar to the passivation layer 2131, can be deposited on the thin-film transistor 2432. In the example of Figure 2.15, the gate electrode 2406 can be considered a first gate electrode.

[0202] The gate electrode 2406 has surface roughness characteristics as described in relation to the gate electrode 2106 of Figure 2.1-2.9. This results in the semiconductor material 2424 having bottom surface 2426 and top surface 2428 with low roughness like the semiconductor material 2124 of Figure 2.9. Accordingly, although the order of deposition of some of the components of the thin- film transistor 2432 is different than the order of deposition of some of the components of the thin- film transistor 2132, the thin-film transistor 2432 has the same beneficial low surface roughness characteristics as the thin-film transistor 2132.

[0203] Figure 2.16 is atop view of the thin-film transistor 2432 of Figure 2.15. The top view of the thin-film transistor 2432 illustrates that the second gate electrode 2434 is positioned over the semiconductor material 2424. The source and drain electrodes 2420,2422 are positioned over the semiconductor material 2424. The semiconductor material 2424 is positioned over the gate electrode 2406.

[0204] In view of the above embodiments of the thin-film electronic devices 2100, 2200, 2300, 2400 as described with respect to Figures 2.1-2.9, 2.11, 2.12, 2.13, 2.14, 2.15, and 2.16, when powered by an external voltage or current, charge carriers travel through the respective semiconductor materials 2124, 2224, 2324, 2424. The charge carriers travel through the semiconductor materials 2124, 2224, 2324, 2424 directed parallel (applies to holes) or antiparallel (applies to electrons) to the electric field lines established within the semiconductor. As these charge carriers move within the semiconductor materials 2124, 2224, 2234, 2424 based on the orientation of the thin- film devices 2100, 2200, 2300, 2400 as shown in Figures 2.1-2.9, 2.11, 2.12, 2.13, 2.14, 2.15, and 2.16, the charge carriers may be exposed to various types of perturbations that cause at least some of the charge carriers to scatter, which as set forth earlier herein generally referred to as "scattering." These perturbations may include interactions with other charge carriers, interactions with chemical impurities being electrically charged or neutral, interactions with lattice vibrations (phonons), interactions with a rough surface located at a gate insulator and semiconductor interface (i.e., surface roughness scattering), or at a gate electrode and gate insulator interface (i.e., remote surface roughness scattering).

[0205] Charge carrier scattering caused by the surface roughness at the gate insulator and semiconductor interface (e.g., where the respective gate insulators 2112, 2212, 2312, 2412 meet the respective semiconductor materials 2124, 2224, 2324, 2424) may be referred to as surface roughness scattering. This type of scattering may also occur at an interface between the second gate insulator 2333 and the semiconductor material 2334 as shown in Figure 2.13 or at an interface between the second gate insulator 2433 and the semiconductor material 2424 as shown in Figure 2.15.

[0206] Figure 2.17 is an illustration of a cross-sectional view of the gate electrode, gate insulator and semiconductor layers of a TFT depicting various types of scattering, including conventional phonon and impurity scattering as well as two types of surface roughness scattering most relevant to the present invention: (1) remote surface roughness scattering due to a rough surface at the interface between the gate electrode and gate insulator; and (2) surface roughness scattering due to a rough surface at the interface between the gate insulator and semiconductor. The interface between the gate electrode and gate insulator and the interface between the gate insulator and semiconductor are indicated.It will be readily appreciated that this discussion of surface roughness scattering may apply to the various embodiments of the thin-film electronic devices 2100, 2200, 2300, 2400 as discussed earlier herein.

[0207] Figure 2.18 is an illustration of a cross-section view showing the gate electrode, gate insulator and semiconductor layers of a TFT illustrating the concept of surface roughness scattering. As shown in Figure 2.18, surface roughness at an interface between a gate insulator and a semiconductor may result in peaks and valleys being present at the bottom semiconductor interface which is also the gate insulator surface. As charge carriers move within the semiconductor, as shown in Figure 2.18, scattering of charge carriers near the interface between the gate insulator and semiconductor occurs locally, due to surface roughness at that interface. This causes a reduction in charge carrier mobility.

[0208] Figure 2.19 is an illustration of a cross-section view showing the gate electrode, gate insulator and semiconductor layers of a TFT illustrating the concept of remote surface roughness scattering. A dotted line represents an average gate insulator thickness (i.e., thickness between the surface of the gate electrode at the gate interface to an imaginary surface of the gate insulator if it were perfectly flat, which is determined by taking an average of the thickness along various points of the surface of the gate insulator at the semiconductor interface). As will be readily appreciated, as the charge carriers as shown in Figure 2.19 are drawn closer to the surface of the gate insulator along the z-direction, due to the placement of charge on the gate electrode (QG), there is an increased likelihood of these electrons scattering due to the roughness of the gate electrode, which causes spatial disturbances or fluctuations in the transverse electric field directed from the gate electrode towards the semiconductor.

[0209] The surface roughness and topography at the interface between the gate insulator and semiconductor is strongly affected by the surface roughness or topography of gate electrode at the interface between the gate and gate insulator. This was found and determined by data collection by the inventors as will become readily apparent in view of the discussion that follows herein with respect to Figures 2.20-2.22. Furthermore, it was found by the inventors that the RMS surface roughness of the surface of the gate electrode at the interface between the gate and gate insulator is transferred to the interface between the gate insulator and the semiconductor to within 10%, regardless of the thickness of the gate insulator, evaluated herein up to 75 nm AI2O3.

[0210] Charge carrier scattering caused by spatial distortions, fluctuations, or nonuniformities of the transverse electric field directed from the gate electrode towards the semiconductor 2124, 2224, 2324, 2424 due to surface roughness of the gate may be referred to as remote surface roughness scattering. The spatial distortions, fluctuations, and nonuniformities of the electric field are caused by the surface roughness or topography at respective top surfaces 2108, 2208, 2308, 2408 of the respective gate electrodes 2106, 2206, 2306, 2406. As distance between the respective top surfaces 2108, 2208, 2308, 2408 from the respective semiconductor materials 2124, 2224, 2324, 2424 varies as charge carriers moves along the respective top surfaces 2106, 2206, 2306, 2406, the magnitude of the electric field seen by charge carriers changes, causing scattering. Remote surface roughness scattering may occur similarly with respect to the second gate electrode 2434 and the semiconductor material 2424 as shown in Figure 2.15.

[0211] In view of above discussion, the inventors have determined that the surface roughness or topography of the gate electrode at the gate interface is directly proportional to an amount of spatial distortion, fluctuation, or non-uniformity of the transverse electric field that results in the remote surface roughness scattering and surface roughness scattering effects as discussed herein. Furthermore, since remote surface roughness relates the position of the charge on the gate electrode to the induced charge in the semiconductor, a high surface roughness at the surface of the gate electrode at the interface between the gate electrode and gate insulator will have a negative impact on performance regardless of a bottom gate configuration or a top gate configuration of a thin-film transistor. In other words, the position of the gate does not appear to matter as much as the smoothness (e.g., low surface roughness) of the surface of the gate electrode at the gate interface.

[0212] In view of the above discussion, preventing or mitigating the effects of surface roughness scattering and remote surface roughness scattering would improve fieldeffect mobility. The inventors have found that by utilizing an amorphous metal for the respective gate electrode 2106, 2206, 2306, 2406 in the various embodiments as set forth above generates a smooth surface roughness or topography of the respective top surfaces 2108, 2208, 2308, 2408 (e.g., the RMS of the surface roughness or topography of the respective top surfaces 2108, 2208, 2308, 2408 is low meaning that the top surfaces 2108, 2208, 2308, 2408 are smooth as compared to when utilizing other types of poly crystalline metals are utilized). Reducing the surface roughness of the respective top surfaces 2108, 2208, 2308, 2408 in turn reduces the surface roughness or topography of the surface of therespective gate insulator 2112, 2212, 2312, 2412 at the respective gate insulator and semiconductor interface since the surface roughness or topography of the respective gate insulators 2112, 2212, 2312, 2412 mimics that of the surface roughness or topography of the respective gate electrode 2106, 2206, 2306, 2406, which will become more readily apparent in view of the following discussion herein with respect to Figures 2.20-2.22. The surface roughness of the gate insulators 2112, 2212, 2312, 2412 mimics that of the surface roughness of the gate electrode 2106, 2206, 2306, 2406 as the gate insulator 2112, 2212, 2312, 2412 is formed on the gate electrode 2106, 2206, 2306, 2406. This reduction in the surface roughness or topography of the top surfaces 2108, 2208, 2308, 2408 and this reduction in the surface roughness or topography at the respective surfaces of the respective gate insulators 2112, 2212, 2312, 2412 at the respective gate insulator and semiconductor material interfaces mitigates or reduces the surface roughness scattering and the remote surface roughness scattering effects as discussed earlier herein. This reduction in the effects of the surface roughness scattering and the remote surface roughness scattering mitigates or reduces scattering of charge carriers passing through the semiconductor materials 2124, 2224, 2324, 2424.

[0213] Figure 2.20 is a plurality of images of various respective surfaces of gate electrodes (e.g., top most row) including 200 nm of TiAh, Mo AlNdo.02 and Ti as well as a plurality of images of various respective surfaces of an AI2O3 gate insulator sputter deposited upon the gate electrodes with different thickness (e.g., 5 lower rows) ranging from 5 nm to 75 nm. These images are atomic force microscopy (AFM) images and illustrate the surface roughness or topography of these various surfaces as modified by gate electrode and / or gate insulator thickness.

[0214] Figure 2.20 is directed to atomic force microscopy images of metallic gate electrodes (a-TiAh, Mo, AlNdo.02 and Ti) with a thickness of 200 nm, and AI2O3 gate insulator surfaces for different gate insulator thicknesses ranging from 5 nm to 75 nm formed on these various metallic gate electrodes. The surface topography of the gate insulator strongly resembles that of the underlying gate electrode and is not particularly influenced by the thickness of the gate insulator.

[0215] In view of the above discussion, the top-most row of Figure 2.20 is directed to respective surfaces of gate electrodes made of various gate metals, immediately following deposition, and is characteristic of the choice of gate electrode. For example, the image in the upper left-hand comer of Figure 2.20 is directed to the surface roughness or topographyof a gate electrode made of TiAh, which is a smooth amorphous metal. The uppermost center-left image of Figure 2.20 is directed to the surface roughness or topography of a gate electrode made of Mo, which is a poly crystalline metal. The uppermost center-right image of Figure 2.20 is directed to the surface roughness or topography of a gate electrode made of AlNdo.02, which is a poly crystalline metal. The image at the upper-right hand comer of Figure 2.20 is directed to the surface roughness or topography of a gate electrode made of Ti, which is a poly crystalline metal. As shown in these images in the top-most row, the TiAh, which is an amorphous metal, is much smoother (e.g., lower surface roughness) as compared to the other materials, which are polycrystalline metals. These various gate electrodes made of various metal materials have a thickness of 200 nanometers (nm).

[0216] The lower five most rows are directed to various gate insulators (e.g., some types of gate oxides or other types of materials suitable for a gate insulator) formed on the various gate electrodes of different materials. For example, the left-most column and the five lower rows are directed to the various gate insulators (made of AI2O3) formed on the surface of TiAh, the left-center column and the five lower rows are directed to the various gate insulators (made of AI2O3) formed on the surface of Mo, the right-center column and the five lower rows are directed to various gate insulators (made of AI2O3) formed on the surface of AlNdo.02, and the right most column and the five lower rows are directed to various gate insulators (made of AI2O3) formed on the surface of Ti. The thicknesses of the gate insulators increases as you move downward along the lower five rows (e.g., 5 nm, 10 nm, 15 nm, 20 nm, and 75 nm).

[0217] As shown in these images in Figure 2.20, the respective surfaces of the gate insulators have a surface roughness or topography very similar to or nearly identical to a surface roughness or topography of the gate electrode on which they are formed regardless of the thickness of the gate insulator. In other words, regardless of how thick the gate insulator is formed on the surface of the gate electrode, the surface roughness of the gate insulator and the surface roughness of the gate electrode will be very similar or mimic each other. Furthermore, as shown in Figure 2.20, since the TiAh has a surface with a surface roughness that is smoother as compared to the surfaces of Mo, AlNdo.02, and Ti, the gate insulators formed on the TiAh, which is an amorphous metal, have a smoother surface as compared to those gate insulators formed on the Mo, AlNdo.02. and Ti, which are polycrystalline metals. In view of this discussion, utilizing the amorphous metal of TiAh means that the surface of the gate electrode and the surface of the gate insulator formed onthe surface of the gate electrode are smoother relative to respective surfaces of gate insulators formed on the gate electrodes made of Mo, AlNdo.02, and Ti. In view of this discussion, utilizing the TiAh, which is an amorphous metal, to form the gate electrode further mitigates or reduces the effects of surface roughness scattering and remote surface roughness scattering as compared to when the gate electrodes are made of Mo, AlNdo.02, and Ti, which are poly crystalline metals.

[0218] Figure 2.21 is a graph illustrating data collected with respect to the surfaces of the materials contained within the various images as shown in Figure 2.20. The points in the graph are representative of root mean squares (RMS) measurements of surface roughness of the AI2O3 gate insulators when formed with different thicknesses (e.g., 0 nm, 5 nm, 10 nm, 15 nm, 20 nm, and 75 nm) on different gate electrodes (TiAh, Mo, AlNdo.02, and Ti). As may be readily appreciated the measurements of the surface roughness when the gate insulator has a thickness of 0 nm is actually the surface roughness or topography measurement for the surface of the gate electrode itself. As shown in Figure 2.21, the RMS of the surfaces of the various gate insulators formed on the various gate electrodes made of the various gate metals essentially remains the same regardless of the thickness of the gate insulator. Furthermore, the RMS of the surfaces of the various gate insulators is essentially the same of the RMS of the surfaces of the gate electrodes on which they are formed. Additionally, the RMS surfaces of the gate insulators are the smallest when formed on the TiAh, which is an amorphous metal, as compared to when formed on the Mo, AlNdo.02, and Ti, which are polycrystalline metals.

[0219] Figure 2.22 is a graph illustrating the data collected and depicted in the graphs as shown in Figures 2.20 and Figure 2.21 in another format (versus gate insulator thickness). The circles represent averages of the data points collected with respect to the various thickness of the gate insulator formed on the gate electrode made of various metals. The dotted lines represent a best-fit linear regression for the relationship between RMS roughness and gate insulator thickness and is representative of the variation in surface roughness of the gate insulators as formed with varying thickness on the various gate electrodes made of various gate metals. There is no particular decreasing or increasing trend in RMS roughness as the gate insulator thickness is increased from 5 nm to 75 nm. As shown in Figure 7C, one can readily appreciate that the gate insulators formed on the smoother surface of the TiAh, which is an amorphous metal, are smoother and have a lower RMS surface roughness aswhen compared to the gate insulators formed on the gate electrodes made of Mo, AlNdo.02, and Ti, which are polycrystalline metals.

[0220] Figure 2.22 is directed to RMS roughness of the gate insulator as a function of gate insulator thickness, for different gate metals. Evidently, based on the linear regression trendline as shown in Figure 2.22, the surface roughness and topography of the gate insulator is strongly related to the surface roughness and topography of the underlying gate electrode regardless of the thickness of the gate insulator formed on the gate electrode.

[0221] Figure 2.24 is a graph showing the measured field-effect mobility of various IGZO TFTs having a 75 nm AI2O3 gate insulator but different gate electrodes (a-TiAlx, such as a-TiAh, Mo, Ti and AlNdo.02). As shown in Figure 2.24, when the gate electrode is made of the TiAh, which is an amorphous metal (TiAh, such as a-TiAh), the field-effect mobility is larger than field-effect mobility when the gate electrode is made of Mo, AlNdo.02, or Ti, which are polycrystalline metals. In view of this discussion, forming the gate electrode from TiAh, which is an amorphous metal, instead of Mo, AlNdo.02, and Ti, which are poly crystalline metals, more readily mitigates or reduces the effects of both surface roughness scattering and remote surface roughness scattering as the surfaces of the gate insulators formed on the gate electrode made of TiAh are smoother as compared to gate insulators formed on surfaces of the Mo, AlNdo.02, and Ti.

[0222] Figure 2.23 is directed to Field-effect mobility versus RMS roughness for IGZO TFTs with different gate electrodes at room temperature (300 K). Ultimately, the surface roughness of the gate insulator results from the underlying gate electrode, causing a reduction in field-effect mobility.

[0223] Furthermore, as one reduces the thickness of the TiAh gate electrode the mobility of the electrons essentially remains the same. In view of this, the thin-film transistors can be made even thinner by reducing the thickness of the TiAh while at the same time mitigating or reducing the effects of surface roughness scattering and remote surface roughness scattering.

[0224] In view of the above discussion with respect to Figures 2.20-2.22 and 2.23, we begin by discussing the surface characteristics of the gate electrode and gate insulator measured using atomic force microscopy (AFM). The surface of the AI2O3 gate insulator is effectively identical to the underlying gate electrode. AFM images (e.g., see, Figure 2.20) of the surfaces of each of the four metallic gates (a-TiAh, Mo, AlNd0.02 and Ti) are shown in the first row of Figure 2.20. Also shown in the remaining rows of Figure 2.20 are thesurfaces of the A12O3 gate insulator (with thickness ranging from 5 to 75 nm) deposited on top of each gate electrode. We note that the film thickness of each gate metal is the same (200 nm), and all metals are polycrystalline except for a-TiAh which is amorphous.Evidently, the surface topography of the AI2O3 gate insulator strongly resembles that of the underlying gate electrode and is not particularly influenced by the thickness of the gate insulator.

[0225] The RMS roughness of the gate insulator is weakly correlated to the thickness of the gate insulator, but strongly correlated to the gate electrode. Figure 2.22 shows the RMS roughness of the gate insulator, measured over the entire scan area from the data in Figure 2.20, as a function of gate insulator thickness for each of the gate electrodes. The measured RMS roughness ranges from approximately 0.35 nm (a-TiA13) to 4.5 nm (Ti) over the range of gate insulator thickness (5 nm to 75 nm).

[0226] The transfer of the gate electrode's surface structure onto the surface of the gate insulator can be explained based on a low surface mobility of AI2O3 clusters, due to the large melting point of AI2O3 and the low substrate temperature during deposition (300 K).

[0227] In view of the above discussion with respect to the graphs as shown in Figures 2.21 and 2.22, it will be readily appreciated that the effects of the surface roughness scattering and the remote surface roughness scattering may be mitigated or reduced when utilizing TiAh, which is an amorphous metal, for the gate electrode as compared towhen utilizing Mo, AlNdo.02, or Ti, which are poly crystalline metals.

[0228] The increase in roughness of the gate insulator can degrade field-effect mobility through increased charge carrier scattering (e.g., surface roughness scattering and remote surface roughness scattering). The field-effect mobility is shown as function of RMS roughness in Figure 2.23, for IGZO bottom-gate, top-contact TFTs having an equivalent gate insulator thickness of 75 nm. As shown, the field-effect mobility reduces with increasing surface roughness. This result is consistent with the charge carrier mobility being significantly influenced by surface scattering (e.g., surface roughness scattering and remote surface roughness scattering).

[0229] To investigate this further, the field-effect mobility includes using the relaxation time approximation (RTA) for calculating the charge carrier mobility, in which we take into consideration charge carrier scattering by ionized impurities, acoustic phonons, optical phonons (polar and nonpolar), surface roughness and remote surface roughness scattering. Other effects taken into account include a single-exponential band tail oflocalized acceptor states within the semiconductor and contact resistance associated with the source and drain electrodes in accordance with established TFT device models.

[0230] In view of the above discussion herein, ideally, charge carriers in a TFT would exhibit a mobility limited only by atomic structure of the semiconductor (i.e., phonons), assuming a TFT could be realized with pure semiconductor and insulating layers (no charged or neutral impurities) and perfectly flat surfaces (zero RMS roughness). In such a case, TFTs would operate at their theoretically defined maximum field-effect mobility, limited only by the extent of phonon scattering present at the operating temperature of the device.

[0231] Ideal conditions require perfectly flat surfaces (zero RMS roughness) which are not obtainable in practice, requiring a consideration of scattering due to surface roughness both local and nonlocal (i.e., remote) to charge carriers. These are represented by surface roughness scattering and remote surface roughness scattering. Surface roughness scattering is a local scattering mechanism due to variation in the electrostatic potential at the same location of the charge carrier. It depends directly on the surface roughness of the interface between the gate insulator and semiconductor and is exacerbated at higher transverse electric field (directed from gate electrode to semiconductor). By contrast, remote surface roughness scattering is a scattering mechanism in which the magnitude of the transverse electric field (directed from gate electrode to semiconductor) felt by a charge carrier is perturbed due to the spatial variation in charge placed on the gate electrode under normal TFT operation. Because the electric field is additive, each charge positioned at every point along the surface of the gate electrode contributes towards scattering of charge carriers, albeit at a distance. Accordingly, the scattering process is weakened with increasing gate insulator thickness due to spatial interference of the electric field according to the principle of superposition. Consequently, remote surface roughness scattering, like remote charge scattering in traditional CMOS transistors, becomes increasingly important as the gate insulator thickness or semiconductor thickness is reduced and is therefore an important consideration for the optimization of field-effect mobility in TFTs.

[0232] The effects of surface roughness on charge carrier transport are not well understood in IGZO TFTs. In general, remote surface roughness scattering is rarely considered in the analysis of charge carrier transport and field-effect mobility in TFTs, most likely because remote surface roughness scattering is an effect that is more pronounced at smaller gate insulator thickness, and the electrical performance of gate insulators in massproduction (e.g., silicon dioxide and silicon nitride) is not sufficient to facilitate a reduction in thickness without a compromise in some aspect of TFT performance (e.g., device uniformity, bias stability, gate leakage).

[0233] Figure 2.23 is a graph comparing a measured field-effect mobility to a calculated field-effect mobility for different theoretical models. In this case, the measured data corresponds to an IGZO TFT having a 75 nm AI2O3 gate insulator and amorphous TiA13 gate electrode with surface roughness less than 0.5 nm. The square-law model assumes a constant carrier mobility throughout the semiconductor above the flatband voltage. The constant value indicated by the black dashed line in Figure 2.23 is 65 cm2 / Vs, which corresponds to the maximum field-effect mobility measured over the observable voltage range. Also shown is the industry-standard AIMSPICE model commonly used in the electrical analysis and design of TFTs. The relaxation time approximation is used to estimate the charge carrier mobility, influenced by various scattering mechanisms previously discussed. The excellent agreement to the measured data as well as the congruency with the industry-standard AIMSPICE model establishes the validity of the theoretical approach used herein. Moreover, the AIMSPICE model does not consider surface roughness or remote surface roughness scattering, which contributes to the reduction in field-effect mobility with increasing gate-source voltage (VGS). For typical IGZO TFT parameters used in AIMSPICE simulations, a larger contact resistance and charge carrier mobility would be apparent from a best-fit comparison to experimental data — leading to an overestimation of both parameters. Thus, the theoretical model used herein provides a more accurate description of the various physical effects that determine field-effect mobility of IGZO TFTs.

[0234] Having established the validity in the theoretical model used herein, the model can be used to provide practical predictions that illustrate the impact of surface roughness scattering for a given choice of gate insulator material, gate electrode or thickness of the gate insulator.

[0235] An amount of impact an amorphous gate metal has on field-effect mobility may be seen as shown in a graph as shown in Figure 2.24 of the present disclosure. Figure 2.24 shows the calculated field-effect mobility evaluated as a function of gate insulator thickness varied from 5 nm to 100 nm for a bottom-gate, top-contact IGZO TFT. A comparison is made for two different gate insulators (AI2O3 and SiO2) as well as for twodifferent gate electrodes (amorphous TiAh and crystalline Ti) based on the RMS roughness obtained from measured surface profiles.

[0236] From Figure 2.24, the simulation results are clear: the use of amorphous metal gate electrodes in IGZO TFTs significantly increases field-effect mobility, regardless of the choice of gate insulator and for all gate insulator thicknesses. Additionally, the use of higher permittivity gate insulators (i.e., high-k dielectrics) also increases field-effect mobility regardless of the choice of gate electrode. The combined use of amorphous metal gate electrodes and high permittivity gate insulators results in the highest field-effect mobility. The benefit of the former is related to a reduction in surface roughness scattering. The benefit of the latter is related to the screening of long-range potentials, causing a reduction in the efficacy of remote scattering mechanisms (e.g., remote surface roughness scattering or remote charge scattering) that influence charge carrier transport. Screening is much more effective in gate insulators having higher permittivity, which explains the higher field-effect mobility and increased TFT performance.

[0237] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0238] These and other changes can be made to the embodiments in light of the abovedetailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

CLAIMS1. A method, comprising: generating a first electric field strength at a first point at a first interface between a gate insulator and a semiconductor layer of a thin film transistor having an amorphous metal gate; generating a second electric field strength at a second point at the first interface; minimizing the difference between the first electric field strength and the second electric field strength by: forming a first surface roughness value at a first surface of the amorphous metal gate; forming a second surface roughness value at a second surface of the gate insulator, the first and second surface roughness values being less than 10% different from each other.

2. A method, comprising: forming a conductive layer of an amorphous metal with a first surface roughness; forming an insulator layer on the first surface defining a first interface between the conductive layer and the insulator layer, forming the insulator layer includes defining a second surface of the insulator layer spaced apart from the conductive layer and facing away from the conductive layer, the second surface having a second surface roughness substantially equal to the first surface roughness; forming a semiconductor layer on the second surface of the insulator layer defining a second interface between the insulator layer and the semiconductor layer; and managing a flow of electrons through the semiconductor layer in a direction directed from a source to a drain along the semiconductor layer by generating an electrical field utilizing the conductive layer, the electrical field extending from the first interface and through the gate insulator layer to the second interface and being substantially uniform between the first interface and the second interface.

3. The method of claim 2, further comprising selecting a surface roughness threshold to be less than or equal to a root mean square (RMS) surface roughness of 5-nanometers.

4. The method of claim 2, wherein selecting the surface roughness threshold to be less than or equal to the root mean square (RMS) surface roughness of 3 -nanometers.

5. The method of claim 2, wherein selecting the surface roughness threshold to be less than or equal to the root mean square (RMS) surface roughness of 2-nanometers.

6. The method of claim 2, wherein selecting the surface roughness threshold to be less than or equal to the root mean square (RMS) surface roughness of 1 -nanometers.

7. A method, comprising: generating a flow of electrons through a semiconductor layer of a thin film transistor having an amorphous metal gate electrode, the flow of electrons being in a direction from a source to a drain along the semiconductor layer by generating an electrical field utilizing the gate electrode, the generating including: generating the electrical field extending from a first interface between the gate electrode and a gate insulator and a second interface between the gate insulator and the semiconductor layer by forming a surface roughness ratio between a first surface of the gate electrode at the first interface and a second surface of the gate insulator layer at the second interface to have be less than 1.1, the generating including generating the electric field to be substantially uniform between the first interface and the second interface.

8. A device, comprising: a substrate; an amorphous metal gate electrode that includes a first surface having a first peak and a first valley; a gate insulator on the first surface of the gate electrode having a second surface opposite to the gate electrode, the second surface having a second peak and a second valley; a semiconductor layer on the second surface of the gate insulator, the semiconductor layer and gate insulator layer configured to: generate a first electric field strength at a first point; generate a second electric field strength at a second point, a variation between the first and second electric field strength being less than 10%.

9. A method, comprising: managing charge carrier scattering at an interface of a gate insulator and a semiconductor layer in a thin film transistor including an amorphous metal electrode by: forming the gate insulator on a first surface of the amorphous metal electrode; forming the semiconductor layer on a second surface of the gate insulator; and minimizing charge carrier scattering at the interface by managing a variation in a surface roughness of the first surface and the second surface.

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