Resettable magnetoresistance fuse

Abstract

A resettable magnetoresistance fuse. The resettable magnetoresistance fuse is electrically connected to a power supply circuit or a device to be protected by means of a main input pad and a main output pad and electrically connected to a reset pulse circuit by means of a reset input pad and a reset output pad. The magnetoresistance fuse comprises one or more magnetic hysteresis magnetoresistance units, a main current conductor, a reset current conductor, a switch unit, and a control logic unit, wherein any one of the magnetic hysteresis magnetoresistance units has two magnetic states, i.e., magnetic state 0 and magnetic state 1; and an input end, an output end, a first intermediate end, and a second intermediate end of the main current conductor are electrically connected to the main input pad, the main output pad, an input end of the switch unit, and an output end of the switch unit, respectively. The magnetoresistance fuse has the advantages of a simple structure, a memory function, a low price, etc.

Description

A resettable magnetoresistive fuse Technical Field

[0001] The present application relates to the technical field of magnetic sensors, and in particular to a resettable magnetoresistive fuse. Background Art

[0002] In new energy technologies or industrial applications, battery stacks are used as power sources. Multiple batteries are usually connected in parallel to provide power to the load. The structure is shown in Figure 1(a). When one of the batteries fails, the failed battery loses its function as a power source and has very low resistance, causing other batteries connected in parallel with the failed battery to short-circuit, thereby causing explosion or fire due to battery overheating, resulting in adverse consequences. Therefore, it is necessary to introduce a fuse 1 (10) into the battery connection circuit. The circuit structure after the introduction of the fuse 1 (10) is shown in Figure 1(b). In this way, the failed battery can be isolated from other normal batteries by disconnecting the fuse.

[0003] In addition, when electronic components in traditional circuits fail, leak, short circuit or are overloaded due to human error, it is necessary to immediately cut off the power connection or the connection of the electronic components, and fuses are also needed.

[0004] After the above two situations occur, if the power circuit or electronic component fault is eliminated, the power supply can be allowed to be reconnected or the electronic components can be reconnected. This process is called reset.

[0005] Currently, fuses in related technologies include the following:

[0006] 1. Metal fuse: When the current is overloaded, the metal fuse melts and the circuit is disconnected. Its disadvantage is that it cannot be reset and needs to be replaced with a new metal fuse after the fault is eliminated.

[0007] 2. Resettable polymer fuse (PTC): When the current is high, the high heat generated by the current causes the polymer to become a high-resistance state. When the current in the circuit returns to normal, the polymer cools and resets to a low-resistance state. The PTC has a reset function, but when the power is normally turned off and then turned on again or when it is turned off due to circuit abnormality, the PTC does not have a memory function. Because it cannot save the record of the previous erroneous operation, it is impossible to distinguish between the two.

[0008] 3. Circuit breaker: A mechanical relay that automatically trips and opens the circuit when the current is too large. It needs to be mechanically reset after the fault is eliminated and does not have a memory function.

[0009] In summary, it is necessary to develop a fuse that has both a reset function and a function of remembering the previous error.

[0010] Summary of the Invention

[0011] In view of this, the present application proposes a resettable magnetoresistive fuse, which has both a reset function and a previous error memory function.

[0012] The embodiment of the present application provides a resettable magnetoresistive fuse, which is electrically connected to a power supply circuit or a device to be protected through a main input pad and a main output pad, and is electrically connected to a reset pulse circuit through a reset input pad and a reset output pad; the magnetoresistive fuse includes: one or more hysteresis magnetoresistive units, a main current conductor, a reset current conductor, a switch unit and a control logic unit, and any hysteresis magnetoresistive unit has two magnetic states: magnetic state 0 and magnetic state 1; wherein the input end, output end, first intermediate end and second intermediate end of the main current conductor are electrically connected to the main input pad, the main output pad, the input end of the switch unit and the output end of the switch unit respectively. end; when the power supply circuit or the device to be protected is overloaded, the main current in the main current conductor configures the magnetic state of the hysteresis magnetoresistive unit to be in an overload state, and the magnetoresistive fuse is disconnected; when the power supply circuit or the device to be protected is repaired, the reset pulse circuit is started, and the reset current in the reset current conductor configures the magnetic state of the hysteresis magnetoresistive unit to be in a reset state, and the magnetoresistive fuse is reset; when the number N of the hysteresis magnetoresistive units is 1, the main current and the reset current are both in a DC non-critical state, the reset state is magnetic state 1 or magnetic state 0, and the corresponding overload state is magnetic state 0 or magnetic state 1; when the number N of the hysteresis magnetoresistive units is greater than 1, the reset state is a mixture of magnetic state 0 and magnetic state 1; the magnetic state is further configured by the control logic unit as an off signal or an on signal of the control end of the switch unit to start the switch unit to be disconnected or connected, thereby realizing the disconnection and resetting of the magnetoresistive fuse.

[0013] In one embodiment, when the hysteresis magnetoresistive unit is in the overload state, the main magnetic field generated by the main current exceeds the coercive force Hc or -Hc of the hysteresis magnetoresistive unit; when the hysteresis magnetoresistive unit is in the reset state, the reset magnetic field generated by the reset current exceeds the coercive force Hc or -Hc of the hysteresis magnetoresistive unit.

[0014] In one embodiment, the main current and the reset current are both in a non-critical state; when the number N of the hysteresis magnetoresistive units is an odd number other than 1, the magnetic state 1 (N+1) / 2 0 (N-1) / 2 or magnetic state 0 (N+1) / 2 1 (N-1) / 2 is the reset state, magnetic state 1 (N) or magnetic state 0 (N) When the number N of the hysteresis magnetoresistive units is an even number, the magnetic state 1(N / 2) 0 (N / 2) is the reset state, magnetic state 1 (N) or magnetic state 0 (N) This is the overload state.

[0015] In one embodiment, the main current is in a critical state; when the number N of the hysteresis magnetoresistive units is an even number, the magnetic state 1 (N / 2) 0 (N / 2) It is the reset state. If pc+ is set as the critical positive transition probability of the transition from the magnetic state 0 to the magnetic state 1, when p>pc+, it is the overload state, then the magnetic state 1(N / 2*(1+pc+))0(N / 2*(1-pc+)) is the critical positive overload state; if pc- is set as the critical negative transition probability of the transition from the magnetic state 1 to the magnetic state 0, when p>pc-, it is the overload state, then the magnetic state 1(N / 2*(1-pc-))0(N / 2*(1+pc-)) is the critical negative overload state.

[0016] In one embodiment, one end of any of the hysteresis magnetoresistive units is connected to a constant current source Ic, and the other end is grounded; the output voltage across the hysteresis magnetoresistive unit is input to the control logic unit as an output signal of the hysteresis magnetoresistive unit.

[0017] In one embodiment, when the number N of the hysteresis magnetoresistive units is an even number, the magnetic state 1 (N / 2) 0 (N / 2) The reset state is as described, wherein N / 2 of the hysteresis magnetoresistive units whose magnetic state is 1 and N / 2 of the hysteresis magnetoresistive units whose magnetic state is 0 are respectively interconnected as a push arm and a pull arm of a two-port structure, and the push arm and the pull arm are connected in series to form a push-pull half bridge; one end of the power supply end of the push-pull half bridge is grounded, and the other end is connected to a constant voltage source Vc, and the middle end outputs a signal Vo, and Vo / Vc is input into the control logic unit as the output signal of the hysteresis magnetoresistive unit.

[0018] In one embodiment, when the number N / 2 of the hysteresis magnetoresistive units is an even number, the magnetic state 1 (N / 4) 0 (N / 4) 1 (N / 4) 0 (N / 4) The reset state is as described, wherein N / 4 of the hysteresis magnetoresistive units whose magnetic state is 1 and N / 4 of the hysteresis magnetoresistive units whose magnetic state is 0 are interconnected as a push arm and a pull arm of a two-port structure; the push arm and the pull arm are connected to form a push-pull full bridge; one end of the power supply end of the push-pull full bridge is grounded, and the other end is connected to a constant voltage source Vc, and the middle end outputs a signal Vo, and Vo / Vc is input into the control logic unit as the output signal of the hysteresis magnetoresistive unit.

[0019] In one embodiment, when the number N of the hysteresis magnetoresistive units is an even number, the magnetic state 1 (N / 2) 0 (N / 2) It is the reset state, wherein N / 2 of the hysteresis magnetoresistive units whose magnetic state is 1 are connected in series to form an arm 1 of a two-port structure, and the reset resistance of the arm 1 is R1; N / 2 of the hysteresis magnetoresistive units whose magnetic state is 0 are connected in series to form an arm 0 of a two-port structure, and the reset resistance of the arm 0 is R0; the arm 0 and the arm 1 are connected in series to form an arm 01, and the reset resistance of the arm 01 is Rset; the ratio R / Rset of the total resistance R of the arm 01 to Rset is input to the control logic unit as the output signal of the arm 01.

[0020] In one embodiment, when the R / Rset is between [(1-pc-*(R1-R0) / (R1+R0),1+pc+*(R1-R0) / (R1+R0)], the magnetic state of the hysteresis magnetoresistive unit is configured as a reset state by the control logic unit; when the R / Rset is between [2*R0 / (R1+R0),1-pc-*(R1-R0) / (R1+R0)] or [1+pc+*(R1-R0) / (R1+R0),2*R1 / (R1+R0)], the hysteresis magnetoresistive unit is configured as an overload state by the control logic unit.

[0021] In one embodiment, the control logic unit, the reset current conductor, and the hysteresis magnetoresistive unit are powered by an independent discrete power supply, or powered by a battery, and the discrete power supply and the battery are switchable.

[0022] In one embodiment, the magnetoresistive fuse further includes a digital output signal for indicating whether the fuse is disconnected; the digital output signal configures the reset state and the overload state of the control logic unit to 1 and 0, or to 0 and 1.

[0023] In one embodiment, the control logic unit includes: a memory for recording the magnetic state of the hysteresis magnetoresistive unit when the magnetoresistive fuse is disconnected, and being read by the control logic unit when the magnetoresistive fuse works again, so that the control logic unit configures the on and off states of the control end of the switching unit according to the magnetic state of the hysteresis magnetoresistive unit.

[0024] In one embodiment, the switch unit is a triode, a FET, a MOS tube or a mechanical electronic device; the control end of the switch unit is in a normally off state.

[0025] In one embodiment, the hysteresis magnetoresistive unit is an anisotropic magnetoresistive effect AMR element, a giant magnetoresistive effect GMR element, or a tunneling magnetoresistive effect TMR element; the pinned layers of the hysteresis magnetoresistive units have the same magnetization direction; the free layer magnetization direction of the hysteresis magnetoresistive unit is parallel to the magnetization direction of the pinned layer and opposite to the magnetization direction of the pinned layer; the direction of the main magnetic field generated by the main current and the direction of the reset magnetic field generated by the reset current are both parallel to the magnetization direction of the pinned layer.

[0026] In one embodiment, the magnetoresistive fuse is a packaged multi-chip structure, which includes: a magnetic chip die, the control logic unit and the switch unit; the magnetic chip die includes: a wafer substrate, the hysteresis magnetoresistive unit, the main current conductor and the reset current conductor; wherein the hysteresis magnetoresistive unit is located above the wafer substrate; the main current conductor is located above, below or on the lead frame of the wafer substrate; the reset current conductor is located above, below or on the lead frame of the wafer substrate; the control logic unit is an ASIC die; the switch unit is a MOS tube die; the magnetic chip die, the ASIC die and the MOS tube die are respectively mounted on the lead frame and encapsulated in a packaging resin.

[0027] In one embodiment, the magnetoresistive fuse is a packaged module structure, which includes: a PCB, the hysteresis magnetoresistive unit arranged on the PCB, the main current conductor, the reset current conductor, the control logic unit and the switch unit; the hysteresis magnetoresistive unit, the switch unit and the control logic unit are respectively a hysteresis magnetoresistive unit chip, a switch unit chip and a control logic unit chip.

[0028] In one embodiment, a magnetic shielding layer is further included; the magnetic shielding layer is located above and / or below the packaging structure.

[0029] In one embodiment, the magnetic shielding layer is a magnetic shielding layer made of a magnetic thin film material, and the magnetic shielding layer is directly deposited above or below a multilayer stacked structure consisting of a wafer substrate, the hysteresis magnetoresistive unit, the main current conductor, and the reset current conductor.

[0030] In one embodiment, the magnetic shielding layer is located on the upper surface or the lower surface of the packaging resin.

[0031] In one embodiment, a mounting pit is provided on the upper surface or the lower surface of the resin; and the magnetic shielding layer is disposed in the mounting pit.

[0032] In one embodiment, a suspension tongue is provided on the side wall of the installation pit; the magnetic shielding layer is in the shape of a thin strip, and the magnetic shielding layer is inserted into the installation pit through the suspension tongue.

[0033] In one embodiment, the main current conductor includes a main current strip; the reset current conductor includes: a first reset current strip and a second reset current strip; the first reset current strip and the second reset current strip have opposite current directions; the hysteresis magnetoresistive unit includes: a hysteresis magnetoresistive unit array with a reset magnetic state of 1 located on the first reset current strip, the second reset current strip, and the main current strip, respectively, and a hysteresis magnetoresistive array with a reset magnetic state of 0 located on the second reset current strip and the main current strip; the current directions of the first reset current strip, the second reset current strip, and the main current strip are all perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit.

[0034] In one embodiment, the main current conductor includes a main current strip; the reset current conductor is a serpentine current conductor, including: a third reset current strip and a fourth reset current strip that are alternately arranged and parallel to each other; the third reset current strip and the fourth reset current strip have opposite current directions; the hysteresis magnetoresistive unit includes: a hysteresis magnetoresistive unit array with a reset magnetic state of 1 located on the third reset current strip and the main current strip, and a hysteresis magnetoresistive unit array with a reset magnetic state of 0 located on the fourth reset current strip and the main current strip; the flow directions of the main current strip, the third reset current strip, and the fourth reset current strip are all perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit.

[0035] In one embodiment, the main current stripe includes: a plurality of main current sub-strips connected in parallel; the hysteresis magnetoresistive unit array with the reset magnetic state of 1 and the hysteresis magnetoresistive unit array with the reset magnetic state of 0 are both located on the main current sub-strip.

[0036] In one embodiment, the reset current conductor is a spiral current conductor, comprising: a first reset current sub-region and a second reset current sub-region with opposite current directions; the first reset current sub-region and the second reset current sub-region each comprise a plurality of parallel and equidistantly arranged straight strips; the hysteresis magnetoresistive unit array with a reset magnetic state of 1 and the hysteresis magnetoresistive unit array with a reset magnetic state of 0 are located in the first reset current sub-region and the second reset current sub-region, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0038] FIG1 is a schematic diagram of the structure of a fuse when used in a power supply in the related art;

[0039] FIG1(a) is a schematic diagram of the structure of a parallel battery stack circuit, and FIG1(b) is a schematic diagram of the structure of a parallel battery stack circuit with a fuse;

[0040] FIG2 is a schematic diagram of the magnetic moment state and resistance state of the hysteresis magnetoresistive unit provided in an embodiment of the present application;

[0041] 2(a) is a schematic diagram of the magnetic moment state and resistance state of the hysteresis magnetoresistive unit when it is in a low resistance state, and FIG2(b) is a schematic diagram of the magnetic moment state and resistance state of the hysteresis magnetoresistive unit when it is in a high resistance state;

[0042] FIG3 is a schematic diagram of the working principle of the hysteresis magnetoresistive unit provided in an embodiment of the present application;

[0043] Among them, Figure 3(a) is the rectangular transfer curve of hysteresis magnetoresistance ~ magnetic field, Figure 3(b) is the linear diagram of current i ~ external magnetic field H, Figure 3(c) is the non-critical overload current time curve, Figure 3(d) is the non-critical non-overload current time curve, and Figure 3(e) is the critical current time curve;

[0044] FIG4 is a schematic structural diagram of a resettable magnetoresistive fuse provided in an embodiment of the present application;

[0045] Among them, Figure 4(a) is a functional block diagram of the magnetoresistive fuse, Figure 4(b) is a schematic diagram of the external connection of the main circuit, Figure 4(c) is a schematic diagram of the structure of the working power supply of the magnetoresistive fuse, Figure 4(d) is a schematic diagram of the reset pulse circuit, Figure 4(e) is a schematic diagram of the fault analysis of the magnetoresistive fuse, and Figure 4(f) is a schematic diagram of the magnetic state analysis of the magnetoresistive fuse when it is turned on;

[0046] FIG5 is a schematic diagram of a critical magnetic state of a hysteresis magnetoresistive unit according to an embodiment of the present application;

[0047] Among them, Figure 5(a) is a schematic diagram of the magnetic state distribution in the initial state, Figure 5(b) is a schematic diagram of the magnetic state distribution in the critical transition state, Figure 5(c) is a schematic diagram of the magnetic state distribution when the transition probability is 1, and Figure 5(d) is a transition probability configuration diagram of the hysteresis magnetoresistive unit;

[0048] FIG6 is a schematic diagram of a circuit structure of an embodiment of a hysteresis magnetoresistive unit provided in an embodiment of the present application;

[0049] FIG7 is a schematic diagram of a circuit structure of another embodiment of a hysteresis magnetoresistive unit provided in an embodiment of the present application;

[0050] FIG8 is a schematic diagram of a circuit structure of another embodiment of a hysteresis magnetoresistive unit provided in an embodiment of the present application;

[0051] Among them, Figure 8 (a) shows a hysteresis magnetoresistive unit of a half-bridge structure, and Figure 8 (b) shows a hysteresis magnetoresistive unit of a full-bridge structure;

[0052] FIG9 is a schematic diagram of a circuit structure of another embodiment of a hysteresis magnetoresistive unit provided in an embodiment of the present application;

[0053] 9(a) is a circuit structure of the hysteresis magnetoresistance unit in the initial state, FIG9(b) is a circuit structure of the hysteresis magnetoresistance unit in the positive critical transition pc+ state, FIG9(c) is a circuit structure of the hysteresis magnetoresistance unit in the positive transition probability p=1 state, FIG9(d) is a circuit structure of the hysteresis magnetoresistance unit in the negative critical transition pc- state, FIG9(e) is a circuit structure of the hysteresis magnetoresistance unit in the negative transition probability p=1 state, and FIG9(f) is a schematic diagram of the resistivity configuration of the overload state and the reset state;

[0054] FIG10 is a schematic structural diagram of a first magnetoresistive fuse chip structure according to an embodiment of the present application;

[0055] 10( a ) is a cross-sectional view of a magnetoresistive fuse chip, and FIG. 10( b ) is a top view of a hysteresis magnetoresistive chip;

[0056] FIG11 is a schematic structural diagram of a second magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0057] 11( a ) is a cross-sectional view of a magnetoresistive fuse chip, and FIG11( b ) is a top view of a hysteresis magnetoresistive chip;

[0058] FIG12 is a schematic structural diagram of a third magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0059] 12( a ) is a cross-sectional view of a magnetoresistive fuse chip, and FIG12( b ) is a top view of a hysteresis magnetoresistive chip;

[0060] FIG13 is a schematic structural diagram of a fourth magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0061] 13( a ) is a cross-sectional view of a magnetoresistive fuse chip, and FIG13( b ) is a top view of a hysteresis magnetoresistive chip;

[0062] FIG14 is a schematic structural diagram of a fifth magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0063] 14( a ) is a cross-sectional view of a magnetoresistive fuse chip, and FIG14( b ) is a top view of a hysteresis magnetoresistive chip;

[0064] FIG15 is a schematic structural diagram of a configuration of a magnetic shielding layer of a multi-chip magnetoresistive fuse provided in an embodiment of the present application;

[0065] FIG16 is a schematic structural diagram of another configuration of a magnetic shielding layer of a multi-chip magnetoresistive fuse provided in an embodiment of the present application;

[0066] Among them, Figure 16 (a) is a structural block diagram, and Figure 16 (b) is a cross-sectional schematic diagram;

[0067] FIG17 is a schematic structural diagram of a sixth magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0068] FIG18 is a schematic structural diagram of a seventh magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0069] FIG19 is a schematic structural diagram of an eighth magnetoresistive fuse chip structure provided in an embodiment of the present application;

[0070] FIG20 is a schematic structural diagram of a packaging colloid with a mounting pit provided in an embodiment of the present application;

[0071] Among them, Figure 20(a) is a schematic diagram of the three-dimensional structure, Figure 20(b) is a cross-sectional view parallel to the edge direction, and Figure 20(c) is a cross-sectional view perpendicular to the edge direction;

[0072] FIG21 is a schematic diagram of the structure of a modular magnetoresistive fuse provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0074] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0075] First, the hysteresis magnetoresistive unit included in the resettable magnetoresistive fuse in the embodiment of the present application is introduced:

[0076] Please refer to Figure 2. The hysteresis magnetoresistive unit in the embodiment of the present application can adopt an anisotropic magnetoresistive effect AMR element, a giant magnetoresistive effect GMR element or a tunneling magnetoresistive effect TMR element, which includes a pinned layer and a free layer, wherein the direction of the free layer magnetic moment Hf is parallel to the direction of the pinned layer magnetic moment Hp. As shown in Figure 2(a), when the direction of the free layer magnetic moment Hf is the same as the direction of the pinned layer magnetic moment Hp, the above-mentioned hysteresis magnetoresistive unit presents a low resistance state. As shown in Figure 2(b), when the direction of the free layer magnetic moment Hf is opposite to the direction of the pinned layer magnetic moment Hp, the above-mentioned hysteresis magnetoresistive unit presents a high resistance state. The direction of the external magnetic field Hex is parallel to the direction of the pinned layer Hp. The resistance-magnetic field characteristic curve of the hysteresis magnetoresistive unit is rectangular. When the magnetic field Hex is greater than Hc from the positive direction, the hysteresis magnetoresistive unit is in a high resistance state Rh. When the magnetic field Hex is less than -Hc from the negative direction, the hysteresis magnetoresistive unit is in a low resistance state Rl. -Hc and Hc are the recovery magnetic field and the operating magnetic field of the hysteresis magnetoresistive unit, respectively. In the embodiment of the present application, the high resistance Rh is defined as the magnetic state 1, and the low resistance Rl is defined as the magnetic state 0.

[0077] The working principle of the hysteresis magnetic unit is introduced below:

[0078] See Figure 3, where:

[0079] The rectangular transfer curve of hysteresis magnetoresistance and magnetic field shown in Figure 3(a) can be used to detect the on / off state of a fuse.

[0080] In the linear graph of current i and external magnetic field H shown in Figure 3(b), the current corresponding to the operating magnetic field Hc is Ic, and the current corresponding to the recovery magnetic field -Hc is -Ic. When the current increases from the positive direction to greater than Ic, the hysteresis magnetoresistive unit will likely transition to the high-resistance state Rh. When the current decreases from the negative direction to less than -Ic, the hysteresis magnetoresistive unit may transition to the low-resistance state Rl. Therefore, Ic is the threshold for positive current, and -Ic is the threshold for negative current. The success and probability of the specific transition depend on the state of the current waveform, that is, whether it is in the critical state or the non-critical state.

[0081] In the non-critical overload current time curve shown in Figure 3(c), when the current increases in the positive direction from point a, reaches the threshold value Ic at point b, and then returns to the threshold value Ic from point c, the current is above the threshold value for a period of bc long enough, then from point b onwards, the hysteresis magnetoresistance is in a high resistance state Rh. Similarly, when the current decreases from point c to 0, and then reverses to reach the threshold value point -Ic at point d, the current is below the threshold value for a period of de long enough, then from point d onwards, the hysteresis magnetoresistance is in a low resistance state Rl.

[0082] In the non-critical non-overload current time curve shown in FIG3( d ), the current points a, b, c, and d are all within the threshold values ​​Ic and -Ic, and the hysteresis magnetoresistive unit is in the initial state;

[0083] In the critical current-time curve shown in FIG3(e), in the critical state, when the hysteresis magnetoresistance is at the critical threshold Ic or -Ic, the probability p of the hysteresis magnetoresistance changing from the low resistance state Rl to the high resistance state Rh, and from the high resistance state Rh to the low resistance state Rl depends on the time Tpulse staying in the segment above the threshold, and the amplitude of the threshold, i.e., △i. The larger the Tpulse and the △i, the greater the probability p. The probability p is between 0 and 1, that is, if there are N hysteresis magnetoresistance units, then N*p hysteresis magnetoresistance units change state, and N*(1-p) hysteresis magnetoresistance units do not change.

[0084] The resettable magnetoresistive fuse provided in the embodiment of the present application is described in detail below:

[0085] Referring to FIG. 4 , an embodiment of the present application provides a resettable magnetoresistive fuse 1. As shown in FIG. 4( b ), the magnetoresistive fuse 1 is electrically connected to the power circuit or the device to be protected 116 via the main input pad 2 and the main output pad 3 . As shown in FIG. 4( d ), the magnetoresistive fuse 1 is electrically connected to the reset pulse circuit 115 via the reset input pad 5 and the reset output pad 6 . When the power circuit or the device to be protected 116 is overloaded, the magnetoresistive fuse 1 is disconnected. When the power circuit or the device to be protected 116 is repaired, the reset pulse circuit 115 is activated, and the magnetoresistive fuse 1 is reset.

[0086] As shown in FIG4( a ), the magnetoresistive fuse 1 comprises one or more hysteresis magnetoresistive units 7, a main current conductor 4, a reset current conductor 8, a switch unit 10, and a control logic unit 9. Each hysteresis magnetoresistive unit 7 has two magnetic states: magnetic state 0 and magnetic state 1. The input terminal 40, output terminal 43, first intermediate terminal 41, and second intermediate terminal 42 of the main current conductor 4 are electrically connected to the main input pad 2, the main output pad 3, the input terminal 10(1) of the switch unit 10, and the output terminal 10(2) of the switch unit 10, respectively.

[0087] It can be understood that only two groups of hysteresis magnetoresistive units 70 and 71 are shown in Figure 4(a), but this does not mean that the magnetoresistive fuse 1 in the embodiment of the present application can only adopt these two groups of hysteresis magnetoresistive units. The two groups of hysteresis magnetoresistive units 70 and 71 shown in Figure 4(a) are only an example and should not be regarded as a limitation on the number of hysteresis magnetoresistive units 7 in the magnetoresistive fuse 1.

[0088] Similarly, it can be understood that Figure 4(a) only shows two sub-reset current conductors 80 and 81 with opposite current directions, but this does not mean that the magnetoresistive fuse 1 in the embodiment of the present application can only use these two sub-reset current conductors. The two sub-reset current conductors 80 and 81 shown in Figure 4(a) are only an example and should not be regarded as a limitation on the number of sub-reset current conductors in the magnetoresistive fuse 1.

[0089] When the power supply circuit or the device to be protected 116 is overloaded, the magnetic state of the main current configuration hysteresis magnetoresistive unit 7 in the main current conductor 4 is in an overload state, and the magnetoresistive fuse 1 is disconnected; when the power supply circuit or the device to be protected 116 is repaired, the reset pulse circuit 115 is started, the magnetic state of the reset current configuration hysteresis magnetoresistive unit 7 in the reset current conductor 8 is in a reset state, and the magnetoresistive fuse 1 is reset.

[0090] Optionally, when the hysteresis magnetoresistance unit 7 is in an overload state, the main magnetic field generated by the main current exceeds the coercive force Hc or -Hc of the hysteresis magnetoresistance unit 7; when the hysteresis magnetoresistance unit 7 is in a reset state, the reset magnetic field generated by the reset current exceeds the coercive force Hc or -Hc of the hysteresis magnetoresistance unit 7.

[0091] It is understandable that the magnetic state is further configured by the control logic unit 9 as an off signal or an on signal of the control terminal 10 (0) of the switch unit 10 to start the switch unit 10 to be off or on, thereby realizing the disconnection and resetting of the magnetoresistive fuse 1.

[0092] Optionally, the magnetoresistive fuse 1 further comprises an on / off indication signal output port 13 , which is connected to the control logic unit 9 and directly outputs a resettable on / off indication signal of the magnetoresistive fuse 1 .

[0093] Optionally, the control logic unit 9 includes:

[0094] The memory is used to record the magnetic state of the hysteresis magnetoresistive unit 7 when the magnetoresistive fuse 1 is disconnected, and is read by the control logic unit 9 when the magnetoresistive fuse 1 works again, so that the control logic unit 9 configures the on and off states of the control terminal 10(0) of the switch unit 10 according to the magnetic state of the hysteresis magnetoresistive unit 7.

[0095] Optionally, the control logic unit 9 may be powered by a logic power supply 110 , and the hysteresis magnetoresistive unit 7 may be powered by a sensing power supply 111 . The logic power supply 110 and the sensing power supply 111 constitute a working power supply 11 of the magnetoresistive fuse 1 .

[0096] It is understood that the control logic unit 9, reset current conductor 8, and hysteresis magnetoresistive unit 7 are powered by independent discrete power supplies or batteries, and the discrete power supplies and the battery are switchable. As shown in FIG4(c), the logic power supply 110 and the sensor power supply 111 can both be powered by an external power supply 113 or a battery 112, and the external power supply 113 and the battery 112 can be switched by a converter 114.

[0097] As shown in Figure 4(e), when the power supply circuit or the device to be protected 116 is in a non-working state, there are two possible reasons: first, the power supply circuit or the device to be protected 116 is overloaded, and at this time, the magnetic state is an overload state; in this case, if the fault is eliminated, the reset pulse circuit 115 is started and the magnetic state becomes a reset state; second, the power supply circuit or the device to be protected 116 is not normally powered, and the magnetic state is a reset state.

[0098] As shown in FIG4(f), when the power supply circuit or the device to be protected 116 is ready to start working, the magnetic state of the hysteresis magnetoresistive unit is read. If it is in the reset state, the control terminal 10(0) of the switch unit 10 is in the on state, and the input terminal 10(1) and the output terminal 10(2) of the switch unit 10 are in the on state. If it is in the overload state, the control terminal 10(0) of the switch unit 10 is in the off state, and the input terminal 10(1) and the output terminal 10(2) of the switch unit 10 are in the off state. In the default state, the initial state of the switch unit 10 is the off state. The above-mentioned switch unit 10 can be: a transistor, a FET, a MOS tube or a mechanical electronic device.

[0099] The following describes the configuration information of the overload state and reset state in different forms and the corresponding current state according to the number of 7 hysteresis magnetoresistive units:

[0100] Form 1: Both the main current and the reset current are in a non-critical state, and the number N of the hysteresis magnetoresistive units 7 is 1.

[0101] As shown in Table 1, when the number N of hysteresis magnetoresistive units 7 is 1, the main current and the reset current are both in a DC non-critical state, the reset state is magnetic state 1 or magnetic state 0, and the corresponding overload state is magnetic state 0 or magnetic state 1.

[0102] Table 1 Related states when the current is in a non-critical state and the number of hysteresis magnetoresistive units is 1

[0103] It can be understood that when the number N of hysteresis magnetoresistive units is greater than 1, the reset state is a mixture of magnetic state 0 and magnetic state 1.

[0104] Form 2: Both the main current and the reset current are in a non-critical state, and the number N of the hysteresis magnetoresistive units 7 is an odd number other than 1.

[0105] As shown in Table 2, when the number N of the hysteresis magnetoresistive units 7 is an odd number other than 1, the magnetic state 1 (N+1) / 2 0 (N-1) / 2 or magnetic state 0 (N+1) / 2 1 (N-1) / 2 is a reset state, wherein the number of hysteresis magnetoresistive units 7 in magnetic state 1 and magnetic state 0 is (N+1) / 2 and (N-1) / 2 respectively, or the number is (N-1) / 2 and (N+1) / 2 respectively, and the magnetic state 1 is (N) or magnetic state 0 (N) In overload state.

[0106] Table 2 Related states when the current is non-critical and the number of hysteresis magnetoresistive units is an odd number other than 1

[0107] Form 3: Both the main current and the reset current are in a non-critical state, and the number N of the hysteresis magnetoresistive units 7 is an even number.

[0108] As shown in Table 3, when the number N of the hysteresis magnetoresistive units 7 is an even number, the magnetic state 1 (N / 2) 0 (N / 2) The number of hysteresis magnetoresistive units 7 with magnetic states 1 and 0 is N / 2. (N) or magnetic state 0 (N) It is in overload state and the current is in non-critical state.

[0109] Table 3 Related states when the current is non-critical and the number of hysteresis magnetoresistive units is even

[0110] Form 4: The current is in a non-critical state, the number of the hysteresis magnetoresistive units 7 is N, and N / 2 is greater than 1 and is an even number.

[0111] As shown in Table 4, the number of hysteresis magnetoresistive units 7 is N. When N / 2 is greater than 1 and is an even number, the reset magnetic state is 1. (N / 4) 0 (N / 4) 1 (N / 4) 0 (N / 4) , where the number of hysteresis magnetoresistive units with magnetic states of 1 and 0 are N / 4 and N / 4 respectively, and the overload magnetic state is 1 (N) or 0 (N) , which corresponds to the non-critical state.

[0112] Table 4 Related states when the current is in a non-critical state and the number of hysteresis magnetoresistive units is N, and N / 2 is greater than 1 and is an even number

[0113] Form 5: The main current is in a critical state, and the number of hysteresis magnetoresistive units 7 is an even number.

[0114] As shown in Table 5, when the number N of the hysteresis magnetoresistive units 7 is an even number, the magnetic state 1 (N / 2) 0 (N / 2) It is a reset state. If pc+ is set as the critical positive transition probability of the transition from the magnetic state 0 to the magnetic state 1, it is an overload state when p>pc+, then the magnetic state 1(N / 2*(1+pc+))0(N / 2*(1-pc+)) is a critical positive overload state; if pc- is set as the critical negative transition probability of the transition from the magnetic state 1 to the magnetic state 0, it is an overload state when p>pc-, then the magnetic state 1(N / 2*(1-pc-))0(N / 2*(1+pc-)) is a critical negative overload state.

[0115] Table 5 Related states when the main current is in a critical state and the number of hysteresis magnetoresistive units 7 is an even number N

[0116] The critical magnetic state transition of the hysteresis magnetoresistive unit 7 is described in detail below:

[0117] Please refer to Figure 5. Figure 5(a) is a schematic diagram of the magnetic state distribution in the initial state, wherein there are N / 2 hysteresis magnetoresistive units 7 with a magnetic state of 1. These N / 2 hysteresis magnetoresistive units with a magnetic state of 1 are connected in series to form arm 1 of a two-port structure, and the reset resistor of arm 1 is R1; there are N / 2 hysteresis magnetoresistive units 7 with a magnetic state of 0. These N / 2 hysteresis magnetoresistive units with a magnetic state of 0 are connected in series to form arm 0 of a two-port structure, and the reset resistor of arm 0 is R0. Figure 5(b) is a schematic diagram of the magnetic state distribution in the critical transition state. At this time, some hysteresis magnetoresistive units in arm 1 change from magnetic state 1 to magnetic state 0. The negative critical transition probability is pc-, then the critical magnetic state is 1(N*(1-pc-) / 2)0 (N*pc- / 2) , the resistance of arm 01 is R1*(1-pc-)+R0*pc-, some hysteresis magnetoresistance units in arm 0 change from magnetic state 0 to magnetic state 1, the positive critical transition probability is pc+, then the critical magnetic state is 0(N*(1-pc+) / 2)1 (N*pc+ / 2) , the resistance of arm 01 is R0*(1-pc+)+R1*pc+. Figure 5(c) is a schematic diagram of the magnetic state distribution when the transition probability is 1. The transition probability p=1, the magnetic states of the hysteresis magnetoresistive unit are 0 (N / 2) and 1 (N / 2)Figure 5(d) is a diagram showing the transition probability configuration of the hysteretic magnetoresistive element. When the transition probabilities of resetting the magnetic states 0 or 1 are distributed between 0 and pc- or pc+, the magnetic state is defined as the reset state. When the transition probabilities are between pc+ and 1, the magnetic state is defined as the overload state.

[0118] The following will separately introduce the circuit structures of the hysteretic magnetoresistive elements corresponding to the relevant configurations in Tables 1 to 5 above:

[0119] For Table 1: Refer to Figure 6. When the number N of the hysteretic magnetoresistive elements 7 is 1, one end of the hysteretic magnetoresistive element 7 can be connected to the constant current source Ic, and the other end is grounded. The output voltage V0 across the hysteretic magnetoresistive element 7 is input as the output signal of the hysteretic magnetoresistive element 7 to the control logic unit 9. When the magnetic state of the hysteretic magnetoresistive element 7 is 1 or 0, Vo outputs a logic level of 1 or 0, and the control logic unit 9 is configured to a logic level of 1 or 0 of the control signal, and the configuration table is Table 1.

[0120] For Tables 2 and 3: Refer to Figure 7. When the number N of the hysteretic magnetoresistive elements 7 is greater than 1, any one of the hysteretic magnetoresistive elements 7 is powered by the constant current source Ic, that is, one end of any one of the hysteretic magnetoresistive elements 7 is connected to the constant current source Ic, and the other end is grounded; the output signal terminal of the hysteretic magnetoresistive element 7 is V i , where i is between 1 and the number N of the hysteretic magnetoresistors. The magnetic state of the hysteretic magnetoresistive element 7 is 1 or 0. Similarly, V i outputs a logic level of 1 or 0, and then is configured by the control logic unit 9 to a logic level of 1 or 0 of the control signal, and the configuration tables are Tables 2 and 3.

[0121] For Tables 3 and 4: Refer to Figure 8. As shown in Figure 8(a), when the number N of the hysteretic magnetoresistive elements 7 is even, the magnetic state 1 (N / 2) 0 (N / 2) is the reset state. Among them, N / 2 hysteretic magnetoresistive elements with a magnetic state of 1 and N / 2 hysteretic magnetoresistive elements with a magnetic state of 0 are respectively interconnected into the push arm 701 and the pull arm 702 of the two-port structure. The push arm 701 and the pull arm 702 are connected in series to form a push-pull half-bridge. One end of the power supply terminal of the push-pull half-bridge is grounded, and the other end is connected to the constant voltage source Vc. The middle terminal outputs the signal Vo, and Vo / Vc is input as the output signal of the hysteretic magnetoresistive element 7 to the control logic unit 9. The output result corresponding to the push-pull half-bridge is shown in Table 6. In the overload state, the output voltage of Vo is Vc / 2, and in the reset state, the output voltage of Vo is >Vc / 2 or <Vc / 2. Therefore, in the control logic unit 9, the input signal Vo / Vc = 1 / 2 can be configured as the logic level 0 of the control signal, that is, the overload state, and the input level greater than or less than 1 / 2 is configured as the logic level 1 of the control signal, that is, the reset state.

[0122] Of course, the intermediate terminal output signal Vo can also be directly connected to the control logic unit 9. The output results of the corresponding push-pull half-bridge are shown in Table 6. In the overload state, the output voltage of Vo is Vc / 2, and in the reset state, the output voltage of Vo is >Vc / 2 or <Vc / 2. Therefore, in the control logic unit 9, the input level of Vc / 2 can be respectively configured as the logic level 0 of the control signal, which is the overload state, and the level greater than or less than Vc / 2 is configured as the logic level 1 of the control signal, which is the reset state.

[0123] Table 6 Output Results of Push-Pull Half-Bridge Corresponding to Fuse States

[0124] As shown in Fig. 8(b), when the number N / 2 of the hysteretic magnetoresistive units 7 is an even number, where N / 4 hysteretic magnetoresistive units with reset magnetic states of 0 and 1 are respectively interconnected to form two-port push arms 703, 704 and pull arms 705, 706. Then, the push arms 703, 704 and the pull arms 705, 706 form a push-pull full bridge. One end of the push-pull full bridge is connected to the constant voltage source Vc, and the other end is grounded. The intermediate terminal output signal Vo includes Vo+ and Vo-. It can be understood that after calculating Vo based on the difference between Vo+ and Vo- and taking Vo / Vc as the output signal of the hysteretic magnetoresistive unit 7, it is input to the control logic unit 9. The output results of the corresponding push-pull full bridge are shown in Table 7. In the overload state, the output voltage of Vo is 0, and in the reset state, the output voltage of Vo is >Vc / 2 or <Vc / 2. Therefore, in the control logic element 9, the input signal Vo / Vc = 0 can be configured as the logic level 0 of the control signal, which is the overload state, and the input signal Vo / Vc > 1 / 2 or < 1 / 2 is configured as the logic level 1 of the control signal, which is the reset state.

[0125] Of course, the intermediate terminal output signal Vo, that is, Vo+ and Vo- can also be directly input to the control logic unit 9. The output results of the corresponding push-pull full bridge are shown in Table 7. In the overload state, the output voltage of Vo+-Vo- is 0, and in the reset state, the output voltage of Vo is >Vc / 2 or <Vc / 2. Therefore, in the control logic element 9, the logic level 0 of the Vo+-Vo- input signal can be configured as the logic level 0 of the control signal, which is the overload state, and the logic level >Vc / 2 or <Vc / 2 of the Vo+-Vo- input signal is configured as the logic level 1 of the control signal, which is the reset state.

[0126] Table 7 Output Results of Push-Pull Full Bridge Corresponding to Fuse States

[0127] Regarding Table 5: Please refer to FIG9. As shown in FIG9(a), in the initial state, that is, when the transition probability p = 0, the hysteresis magnetoresistive units with a magnetic state of 1 are interconnected into a two-port structure arm 1 707, whose resistance is R1, and the hysteresis magnetoresistive units with a magnetic state of 0 are interconnected into a two-port structure arm 0 708, whose resistance is R0. R1 and R0 are connected in series, and their total resistance is R set =R1+R0.

[0128] As shown in FIG9(b), in the positive critical transition pc+ state, assuming that the probability that the hysteresis magnetoresistive unit with a magnetic state of 0 transitions to a magnetic state of 1 is pc+, the total resistance of arm 01 709 is pc+*R1+(1-pc+)*R0, and the total series resistance is: (1+pc+)*R1+(1-pc+)*R0, which is 1+pc+*(R1-R0) / (R1+R0) relative to the resistivity when p=0.

[0129] As shown in FIG9(c), in the forward transition probability p=1 state, all hysteresis magnetoresistive unit resistances in arm 0 are transformed into R1 710, and the total series resistance is 2*R1, which is 2*R1 / (R1+R0) relative to the resistivity when p=0.

[0130] As shown in Figure 9(d), in the negative critical transition pc- state, assuming that the probability of the hysteresis magnetoresistive unit with a magnetic state of 1 transitioning to a magnetic state of 0 is pc-, the resistance of arm 01 711 is pc-*R0+(1-pc-)*R1, and the total series resistance is (1+pc-)*R0+(1-pc-)*R1, and the resistivity relative to p=0 is 1-p*(Rh-Rl) / (Rh+Rl).

[0131] As shown in FIG9(e), in the negative transition probability p=1 state, all resistors in arm 1 are transformed into R0 712, and the total series resistance is 2*R0, which is 2*R0 / (R1+R0) relative to the resistivity when p=0.

[0132] As shown in Figure 9(f), assuming that pc+ and pc- are the positive critical transition probability and the negative critical transition probability, respectively, the controlled logic unit with a resistivity between [(1-pc-*(R1-R0) / (R1+R0),1+pc+*(R1-R0) / (R1+R0)] is configured as reset state 1, that is, the logic level of the control signal end is high, and the controlled logic unit with a resistivity between [2*R0 / (R1+R0),1-pc-*(R1-R0) / (R1+R0)] or [1+pc+*(R1-R0) / (R1+R0),2*R1 / (R1+R0)] is configured as overload state 0, that is, the logic level of the control signal end is low.

[0133] The following is a detailed introduction to the chip structure of the above-mentioned magnetoresistive fuse:

[0134] Structure 1: Referring to FIG. 10 , a magnetoresistive fuse chip 100 of the first structure includes: a wafer substrate 101 , a hysteresis magnetoresistive unit located above the wafer substrate 101 , a strip-shaped reset current conductor 103 , and a main current conductor 104 .

[0135] It is understood that the number of the above-mentioned hysteresis magnetoresistive units is one or more, and FIG10 only shows the case of multiple hysteresis magnetoresistive units. However, the case of one hysteresis magnetoresistive unit can be obtained by transformation based on the following scheme including multiple hysteresis magnetoresistive units. The magnetoresistive fuse chip 100 shown in FIG10 includes two groups of hysteresis magnetoresistive unit arrays 102, namely, a hysteresis magnetoresistive unit array 102 (1) with a reset magnetic state of 1 and a hysteresis magnetoresistive unit array 102 (0) with a reset magnetic state of 0.

[0136] The strip-mounted reset current conductor 103 includes a first reset current strip 103 ( 0 ) and a second reset current strip 103 ( 1 ) having opposite reset current directions.

[0137] The main current conductor 104 and the reset current conductor 103 can be located below the wafer substrate 101, or above the wafer substrate 101. In the structure shown in Figure 10, only one layout of the main current conductor 104 and the reset current conductor 103 is given, that is, the main current conductor 104 is located below the wafer substrate 101, and the reset current conductor 104 is located above the wafer substrate 101 and above the hysteresis magnetoresistive unit array 102. However, this does not mean that the main current conductor 104 and the reset current conductor 103 can only be arranged in this way.

[0138] The hysteresis magnetoresistive unit array 102 is located in the surface area of ​​the main current conductor 104, and the main current direction is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array 102. The hysteresis magnetoresistive unit array 102(0) with a magnetic state of 0 and the hysteresis magnetoresistive unit array 102(1) with a magnetic state of 1 are respectively located in the areas of the first current reset current bar 103(0) and the second current reset current bar 103(1), and the directions of the reset currents are respectively perpendicular to the magnetic field sensitive directions of the hysteresis magnetoresistive unit array 102.

[0139] In addition, one or two soft magnetic shielding layers 105 are included. Figure 10 shows the situation where two soft magnetic shielding layers are included, namely, the first soft magnetic shielding layer 105 (0) and the second soft magnetic shielding layer 105 (1) are located at the top and bottom respectively. The purpose of setting the soft magnetic shielding layer is to prevent external interference with the magnetic field.

[0140] Structure 2: Referring to FIG. 11 , a magnetoresistive fuse chip 200 of the second structure includes: a wafer substrate 201 , a hysteresis magnetoresistive unit located above the wafer substrate 201 , a main current conductor 204 , and a reset current conductor 203 .

[0141] It is understood that the number of hysteresis magnetoresistive units is one or more, and FIG11 only shows the case of multiple hysteresis magnetoresistive units. However, the case of one hysteresis magnetoresistive unit can be obtained by transformation based on the scheme including multiple hysteresis magnetoresistive units. The magnetoresistive fuse chip 200 shown in FIG11 includes two groups of hysteresis magnetoresistive unit arrays 202, including a hysteresis magnetoresistive unit array 202 (1) with a reset magnetic state of 1 and a hysteresis magnetoresistive unit array 202 (0) with a reset magnetic state of 0, wherein the hysteresis magnetoresistive unit array 202 (0) and the hysteresis magnetoresistive unit array 202 (1) are arranged crosswise.

[0142] The reset current conductor 203 is serpentine, including a third reset current strip 203 ( 0 ) and a fourth reset current strip 203 ( 1 ) arranged crosswise with opposite current directions. The main current conductor 204 and the reset current conductor 204 can be located below the wafer substrate 201 or above the wafer substrate 201 .

[0143] It can be understood that Figure 11 only shows one layout of the main current conductor 204 and the reset current conductor 203, that is, the main current conductor 204 is located above the wafer substrate 201 and below the hysteresis magnetoresistive unit array 202, and the reset current conductor 203 is located above the wafer substrate 201 and above the hysteresis magnetoresistive unit array 202, but it does not mean that the main current conductor 204 and the reset current conductor 203 can only adopt this layout setting.

[0144] In addition, the hysteresis magnetoresistive unit array 202 is located in the surface area of ​​the main current conductor 204, and the main current direction is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array 202. The hysteresis magnetoresistive unit array 202(0) with a magnetic state of 0 and the hysteresis magnetoresistive unit array 202(1) with a magnetic state of 1 are respectively located in the areas of the third reset current strip 203(0) and the fourth reset current strip 203(1), and the directions of the reset currents are respectively perpendicular to the magnetic field sensitive directions of the hysteresis magnetoresistive unit array 202.

[0145] In addition, one or two soft magnetic shielding layers 205 are included. In the structure shown in FIG11 , two soft magnetic shielding layers are provided, namely a first soft magnetic shielding layer 205(0) and a second soft magnetic shielding layer 205(1). The first soft magnetic shielding layer 205(0) and the second soft magnetic shielding layer 205(1) are respectively located at the top and the bottom of the magnetoresistive fuse chip 200 packaging structure. The purpose of providing the soft magnetic shielding layer is to prevent external interference with the magnetic field.

[0146] Structure Three: Referring to FIG. 12 , a magnetoresistive fuse chip 300 of the third structure includes: a wafer substrate 301 , a hysteresis magnetoresistive unit located above the wafer substrate 301 , a reset current conductor 303 , and a main current conductor 304 .

[0147] It is understood that the number of the above-mentioned hysteresis magnetoresistive units is one or more. FIG12 only shows the case where multiple hysteresis magnetoresistive units are included. However, the case where the number of hysteresis magnetoresistive units is one can be obtained by transformation based on the scheme of units including multiple hysteresis resistors. The magnetoresistive fuse chip 300 shown in FIG12 includes two groups of hysteresis magnetoresistive unit arrays 302, including a hysteresis magnetoresistive unit array 302 (1) with a reset magnetic state of 1 and a hysteresis magnetoresistive unit array 302 (0) with a reset magnetic state of 0. The hysteresis magnetoresistive unit array 302 (1) and the hysteresis magnetoresistive unit array 302 (0) are arranged crosswise.

[0148] The reset current conductor 303 is serpentine and includes a third reset current strip 303 ( 0 ) and a fourth reset current strip 303 ( 1 ) that are cross-arranged and have opposite current directions.

[0149] The main current conductor 304 includes: a plurality of parallel main current sub-strips 304 (0) located in the middle and isolated from each other, and main current end strips 304 (1) located at both ends. The main current conductor 304 and the reset current conductor 303 can be located below the wafer substrate 301, or above the wafer substrate 301.

[0150] It can be understood that Figure 12 only shows one layout of the main current conductor 304 and the reset current conductor 303, that is, the main current conductor 304 is located above the wafer substrate 301 and below the hysteresis magnetoresistive unit array 302, and the reset current conductor 303 is located above the wafer substrate 301 and above the hysteresis magnetoresistive unit array 302, but it does not mean that the main current conductor 304 and the reset current conductor 303 can only adopt this layout setting.

[0151] The hysteresis magnetoresistive unit array 302(0) with a magnetic state of 0 and the hysteresis magnetoresistive unit array 302(1) with a magnetic state of 1 are respectively located in the region of the third reset current strip 303(0) and the fourth reset current strip 303(1), and the directions of the reset currents are respectively perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array 302. In addition, the hysteresis magnetoresistive unit array 302(0) with a magnetic state of 0 and the hysteresis magnetoresistive unit array 302(1) with a magnetic state of 1 are respectively located in the region of the main current sub-strip 304(0), and the directions of the main currents are both perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array 302.

[0152] In addition, one or two soft magnetic shielding layers 305 are included. FIG12 shows a case where two soft magnetic shielding layers are included, namely, a first soft magnetic shielding layer 305(0) and a second soft magnetic shielding layer 305(1). The first soft magnetic shielding layer 305(0) and the second soft magnetic shielding layer 305(1) are respectively disposed at the top and bottom of the package structure of the magnetoresistive fuse chip 300. The purpose of providing the soft magnetic shielding layer is to prevent external interference magnetic fields.

[0153] Structure 4: Referring to FIG. 13 , a magnetoresistive fuse chip 400 of the fourth structure includes: a wafer substrate 401 , a hysteresis magnetoresistive unit located above the wafer substrate 401 , a reset current conductor 403 , and a main current conductor 404 .

[0154] It is understood that the number of the above-mentioned hysteresis magnetoresistive units is one or more. FIG13 only shows the case where multiple hysteresis magnetoresistive units are included. However, the case where the number of hysteresis magnetoresistive units is one can be obtained by transformation based on the scheme of units including multiple hysteresis resistors. The magnetoresistive fuse chip 400 shown in FIG13 includes two groups of hysteresis magnetoresistive unit arrays 402, including a hysteresis magnetoresistive unit array 402 (1) with a reset magnetic state of 1 and a hysteresis magnetoresistive unit array 402 (0) with a reset magnetic state of 0.

[0155] The reset current conductor 403 is spiral-shaped and includes a first reset current sub-region 403(0) and a second reset current sub-region 403(1) having opposite current directions. The hysteresis magnetoresistive unit array 402(1) and the hysteresis magnetoresistive unit array 402(0) are respectively located in the first reset current sub-region 403(0) and the second reset current sub-region 403(1), and the reset current direction is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit 402.

[0156] The main current conductor 404 is strip-shaped, the hysteresis magnetoresistive unit array 402 is located within the main current conductor 404, and the main current direction is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array 402. The main current conductor 404 and the reset current conductor 403 can be disposed below the wafer substrate 401 or above the wafer substrate 401.

[0157] It can be understood that Figure 13 only shows one layout of the main current conductor 404 and the reset current conductor 403, that is, the main current conductor 404 and the reset current conductor 403 are arranged below the wafer substrate 401, and the reset current conductor 403 is located above the wafer substrate 401 and below the hysteresis magnetoresistive unit array 402, but it does not mean that the main current conductor 404 and the reset current conductor 403 can only adopt this layout setting.

[0158] In addition, one or two soft magnetic shielding layers 405 are included. FIG13 shows a case where two soft magnetic shielding layers are included, namely, a first soft magnetic shielding layer 405(0) and a second soft magnetic shielding layer 405(1). The first soft magnetic shielding layer 405(0) and the second soft magnetic shielding layer 405(1) are respectively disposed at the top and bottom of the package structure of the magnetoresistive fuse chip 400. The purpose of providing the soft magnetic shielding layer is to prevent external interference magnetic fields.

[0159] Structure 5: Referring to FIG. 14 , a magnetoresistive fuse chip 500 of the fourth structure includes: a wafer substrate 501 , a hysteresis magnetoresistive unit located above the wafer substrate 501 , a reset current conductor 503 , and a main current conductor 504 .

[0160] It is understood that the number of the above-mentioned hysteresis magnetoresistive units is one or more. FIG14 only shows the case where multiple hysteresis magnetoresistive units are included. However, the case where the number of hysteresis magnetoresistive units is one can be obtained by transformation based on the scheme of units including multiple hysteresis resistors. The magnetoresistive fuse chip 500 shown in FIG14 includes two groups of hysteresis magnetoresistive unit arrays 502, including a hysteresis magnetoresistive unit array 502 (1) with a reset magnetic state of 1 and a hysteresis magnetoresistive unit array 502 (0) with a reset magnetic state of 0.

[0161] The main current conductor 504 is a lead frame, disposed below the bottom of the wafer substrate 501. The reset current conductor 503 includes a first reset sub-conductor 503(0) and a second reset sub-conductor 503(1) with opposite reset current directions, both of which are strip-shaped.

[0162] The reset current conductor 503 may be located below the wafer substrate 501 or above the wafer substrate 501. It is understood that FIG14 only illustrates one layout of the main current conductor 504 and the reset current conductor 503, namely, the reset current conductor 503 is located above the wafer substrate 501 and above the hysteresis magnetoresistive unit array 502, the hysteresis magnetoresistive unit array 502 is located on the surface of the main current conductor 504, and the main current direction is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array 502. However, this does not mean that the main current conductor 504 and the reset current conductor 503 can only adopt this layout.

[0163] In addition, one or two soft magnetic shielding layers 505 are included. Figure 14 shows a case where one soft magnetic shielding layer 505 is included. The soft magnetic shielding layer 505 can be disposed on the top of the package structure of the magnetoresistive fuse chip 500. The purpose of providing the soft magnetic shielding layer is to prevent external interference magnetic field.

[0164] The following is a detailed introduction to the two ways to set up the magnetic shielding layer in combination with the multi-chip packaging structure of the magnetoresistive fuse chip:

[0165] The first configuration method: Please refer to FIG15 , a single magnetoresistive fuse chip 600 in a multi-chip package structure includes: a control logic unit die 601 , a switch unit die 602 and a magnetic chip die 603 arranged on a lead frame.

[0166] The magnetic chip grain 603 includes: a reset current conductor 603(0), a hysteresis magnetoresistive unit 603(1), a main current conductor 603(2), and a first magnetic shielding layer 603(3) and / or a second magnetic shielding layer 603(4) located on the surface of the wafer substrate. The reset current conductor 603(0), the hysteresis magnetoresistive unit 603(1), and the main current conductor 603(2) form a multi-layer stacked structure, and the first magnetic shielding layer 603(3) and the second magnetic shielding layer 603(4) can be respectively arranged above or below the multi-layer stacked structure.

[0167] It is understandable that the magnetoresistive fuse chip 600 can be packaged into a chip using a packaging resin. For the sake of convenience, the wafer substrate, resin, lead frame, etc. are not shown in FIG. 15 .

[0168] It is understood that the magnetic shielding layer arrangement shown in FIG15 is only one arrangement of the magnetic shielding layer in the embodiment of the present application. The corresponding chip structures in FIG10 to FIG14 all adopt the magnetic shielding layer arrangement shown in FIG15. Another arrangement of the magnetic shielding layer will be described below in the description of Structure 6.

[0169] Second configuration: Please refer to FIG. 16 , a single magnetoresistive fuse chip 600 ′ in a multi-chip package structure includes: a control logic unit die 601 ′, a switch unit die 602 ′, and a magnetic chip die 603 ′ arranged on a lead frame.

[0170] The magnetic chip crystal grain 603 ′ includes: a reset current conductor 603 ′ ( 0 ), a hysteresis magnetoresistive unit 603 ′ ( 1 ) and a main current conductor 603 ′ ( 2 ) arranged on a wafer substrate.

[0171] The control logic unit die 601', switch unit die 602', and magnetic chip die 603' can be encapsulated into a chip using an encapsulated resin capsule, and then the first magnetic shielding layer 604'(0) and the second magnetic shielding layer 604'(1) are disposed on the upper and lower surfaces of the encapsulated resin. It is understood that for convenience, the wafer substrate, resin, and lead frame are not shown in FIG16 .

[0172] In addition, it can be understood that the control logic unit die 601 ′, the switch unit die 602 ′ and the magnetic chip die 603 ′ are connected to each other by wire bonding, which is equivalent to an effective die 61 , and the effective die is connected to the lead frame through the output input pad 62 .

[0173] It is understandable that the chip structures corresponding to Figures 17 to 20 in the following description all adopt the second magnetic shielding layer setting method mentioned above.

[0174] Structure Six: Please refer to FIG17 . In the sixth structure of the magnetoresistive fuse chip 700 , the output input pad 62 of the effective die 61 is connected to the lead frame 68 through the lead 63 and then encapsulated in the encapsulation resin 64 . The magnetic shielding layers 65 (0) and 65 (1) are respectively arranged on the upper surface and the lower surface of the encapsulation resin and are fixed to the encapsulation resin 64 through the first adhesive layer 66 and the second adhesive layer 67 .

[0175] Structure Seven: Please refer to Figure 18. In the seventh structure of the magnetoresistive fuse chip 800, only one magnetic shielding layer 65 is provided, and it is adhered to the upper surface of the encapsulation body 78 via an adhesive layer 66. This is because the effective die 61 adopts a ball array packaging structure. The effective die 61 is adhered to the lead frame 74 using epoxy resin or elastomer 75 material. The lead frame 74 includes conductive traces 76 connected to solder balls 77. The solder balls 77 are located on the bottom surface of the lead frame 74 and are arranged in an array. The solder balls 77 are used to electrically connect to the external circuit. The leads 73 are used to connect the output and input pads 62 of the effective die 61 and the conductive traces 76. The encapsulation body 78 encapsulates the effective die 61 on the lead frame 74, and the solder balls 77 are not covered by the encapsulation body 78 and are exposed on the bottom surface. In this case, the magnetic shielding layer 65 can only be provided on the upper surface of the encapsulation body 78 and adhered via the adhesive layer 66.

[0176] Structure Eight: Please refer to Figure 19. In the eighth structure of the magnetoresistive fuse chip 900, the output input pad 62 of the effective grain 61 is connected to the lead frame 68 through the lead 63, and then encapsulated in the encapsulation resin 81. The characteristic of the encapsulation resin 81 is that the upper surface and the lower surface are respectively provided with a first mounting pit 82 and a second mounting pit 83. The first magnetic shielding layer 85(0) and the second magnetic shielding layer 85(1) are respectively located in the mounting pits 82 and 83, and are respectively fixed on the encapsulation resin 64 by the adhesive layers 66 and 67. The mounting pits 82 and 83 have two functions. First, they can be used to position the magnetic shielding layer. Second, the first magnetic shielding layer 85(0) and the second magnetic shielding layer 85(1) have a certain thickness. After being placed in the first mounting pit 82 and the second mounting pit 83, the first magnetic shielding layer 85(0) and the second magnetic shielding layer 85(1) are flush with or lower than the surface of the encapsulation colloid 81, which has a protective effect.

[0177] Referring to FIG20(a), a first mounting pit 82 is provided on the top surface 811 of the encapsulation body 81. On the side wall 811(0) of the first mounting pit 82, which is approximately perpendicular to the ground, one or more overhanging tabs 812 are installed along the edge 811(1). As shown in FIG20(b), FIG20(b) is a cross-sectional view parallel to the edge 811(1), and it can be seen that the first magnetic shielding layer 85(0) can be placed in the first mounting pit 82. As shown in FIG20(c), FIG20(c) is a cross-sectional view perpendicular to the edge 811(1), and it can be seen that the two overhanging tabs 812 clamp the magnetic shielding layer in the first mounting pit 82. The function of the overhanging tongue 812 is that the first magnetic shielding layer 85 (0) can be fixed in the first installation pit 82 without the use of colloid. Moreover, when the first magnetic shielding layer 85 (0) is a thin strip, it can be installed in the first installation pit 82 by breaking through the limitation of the overhanging tongue 812 in the form of bending and deflection, and can be taken out from the installation pit at any time in the form of bending and deflection.

[0178] It can be understood that the mounting pit structure shown in FIG. 20 can be applied to chips with a double-layer shielding layer structure as shown in FIG. 17 and FIG. 19 , and can also be applied to chips with a single-layer shielding layer as shown in FIG. 18 .

[0179] The following is a detailed introduction to the modular structure of a magnetoresistive fuse:

[0180] Please refer to Figure 21. The modular magnetoresistive fuse 1000 includes: a PCB board 901, a hysteresis magnetoresistive unit array 902 located on the surface of the PCB board 901, a reset current conductor 903, a main current conductor 904, an ASIC chip 905 used as a control logic unit 9, a MOSFET chip 906 used as a switch unit 10, a first magnetic shielding layer 907(0) and a second magnetic shielding layer 907(1).

[0181] The reset current conductor 903 includes a first reset current subconductor 903(0) and a second reset current subconductor 903(1) having opposite current directions. The hysteresis magnetoresistive unit array 902 includes a hysteresis magnetoresistive unit 902(0) with a magnetic state of 0 and a hysteresis magnetoresistive unit 902(1) with a magnetic state of 1, which are respectively located above the first reset current subconductor 903(0) and the second reset current subconductor 903(1), and the reset current is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit. The main current conductor 904 is located on the lower surface of the PCB board 901, and the hysteresis magnetoresistive unit array 902 is set in the main current conductor 904 area, and the main current direction is perpendicular to the magnetic field sensitive direction of the hysteresis magnetoresistive unit array. The ASIC chip 905 and the MOSFET chip 906 are respectively arranged on the upper surface and the lower surface of the PCB board. The first magnetic shielding layer 907 and the second magnetic shielding layer 908 are respectively arranged on the uppermost surface and the lowermost surface of the module structure.

[0182] It can be understood that, in the above modular structure as shown in FIG. 21 , the positions of the various parts on the surface of the PCB board 901 can be adaptively set and are not limited to the layout shown in FIG. 21 .

[0183] Optionally, the magnetic shielding layer in the above solution may be a magnetic shielding layer made of a magnetic thin film material.

[0184] It should be noted that, unless there is any conflict, the features in the embodiments of this application can be combined with each other.

[0185] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A resettable magnetoresistive fuse, characterized in that, The magnetoresistive fuse is electrically connected to a power supply circuit or a device to be protected through a main input pad and a main output pad, and is electrically connected to a reset pulse circuit through a reset input pad and a reset output pad; The magnetoresistive fuse includes: One or more hysteretic magnetoresistive units, a main current conductor, a reset current conductor, a switching unit, and a control logic unit. Any hysteretic magnetoresistive unit has two magnetic states, magnetic state 0 and magnetic state 1; Wherein, the input end, output end, first intermediate end, and second intermediate end of the main current conductor are electrically connected to the main input pad, the main output pad, the input end of the switching unit, and the output end of the switching unit, respectively; When the power supply circuit or the device to be protected is overloaded, the main current in the main current conductor configures the magnetic state of the hysteretic magnetoresistive unit to the overloaded state, and the magnetoresistive fuse is disconnected; when the power supply circuit or the device to be protected is repaired, the reset pulse circuit is activated, and the reset current in the reset current conductor configures the magnetic state of the hysteretic magnetoresistive unit to the reset state, and the magnetoresistive fuse is reset; When the number N of the hysteretic magnetoresistive units is 1, both the main current and the reset current are in a non-critical DC state, the reset state is magnetic state 1 or magnetic state 0, and the corresponding overloaded state is magnetic state 0 or magnetic state 1; when the number N of the hysteretic magnetoresistive units is greater than 1, the reset state is a mixture of magnetic state 0 and magnetic state 1; The magnetic state is further configured by the control logic unit as a break signal or a conduction signal at the control end of the switching unit to activate the switching unit to break or conduct, thereby realizing the disconnection and reset of the magnetoresistive fuse.

2. The resettable magnetoresistive fuse according to claim 1, characterized in that, When the hysteretic magnetoresistive unit is in the overloaded state, the main magnetic field generated by the main current exceeds the coercive force Hc or -Hc of the hysteretic magnetoresistive unit; When the hysteretic magnetoresistive unit is in the reset state, the reset magnetic field generated by the reset current exceeds the coercive force Hc or -Hc of the hysteretic magnetoresistive unit.

3. The resettable magnetoresistive fuse according to claim 1, characterized in that, Both the main current and the reset current are in a non-critical state; When the number N of the hysteretic magnetoresistance units is an odd number other than 1, magnetic state 1 (N+1) / 2 0 (N-1) / 2 or magnetic state 0 (N+1) / 2 1 (N-1) / 2 is the reset state, and magnetic state 1 (N) or magnetic state 0 (N) is the overload state; When the number N of the hysteretic magnetoresistive units is an even number, magnetic state 1 (N / 2) 0 (N / 2) is the reset state, and magnetic state 1 (N) or magnetic state 0 (N) is the overload state.

4. The resettable magnetoresistive fuse according to claim 1, wherein The main current is in a critical state; When the number N of the hysteretic magnetoresistance units is an even number, magnetic state 1 (N / 2) 0 (N / 2) is the reset state. If pc+ is set as the critical forward transition probability from magnetic state 0 to magnetic state 1, and the state is the overload state when p > pc+, then magnetic state 1(N / 2*(1+pc+))0(N / 2*(1-pc+)) is the critical forward overload state; if pc- is set as the critical negative transition probability from magnetic state 1 to magnetic state 0, and the state is the overload state when p > pc-, then magnetic state 1(N / 2*(1-pc-))0(N / 2*(1+pc-)) is the critical negative overload state.

5. The resettable magnetoresistive fuse according to claim 1 or 3, characterized in that, One end of any hysteretic magnetoresistive unit is connected to a constant current source Ic, and the other end is grounded; the output voltage across the hysteretic magnetoresistive unit is input to the control logic unit as the output signal of the hysteretic magnetoresistive unit.

6. The resettable magnetoresistive fuse according to claim 3, characterized in that, When the number N of the hysteretic magnetoresistive units is an even number, the magnetic state 1 (N / 2) 0 (N / 2) is the reset state. Among them, N / 2 hysteretic magnetoresistive units with the magnetic state of 1 and N / 2 hysteretic magnetoresistive units with the magnetic state of 0 are respectively interconnected into a push arm and a pull arm of a two-port structure. The push arm and the pull arm are connected in series to form a push-pull half-bridge. One end of the power supply terminal of the push-pull half-bridge is grounded, the other end is connected to a constant voltage source Vc, and the middle terminal outputs a signal Vo. Vo / Vc is used as the output signal of the hysteretic magnetoresistive unit and input to the control logic unit.

7. The resettable magnetoresistive fuse according to claim 3, characterized in that, When the number N / 2 of the magnetoresistive elements is an even number, the magnetic state 1 (N / 4) 0 (N / 4) 1 (N / 4) 0 (N / 4) is the reset state, where N / 4 magnetoresistive elements with the magnetic state of 1 and N / 4 magnetoresistive elements with the magnetic state of 0 are respectively interconnected into a push arm and a pull arm of a two-port structure; the push arm and the pull arm are connected into a push-pull full bridge; one end of the power supply terminal of the push-pull full bridge is grounded, the other end is connected to a constant voltage source Vc, and the middle terminal outputs a signal Vo. Vo / Vc is used as the output signal of the magnetoresistive element and input to the control logic unit.

8. The resettable magnetoresistive fuse according to claim 4, wherein, When the number N of the hysteroresistive magnetoresistive units is an even number, magnetic state 1 (N / 2) 0 (N / 2) is the reset state, where N / 2 hysteroresistive magnetoresistive units with magnetic state 1 are connected in series to form arm 1 with a two-port structure, and the reset resistance of arm 1 is R1; N / 2 hysteroresistive magnetoresistive units with magnetic state 0 are connected in series to form arm 0 with a two-port structure, and the reset resistance of arm 0 is R0; arm 0 and arm 1 are connected in series to form arm 01, and the reset resistance of arm 01 is Rset; the ratio R / Rset of the total resistance R of arm 01 to Rset is input as the output signal of arm 01 to the control logic unit.

9. The resettable magnetoresistive fuse according to claim 8, wherein When R / Rset is between [(1 - pc - *(R1 - R0) / (R1 + R0), 1 + pc + *(R1 - R0) / (R1 + R0)], the magnetic state of the hysteretic magnetoresistive unit is configured by the control logic unit to the reset state; When R / Rset is between [2*R0 / (R1 + R0), 1 - pc - *(R1 - R0) / (R1 + R0)] or [1 + pc + *(R1 - R0) / (R1 + R0), 2*R1 / (R1 + R0)], the hysteretic magnetoresistive unit is configured by the control logic unit to the overloaded state.

10. The resettable magnetoresistive fuse according to claim 1, characterized in that, The control logic unit, the reset current conductor, and the hysteretic magnetoresistive unit are powered by independent discrete power supplies or by a battery, and the discrete power supply and the battery are switchable.

11. The resettable magnetoresistive fuse according to claim 1, wherein The magnetoresistive fuse further includes a digital output signal for indicating whether the fuse is open; the digital output signal configures the reset state and the overload state of the control logic unit as 1 and 0, or as 0 and 1.

12. The resettable magnetoresistive fuse according to claim 1, characterized in that, The control logic unit includes: A memory for recording the magnetic state of the hysteretic magnetoresistive unit when the magnetoresistive fuse is open and being read by the control logic unit when the magnetoresistive fuse works again, so that the control logic unit configures the on and off states of the control terminal of the switching unit according to the magnetic state of the hysteretic magnetoresistive unit.

13. The resettable magnetoresistive fuse according to claim 1, characterized in that, The switching unit is: a triode, an FET, a MOS transistor or a mechatronic device; the control terminal of the switching unit is in a normally off state.

14. The resettable magnetoresistive fuse according to claim 1, wherein, The hysteretic magnetoresistive unit is an anisotropic magnetoresistive effect (AMR) element, a giant magnetoresistive effect (GMR) element or a tunneling magnetoresistive effect (TMR) element; the magnetization directions of the pinned layers of the hysteretic magnetoresistive units are the same; the magnetization direction of the free layer of the hysteretic magnetoresistive unit is parallel to the magnetization direction of the pinned layer and opposite to the direction of the magnetization direction of the pinned layer; the directions of the main magnetic field generated by the main current and the reset magnetic field generated by the reset current are both parallel to the magnetization direction of the pinned layer.

15. The resettable magnetoresistive fuse according to claim 1, characterized in that, The magnetoresistive fuse is a packaged multi-chip structure, and this structure includes: a magnetic chip die, the control logic unit and the switching unit; the magnetic chip die includes: a wafer substrate, the hysteretic magnetoresistive unit, the main current conductor and the reset current conductor; Wherein, the hysteretic magnetoresistive unit is located above the wafer substrate; the main current conductor is located above, below or on the lead frame of the wafer substrate; the reset current conductor is located above, below or on the lead frame of the wafer substrate; The control logic unit is an ASIC die; the switching unit is a MOS transistor die; the magnetic chip die, the ASIC die and the MOS transistor die are respectively mounted on the lead frame and encapsulated in the encapsulation resin.

16. The resettable magnetoresistive fuse according to claim 1, characterized in that, The magnetoresistive fuse is a packaged module structure, and this structure includes: a PCB, the hysteretic magnetoresistive unit, the main current conductor, the reset current conductor, the control logic unit and the switching unit provided on the PCB; the hysteretic magnetoresistive unit, the switching unit and the control logic unit are respectively a hysteretic magnetoresistive unit chip, a switching unit chip and a control logic unit chip.

17. The resettable magnetoresistive fuse according to claim 15 or 16, characterized in that, It further includes a magnetic shielding layer; the magnetic shielding layer is located above and / or below the packaging structure.

18. The resettable magnetoresistive fuse according to claim 17, wherein The magnetic shielding layer is a magnetic shielding layer made of a magnetic thin film material, and the magnetic shielding layer is directly deposited above or below the multi-layer stacked structure composed of the wafer substrate, the hysteretic magnetoresistive unit, the main current conductor and the reset current conductor.

19. The resettable magnetoresistive fuse according to claim 17, wherein, The magnetic shielding layer is located on the upper surface or the lower surface of the encapsulation resin.

20. The resettable magnetoresistive fuse according to claim 19, wherein An installation pit is provided on the upper surface or the lower surface of the resin; the magnetic shielding layer is disposed in the installation pit.

21. The resettable magnetoresistive fuse according to claim 20, characterized in that, A suspension tongue is provided on the side wall of the installation pit; the magnetic shielding layer is in a thin strip shape, and the magnetic shielding layer is snapped into the installation pit through the suspension tongue.

22. The resettable magnetoresistive fuse according to claim 15, wherein, The main current conductor includes a main current strip; the reset current conductor includes: a first reset current strip and a second reset current strip; the first reset current strip and the second reset current strip have opposite current directions; The magnetoresistive unit includes: an array of magnetoresistive units with a reset magnetic state of 1 respectively located on the first reset current strip, the second reset current strip, and the main current strip, and an array of magnetoresistive units with a reset magnetic state of 0 located on the second reset current strip and the main current strip; The current directions of the first reset current strip, the second reset current strip, and the main current strip are all perpendicular to the magnetic field sensitive direction of the magnetoresistive unit.

23. The resettable magnetoresistive fuse according to claim 15, wherein, The main current conductor includes a main current strip; the reset current conductor is a meandering current conductor, including: a third reset current strip and a fourth reset current strip arranged alternately and parallel to each other; the third reset current strip and the fourth reset current strip have opposite current directions; The magnetoresistive unit includes: an array of magnetoresistive units with a reset magnetic state of 1 located on the third reset current strip and the main current strip, and an array of magnetoresistive units with a reset magnetic state of 0 located on the fourth reset current strip and the main current strip; The current directions of the main current strip, the third reset current strip, and the fourth reset current strip are all perpendicular to the magnetic field sensitive direction of the magnetoresistive unit.

24. The resettable magnetoresistive fuse according to claim 23, wherein The main current strip includes: a plurality of main current sub-strips connected in parallel and arranged in parallel; the array of magnetoresistive units with a reset magnetic state of 1 and the array of magnetoresistive units with a reset magnetic state of 0 are both located on the main current sub-strip.

25. The resettable magnetoresistive fuse according to claim 15, wherein The reset current conductor is a spiral current conductor, including: a first reset current sub-region and a second reset current sub-region with opposite current directions; both the first reset current sub-region and the second reset current sub-region include a plurality of straight strips arranged parallel and equidistantly; the array of magnetoresistive units with a reset magnetic state of 1 and the array of magnetoresistive units with a reset magnetic state of 0 are respectively located in the first reset current sub-region and the second reset current sub-region.

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