Multilevel inverter

Abstract

The present invention addresses the problem of suppressing reductions in the voltage of a bootstrap circuit and fluctuations in the potential at an intermediate potential point. A control device (6) controls a plurality of inverter circuits (1). The control device (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a power supply unit (9), and a control unit (60). The control unit (60) has a first control mode for raising the potential at an intermediate potential point (M1), a second control mode for reducing the potential at the intermediate potential point (M1), and a third control mode for maintaining the potential at the intermediate potential point (M1).

Description

Multilevel Inverter

[0001] The present disclosure relates to a multilevel inverter, and more particularly to a multilevel inverter with a bootstrap circuit.

[0002] Patent Document 1 discloses a three-phase voltage-type PWM inverter circuit using a bootstrap circuit.

[0003] Furthermore, Patent Document 1 discloses an inverter control method in which a predetermined switching pattern is applied to each phase of a three-phase inverter to obtain a desired voltage vector and supply it to a load, and a control voltage is supplied by a bootstrap circuit of each phase. In this inverter control method, switching control is performed to replace a voltage vector selected during a period in which the bootstrap circuit of any phase maintains a discharging state and does not affect the output voltage, with a voltage vector that can be charged by the bootstrap circuit at predetermined intervals.

[0004] In a multilevel inverter, the voltage of the bootstrap circuit may drop, but the inverter control method disclosed in Patent Document 1 is a technique related to a two-level inverter and cannot be applied to a multilevel inverter.

[0005] Furthermore, in a multilevel inverter, the potential at the intermediate potential point may fluctuate.

[0006] Japanese Patent Application Publication No. 5-292755

[0007] An object of the present disclosure is to provide a multilevel inverter capable of suppressing a voltage drop in a bootstrap circuit and fluctuations in the potential at the midpoint.

[0008] A multilevel inverter according to one aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits, and a control device. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The control device controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes a first switching element, a second switching element, a third switching element, and a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode. The first diode, the second diode, the third diode, and the fourth diode are connected in anti-parallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively. In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series from the positive electrode side to the negative electrode side, in that order. In each of the plurality of inverter circuits, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and an output point. The output point is a connection point between the first switching element and the second switching element. The control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply unit, and a control unit. The plurality of first gate drivers drive the first switching element of each of the plurality of inverter circuits. The plurality of second gate drivers drive the second switching element of each of the plurality of inverter circuits. The plurality of third gate drivers drive the third switching element of each of the plurality of inverter circuits. The plurality of fourth gate drivers drive the fourth switching element of each of the plurality of inverter circuits. The plurality of bootstrap circuits are connected to the plurality of first gate drivers. The power supply unit supplies voltages to the plurality of second gate drivers and the plurality of third gate drivers.The control unit has a first control mode in which the potential of the intermediate potential point is increased, a second control mode in which the potential of the intermediate potential point is decreased, and a third control mode in which the potential of the intermediate potential point is maintained. The control unit selects a plurality of voltage vectors adjacent to a command voltage vector from a group of voltage vectors determined by a combination of potential levels of the plurality of output points. The group of voltage vectors includes a zero vector of a combination in which the potential levels of the plurality of output points all become the negative potential. In the first control mode, the control unit replaces a first first voltage vector, which is one of two first voltage vectors of a reference magnitude that is closest to the command voltage vector and whose combination of potential levels of the plurality of output points includes the negative potential level, with the zero vector and a second voltage vector that has the same orientation as the first first voltage vector and is twice as large as the first first voltage vector. In the first control mode, the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so as to make a composite vector of one or more voltage vectors other than the two first voltage vectors among the plurality of voltage vectors, a second first voltage vector among the two first voltage vectors that includes the positive potential level among a combination of potential levels of the plurality of output points, the zero vector, and the second voltage vector coincide with the command voltage vector. In the second control mode, the control unit replaces the second first voltage vector with the zero vector and the second voltage vector. In the second control mode, the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within the control period so as to make a composite vector of the one or more voltage vectors, the first first voltage vector, the zero vector, and the second voltage vector coincide with the command voltage vector.In the third control mode, the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within the control period so as to make a composite vector of the one or more voltage vectors, the first first voltage vector, the second first voltage vector, the zero vector, and the second voltage vector coincide with the command voltage vector.

[0009] FIG. 1 is a circuit diagram of a system including a multilevel inverter according to a first embodiment. FIG. 2 is an explanatory diagram of a current path when an inverter circuit in the multilevel inverter is in a first switching state. FIG. 3 is an explanatory diagram of a discharge path when the inverter circuit in the multilevel inverter is in the first switching state. FIG. 4 is an explanatory diagram of a current path when the inverter circuit in the multilevel inverter is in a second switching state. FIG. 5 is an explanatory diagram of a discharge path when the inverter circuit in the multilevel inverter is in the second switching state. FIG. 6 is an explanatory diagram of a current path when the inverter circuit in the multilevel inverter is in a third switching state. FIG. 7 is an explanatory diagram of a discharge path and a charge path when the inverter circuit in the multilevel inverter is in the third switching state. FIG. 8 is an explanatory diagram of a current path when the inverter circuit in the multilevel inverter is in the second switching state. FIG. 9 is an explanatory diagram of a voltage command value for each phase in the multilevel inverter. FIG. 10 is an explanatory diagram of a group of voltage vectors related to the multilevel inverter. FIG. 11 is a more detailed explanatory diagram of a group of voltage vectors related to the multilevel inverter. FIG. 12 is a vector diagram illustrating the operation of a control unit in the multilevel inverter according to the embodiment. FIG. 13A is an explanatory diagram of a command voltage vector and a first voltage vector for the multilevel inverter according to the embodiment. FIG. 13B is an explanatory diagram of a command voltage vector, a zero vector, and a second voltage vector for the multilevel inverter according to the embodiment. FIG. 14 is a time chart of the switching states of each phase of a multilevel inverter according to a comparative example. FIG. 15 is a time chart of the on / off states of first to fourth switching elements of the multilevel inverter according to the embodiment. FIG. 16 is a characteristic diagram of the load current of each phase and the potential of the intermediate potential point when a control unit controls an inverter circuit of each phase in a multilevel inverter according to a comparative example. FIG. 17A is an explanatory diagram of a group of voltage vectors for the multilevel inverter according to the first embodiment. FIG. 17B is an equivalent circuit diagram when a control unit controls the multilevel inverter according to the embodiment using one of the three zero vectors shown in FIG. 17A.17C is an equivalent circuit diagram of the multilevel inverter of the same embodiment when the control unit controls with another zero vector. FIG. 17D is an equivalent circuit diagram of the multilevel inverter of the same embodiment when the control unit controls with the remaining zero vector. FIG. 18A is an explanatory diagram of a group of voltage vectors related to the multilevel inverter of the same embodiment. FIG. 18B is an equivalent circuit diagram of the multilevel inverter of the same embodiment when the control unit controls with one of the 12 voltage vectors shown in FIG. 18A. FIG. 18C is an equivalent circuit diagram of the multilevel inverter of the same embodiment when the control unit controls with one of the 12 voltage vectors shown in FIG. 18A. FIG. 19A is an explanatory diagram of a group of voltage vectors related to the multilevel inverter of the same embodiment. FIG. 19B is an equivalent circuit diagram of the multilevel inverter of the same embodiment when the control unit controls with one of the 12 voltage vectors shown in FIG. 19A. FIG. 19C is an equivalent circuit diagram of the multilevel inverter of the same embodiment when the control unit controls with one of the 12 voltage vectors shown in FIG. 19A. FIG. 20 is a time chart of the switching states of each phase when the control unit controls the inverter circuits of each phase in the first control mode in the multilevel inverter according to the first embodiment. FIG. 21 is a time chart of the on / off states of the first to fourth switching elements when the control unit controls the inverter circuits of each phase in the first control mode in the multilevel inverter according to the first embodiment. FIG. 22 is a characteristic diagram of the load current and the potential at the intermediate potential point of each phase when the control unit controls the inverter circuits of each phase in the first control mode in the multilevel inverter according to the first embodiment. FIG. 23 is a time chart of the switching states of each phase when the control unit controls the inverter circuits of each phase in the second control mode in the multilevel inverter according to the first embodiment. FIG. 24 is a time chart of the on / off states of the first to fourth switching elements when the control unit controls the inverter circuits of each phase in the second control mode in the multilevel inverter according to the first embodiment. FIG. 25 is a characteristic diagram of the load current and the potential at the intermediate potential point of each phase when the control unit controls the inverter circuits of each phase in the multilevel inverter according to the second control mode.FIG. 26 is a time chart of the switching state of each phase when the control unit controls the inverter circuit of each phase in the multilevel inverter in the third control mode. FIG. 27 is a time chart of the on / off states of the first to fourth switching elements when the control unit controls the inverter circuit of each phase in the multilevel inverter in the third control mode. FIG. 28 is a characteristic diagram of the load current of each phase and the potential of the intermediate potential point when the control unit controls the inverter circuit of each phase in the multilevel inverter in the third control mode. FIG. 29 is a circuit diagram of a system including a multilevel inverter according to a third embodiment. FIG. 30 is a circuit diagram of a system including a multilevel inverter according to a fourth embodiment. FIG. 31 is a circuit diagram of a system including a multilevel inverter according to a fifth embodiment. FIG. 32 is a circuit diagram of a system including a multilevel inverter according to a sixth embodiment.

[0010] First Embodiment A multilevel inverter 100 according to a first embodiment will be described below with reference to FIGS. 1 to 13B and 17A to 28. FIG.

[0011] (1) Overview As shown in FIG. 1 , a multilevel inverter 100 includes a DC power supply unit 3, multiple (e.g., three) inverter circuits 1, and a control device 6. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. Ideally, the "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. In the first embodiment, assuming that the voltage across the DC power supply unit 3 is Vdc (e.g., 400 V), the potential of the positive electrode P1 is approximately Vdc, the potential of the negative electrode N1 is approximately 0 V, and the potential of the intermediate potential point M1 is approximately Vdc / 2. The multiple inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6 controls the multiple inverter circuits 1.

[0012] The multilevel inverter 100 is a T-type three-level three-phase inverter. In the multilevel inverter 100, each of a plurality of inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the plurality of output terminals (AC terminals) 41. The AC load RA1 is, for example, a three-phase servo motor. In the multilevel inverter 100, one of the plurality of inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage.

[0013] Each of the inverter circuits 1 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4, as well as a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 are connected in anti-parallel to the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4, respectively. In each of the inverter circuits 1, the first switching element Q1 and the second switching element Q2 are connected in series from the positive electrode P1 side to the negative electrode N1 side in this order. That is, as shown in FIGS. 1 and 2 , a series circuit (first circuit 11) of the first switching element Q1 and the second switching element Q2 is connected between the positive electrode P1 and the negative electrode N1. In each of the multiple inverter circuits 1, a series circuit (second circuit 12) of a third switching element Q3 and a fourth switching element Q4 is connected between an intermediate potential point M1 and an output point 13. The output point 13 is a connection point between the first switching element Q1 and the second switching element Q2. The second circuit 12 has a bidirectional switch including the third switching element Q3, the fourth switching element Q4, a third diode D3, and a fourth diode D4.

[0014] The control device 6 has a plurality of (e.g., three) first gate drivers 61, a plurality of (e.g., three) second gate drivers 62, a plurality of (e.g., three) third gate drivers 63, and a plurality of (e.g., three) fourth gate drivers 64. The control device 6 also has a plurality of (e.g., three) bootstrap circuits 71 (hereinafter also referred to as first bootstrap circuits 71), a plurality of (e.g., three) second bootstrap circuits 72, a power supply unit 9, and a control unit 60.

[0015] The plurality of first gate drivers 61 drive the first switching elements Q1 of the plurality of inverter circuits 1. The plurality of second gate drivers 62 drive the second switching elements Q2 of the plurality of inverter circuits 1. The plurality of third gate drivers 63 drive the third switching elements Q3 of the plurality of inverter circuits 1. The plurality of fourth gate drivers 64 drive the fourth switching elements Q4 of the plurality of inverter circuits 1.

[0016] The plurality of first bootstrap circuits 71 correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first bootstrap circuits 71 supplies a voltage to the corresponding first gate driver 61. The plurality of second bootstrap circuits 72 correspond to the plurality of third gate drivers 63 and the plurality of fourth gate drivers 64. Each of the plurality of second bootstrap circuits 72 supplies a voltage to the corresponding third gate driver 63 and the corresponding fourth gate driver 64. The power supply unit 9 supplies a voltage to the plurality of second gate drivers 62.

[0017] The control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 .

[0018] (2) Details of the Multilevel Inverter (Power Conversion Apparatus) As shown in FIG. 1 , the DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. In the DC power supply unit 3, a first end of the first capacitor C1 is connected to a first DC terminal 31, a second end of the first capacitor C1 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to a second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1. The DC power supply unit 3 further includes a first DC terminal 31 connected to a positive electrode P1 and a second DC terminal 32 connected to a negative electrode N1. A DC voltage source E1, for example, is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. The phrase "the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not necessarily mean that the capacitance of the second capacitor C2 exactly matches the capacitance of the first capacitor C1, but may mean that the capacitance of the second capacitor C2 is within a range of 95% to 105% of the capacitance of the first capacitor C1.

[0019] For ease of explanation, the output terminal 41 included in inverter circuit 1U among the multiple output terminals 41 will be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V will be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W will be referred to as output terminal 41W. Furthermore, in the following explanation, the polarity of load currents iU, iV, and iW flowing through the U phase, V phase, and W phase of AC load RA1, respectively, will be described as positive when flowing in the direction of the arrow in Fig. 1, and as negative when flowing in the direction opposite to the direction of the arrow in Fig. 1.

[0020] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each inverter circuit 1 have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each inverter circuit 1 are, for example, MOSFETs. Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each inverter circuit 1 are, for example, a normally-off n-channel MOSFET. The MOSFETs are, for example, Si-based MOSFETs or SiC-based MOSFETs.

[0021] A control terminal of the first switching element Q1 of each inverter circuit 1 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each inverter circuit 1 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each inverter circuit 1 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each inverter circuit 1 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0022] In each inverter circuit 1, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of a DC power supply 3, a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2, and a second main terminal of the second switching element Q2 is connected to a negative electrode N1 of the DC power supply 3.

[0023] In each inverter circuit 1, the first main terminal of the third switching element Q3 is connected to the intermediate potential point M1, the second main terminal of the third switching element Q3 is connected to the second main terminal of the fourth switching element Q4, and the first main terminal of the fourth switching element Q4 is connected to the output point 13. Therefore, the bidirectional switch of the second circuit 12 (see FIG. 2 ) is a common-source bidirectional switch in which the second main terminal (source terminal) of the third switching element Q3 and the second main terminal (source terminal) of the fourth switching element Q4 are connected. The “intermediate potential point M1” is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.

[0024] In the inverter circuit 1U, the output point 13 (the connection point between the first switching element Q1 and the second switching element Q2) is connected to the output terminal 41U. In the inverter circuit 1V, the output point 13 (the connection point between the first switching element Q1 and the second switching element Q2) is connected to the output terminal 41V. In the inverter circuit 1W, the output point 13 (the connection point between the first switching element Q1 and the second switching element Q2) is connected to the output terminal 41W. For example, a U-phase load RA1u of the AC load RA1 (see FIG. 17B) is connected to the output point 13 of the inverter circuit 1U via the output terminal 41U. In addition, for example, a V-phase load RA1v of the AC load RA1 (see FIG. 17B) is connected to the output point 13 of the inverter circuit 1V via the output terminal 41V. Furthermore, for example, a W-phase load RA1w (see FIG. 17B) of the AC load RA1 is connected to the output point 13 of the inverter circuit 1W via an output terminal 41W.

[0025] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element Q1. In each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (source terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (drain terminal) of the second switching element Q2. In each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (source terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (drain terminal) of the third switching element Q3. In each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (source terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (drain terminal) of the fourth switching element Q4.

[0026] In each inverter circuit 1, the first diode D1 may be substituted with a parasitic diode of the MOSFET that constitutes the first switching element Q1. Also, in each inverter circuit 1, the second diode D2 may be substituted with a parasitic diode of the MOSFET that constitutes the second switching element Q2. Also, in each inverter circuit 1, the third diode D3 may be substituted with a parasitic diode of the MOSFET that constitutes the third switching element Q3. Also, in each inverter circuit 1, the fourth diode D4 may be substituted with a parasitic diode of the MOSFET that constitutes the fourth switching element Q4.

[0027] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs a plurality of first control signals S1 (see FIG. 2 ) that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0028] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding second switching element Q2. Each of the second gate drivers 62 drives a corresponding second switching element Q2. The second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs second control signals S2 (see FIG. 2 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0029] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs a plurality of third control signals S3 (see FIG. 2 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0030] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 drives the corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 is connected to the control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 2 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0031] The multiple first bootstrap circuits 71 correspond one-to-one to the multiple first gate drivers 61. Each of the multiple first bootstrap circuits 71 supplies a voltage to the corresponding first gate driver 61. As shown in FIGS. 1 and 3 , each of the multiple first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also referred to as a boost capacitor C17). In each first bootstrap circuit 71, the anode of the diode D17 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D17 is connected to a first end of the capacitor C17 via the resistor R17. The first end of the capacitor C17 is connected to a high-potential power supply terminal 61H (see FIG. 3 ) of the first gate driver 61, and the second end of the capacitor C17 is connected to a low-potential power supply terminal 61L (see FIG. 3 ) of the first gate driver 61. The first bootstrap circuit 71 supplies a voltage required to turn on the first switching element Q1 in the first gate driver 61 to the first gate driver 61. Each of the multiple first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel to the capacitor C17.

[0032] The second bootstrap circuits 72 correspond to the third gate drivers 63 and the fourth gate drivers 64. Each of the second bootstrap circuits 72 supplies a voltage to the corresponding third gate driver 63 and the corresponding fourth gate driver 64. Each of the second bootstrap circuits 72 includes a diode D27, a resistor R27, and a capacitor C27 (also referred to as a boost capacitor C27). In each second bootstrap circuit 72, the anode of the diode D27 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D27 is connected to a first end of the capacitor C27 via the resistor R27. A first end of the capacitor C27 is connected to the high-potential power supply terminal 63H (see FIG. 3 ) of the third gate driver 63 and the high-potential power supply terminal 64H (see FIG. 3 ) of the fourth gate driver 64, and a second end of the capacitor C27 is connected to the low-potential power supply terminal 63L (see FIG. 3 ) of the third gate driver 63 and the low-potential power supply terminal 64L (see FIG. 3 ) of the fourth gate driver 64. Each of the multiple second bootstrap circuits 72 supplies a voltage required to turn on the third switching element Q3 in the corresponding third gate driver 63 to the third gate driver 63, and supplies a voltage required to turn on the fourth switching element Q4 in the corresponding fourth gate driver 64 to the fourth gate driver 64. Each of the multiple second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel to the capacitor C27.

[0033] The power supply unit 9 supplies voltage to the multiple (three) first bootstrap circuits 71, the multiple (three) second bootstrap circuits 72, and the multiple (three) second gate drivers 62. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. A positive terminal of the power supply unit 9 is connected to the high-potential power supply terminal 62H (see FIG. 3) of each of the multiple second gate drivers 62, and a negative terminal of the power supply unit 9 is connected to the low-potential power supply terminal 62L (see FIG. 3) of each of the multiple second gate drivers 62.

[0034] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0035] The control unit 60 outputs a plurality of (three) first control signals S1 (see FIG. 2 ) for controlling a plurality of (three) first switching elements Q1, a plurality of (three) second control signals S2 (see FIG. 2 ) for controlling a plurality of (three) second switching elements Q2, a plurality of (three) third control signals S3 (see FIG. 2 ) for controlling a plurality of third switching elements Q3, and a plurality of (three) fourth control signals S4 (see FIG. 2 ) for controlling a plurality of (three) fourth switching elements Q4. Note that FIG. 2 illustrates only one of the three inverter circuits 1, and does not illustrate the remaining two inverter circuits 1. Also, FIG. 2 does not illustrate a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of first bootstrap circuits 71, a plurality of second bootstrap circuits 72, and the power supply unit 9. 3 illustrates only one of the three inverter circuits 1, and omits the illustration of the remaining two inverter circuits 1. Also, in FIG. 3, the illustration of the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, and the two second bootstrap circuits 72 is omitted.

[0036] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the inverter circuit 1U, a first control signal S1V that controls the first switching element Q1 of the inverter circuit 1V, and a first control signal S1W that controls the first switching element Q1 of the inverter circuit 1W.

[0037] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the inverter circuit 1U, a second control signal S2V that controls the second switching element Q2 of the inverter circuit 1V, and a second control signal S2W that controls the second switching element Q2 of the inverter circuit 1W.

[0038] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the inverter circuit 1U, a third control signal S3V that controls the third switching element Q3 of the inverter circuit 1V, and a third control signal S3W that controls the third switching element Q3 of the inverter circuit 1W.

[0039] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the inverter circuit 1U, a fourth control signal S4V that controls the fourth switching element Q4 of the inverter circuit 1V, and a fourth control signal S4W that controls the fourth switching element Q4 of the inverter circuit 1W.

[0040] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) higher than the first potential level. The first potential level is, for example, 0 V, and the second potential level is a potential level higher than the gate threshold voltage of the MOSFET. That is, in each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off a switching element corresponding to that control signal, and the second potential level is a potential level for turning on a switching element corresponding to that control signal.

[0041] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0042] In the multilevel inverter 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100, the switching state of each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state differ from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Note that, with regard to the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with one another.

[0043] The first switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the ON state and both the second switching element Q2 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the output point 13 becomes the potential level (e.g., Vdc) of the positive electrode P1 of the DC power supply unit 3.

[0044] The second switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the output point 13 becomes the potential level of the intermediate potential point M1 (e.g., Vdc / 2).

[0045] The third switching state is a combination in which both the first switching element Q1 and the third switching element Q3 are in the OFF state and both the second switching element Q2 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the output point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., 0).

[0046] When the inverter circuit 1 is in the first switching state, current flows through the path from the positive electrode P1 of the DC power supply unit 3 to the first switching element Q1, the output point 13, and the output terminal 41, as shown by the thick arrow in FIG. 2, and the voltage value of the output voltage to the AC load RA1 (see FIG. 1) becomes approximately Vdc.

[0047] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C17 of the first bootstrap circuit 71, and instead the capacitor C17 of the first bootstrap circuit 71 supplies to the first gate driver 61 a voltage necessary for the first gate driver 61 to turn on the first switching element Q1. Therefore, as shown in FIG. 3 , the charge in the capacitor C17 of the first bootstrap circuit 71 is discharged along a discharge path Ru1 that connects the capacitor C17 to the high-potential power supply terminal 61H of the first gate driver 61, the low-potential power supply terminal 61L of the first gate driver 61, and the capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across the capacitor C17 decreases over time.

[0048] Furthermore, when the inverter circuit 1 is in the first switching state, the power supply unit 9 does not charge the capacitor C27 of the second bootstrap circuit 72, and instead supplies the voltage required for the third gate driver 63 to turn on the third switching element Q3 from the capacitor C27 of the second bootstrap circuit 72 to the third gate driver 63. Therefore, as shown in FIG. 3 , the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru3 that connects the capacitor C27 to the high-potential power supply terminal 63H of the third gate driver 63, the low-potential power supply terminal 63L of the third gate driver 63, and the capacitor C27. As a result, in the second bootstrap circuit 72, the voltage across the capacitor C27 decreases over time.

[0049] Furthermore, when the inverter circuit 1 is in the second switching state (when it changes from the first switching state to the second switching state), for example, as shown by the thick arrows in Fig. 4, a current flows through a path of the intermediate potential point M1 of the DC power supply unit 3, the third switching element Q3, the fourth switching element Q4, the output point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes approximately Vdc / 2. More specifically, when the inverter circuits 1U, 1V, and 1W are in the second switching state, the third switching state, and the third switching state, respectively, a current flows through a path of the intermediate potential point M1 of the DC power supply unit 3, the third switching element Q3 of the inverter circuit 1U, the fourth switching element Q4 of the inverter circuit 1U, the output point 13, and the output terminal 41U.

[0050] Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required for turning on the third switching element Q3 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the third gate driver 63 by the third gate driver 63. Therefore, the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged along a discharge path Ru3 that connects the capacitor C27 to the high-potential power supply terminal 63H of the third gate driver 63, the low-potential power supply terminal 63L of the third gate driver 63, and the capacitor C27, as shown in FIG. 5 . Furthermore, when the inverter circuit 1 is in the second switching state, a voltage required for turning on the fourth switching element Q4 is supplied from the capacitor C27 of the second bootstrap circuit 72 to the fourth gate driver 64 by the fourth gate driver 64. Therefore, the charge in the capacitor C27 of the second bootstrap circuit 72 is discharged through a discharge path Ru4 from the capacitor C27 to the high potential side power supply terminal 64H of the fourth gate driver 64 to the low potential side power supply terminal 64L of the fourth gate driver 64 and back to the capacitor C27.

[0051] Furthermore, when the inverter circuit 1 is in the third switching state, as shown by the bold arrow in Fig. 6, a current flows through the path from the output terminal 41 to the output point 13 to the second switching element Q2 to the negative pole N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load RA1 becomes approximately 0. Furthermore, when the inverter circuit 1 is in the third switching state, the power supply unit 9 charges the capacitor C17 of the first bootstrap circuit 71, so that the voltage of the capacitor C17 increases over time until the capacitor C17 becomes fully charged. As shown in Fig. 7, the charging path Ru91 along which the power supply unit 9 charges the capacitor C17 is the path from the positive terminal of the power supply unit 9 to the diode D17 to the resistor R17 to the capacitor C17 to the output point 13 to the second switching element Q2 to the negative terminal of the power supply unit 9.

[0052] Furthermore, when the inverter circuit 1 is in the third switching state, the capacitor C27 of the second bootstrap circuit 72 is charged by the power supply unit 9. A charging path Ru92 along which the capacitor C27 is charged by the power supply unit 9 is a path from the positive terminal of the power supply unit 9 to the diode D27, resistor R27, capacitor C27, fourth switching element Q4, output point 13, second switching element Q2, and negative terminal of the power supply unit 9.

[0053] Furthermore, when the inverter circuit 1 is in the second switching state (when it changes from the third switching state to the second switching state), for example, as shown by the thick arrows in Fig. 8, a current flows through the path of the output terminal 41-output point 13-fourth switching element Q4-third switching element Q3-midpoint potential point M1, and the voltage value of the output voltage to the AC load RA1 becomes approximately Vdc / 2. More specifically, when the inverter circuits 1U, 1V, and 1W are in the second switching state, the second switching state, and the first switching state, respectively, a current flows through the path of the output terminal 41 of the inverter circuit 1U-output point 13-fourth switching element Q4-third switching element Q3-midpoint potential point M1, and the voltage value of the output voltage to the AC load RA1 becomes approximately Vdc / 2.

[0054] When the inverter circuit 1 is in the second switching state, the charge in the capacitor C27 is discharged through the discharge paths Ru3 and Ru4 shown in FIG.

[0055] The control unit 60 generates, for example, first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U, first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W based on voltage commands Vu, Vv, and Vw (see FIG. 9) relating to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.

[0056] As shown in FIG. 9 , the voltage commands Vu, Vv, and Vw are sinusoidal signals, each having a phase difference of 120°, and their respective values ​​(voltage command values) change over time. The voltage commands Vu, Vv, and Vw have the same cycle length. The control unit 60 (see FIG. 1 ) may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detection unit 8 (see FIG. 1 ) that detects the state of the AC load RA1 (see FIG. 1 ). If the AC load RA1 is a three-phase servo motor, the information output from the detection unit 8 may include, for example, at least one of the following: information on the detection results of multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1; and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0057] 1 (for example, the U-phase inverter circuit 1U). The operations of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W are similar to those of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.

[0058] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control.

[0059] The voltage vector control by the control unit 60 will be described in more detail below.

[0060] The control unit 60 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of the potential levels of the output points 13 of the first switching elements Q1 and second switching elements Q2 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the inverter circuit 1U corresponding to the U phase, the switching state of the inverter circuit 1V corresponding to the V phase, and the switching state of the inverter circuit 1W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 3. ３ = 27 pieces.

[0061] As shown in FIG. 10, the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. The group of voltage vectors also includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of (2 / 3) １／２ The group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The magnitude of each of the voltage vectors is (2 / 3) １／２ The group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２ - Includes six voltage vectors V13, V14, V15, V16, V17, and V18 that are Vdc and have different directions. In Figure 10, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees. Note that Figure 10 is a vector diagram illustrating a group of voltage vectors on an orthogonal α-β coordinate system.

[0062] A group of voltage vectors can be expressed as shown in FIG. 11 by representing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating the U phase, V phase, and W phase in that order.

[0063] As shown in FIG. 11 , the three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1U is "P," the switching state of the V-phase inverter circuit 1V is "P," and the switching state of the W-phase inverter circuit 1W is "P." For example, a voltage vector with a "p" appended, such as V10p, includes "P" but does not include "N." This also applies hereinafter. A voltage vector with a "n" appended, such as V10n, includes "N" but does not include "P." This also applies hereinafter. A voltage vector with a "o" appended, such as V10o, includes "0" but does not include "P" or "N." When the switching state of the inverter circuit 1 is "P", the potential of the output point 13 of the inverter circuit 1 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the inverter circuit 1 is "N", the potential of the output point 13 of the inverter circuit 1 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the inverter circuit 1 is "0", the potential of the output point 13 of the inverter circuit 1 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0064] Furthermore, the six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors that do not have "p," "n," or "o" added after the number added to "V," such as voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases.

[0065] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0066] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively.

[0067] The control unit 60 calculates the instantaneous value of the command voltage for each output voltage of the plurality of inverter circuits 1 as a command voltage vector V ＊ (See FIG. 12) to convert the command voltage vector V ＊ The α-axis component on the orthogonal α-β coordinate system is Vα, and the command voltage vector V ＊ If the β-axis component on the orthogonal α-β coordinate system is Vβ, then the command voltage vector V ＊ can be calculated using equation (1).

[0068]

[0069] The control unit 60 selects a command voltage vector V ＊ In the example of Fig. 13A, the multiple voltage vectors are voltage vectors V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].

[0070] The control unit 60 selects a command voltage vector V ＊One of the two first voltage vectors VV1 (V8p[PP0] and V8n[00N] in the examples of FIGS. 12 and 13A) closest to the first voltage vector VV1 is replaced with a zero vector V0n[NNN] that is a combination in which the potential level of the output points 13 of the multiple inverter circuits 1 becomes a negative potential, and at least one second voltage vector VV2 (V2[PPN] in the example of FIG. 13B) that is oriented in the same direction as the two first voltage vectors VV1 but has a different magnitude from the two first voltage vectors VV1. The reference magnitude is, for example, (2 / 3) １／２ Therefore, the plurality of voltage vectors include 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0] as voltage vectors whose magnitude is a reference magnitude (reference vectors). ＊ The first voltage vector VV1 and the command voltage vector V ＊ The angle between them is less than 30 degrees.

[0071] The control unit 60 determines a synthetic vector of at least one of the two first voltage vectors VV1 (V8p[PP0] and V8n[00N] in the example of FIG. 13A), one or more voltage vectors other than the first voltage vector VV1 (voltage vectors V13[P0N] and V7p[P00] in the example of FIG. 13B) among the plurality of voltage vectors, the zero vector V0n[NNN], and the second voltage vector VV2 as a command voltage vector V ＊ The control circuit controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts (see FIGS. 20 and 21 ) so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other. The predetermined control period Ts is, for example, two periods of the carrier signal.

[0072] In a comparative example in which control is performed without replacing the first voltage vector with a zero vector and a second voltage vector, the command voltage vector V ＊The resultant vector of the vectors at the vertices of the equilateral triangle surrounding ＊ That is, in the comparative example, the command voltage vector V ＊ In this case, the resultant vector of the two first voltage vectors VV1 (in the example of FIG. 13A, the voltage vector V8p[PP0] and the voltage vector V8n[00N]), the voltage vector V13[P0N], and the voltage vector V7p[P00] is defined as the command voltage vector V ＊ In the comparative example, a control period Ts (see FIGS. 14 and 15 ) corresponds to one period of the carrier signal. In the comparative example, within the control period Ts, as shown in FIG. 14 , for example, the switching state of only one of the U, V, and W phases in two voltage vectors arranged in time series changes between “P” and “0” or between “0” and “N,” and the same voltage vector is output twice. In FIG. 14 , a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 are output in the order of voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. 14 illustrates an example in which the allocation time of the voltage vectors V8p and V8n for the control period Ts is T0, the allocation time of the voltage vector V13 is T1, and the allocation time of the voltage vectors V7p and V7n is T2. ＊ The voltage vectors at the vertices of the equilateral triangle surrounding are Va, Vb, and Vc, and the command voltage vector V ＊ The magnitude of the command voltage vector V ＊When the angle between the α-axis and the voltage vector Vp[PP0] is θ, the control unit 60 determines T0, T1, and T2 so as to satisfy equations (2) and (3). "j" in equation (2) is an imaginary unit. In the example of FIG. 14 , for example, the voltage vector Va is the voltage vector V8p[PP0] and the voltage vector V8n[00N], the voltage vector Vb is the voltage vector V13[P0N], and the voltage vector Vc is the voltage vector V7p[P00] and the voltage vector V7n[0NN].

[0073]

[0074]

[0075] In the example of Fig. 14, as shown in Fig. 15, the third switching element Q3 of the inverter circuits 1U and 1V is in the on state throughout the entire control period Ts, resulting in a large voltage drop in the second bootstrap circuit 72 corresponding to each of the inverter circuits 1U and 1V. In the comparative example, the U-phase load current iU, the V-phase load current iV, and the W-phase load current iW have sinusoidal waveforms as shown in Fig. 16, and are out of phase with each other by 120 degrees. In the comparative example, the potential at the intermediate potential point M1 is substantially constant, as shown in Fig. 16.

[0076] The control unit 60 of the multilevel inverter 100 according to the first embodiment has a first control mode in which the potential of the intermediate potential point M1 is increased, a second control mode in which the potential of the intermediate potential point M1 is decreased, and a third control mode in which the potential of the intermediate potential point M1 is maintained.

[0077] Before describing the first, second, and third control modes, the relationship between the voltage vector and the potential at the intermediate potential point M1 will be described below. Note that the following explanations of Figures 17A, 18A, and 19A can be interpreted in the same way as Figure 11.

[0078] Fig. 17B is an equivalent circuit showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, V-phase load RA1v, and W-phase load RA1w of the AC load RA1 when the control unit 60 performs control using the zero vector V0p [PPP] in Fig. 17A. Fig. 17C is an equivalent circuit showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, V-phase load RA1v, and W-phase load RA1w of the AC load RA1 when the control unit 60 performs control using the zero vector V0o

[000] . Fig. 17D is an equivalent circuit showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, V-phase load RA1v, and W-phase load RA1w of the AC load RA1 when the control unit 60 performs control using the zero vector V0n [NNN]. In each of the equivalent circuits of Figures 17B, 17C, and 17D, there is no potential difference at the points where the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w are connected in the multilevel inverter 100, so the potential at the intermediate potential point M1 does not change.

[0079] 18B is an equivalent circuit diagram showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w of the AC load RA1 when the control unit 60 performs control using V1[PNN] among the six voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP] shown in FIG. 18A . In other words, FIG. 18B is an equivalent circuit diagram when the control unit 60 performs control using a voltage vector that includes the potential level of the positive electrode P1 and the potential level of the negative electrode N1 but does not include the potential level of the intermediate potential point M1. In the equivalent circuit diagram of FIG. 18B , none of the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w is connected to the intermediate potential point M1 in the multilevel inverter 100, so the potential of the intermediate potential point M1 does not change. In the case of voltage vectors V2 [PPN], V3 [NPN], V4 [NPP], V5 [NNP], and V6 [PNP] in FIG. 18A, none of the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w in the multilevel inverter 100 are connected to the intermediate potential point M1, so the potential of the intermediate potential point M1 does not change.

[0080] 18C is an equivalent circuit diagram showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, V-phase load RA1v, and W-phase load RA1w of the AC load RA1 when the control unit 60 controls the voltage vector V13[P0N] among the six voltage vectors V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0] shown in FIG. 18A . That is, FIG. 18C is an equivalent circuit diagram when the control unit 60 controls the voltage vector including the potential level of the positive electrode P1, the potential level of the negative electrode N1, and the potential level of the intermediate potential point M1. In the equivalent circuit diagram of FIG. 18C , if the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w are in equilibrium, the potential of the intermediate potential point M1 does not change. In the case of voltage vectors V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0] in Figure 18A, if the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w are in balance, the potential at the intermediate potential point M1 will not change.

[0081] 19B is an equivalent circuit diagram showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w of the AC load RA1 when the control unit 60 performs control using one of the six voltage vectors V7p[P00], V8p[PP0], V9p[0P0], V10p[0PP], V11p[00P], and V12p[P0P] shown in FIG. 19A. That is, FIG. 19B shows an equivalent circuit diagram when the control unit 60 performs control using a voltage vector that includes the potential level of the positive electrode P1 and the potential level of the intermediate potential point M1 but does not include the potential level of the negative electrode N1. In the equivalent circuit diagram of FIG. 19B, the potential of the intermediate potential point M1 increases. 19C is an equivalent circuit diagram showing the relationship between the intermediate potential point M1 and the U-phase load RA1u, the V-phase load RA1v, and the W-phase load RA1w of the AC load RA1 when the control unit 60 controls the AC load RA1 using one of the six voltage vectors V7n[0NN], V8n[00N], V9n[N0N], V10n[N00], V11n[NN0], and V12n[0N0] shown in FIG. 19A. That is, FIG. 19C shows an equivalent circuit diagram when the control unit 60 controls the AC load RA1 using a voltage vector that includes the potential level of the negative electrode N1 and the potential level of the intermediate potential point M1 but does not include the potential level of the positive electrode P1. In the equivalent circuit diagram of FIG. 19C, the potential of the intermediate potential point M1 increases.

[0082] In the first control mode, the control unit 60 selects a command voltage vector V ＊ Among the two first voltage vectors VV1 (in the example of FIG. 13A , the voltage vector V8p[PP0] and the voltage vector V8n[00N]), which are closest to the first voltage vector VV1, the first first voltage vector VV1 (in the example of FIG. 12A , the voltage vector V8n[00N]) that includes the potential level of the negative pole N1 in the combination of the potential levels of the multiple output points 13 is replaced with a zero vector V0n[NNN] and a second voltage vector VV2 (in the example of FIG. 13A , the voltage vector V2[PPN]) that is oriented in the same direction as the first first voltage vector VV1 and has twice the size of the first first voltage vector VV1. In the first control mode, the control unit 60 determines a composite vector of one or more voltage vectors other than two first voltage vectors VV1 among the plurality of voltage vectors (in the example of FIG. 13A, voltage vector V13[P0N] and voltage vector V7p[P00]), a second first voltage vector (in the example of FIG. 13A, voltage vector V8p[PP0]) among the two first voltage vectors VV1 that includes the potential level of the positive pole P1 in the combination of the potential levels of the plurality of output points 13, a zero vector V0n[NNN], and a second voltage vector VV2 (in the example of FIG. 13B, voltage vector V2[PPN]) as a command voltage vector V ＊ The control circuit controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other.

[0083] In the first control mode of the control unit 60, within two periods of the carrier signal, a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 are output in the order of voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V2[PPN] → zero vector V0n[NNN] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0], for example, as shown in Fig. 20. In the first control mode of the control unit 60, the voltage vectors V8n[00N] and V8n[00N] in the example of Fig. 14 in the comparative example are replaced with the second voltage vector VV2 (voltage vector V2[PPN]) and the zero vector V0n[NNN], respectively, so that a period in which the switching state of the U phase is "N" can be generated, as shown in Fig. 20. As a result, the multilevel inverter 100 according to the first embodiment can generate a third switching state in which both the first switching element Q1 and the second switching element Q2 of the inverter circuit 1U are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state, as shown in FIG. 21 . Therefore, the multilevel inverter 100 according to the first embodiment can suppress voltage drops in the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72. In the example of FIG. 20 , there are periods in which the V-phase switching state and the W-phase switching state are both “N,” so the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to each of the inverter circuits 1V and 1W are charged and maintain their voltages. Therefore, in the example of FIG. 20 , the multilevel inverter 100 is in a mode in which the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to each of the three inverter circuits 1U, 1V, and 1W can be charged.

[0084] In the first control mode of the control unit 60, a composite vector of one or more voltage vectors other than the two first voltage vectors VV1 (in the example of FIG. 13A, voltage vector V13[P0N] and voltage vector V7p[P00]) among the multiple voltage vectors, a second first voltage vector (in the example of FIG. 13A, voltage vector V8p[PP0]) among the two first voltage vectors VV1 that includes the potential level of the positive pole P1 in the combination of the potential levels of the multiple output points 13, a zero vector V0n[NNN], and a second voltage vector VV2 (in the example of FIG. 13B, voltage vector V2[PPN]) is defined as a command voltage vector V ＊ The control circuit 100 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the voltages of the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other. As a result, the multilevel inverter 100 according to the first embodiment can increase the potential of the intermediate potential point M1 as shown in FIG.

[0085] In the second control mode, the control unit 60 selects a command voltage vector V ＊ Among the two first voltage vectors VV1 (voltage vector V8p[PP0] and voltage vector V8n[00N] in the example of FIG. 13A ) that are closest to the second first voltage vector VV1, the second first voltage vector VV1 (voltage vector V8p[PP0] in the example of FIG. 13A ) that includes the potential level of the positive pole P1 in the combination of the potential levels of the multiple output points 13 is replaced with a zero vector V0n[NNN] and a second voltage vector VV2 (V2[PPN] in the example of FIG. 13B ) that is oriented in the same direction as the second first voltage vector VV1 and has twice the magnitude of the second first voltage vector VV1. In the second control mode, the control unit 60 determines a composite vector of one or more voltage vectors other than the two first voltage vectors VV1 (in the example of FIG. 13A, the voltage vector V13[P0N] and the voltage vector V7p[P00]) among the multiple voltage vectors, a first voltage vector (in the example of FIG. 13A, V8n[00N]) among the two first voltage vectors VV1 that includes the potential level of the negative pole N1 in the combination of the potential levels of the multiple output points 13, the zero vector V0n[NNN], and the second voltage vector VV2 (in the example of FIG. 13B, V2[PPN]) as the command voltage vector V＊ The control circuit controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other.

[0086] In the second control mode of the control unit 60, within two periods of the carrier signal, a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 are output in the order of voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V2[PPN] → zero vector V0n[NNN] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N], for example, as shown in Fig. 23. In the second control mode of the control unit 60, the voltage vectors V8p[PP0] and V8p[PP0] in the example of Fig. 14 in the comparative example are replaced with the second voltage vector VV2 (V2[PPN]) and the zero vector V0n[NNN], respectively, so that a period in which the switching state of the U phase is "N" can be generated as shown in Fig. 23. As a result, the multilevel inverter 100 according to the first embodiment can generate a third switching state in which both the first switching element Q1 and the second switching element Q2 of the inverter circuit 1U are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 of the inverter circuit 1U are in the ON state, as shown in Fig. 23 . Therefore, the multilevel inverter 100 according to the first embodiment can suppress voltage drops in the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to the inverter circuit 1U. Note that in the example of Fig. 23 , there are periods in which the switching state of the V phase and the switching state of the W phase are both "N," so the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to the inverter circuits 1V and 1W are charged and maintain their voltages. Therefore, in the example of FIG. 24, the multilevel inverter 100 is in a mode in which the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to each of the three inverter circuits 1U, 1V, and 1W can be charged.

[0087] In the second control mode of the control unit 60, a composite vector of one or more voltage vectors other than the two first voltage vectors VV1 (in the example of FIG. 13A, the voltage vector V13[P0N] and the voltage vector V7p[P00]) among the multiple voltage vectors, a second first voltage vector (in the example of FIG. 13A, V8n[00N]) among the two first voltage vectors VV1 that includes the potential level of the negative pole N1 in the combination of the potential levels of the multiple output points 13, the zero vector V0n[NNN], and the second voltage vector VV2 (in the example of FIG. 13B, V2[PPN]) is defined as the command voltage vector V ＊ The control circuit 100 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the potentials of the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other. As a result, the multilevel inverter 100 according to the first embodiment can reduce the potential of the intermediate potential point M1 as shown in FIG.

[0088] In the third control mode, the control unit 60 selects the zero vector V0n[NNN] and a second voltage vector VV2 (V2[PPN] in the example of Figure 13B) that is oriented in the same direction as the first voltage vector VV1 and is twice as large as the first voltage vector VV1. In the third control mode, the control unit 60 determines, as a command voltage vector V, a composite vector of one or more voltage vectors (in the example of FIG. 13A , voltage vector V13[P0N] and voltage vector V7p[P00]) other than the two first voltage vectors VV1 among the plurality of voltage vectors, a first first voltage vector (in the example of FIG. 13A , V8p[PP0]) among the two first voltage vectors VV1 that includes the potential level of the positive pole P1 among the combination of the potential levels of the plurality of output points 13, a second first voltage vector (in the example of FIG. 13A , V8n[00N]) among the two first voltage vectors VV1 that includes the potential level of the negative pole N1 among the combination of the potential levels of the plurality of output points 13, the zero vector V0n[NNN], and the second voltage vector VV2 (in the example of FIG. 13B , V2[PPN]). ＊ The control circuit controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other.

[0089] In the third control mode of the control unit 60, within two periods of the carrier signal, a plurality of first control signals S1, a plurality of second control signals S2, a plurality of third control signals S3, and a plurality of fourth control signals S4 are output in the order of voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V2[PPN] → zero vector V0n[NNN] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0], for example, as shown in Fig. 26. In the third control mode of the control unit 60, the voltage vectors V8p[PP0] and V8p[PP0] in the example of Fig. 14 in the comparative example are replaced with the second voltage vector VV2 (V2[PPN]) and the zero vector V0n[NNN], respectively, so that a period in which the switching state of the U phase is "N" can be generated, as shown in Fig. 26. As a result, the multilevel inverter 100 according to the first embodiment can generate a third switching state in which both the first switching element Q1 and the second switching element Q2 of the inverter circuit 1U are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 of the inverter circuit 1U are in the ON state, as shown in Fig. 27 . Therefore, the multilevel inverter 100 according to the first embodiment can suppress voltage drops in the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to the inverter circuit 1U. Note that in the example of Fig. 26 , there are periods in which the switching state of the V phase and the switching state of the W phase are both "N," so the capacitor C17 of the first bootstrap circuit 71 and the capacitor C27 of the second bootstrap circuit 72 corresponding to the inverter circuits 1V and 1W are charged and maintain their voltages.

[0090] In the third control mode of the control unit 60, a composite vector of one or more voltage vectors other than two first voltage vectors VV1 (in the example of FIG. 13A, voltage vector V13[P0N] and voltage vector V7p[P00]) among the plurality of voltage vectors, the first first voltage vector VV1, the second first voltage vector VV1, the zero vector V0n[NNN], and the second voltage vector VV2 (in the example of FIG. 13B, V2[PPN]) is defined as a command voltage vector V＊ 28 , the multilevel inverter 100 according to the first embodiment controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so as to match the potential of the intermediate potential point M1. As a result, the multilevel inverter 100 according to the first embodiment can maintain (approximately constant) the potential of the intermediate potential point M1, as shown in FIG.

[0091] In the multilevel inverter 100 according to the first embodiment, the control unit 60 calculates the command voltage vector V ＊ When the polarity of the command voltage corresponding to is positive, the control unit 60 replaces the first voltage vector VV1 with the zero vector V0n[NNN] and the second voltage vector VV2. ＊ When the polarity of the command voltage corresponding to is negative, the first voltage vector VV1 is not replaced with the zero vector V0n[NNN] and the second voltage vector VV2.

[0092] Furthermore, in the multilevel inverter 100, the control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 so that the output voltages of the plurality of first bootstrap circuits 71 and the plurality of second bootstrap circuits 72 do not fall below a predetermined value.

[0093] Furthermore, in the multilevel inverter 100 according to the first embodiment, the control unit 60 may be configured to determine the operation time in the first control mode and the operation time in the second control mode so that the average operation time in the first control mode and the average operation time in the second control mode are the same. For example, when the sum of the total operation time in the first control mode and the total operation time in the second control mode is 10 seconds, the control unit 60 may determine the operation time in the first control mode and the operation time in the second control mode so that the average operation time in the first control mode is 5 seconds and the average operation time in the second control mode is 5 seconds.

[0094] Furthermore, in the multilevel inverter 100 according to the first embodiment, when the control unit 60 operates in the third control mode, for example, within a control period Ts, the first control time for increasing the potential of the intermediate potential point M1 (T0 / 4 assigned to V8p[PP0] in the example of FIG. 26) and the second control time for decreasing the potential of the intermediate potential point M1 (T0 / 4 assigned to V8n[00N] in the example of FIG. 26) are the same, but may be different.

[0095] (3) Advantages In the multilevel inverter 100 according to the first embodiment, the control unit 60 selects the command voltage vector V ＊ The control unit 60 selects a plurality of (five) voltage vectors (for example, V8p[PP0], V8n[00N], V13[P0N], V7p[P00], V7n[0NN]) adjacent to the voltage vector V. Each of the group of voltage vectors is determined by a combination of the potential levels of the output points 13 between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1. The control unit 60 has a first control mode for increasing the potential of the intermediate potential point M1, a second control mode for decreasing the potential of the intermediate potential point M1, and a third control mode for maintaining the potential of the intermediate potential point M1. The control unit 60 selects a command voltage vector V from the group of (27) voltage vectors determined by a combination of the potential levels of the plurality of output points 13. ＊ The group of voltage vectors includes a zero vector V0n[NNN] that is a combination of a plurality of output points 13 whose potential levels are all at the potential of the negative pole N1. In the first control mode, the control unit 60 selects a plurality of voltage vectors whose magnitude is the reference magnitude and which are the command voltage vector V ＊The control unit 60 replaces a first first voltage vector VV1, which is one of the two first voltage vectors VV1 closest to the first voltage vector VV1 and which includes the potential level of the negative pole N1 in the combination of the potential levels of the multiple output points 13, with a zero vector V0n[NNN] and a second voltage vector VV2 which has the same direction as the first first voltage vector VV1 and is twice as large as the first first voltage vector VV1. In the first control mode, the control unit 60 replaces one or more voltage vectors other than the two first voltage vectors VV1 among the multiple voltage vectors, a second first voltage vector VV1, which is one of the two first voltage vectors VV1 and which includes the potential level of the positive pole P1 in the combination of the potential levels of the multiple output points 13, the zero vector V0n[NNN], and the second voltage vector VV2 as a command voltage vector V ＊ In the second control mode, the control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the first voltage vector VV1 coincides with the first voltage vector VV1. In the second control mode, the control unit 60 replaces the second first voltage vector VV1 with a zero vector V0n[NNN] and a second voltage vector VV2. In the second control mode, the control unit 60 replaces the one or more voltage vectors, the first first voltage vector VV1, the zero vector V0n[NNN], and the second voltage vector VV2 as a command voltage vector VV1. ＊ In the third control mode, the control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within the control period Ts so that the voltages of the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 coincide with each other. In the third control mode, the control unit 60 replaces one of the two first voltage vectors VV1 with a zero vector V0n[NNN] and a second voltage vector VV2. In the third control mode, the control unit 60 replaces the one or more voltage vectors VV1, the first first voltage vector VV1, the second first voltage vector VV1, the zero vector V0n[NNN], and the second voltage vector VV2 as a command voltage vector V ＊ The control circuit 100 controls the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 within the control period Ts so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other.

[0096] The above configuration makes it possible to suppress a voltage drop in the bootstrap circuit and fluctuations in the potential at the intermediate potential point M1. More specifically, the above configuration makes it possible to suppress a voltage drop in each of the capacitors C17 of the plurality of first bootstrap circuits 71 and the capacitors C27 of the plurality of second bootstrap circuits 72. Furthermore, the above configuration makes it possible for the control unit 60 to have a first control mode in which the potential at the intermediate potential point M1 is increased, a second control mode in which the potential at the intermediate potential point M1 is decreased, and a third control mode in which the potential at the intermediate potential point M1 is maintained, making it possible to suppress fluctuations in the potential at the intermediate potential point M1.

[0097] Furthermore, in the multilevel inverter 100 according to the first embodiment, the control unit 60 determines the operating time in the first control mode and the operating time in the second control mode so that the average operating time in the first control mode and the average operating time in the second control mode are the same.

[0098] According to the above configuration, it is possible to keep the potential of the intermediate potential point M1 constant.

[0099] Furthermore, in the multilevel inverter 100 according to the first embodiment, when the control unit 60 operates in the third control mode, the control unit 60 makes the first control time for increasing the potential of the intermediate potential point M1 and the second control time for decreasing the potential of the intermediate potential point M1 equal within the control period Ts.

[0100] According to the above configuration, it is possible to keep the potential of the intermediate potential point M1 constant.

[0101] Furthermore, in the multilevel inverter 100 according to the first embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the plurality of second gate drivers 62, the plurality of first bootstrap circuits 71, and the plurality of second bootstrap circuits 72.

[0102] According to the above configuration, it is possible to achieve miniaturization.

[0103] Second Embodiment A multilevel inverter 100A according to a second embodiment will be described with reference to Fig. 29. Regarding the multilevel inverter 100A, components similar to those of the multilevel inverter 100 according to the first embodiment (see Figs. 1 and 2) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0104] The multilevel inverter 100A differs from the multilevel inverter 100 in that the power supply unit 9 includes a plurality of (three) DC-DC converters 91.

[0105] In the multilevel inverter 100A, the multiple DC-DC converters 91 correspond to the multiple (three) second gate drivers 62. Each of the multiple DC-DC converters 91 supplies a voltage to the corresponding second gate driver 62. Furthermore, in the multilevel inverter 100A, the multiple DC-DC converters 91 correspond to the multiple first bootstrap circuits 71. Each of the multiple DC-DC converters 91 is connected to the corresponding first bootstrap circuit 71. More specifically, the positive terminal of each of the multiple DC-DC converters 91 is connected to the anode of the diode D17 in the corresponding first bootstrap circuit 71, and the negative terminal is connected to the negative electrode N1 of the DC power supply unit 3.

[0106] In the multilevel inverter 100A, the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control similar to that of the control unit 60 of the multilevel inverter 100.

[0107] Therefore, similar to the multilevel inverter 100, the multilevel inverter 100A according to the second embodiment can suppress the voltage drop of the capacitor C17 of the plurality of first bootstrap circuits 71 and the capacitor C27 of the plurality of second bootstrap circuits 72.

[0108] (Embodiment 3) A multilevel inverter 100B according to embodiment 3 will be described with reference to Fig. 30. Regarding the multilevel inverter 100B, components similar to those of the multilevel inverter 100 according to embodiment 1 (see Figs. 1 and 2) are denoted by the same reference numerals, and description thereof will be omitted.

[0109] In the multilevel inverter 100B, the bidirectional switch including the third switching element Q3 and the fourth switching element Q4 is a common-drain bidirectional switch in which the first main terminals (drain terminals) of the third switching element Q3 and the fourth switching element Q4 are connected to each other. In the bidirectional switch of the multilevel inverter 100B, the second main terminal (source terminal) of the fourth switching element Q4 is connected to the intermediate potential point M1, and the second main terminal (source terminal) of the third switching element Q3 is connected to the output point 13.

[0110] Furthermore, in the multilevel inverter 100B, the power supply unit 9 has, in addition to the DC-DC converter 91 (hereinafter also referred to as the first DC-DC converter 91), a plurality of (three) second DC-DC converters 92. Note that in Fig. 30, each of the plurality of second DC-DC converters 92 is illustrated with the symbol for a DC power supply.

[0111] The first DC-DC converter 91 supplies voltage to the plurality of second gate drivers 62 , the plurality of first bootstrap circuits 71 and the plurality of second bootstrap circuits 72 .

[0112] The second DC-DC converters 92 correspond one-to-one to the fourth gate drivers 64. Each of the second DC-DC converters 92 supplies a voltage to the corresponding fourth gate driver 64. The second DC-DC converter 92 has a positive terminal connected to the high-potential power supply terminal of the fourth gate driver 64, and a negative terminal connected to the intermediate potential point M1, the low-potential power supply terminal of the fourth gate driver 64, and the second main terminal of the fourth switching element Q4.

[0113] In the multilevel inverter 100B, the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control similar to that of the control unit 60 of the multilevel inverter 100.

[0114] Therefore, similar to the multilevel inverter 100, the multilevel inverter 100B according to the third embodiment can suppress voltage drops in the capacitors C17 of the plurality of first bootstrap circuits 71 and the capacitors C27 of the plurality of second bootstrap circuits 72.

[0115] (Embodiment 4) A multilevel inverter 100C according to embodiment 4 will be described with reference to Fig. 31. Regarding the multilevel inverter 100C, components similar to those of the multilevel inverter 100 according to embodiment 1 (see Figs. 1 and 2) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0116] The multilevel inverter 100C does not include the multiple second bootstrap circuits 72 in the multilevel inverter 100, and the power supply unit 9 includes a DC-DC converter 91 (hereinafter also referred to as a first DC-DC converter 91) and multiple (three) second DC-DC converters 92. Note that in Fig. 31, each of the multiple second DC-DC converters 92 is illustrated with the symbol for a DC power supply.

[0117] The first DC-DC converter 91 supplies voltage to the plurality of second gate drivers 62 and the plurality of first bootstrap circuits 71 .

[0118] The plurality of second DC-DC converters 92 correspond to the plurality of third gate drivers 63 and the plurality of fourth gate drivers 64, and supply voltages to the corresponding third gate drivers 63 and corresponding fourth gate drivers 64. The positive terminal of each of the plurality of second DC-DC converters 92 is connected to the high potential power supply terminal of the corresponding third gate driver 63 and the high potential power supply terminal of the corresponding fourth gate driver 64. Furthermore, the negative terminal of each of the plurality of second DC-DC converters 92 is connected to the low potential power supply terminal of the corresponding third gate driver 63 and the low potential power supply terminal of the corresponding fourth gate driver 64.

[0119] In the multilevel inverter 100C, the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control similar to that of the control unit 60 of the multilevel inverter 100.

[0120] Therefore, the multilevel inverter 100C according to the fourth embodiment can suppress a voltage drop across the capacitor C17 of each of the plurality of first bootstrap circuits 71.

[0121] Fifth Embodiment A multilevel inverter 100D according to a fifth embodiment will be described with reference to Fig. 32. Regarding the multilevel inverter 100D, components similar to those of the multilevel inverter 100C according to the fourth embodiment (see Fig. 31) are denoted by the same reference numerals, and description thereof will be omitted.

[0122] In the multilevel inverter 100D, the first DC-DC converter 91 is not connected to the plurality of first bootstrap circuits 71, and the positive terminal of the second DC-DC converter 92 is connected to the anode of the diode D17 of the first bootstrap circuit 71.

[0123] In the multilevel inverter 100D, the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control similar to that performed by the control unit 60 of the multilevel inverter 100 according to the first embodiment.

[0124] Therefore, the multilevel inverter 100D according to the fifth embodiment can suppress a voltage drop across the capacitor C17 of each of the plurality of first bootstrap circuits 71.

[0125] (Other Modifications) The above-described first to fifth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to fifth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0126] For example, each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4 is not limited to a MOSFET, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor). In this case, the control terminal, the first main terminal, and the second main terminal of each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4 are a gate terminal, a collector terminal, and an emitter terminal, respectively.

[0127] In the multilevel inverters 100, 100A to 100D according to the first, second to fifth embodiments, the control unit 60 controls the command voltage vector V ＊ The first voltage vector VV1 may be replaced with the zero vector V0n[NNN] and the second voltage vector VV2 not only when the polarity of the command voltage corresponding to is positive but also when it is negative.

[0128] Each of the first bootstrap circuits 71 includes the Zener diode Z17, but may not include the Zener diode Z17. Each of the second bootstrap circuits 72 includes the Zener diode Z27, but may not include the Zener diode Z27.

[0129] Furthermore, the multilevel inverters 100, 100A to 100D may be any multilevel inverter having three or more levels, and may be, for example, a five-level inverter.

[0130] (Aspects) The following aspects are disclosed in this specification.

[0131] A multilevel inverter (100; 100A; 100B; 100C; 100D) according to a first aspect includes a DC power supply unit (3), a plurality of inverter circuits (1), and a control device (6). The DC power supply unit (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of inverter circuits (1) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The control device (6) controls the plurality of inverter circuits (1). Each of the plurality of inverter circuits (1) includes a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4), as well as a first diode (D1), a second diode (D2), a third diode (D3), and a fourth diode (D4). The first diode (D1), the second diode (D2), the third diode (D3), and the fourth diode (D4) are connected in anti-parallel to the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4), respectively. In each of the multiple inverter circuits (1), the first switching element (Q1) and the second switching element (Q2) are connected in series from the positive electrode (P1) side to the negative electrode (N1) side, in that order, the first switching element (Q1) and the second switching element (Q2). In each of the multiple inverter circuits (1), a series circuit of the third switching element (Q3) and the fourth switching element (Q4) is connected between the intermediate potential point (M1) and the output point (13). The output point (13) is the connection point between the first switching element (Q1) and the second switching element (Q2). The control device (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of bootstrap circuits (71), a power supply unit (9), and a control unit (60). The plurality of first gate drivers (61) drive first switching elements (Q1) of the plurality of inverter circuits (1). The plurality of second gate drivers (62) drive second switching elements (Q2) of the plurality of inverter circuits (1). The plurality of third gate drivers (63) drive third switching elements (Q3) of the plurality of inverter circuits (1).A plurality of fourth gate drivers (64) drive fourth switching elements (Q4) of the plurality of inverter circuits (1). A plurality of bootstrap circuits (71) are connected to the plurality of first gate drivers (61). A power supply unit (9) supplies voltages to the plurality of second gate drivers (62) and the plurality of third gate drivers (63). The control unit (60) has a first control mode for increasing the potential of the intermediate potential point (M1), a second control mode for decreasing the potential of the intermediate potential point (M1), and a third control mode for maintaining the potential of the intermediate potential point (M1). The control unit (60) controls a command voltage vector (V) from among a group of voltage vectors determined by a combination of potential levels of a plurality of output points (13). ＊ ) is selected. The group of voltage vectors includes a zero vector (V0n[NNN]) of a combination in which the potential levels of the plurality of output points (13) are all at the negative potential (N1). In the first control mode, the control unit (60) selects a zero vector (V0n[NNN]) of the plurality of voltage vectors whose magnitude is the reference magnitude and which is the command voltage vector (V ＊ In the first control mode, the control unit (60) replaces a first first voltage vector (VV1) that includes a negative pole (N1) potential level in a combination of potential levels of a plurality of output points (13) among two first voltage vectors (VV1) that are closest to the first first voltage vector (VV1), with a zero vector (V0n[NNN]) and a second voltage vector (VV2) that has the same direction as the first first voltage vector (VV1) and is twice as large as the first first voltage vector (VV1). In the first control mode, the control unit (60) replaces one or more voltage vectors other than the two first voltage vectors (VV1) among the plurality of voltage vectors, a second first voltage vector (VV1) that includes a positive pole (P1) potential level in a combination of potential levels of a plurality of output points (13) among the two first voltage vectors (VV1), the zero vector (V0n[NNN]), and the second voltage vector (VV2) as a command voltage vector (V ＊The control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) within a predetermined control period (Ts) so as to match the first voltage vector (VV1) with a zero vector (V0n[NNN]) and a second voltage vector (VV2). In the second control mode, the control unit (60) replaces the second first voltage vector (VV1) with a zero vector (V0n[NNN]) and a second voltage vector (VV2). In the second control mode, the control unit (60) replaces the one or more voltage vectors, the first first voltage vector (VV1), the zero vector (V0n[NNN]), and the second voltage vector (VV2) with a command voltage vector (V ＊ In the third control mode, the control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) within a control period (Ts) so as to match the one or more voltage vectors, the first first voltage vector (VV1), the second first voltage vector (VV1), the zero vector (V0n[NNN]), and the second voltage vector (VV2) to a command voltage vector (V ＊ A plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) are controlled within a control period (Ts) so as to coincide with the control period (Ts).

[0132] According to this aspect, it is possible to suppress a voltage drop in the bootstrap circuit (71) and a fluctuation in the potential of the intermediate potential point (M1). More specifically, according to this aspect, it is possible to suppress a voltage drop in the capacitors (C17) of the multiple bootstrap circuits (71). Furthermore, according to this aspect, since the control unit (60) has the first control mode, the second control mode, and the third control mode, it is possible to suppress a fluctuation in the potential of the intermediate potential point (M1).

[0133] In the multilevel inverter (100; 100A) according to the second aspect, in the first aspect, the control unit (60) determines the operating time in the first control mode and the operating time in the second control mode so that the average operating time in the first control mode and the average operating time in the second control mode are the same.

[0134] According to this embodiment, it is possible to keep the potential of the intermediate potential point (M1) constant.

[0135] In the multilevel inverter (100; 100A) according to the third aspect, in the first or second aspect, when the control unit (60) operates in the third control mode, the control unit (60) makes the first control time for increasing the potential of the intermediate potential point (M1) equal to the second control time for decreasing the potential of the intermediate potential point (M1) within the control period (Ts).

[0136] According to this embodiment, it is possible to keep the potential of the intermediate potential point (M1) constant.

[0137] In the multilevel inverter (100; 100A) according to the fourth aspect, in any one of the first to third aspects, the control unit (60) calculates a command voltage vector (V ＊ When the polarity of the command voltage corresponding to V0n[NNN] is positive, the first voltage vector (VV1) is replaced with a zero vector (V0n[NNN]) and a second voltage vector (VV2).

[0138] According to this aspect, the number of times the first voltage vector (VV1) is replaced with the zero vector (V0n[NNN]) and the second voltage vector (VV2) can be reduced.

[0139] In a multilevel inverter (100; 100A) according to a fifth aspect, in any one of the first to fourth aspects, a control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) so ​​that the output voltage of each of the plurality of bootstrap circuits (71) does not drop below a predetermined value.

[0140] According to this aspect, it is possible to prevent the output voltage of each of the plurality of bootstrap circuits (71) from falling below a predetermined value.

[0141] In a multilevel inverter (100; 100A; 100B; 100C; 100D) according to a sixth aspect, in any one of the first to fifth aspects, each of the plurality of bootstrap circuits (71) includes a capacitor (C17) and a diode (D17). The diode (D17) is connected in series with the capacitor (C17).

[0142] In a multilevel inverter (100; 100A; 100B; 100C; 100D) according to a seventh aspect, in the sixth aspect, each of the plurality of bootstrap circuits (71) further includes a resistor (R17), which is connected in series with the capacitor (C17).

[0143] In a multilevel inverter (100; 100A; 100B; 100C; 100D) according to an eighth aspect, in any one of the first to seventh aspects, the power supply unit (9) includes a DC-DC converter (91). The DC-DC converter (91) supplies voltage to the plurality of second gate drivers (62) and the plurality of bootstrap circuits (71).

[0144] According to this aspect, it is possible to reduce the size of the multilevel inverter (100; 100A; 100B; 100C; 100D).

[0145] REFERENCE SIGNS LIST 1 inverter circuit 3 DC power supply unit 6 control device 60 control unit 61 first gate driver 62 second gate driver 63 third gate driver 64 fourth gate driver 9 power supply unit 91 DC-DC converter (first DC-DC converter) 92 second DC-DC converter 11 first circuit 12 second circuit 13 output point 71 bootstrap circuit (first bootstrap circuit) 72 second bootstrap circuit 100, 100A, 100B, 100C, 100D multilevel inverter C17, C27 capacitor D1 first diode D2 second diode D3 third diode D4 fourth diode D17, D27 diode P1 positive pole Q1 first switching element Q2 second switching element Q3 third switching element Q4 fourth switching element M1 intermediate potential point N1 negative pole R17, R27 Resistance Ts Control period V0 to V18 Voltage vector V ＊ Command voltage vector VV1 First voltage vector VV2 Second voltage vector

Claims

1. A power supply device comprising: a DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; a plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; and a control device for controlling the plurality of inverter circuits, wherein each of the plurality of inverter circuits has a first switching element, a second switching element, a third switching element, and a fourth switching element; and a first diode, a second diode, a third diode, and a fourth diode connected in anti-parallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively; and in each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element and the second switching element, and a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and an output point, the output point being a connection point between the first switching element and the second switching element; and the control device comprises: a plurality of first gate drivers for driving the first switching elements of each of the plurality of inverter circuits; the control unit includes: a plurality of second gate drivers driving the second switching elements of the respective inverter circuits; a plurality of third gate drivers driving the third switching elements of the respective inverter circuits; a plurality of fourth gate drivers driving the fourth switching elements of the respective inverter circuits; a plurality of bootstrap circuits connected to the plurality of first gate drivers; a power supply unit supplying voltages to the plurality of second gate drivers and the plurality of third gate drivers; and a control unit having a first control mode for increasing a potential of the intermediate potential point, a second control mode for decreasing the potential of the intermediate potential point, and a third control mode for maintaining the potential of the intermediate potential point, wherein the control unit selects a plurality of voltage vectors adjacent to a command voltage vector from a group of voltage vectors determined by a combination of potential levels of a plurality of the output points,the group of voltage vectors includes a zero vector of a combination in which all of the potential levels of the plurality of output points are the negative potential, and in the first control mode, a first first voltage vector, which is one of two first voltage vectors among the plurality of voltage vectors and has a reference magnitude and is closest to the command voltage vector and which includes the negative potential level in a combination of the potential levels of the plurality of output points, is replaced with the zero vector and a second voltage vector which has the same orientation as the first first voltage vector and is twice as large as the first first voltage vector, and the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers are controlled within a predetermined control period so as to make a composite vector of one or more voltage vectors other than the two first voltage vectors among the plurality of voltage vectors, a second first voltage vector, which is one of the two first voltage vectors and which includes the positive potential level in a combination of the potential levels of the plurality of output points, the zero vector, and the second voltage vector coincide with the command voltage vector, and in the second control mode, a first control mode for controlling the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers within the control period so as to make a composite vector of the one or more voltage vectors, the first first voltage vector, the zero vector, and the second voltage vector coincide with the command voltage vector; and in the third control mode, a first control mode for controlling the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers within the control period so as to make a composite vector of the one or more voltage vectors, the first first voltage vector, the second first voltage vector, the zero vector, and the second voltage vector coincide with the command voltage vector.

2. The multilevel inverter according to claim 1, wherein the control unit determines the operation time in the first control mode and the operation time in the second control mode such that an average operation time in the first control mode and an average operation time in the second control mode are the same.

3. The multilevel inverter according to claim 1 or 2, wherein, when the control unit operates in the third control mode, within the control period, a first control time for increasing the potential of the intermediate potential point is equal to a second control time for decreasing the potential of the intermediate potential point.

4. The multilevel inverter according to any one of claims 1 to 3, wherein the control unit replaces the first voltage vector with the zero vector and the second voltage vector when the polarity of the command voltage corresponding to the command voltage vector is positive.

5. The multilevel inverter according to any one of claims 1 to 4, wherein the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers so that the output voltage of each of the plurality of bootstrap circuits does not fall below a predetermined value.

6. The multilevel inverter according to claim 1, wherein each of the plurality of bootstrap circuits includes a capacitor and a diode connected in series to the capacitor.

7. The multilevel inverter according to claim 6, wherein each of the plurality of bootstrap circuits further includes a resistor connected in series with the capacitor.

8. The multilevel inverter according to any one of claims 1 to 7, wherein the power supply unit includes a DC-DC converter that supplies voltage to the plurality of second gate drivers and the plurality of bootstrap circuits.

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