Multi-level reallocation mechanism-based gpgpu branch instruction scheduling method

Abstract

The present application relates to the technical field of computers. Disclosed is a multi-level reallocation mechanism-based GPGPU branch instruction scheduling method, comprising: a CPU sends instruction information to a GPGPU by using a PCIE; and the GPGPU performs multi-level reallocation scheduling processing on the instruction information. The multi-level reallocation scheduling processing comprises: a first-level general instruction execution unit / branch preprocessing unit determining the instruction information, if the instruction information is a non-conditional branch instruction, performing sequential computing execution, and if the instruction is a conditional branch instruction, pre-computing branch-instruction instruction blocks corresponding to warps / threads and sending same to a second-level branch scheduling unit; and the second-level branch scheduling unit reallocating corresponding thread execution statements according to a corresponding relationship between the received warps / threads and the branch-instruction instruction blocks. The present disclosure ensures the high concurrency of GPGPUs in processing branch instructions.

Description

GPGPU branch instruction scheduling method based on multi-level redistribution mechanism TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, for example to a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism. BACKGROUND

[0002] With the increasing of large models and artificial intelligence as new growth factors of economic development, the demand for computing power of various countries and manufacturers is increasing, and the development of high-performance chips is also becoming increasingly popular. Among them, general-purpose graphics processing units (GPGPU) products have high computing power, high concurrency and high versatility, and with the increase of their adaptive artificial intelligence computing tensor core units and artificial intelligence computing core units, they have gradually become the mainstream products in the field of high-performance hardware support.

[0003] The existing GPGPU scheduling strategy has excellent effect in processing general instructions, all thread instructions in a warp thread execute the same instruction synchronously, effectively improving the GPGPU computing power.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

[0005] When facing branch instructions (such as if-else), the existing warp scheduling method is sequential and serial execution, the threads that meet the if condition execute the instructions first, and then the threads that meet the else condition execute, especially when multiple branch instructions are involved, this serial execution scheduling strategy greatly increases the execution time of a single warp, hinders the high concurrency execution efficiency of GPGPU, and gradually hinders the product development of GPGPU.

[0006] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0007] SUMMARY

[0008] In order to have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not a general review, nor is it intended to determine key / important elements or delineate the scope of protection of these embodiments, but as a prelude to the detailed description below.

[0009] The embodiment of the present disclosure provides a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism and a storage medium, which effectively guarantees the high concurrency of GPGPU processing branch instructions, especially in the face of multi-layer branch statements, greatly improves the resource utilization and execution efficiency of the GPGPU. In some embodiments, the method comprises:

[0010] The CPU sends instruction information to the GPGPU through the PCIE;

[0011] The GPGPU performs multi-level redistribution scheduling processing on the instruction information, wherein the multi-level redistribution scheduling processing comprises a first level based on a general instruction execution unit / branch preprocessing unit, judging the instruction information, if the instruction information is a non-conditional branch instruction, performing sequential calculation execution; if the instruction is a conditional branch instruction, pre-calculating the branch instruction instruction block corresponding to each warp / thread, and sending it to a second level branch scheduling unit;

[0012] The second level branch scheduling unit redistributes the thread execution statements corresponding to the received warp / thread and branch instruction instruction block according to the correspondence.

[0013] In some embodiments, the storage medium stores program instructions, characterized in that the program instructions execute the GPGPU branch instruction scheduling method based on the multi-level redistribution mechanism in the above embodiments when running.

[0014] The GPGPU branch instruction scheduling method based on the multi-level redistribution mechanism and the storage medium provided by the embodiment of the present disclosure can achieve the following technical effects:

[0015] The present disclosure divides the GPGPU instruction scheduling strategy into two levels: one layer is the traditional instruction scheduling, which is used for processing the front-end execution of general instructions and branch instructions; the other layer is the back-end rescheduling process of the branch instruction, which is used for scheduling the threads of the branch instruction in high concurrency, and by redistributing the threads involved in the branch instruction, the threads executing the same instruction branch are bundled into a new warp. Based on the existing execution unit, the warp-processing unit correspondence is redistributed, and each execution unit processes the branch instruction block at the same time. Through the GPGPU branch instruction scheduling scheme based on the multi-level redistribution mechanism of the present disclosure, the high concurrency of GPGPU processing branch instructions is effectively guaranteed, especially in the face of multi-layer branch statements, which greatly improves the resource utilization and execution efficiency of the GPGPU.

[0016] The general description above and the following description below are only exemplary and explanatory, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] One or more embodiments are illustrated by way of example, in which are shown and described specific embodiments with reference to the figures. These embodiments are described in enough detail to enable those skilled in the art to practice the embodiments. The embodiments can be combined, other embodiments can be utilized, and structural, logical and electrical changes can be made without departing from the scope of the present disclosure. To avoid detail not relevant to the disclosure, reference is made to the drawings which form a part of the disclosure, wherein like reference characters are used to designate like components in multiple views, and in which are shown by way of illustration specific embodiments in which the principles of the present disclosure can be applied. The figures are not drawn to scale and are not intended for use in construction or fabrication but are merely provided to explain the principles of the present disclosure.

[0018] FIG. 1 is a flow diagram of a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism according to an embodiment of the present disclosure;

[0019] FIG. 2 is an architecture diagram of a GPGPU branch instruction scheduling based on a multi-level redistribution mechanism according to an embodiment of the present disclosure;

[0020] FIG. 3 is a branch instruction structure diagram in a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism according to an embodiment of the present disclosure;

[0021] FIG. 4 is a flow diagram of a general GPGPU processing of a branch instruction according to an embodiment of the present disclosure;

[0022] FIG. 5 is a flow diagram of a branch instruction processing based on a multi-level scheduling strategy in a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism according to an embodiment of the present disclosure;

[0023] FIG. 6 is a structure diagram of a GPGPU branch instruction scheduling system based on a multi-level redistribution mechanism according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are for reference only and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified to facilitate the drawings.

[0025] The terms "first", "second", and the like in the embodiments of the present disclosure are used to distinguish similar objects, and do not necessarily mean a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0026] Unless otherwise specified, the term "a plurality of" means two or more.

[0027] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B means A or B.

[0028] The term "and / or" is a description of an association relationship of objects, which means that there can be three relationships. For example, A and / or B means that there are three relationships of A or B, or A and B.

[0029] The term "corresponding" can refer to an association relationship or a binding relationship. A and B correspond to each other means that there is an association relationship or a binding relationship between A and B.

[0030] Figure 1 is a flowchart of a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism according to an embodiment of the present disclosure;

[0031] In combination with Figure 1, the GPGPU branch instruction scheduling method based on the multi-level redistribution mechanism provided by the embodiment of the present disclosure comprises:

[0032] S01, the central processing unit (CPU) sends instruction information to the GPGPU through the peripheral component interconnect express (PCIE);

[0033] S02, the GPGPU performs multi-level redistribution scheduling processing on the instruction information, wherein the multi-level redistribution scheduling processing comprises a first level based on a general instruction execution unit / branch preprocessing unit, judging the instruction information, if the instruction information is a non-conditional branch instruction, performing sequential calculation execution; if the instruction is a conditional branch instruction, pre-calculating the branch instruction instruction block corresponding to each warp / thread, and sending it to a second level branch scheduling unit;

[0034] The second level branch scheduling unit redistributes the thread execution statement according to the received warp / thread and branch instruction instruction block correspondence.

[0035] The present disclosure divides the GPGPU instruction scheduling strategy into two levels: one layer is the traditional instruction scheduling, which is used for processing the front-end execution of general instructions and branch instructions; the other layer is the back-end rescheduling process of branch instructions, which is used for scheduling the threads of branch instructions with high concurrency. By redistributing the threads involved in the branch instruction, the threads executing the same instruction branch are bundled into a new warp. Based on the existing execution unit, the warp-processing unit correspondence is redistributed, and each execution unit processes the branch instruction block at the same time. Through the GPGPU branch instruction scheduling scheme based on the multi-level redistribution mechanism of the present disclosure, the high concurrency of GPGPU processing branch instructions is effectively guaranteed, especially in the face of multi-layer branch statements, which greatly improves the resource utilization and execution efficiency of GPGPU.

[0036] Figure 2 is a schematic diagram of an architecture of a GPGPU branch instruction scheduling based on a multi-level redistribution mechanism according to an embodiment of the present disclosure. The GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism in Figure 1 is further described in combination with Figure 2.

[0037] In some embodiments, the GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism further includes memory synchronization of instructions, instruction fetch and decode, dispatch and launch, branch preprocessing, branch rescheduling, operation execution, and write-back refresh processing.

[0038] In some embodiments, the memory synchronization includes instruction storage and data storage, and is used to complete the receiving of instruction / data information from the CPU to the GPGPU and the sending of instruction / data information from the GPGPU to the CPU.

[0039] In some embodiments, the instruction fetch and decode includes fetching instructions cached by the GPGPU and decoding and converting the instructions into instructions executable by the GPGPU.

[0040] In some embodiments, the scheduling in the dispatch and launch includes matching thread-blocks / threads in the instructions with Streaming Multiprocessors (SMs) / Streaming Processors (SPs) in the GPGPU hardware according to the extracted instruction information, and sending information to the launch unit in units of a plurality of thread-integrated warps.

[0041] In some embodiments, the launch unit is used to send the information to the corresponding SM / SP hardware for execution.

[0042] In some embodiments, the branch preprocessing includes sequentially executing if it is a general instruction, and storing related branch instruction block information and sending it to a branch scheduling unit if it is a branch execution. The branch scheduling unit receives branch instruction block information sent by a plurality of warps, bundles it into a new warp, releases the original hardware execution unit SM / SP at the same time, and allocates the new warp to the released SM / SP.

[0043] In some embodiments, the operation execution includes executing the instructions sent to the SM / SP, and feeding back the instruction execution status to the scorecard.

[0044] In some embodiments, the write-back refresh includes receiving execution information from the execution unit, and sending the execution information to the scheduling unit for scheduling of the next instruction by the scheduling unit.

[0045] That is, the CPU level part completes the data sending task, and data thereof can be divided into instruction data and operation data. The instruction data is an operation to be performed, and the operation data is data to be operated. The two types of data are copied and synchronized from the CPU memory to the GPGPU memory through the PCIE physical link by the memory synchronization function of the CPU.

[0046] The GPGPU level part is mainly divided into seven processes, including a memory synchronization process, an instruction fetching and decoding process, a scheduling and sending process, a branch preprocessing process, a branch rescheduling process, an operation execution process, and a write-back and refreshing process. The memory synchronization process includes instruction storage and data storage, and is responsible for receiving instruction / data information from the CPU to the GPGPU and sending instruction / data information from the GPGPU to the CPU. The instruction fetching and decoding process is responsible for fetching instructions in the GPGPU cache and decoding them into executable instructions of the GPGPU. The scheduling and sending process is divided into a scheduling unit and a sending unit. The scheduling unit matches thread-block / thread in the instruction information with SM / SP in the GPGPU hardware according to the extracted instruction information, sends information to the sending unit in the form of a warp integrated with multiple threads, and the sending unit is responsible for sending information to the corresponding SM / SP hardware for execution. The branch preprocessing process is divided into a general instruction execution unit and a branch execution preprocessing unit, and the actual hardware unit is SM / SP. If it is a general instruction, it is directly executed in sequence; if it is a branch execution, the related branch instruction block information is stored and sent to the branch scheduling unit. The branch scheduling unit receives branch instruction block information sent by multiple warps, especially instruction information of multiple personal computers (PCs), bundles the information into a new warp, releases the original hardware execution unit SM / SP, and allocates the new warp to the released SM / SP. The operation execution process is responsible for executing the instructions sent to the SM / SP, and feeds back the instruction execution state to the scorecard. The write-back and refreshing process is responsible for receiving execution information from the execution unit and sending the execution information to the scheduling unit for scheduling of the next instruction by the scheduling unit.

[0047] FIG. 3 is a schematic diagram of a branch instruction structure in a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism according to an embodiment of the present disclosure;

[0048] FIG. 4 is a flowchart of a general GPGPU processing process for a branch instruction according to an embodiment of the present disclosure;

[0049] Figure 5 is a flow chart of a branch instruction processing method based on a multi-level scheduling strategy in a GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism according to an embodiment of the present disclosure. The GPGPU branch instruction scheduling method based on a multi-level redistribution mechanism is further described in combination with Figures 3-5.

[0050] Suppose that the instructions sent by the CPU this time call 12 threads (in the actual instruction transmission process, the number of threads is much larger than this number, and the present patent example is only for the purpose of illustrating the scheduling process), and each thread executes the same branch instruction. The GPGPU scheduling unit distributes the 12 threads to 3 warps evenly and sends them to the execution unit for execution. The specific branch instruction structure is shown in Figure 3.

[0051] The specific instruction branch structure is shown in Figure 3. First, each thread executes the A instruction block. When the A instruction block ends, a conditional branch instruction appears. The threads that satisfy the conditional branch instruction execute the instruction block B, and the threads that do not satisfy the conditional branch instruction execute the instruction block C. After the threads that execute the instruction block C finish executing, a conditional branch statement appears again. The threads that satisfy the conditional branch statement continue to execute the instruction block E, and the threads that do not satisfy the conditional branch instruction execute the instruction block D. After the threads that execute the instruction block D finish executing, the threads sequentially execute the instructions in the instruction block F. Finally, the threads that execute the instruction block E and the instruction block F are aggregated before the instruction block G and execute the instruction block G together. After the instruction block G is executed, the threads that execute the instruction block B are aggregated before the instruction block H and execute the instruction block H together, and finally the execution of the entire instruction is completed.

[0052] Because in the common architecture of GPGPU, in order to ensure high concurrency, a single instruction multiple thread (SIMT) structure is often used, that is, it is necessary to ensure that the instructions executed by all threads running in a warp are the same. Therefore, when a warp executes a branch instruction, it often sequentially executes each branch statement (for example, threads that satisfy the if condition are executed first, and then threads that satisfy the else statement are executed). The threads that have finished executing first also need to wait for the subsequent threads to finish executing before ending the current calculation task, which greatly reduces the operation efficiency and operation time of the execution unit. As shown in Figure 4, all 4 threads in the 3 warps need to wait for all instructions to be executed before they can exit the instruction execution.

[0053] The GPGPU branch instruction scheduling scheme based on the multi-stage redistribution mechanism of the application adopts a multi-stage redistribution scheduling mechanism: firstly, the first stage is a general instruction execution unit / branch preprocessing unit, and the two unit modules are composed of the same hardware SM / SP, and the instruction information from the scheduling unit is arbitrated, if the instruction information is a non-conditional branch instruction, sequential calculation execution is performed; if the instruction is a conditional branch instruction, the branch instruction instruction block corresponding to each warp / thread is pre-calculated and sent to the second stage branch scheduling unit. The second stage branch scheduling unit redistributes the corresponding thread execution statements according to the received warp / thread and branch instruction instruction block corresponding relationship, so that each thread can exit the instruction execution directly after the calculation is completed without waiting

[0054] The specific execution process of the GPGPU branch instruction scheduling scheme based on the multi-stage redistribution mechanism is shown in FIG. 5, firstly, the branch preprocessing unit pre-calculates the branch instruction instruction block corresponding to each warp / thread, obtains the following information and sends it to the second stage branch scheduling unit:

[0055] 1) warp0, warp1 and warp2 thread0 need to execute A, B, H instruction blocks;

[0056] 2) warp0, warp1 and warp2 thread1 need to execute A, C, E, G, H instruction blocks;

[0057] 3) warp0, warp1 and warp2 thread2, thread3 need to execute A, C, D, F, G, H instruction blocks;

[0058] After the second stage branch scheduling unit receives the above information, the thread is redistributed based on the original warp number 3. The warp0 / thread0, warp1 / thread0, warp2 / thread0 executing instruction blocks A, B, H are bundled to a new warp0*, and sent to the original warp0 execution unit for execution by the sending unit; the warp0 / thread1, warp1 / thread1, warp2 / thread1 executing instruction blocks A, C, E, G, H are bundled to a new warp1*, and sent to the original warp1 execution unit for execution by the sending unit; the warp0 / thread2, warp0 / thread3, warp1 / thread2, warp1 / thread3, warp2 / thread2, warp2 / thread3 executing instruction blocks A, C, D, F, G, H are bundled to a new warp2*, and sent to the original warp2 execution unit for execution by the sending unit.

[0059] Through the multi-level redistribution scheduling scheme of the patent, the warp0* executing the instruction blocks A, B and H can complete the execution of the instructions and exit the execution in only 3 cycles, the warp1* executing the instruction blocks A, C, E, G and H can complete the execution of the instructions and exit the execution in only 5 cycles, and the warp2* executing the instruction blocks A, C, D, F, G and H can complete the execution of the instructions and exit the execution in only 6 cycles. The overall execution time of the patent is saved by 10 cycles compared with the common branch execution execution strategy in FIG. 4, and the execution efficiency is improved by nearly half. Meanwhile, each thread does not need to be masked and waited, and thus the execution unit does not need to maintain a SIMT stack or a branch barrier table to schedule whether each thread in each warp executes, and the running logic of the execution unit is further simplified, and the execution efficiency of the execution unit is improved.

[0060] The application has the advantages that: the application proposes a GPGPU branch instruction scheduling scheme based on a multi-level redistribution mechanism in view of the problem that the existing GPGPU scheduling strategy has low branch instruction execution efficiency and destroys the high concurrency of the GPGPU. Different from the common GPGPU instruction scheduling scheme, the scheme divides the GPGPU instruction scheduling strategy into two levels: one level is the traditional instruction scheduling, which is used for processing the front-end execution of general instructions and branch instructions; the other level is the back-end rescheduling process of the branch instructions, which is used for scheduling the threads of the branch instructions in high concurrency, and the threads executing the same instruction branch are bundled in a new warp by redistributing the threads involved in the branch instructions. Based on the existing execution unit, the warp-processing unit correspondence is redistributed, and each execution unit processes the branch instruction block at the same time. Through the GPGPU branch instruction scheduling scheme based on the multi-level redistribution mechanism of the application, the high concurrency of the GPGPU processing branch instructions is effectively guaranteed, and especially in the face of multi-layer branch statements, the resource utilization rate and the execution efficiency of the GPGPU are greatly improved.

[0061] In combination with FIG. 6, the embodiment of the disclosure provides a GPGPU branch instruction scheduling system 600 based on a multi-level redistribution mechanism, which comprises a processor 604 and a memory 601. Optionally, the device can further comprise a communication interface 602 and a bus 603. The processor 604, the communication interface 602 and the memory 601 can complete the communication among each other through the bus 603. The communication interface 602 can be used for information transmission. The processor 604 can call the logical instructions in the memory 601 to execute the GPGPU branch instruction scheduling method based on the multi-level redistribution mechanism of the above-mentioned embodiment.

[0062] In addition, the logic instructions in the memory 601 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium.

[0063] The memory 601 as a computer readable storage medium can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiments of the present disclosure. The processor 604 executes the program instructions / modules stored in the memory 601, thereby performing functional applications and data processing, that is, implementing the GPGPU branch instruction scheduling method based on the multi-level redistribution mechanism in the above embodiments.

[0064] The memory 601 can include a program storage area and a data storage area, wherein the program storage area can store an operating system and application programs required by at least one function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 601 can include a high-speed random access memory, and can also include a non-volatile memory.

[0065] The embodiments of the present disclosure provide a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are configured to execute the GPGPU branch instruction scheduling method based on the multi-level redistribution mechanism.

[0066] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0067] The technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc. various media that can store program codes, or a transitory storage medium.

[0068] The above description and drawings are illustrative of embodiments of the present disclosure and are not intended to be limiting. Other embodiments can include structural, logical, electrical, process, and other changes. Embodiments are merely representative of possible variations. Individual components and functions are optional unless explicitly required, and the order of operations can be varied. Portions and features of some embodiments can be included in, or substituted for, those of other embodiments. As used in the description of the embodiments, the article "a" is intended to include one or more items unless the context clearly indicates otherwise. Likewise, the term "and / or" as used in the application refers to any and all possible combinations of one or more of the associated listed items. In addition, the term "comprise" and variations thereof, as used in the application, are intended to mean that the claim encompasses the recited features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. An element procured under the recitation "a..." does not, without more constraints, exclude the presence of additional identical elements in the process, method, or apparatus. In this document, each embodiment focuses on what is different from other embodiments, and the same or similar parts between embodiments can be cross-referenced. For the methods, products, and the like disclosed by the embodiments, if they correspond to the method part disclosed by the embodiments, the relevant parts can be referred to the description of the method part.

[0069] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure. The skilled person can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0070] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to apparatuses, devices, etc.) can be implemented in other manners. For example, the apparatus embodiments described above are merely schematic. For example, the division of the units is merely logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, apparatuses, or units, and can be in electrical, mechanical, or other forms. The units described as separated components can or can not be physically separated, and components displayed as units can or can not be physical units. Some or all of the units can be selected according to actual needs to achieve the embodiments.

[0071] The flowcharts and block diagrams in the drawings show the possible implementation architectures, functions, and operations of the systems, methods, and computer program products according to the embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions noted in the blocks can occur in different orders than those noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the drawings, the operations or steps corresponding to different blocks can also occur in different orders than those disclosed in the descriptions, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. Each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A GPGPU branch instruction scheduling method based on a multi-level reallocation mechanism, characterized in that: The method comprises: The CPU sends instruction information to the GPGPU through PCIE; The GPGPU performs multi-level redistribution and scheduling processing on the instruction information, wherein the multi-level redistribution and scheduling processing includes a first-level general instruction execution unit / branch pre-processing unit to judge the instruction information, and if the instruction information is an unconditional branch instruction, perform sequential calculation and execution; if the instruction information is a conditional branch instruction, pre-calculate the branch instruction block corresponding to each warp / thread and send it to the second-level branch scheduling unit; The second-level branch scheduling unit reallocates the corresponding thread execution statement according to the correspondence between the received warp / thread and the branch instruction block.

2. The method according to claim 1, characterized in that The method further includes GPGPU performing memory synchronization, instruction fetching and decoding, scheduling and issuing, branch pre-processing, branch rescheduling, operation execution and write-back refresh processing on the instructions.

3. The method according to claim 2, characterized in that The memory synchronization includes instruction storage and data storage, and is used to complete the reception of instruction / data information from the CPU to the GPGPU and the transmission of instruction / data information from the GPGPU to the CPU.

4. The method according to claim 3, characterized in that The instruction fetch and decoding includes fetching instructions from the GPGPU cache and decoding and converting them into instructions executable by the GPGPU.

5. The method according to claim 4, characterized in that The scheduling in the scheduling emission includes matching the thread-block / thread in the instruction and the SM / SP in the GPGPU hardware according to the extracted instruction information, and sending information to the emission unit in units of warps integrated with multiple threads.

6. The method according to claim 5, characterized in that The transmitting unit is used to send information to the corresponding SM / SP hardware for execution.

7. The method according to claim 2, characterized in that The branch preprocessing includes sequential execution if it is a general instruction; If it is a branch execution, the relevant branch instruction block information is stored and sent to the branch scheduling unit. The branch scheduling unit receives the branch instruction block information sent by multiple warps, bundles it into a new warp, and releases the original hardware execution unit SM / SP at the same time, and allocates the new warp to the released SM / SP.

8. The method according to claim 7, characterized in that The operation execution includes executing the instructions sent to the SM / SP and feeding back the instruction execution status to the scoreboard.

9. The method according to claim 8, characterized in that The write-back refresh includes receiving execution information from the execution unit and sending the execution information to the scheduling unit so that the scheduling unit can schedule the next instruction.

10. A storage medium storing program instructions, characterized in that: When the program instructions are run, the GPGPU branch instruction scheduling method based on the multi-level reallocation mechanism is executed as described in any one of claims 1 to 9.

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