Safe operating area protected switch for high resistive off mode

Abstract

A switch circuit has a transistor switch (305, 353, 401, 451, 501) and a first MOS transistor (T1, T3, 505), both of a first type, and a second MOS transistor (T2, T4, 517) of a second type that is complementary to the first type, wherein the first type is an NFET or a PFET. The transistor switch (305, 353, 401, 451, 501) has a source (311, 355, 515), a drain (309, 359, 516), and a gate (503), wherein the gate (503) is connected to a first control signal (307, 403, 453, 503) having at least a first voltage state for turning the transistor switch (305, 353, 401, 451, 501) on and a second voltage state for turning the transistor switch (305, 353, 401, 451, 501) off. The first MOS transistor (T1, T3, 505) has a first non-gate terminal (507) connected to receive a second control signal (405, 455, 509), a gate terminal (511) connected to a voltage source that supplies a DC bias voltage, and a second non-gate terminal (513) connected to a first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) that is one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501). The second control signal (405, 455, 509) has at least a first voltage state that is inversely related to the first voltage state of the first control signal (307, 403, 453, 503) and a second voltage state that is inversely related to the second voltage state of the first control signal (307, 403, 453, 503). The second MOS transistor (T2, T4, 517) has a first non-gate terminal (519) connected to receive the second control signal (405, 455, 509); a gate terminal (521) connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal (523) connected to the first terminal of the transistor switch (305, 353, 401, 451, 501). When the first type is the NFET, then the DC bias voltage is less than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and greater than the second voltage state of the first control signal (307, 403, 453, 503); and when the first type is the PFET, then the DC bias voltage is greater than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and less than the second voltage state of the first control signal (307, 403, 453, 503).

Description

[0001] SAFE OPERATING AREA PROTECTED SWITCH FOR HIGH RESISTIVE OFF MODE

[0002] BACKGROUND

[0003] The present invention relates to transistor switches, and more particularly to circuit arrangements for ensuring that transistor switches maintain operation within a safe operating area during off mode when employed in high frequency applications.

[0004] Some or all of the following abbreviations are used in this specification:

[0005] Abbreviation Explanation

[0006] ADPLL All Digital Phase Locked Loop

[0007] DCO Digitally Controlled Oscillator

[0008] LO Local Oscillator

[0009] MOM Metal Oxide Metal

[0010] MIMO Multiple Input, Multiple Output

[0011] PLL Phase-Locked Loop

[0012] PVT Process, Voltage, and Temperature

[0013] S / D Source / Drain

[0014] SOA Safe Operating Area

[0015] VG Gate Voltage

[0016] VT Threshold Voltage

[0017] Wireless communication technologies continue to evolve to meet the demand for increased data throughput. This is addressed on many levels with different approaches including higher order modulation, MIMO, scheduling, increased bandwidth, and so on. Higher carrier frequencies, and mmW frequencies in particular, have attracted a lot of interest because there are larger blocks of continuous spectra available, up to several tens of GHz. A mmW-based air interface targeting frequencies up to 7. IGhz is an important component of the 5G New Radio Frequency Range 2 standard (5G NR FR2).

[0018] For the purpose of up-conversion of signals from baseband or intermediate frequencies to these higher carrier frequencies and for down-conversion from these higher carrier frequencies to baseband or intermediate frequencies, there is a need for a local oscillator (LO) generation circuit, commonly in the form of a phase-locked loop (PLL). The PLL produces frequencies from which the final LO frequency is generated. The PLL contains an oscillator core, most commonly one configured as an LC-tank with negative gain.

[0019] To illustrate this point, Figure 1 is a schematic diagram of a local oscillator 100 having a cross-coupled pair of transistors 101 and an inductor-capacitor (LC) tank 103. The LC-tank 103 has a fixed inductance 105 and a variable capacitance 107 for frequency control. The variable capacitance 107 is used for tuning. Oscillators 100 such as this are typically part of a frequency synthesizer 109, such as a PLL, in which the oscillator 100 is tuned to generate the correct frequency.

[0020] The standard solution for a high frequency oscillator is a cross coupled common source core comprising a fixed metal inductance 105 and a variable capacitance bank 107, as shown in Figure 1. The capacitance bank 107 can be configured as, for example, a plurality of capacitor circuits connected in parallel, with a switching circuit being employed (e.g., a switch connected in series with each capacitor) to selectively engage or disable particular ones of the capacitor circuits in order to achieve a desired level of capacitance.

[0021] A capacitor bank can be used in other blocks as well where there is a need for such actions as calibration, trimming, or tuning (e.g., in a filter).

[0022] The capacitance range has three main objectives:

[0023] Coverage of a large range of selectable operating frequencies with a high spectral purity.

[0024] Removal of the process, voltage, and temperature (PVT) variation of the unlocked PLL by coarse calibration

[0025] Fine tuning to remove the errors in the locked PLL

[0026] All of the above can be achieved with one common or several different capacitor banks 107. A Metal -Oxi de-Metal (MOM) capacitor bank is often used for achieving coarse calibration.

[0027] As mentioned above, different capacitors can be selectively engaged and disengaged in a capacitor bank 107 by means of switches. Figure 2A is a circuit diagram illustrating one known capacitor / switch arrangement in which the source and drain of an NFET switch 201 are maintained at inverse levels relative to the gate voltage. In the exemplary circuit, this is achieved by means of an inverter 203 for producing a gate control signal (Ctrl) from a source / drain voltage (Ctrl b). The reason for maintaining this inverse relationship is to achieve maximum conductance when the switch 201 is switched on and a minimum conductance when switched off. The resistance R1 and R2 to the source and drain, respectively, needs to be sufficiently large to avoid degradation of the Q-value of the LC tank when the switch 201 is in an off-state. Those skilled in the art will recognize that in alternative embodiments, a PFET switch can be substituted in place of the NFET switch with straightforward adaptations made to account for different biasing and on / off control signal requirements.

[0028] There are a number of ways that a biasing voltage can be supplied to the source and drain (S / D) nodes to maintain an optimal switch conductance state, regardless of whether it should be a fixed or variable bias voltage. The following are a few non-limiting examples that assume the presence of an NFET switch. PFET embodiments are easily derivable using flipped / reversed logic.

[0029] One possibility is the use of high resistive resistors, as already shown with reference to

[0030] Figure 2A. Alternative embodiments include: o Connection to a control signal (as illustrated). o Maintenance at a fixed biasing voltage (e.g., ground).

[0031] Another option involves the use of the switch’s gate control to also control one pair of NFETs and one pair of PFETs, connecting the S / D nodes to ground or supply for the respective on- and off-states of the switch. (In practice, this would involve the use of two inverters.)

[0032] Another possibility is to use the switch’s gate control to also control one pair of NFETs, where the switch’s on-state provides bias to low voltage, while the off-state provides only leakage to the same voltage. o The on-state can either be a fixed setting (with or without resistors in parallel) or a short pulse (with resistors in parallel).

[0033] Another possibility is to use the switch’s gate control to also control two pairs of NFETs, one for use during the switch’s on-state, and the other for the off-state. The pairs are configured such that the switch’s on-state pair provides bias to a low voltage at the switch’s drain and source, while the off-state pair provides a high voltage.

[0034] Another option employs an NFET pair that is always kept in an off-state, regardless of whether the switch is on or off. The NFET pair in this embodiment provides bias to the switch’s drain and source only through leakage.

[0035] Another possibility uses the switch’s gate control to also control one pair of NFETs that bias the respective source and drain nodes of the switch during its on-state, while a pair of resistors are switched in for the off-state in order to provide a high bias voltage. Another possibility involves applying a control signal at the source of each one of a pair of NFETs (one NFET for biasing the switch’s drain and the other for biasing the switch’s source). To enable the control signal at the source to control the on / off state of each NFET and thereby provide for two different biasing states, the gate of each NFET is biased by VDD. During the switch’s on-state, the source and drain nodes are forced to a low voltage with a low voltage control value being applied at each NFET’s source terminal. For the switch’s off-state, a high voltage control value at the source of each NFET sets each NFET in the pair in a sub-threshold, high-ohmic state that provides a high voltage bias to the switch’s source and drain nodes.

[0036] The inventor of the subject matter described herein has determined, through investigation and inventive skill, that a problem arises in connection with the Safe Operating Area (SOA) performance of a MOS switch when used to control a circuit branch having a Metal Oxide Metal (MOM) capacitor. The switch will ideally have a low peak voltage and high current in its on- state, while the peak voltage will be high and the current low in its off-state. It is during the off- state that the switch risks being exposed to SOA limits due to the high peak voltage. It is therefore important to have an efficient way of controlling both states so that a high Q is maintained in the on-state, and maintenance within the switch’s SOA in the off-state.

[0037] The safe operating area for any given MOS transistor is influenced by a number of factors, including its size and geometry. For high operating frequencies (e.g., mmW frequencies), there is a need for structures to be physically small in order to avoid (or at least minimize) parasitic inductance and capacitance. Considering some of the above-described approaches for maintaining an optimal switch conductance state, the use of resistors will be physically too large to be able to let the switch transistor determine the off resistance of the capacitor cell. See, for example:

[0038] Henrik Sj bland, “Improved Switched Tuning of Differential CMOS VCOs”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS— II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 5, MAY 2002, pages 352-355

[0039] Peeyoosh Mirajkar et al., “Low Phase Noise Ku-Band VCO With Optimal Switched- Capacitor Bank Design”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 3, MARCH 2018, pages 589-593 Yanlu Wang et al., “Ultralow Power, 3.15mW, 76.7 GHz Digitally Controlled Oscillator in 65 nm CMOS for High Data-Rate Application”, Proceedings of the 14th European Microwave Integrated Circuits Conference, pages 5-8; and Pietro Andreani et al., “A TX VCO for WCDMA / EDGE in 90 nm RF CMOS”, IEEE

[0040] JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7, JULY 2011, pages 1618-

[0041] 1626

[0042] Looking at other approaches, designs that provide a constant on-connection or a leakage off-connection to ground (in the NFET switch case) have been described. See, for example:

[0043] Hamed Abbasizadeh et al., “260-pW DCO With Constant Current Over PVT Variations Using FLL and Adjustable LDO”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS— II: EXPRESS BRIEFS, VOL. 65, NO. 6, JUNE 2018, pages 739-743 Li, Yun-kun, Jieyang Li and Zhi-liang Hong. “A 23-30.8 GHz Digital-Controlled- Oscillator in 28nm CMOS”, 2018 14th IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) 2018, pages 1-3.

[0044] But to get the best on / off relation with respect to switch resistance, the source and drain nodes of the MOS switch each need to toggle inversely with respect to the gate voltage. Therefore, the constant on-connection / leakage off-connection solutions are therefore not optimal.

[0045] An inverse toggling of source and drain node voltage based on gate voltage can be implemented by adding an inverter to each node. Due to the need to have an acceptable on / off Q, the size relation between the NFET and PFET transistors in the inverter needs to be such that the NFET in the inverter will be much larger than the PFET. This makes the overall switch structure larger than necessary and degrades the overall Q. Moreover, merely adding a toggle in this manner does not prevent SOA issues. See, for example, Deyuan Lin et al., “An 11.7-17.2GHz digitally-controlled oscillator in 65nm CMOS for high-band UWB applications, 2012”, IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY, pages 1-3.

[0046] The PFET of the inverter can be replaced by an NFET connected as a voltage follower with a VBIAS as gate voltage. When the MOS switch is in its off-state, the source and drain nodes will be pinned to the lowest voltage, corresponding to VG-VT. As a result, the operating DC point will be set by VBIAS and the peak voltage. The system needs a bias voltage to operate because VDD on the gate will generate a DC value higher than VDD on the source and drain nodes. For more information about this, see Benjamin Hershberg et al., “A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction”, ESSCIRC 2014 - 40TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pages 83-86.

[0047] The toggling of the source and drain nodes relative to the switch’s gate can be done as illustrated in Figure 2B, using one pair of NFETs 205, 207, each having a control signal (Ctrl b) 209 connected to its source instead of to the gate (as in other arrangements). Further, the control signal 209 for each NFET 205, 207 is inverse to the control signal 211 applied at the gate of the transistor switch 213, while the gate of each NFET 205, 207 is fixed at a DC level, vbias (e.g., = VDD). With this arrangement, the on / off state of each NFET 205, 207 will be controlled by the state of the control signal 209. When the transistor switch 213 is on, its control signal 211 is high and the control signal 209 applied at the source of each NFET 205, 207 is therefore low (e.g., = Vss). This turns on each NFET 205, 207, and the outputs of the NFETs 205, 207 then pull the respective source and drain nodes of the transistor switch 205 to the low value of the control signal 209, and this is the DC operating point of the transistor switch 213 when an AC signal passes through it.

[0048] In the switch’s off-state, its control signal 211 assumes a low value which means that the control signal 209 at the source of each NFET 205, 207 assumes a high value (e.g., = VDD) and VGS is zero. This puts each NFET 205, 207 into a high ohmic state. Consequently, the source and drain nodes of the transistor switch 213 are, in this instance, connected to vbias (e.g., = VDD).

[0049] A problem with an embodiment like that shown in Figure 2B is that, when the transistor switch 213 is in an off-state, the operating DC point is set by the gate voltage of the NFETs 205, 207 (=VDD) and the peak voltage swing of an AC signal applied across the nodes marked Osc_p and Osc n. In other words, the lowest voltage within the period is set to VG(=VDD)-VT, and this makes the source and drain nodes of the transistor switch 213 rise higher than vbias (VDD) during other parts of the period. This risks generating SOA issues for high amplitudes of the AC signal because, with VG at a low (off-state) value, very high voltages at the source and drain nodes result in very high values of VGS and VGD, respectively, and this is not very well controlled in the circuit of Figure 2B. This is illustrated in the solid line curves, such as the curve 701, shown in Figure 7. There it can be seen that each curve has a minimum value in a region near 0.7V, so that the higher the amplitude of the AC signal, the higher the maximum value (e.g., approximately 1.56V for the curve 701). But notably, not only is the peak value of each solid-line curve higher for a given AC signal, the DC operating point becomes higher with larger signals, as shown at 703. For a discussion of this problem, see, for example, Lantao Wang et al., “An 8.2-10.2 GHz Digitally Controlled Oscillator in 28-nm CMOS Using Constantly-Conducting NMOS Biased Switchable Capacitor”, 2022 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, pages 207-210.

[0050] In view of the foregoing, there is a need for technology that addresses the abovedescribed and related problems, including but not limited to problems associated with providing the best conductance state of a MOS transistor switch while maintaining high Q and also maintaining operation of the MOS transistor within its SOA.

[0051] SUMMARY

[0052] It should be emphasized that the terms “comprises” and “comprising”, when used in this specification, are taken to specify the presence of stated features, integers, steps or components; but the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0053] Moreover, reference letters may be provided in some instances (e.g., in the claims and summary) to facilitate identification of various steps and / or elements. However, the use of reference letters is not intended to impute or suggest that the so-referenced steps and / or elements are to be performed or operated in any particular order.

[0054] In accordance with one aspect of the present invention, the foregoing and other objects are achieved in technology (e.g., methods, apparatuses, nontransitory computer readable storage media, program means) in which DC voltage levels at the drain and / or source of a transistor switch are controlled during the switch’s off-state.

[0055] In some but not necessarily all inventive embodiments, a switch circuit is provided that comprises a transistor switch of a first type, a first MOS transistor also of a first type, and a second MOS transistor of a second type that is complementary to the first type, wherein the first type is selected from an N-channel Field Effect Transistor, NFET, and a P-channel Field Effect Transistor, PFET. The transistor switch has a source, a drain, and a gate, wherein the gate of the transistor switch is connected to a first control signal having at least a first voltage state for turning the transistor switch on and a second voltage state for turning the transistor switch off.

[0056] The first MOS transistor comprises a first non-gate terminal connected to receive a second control signal, wherein the second control signal has at least a first voltage state that is inversely related to the first voltage state of the first control signal and a second voltage state that is inversely related to the second voltage state of the first control signal; a gate terminal connected to a voltage source that supplies a DC bias voltage; and a second non-gate terminal connected to a first terminal of the transistor switch that is one of the source of the transistor switch and the drain of the transistor switch.

[0057] The second MOS transistor comprises a first non-gate terminal connected to receive the second control signal; a gate terminal connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal connected to the first terminal of the transistor switch.

[0058] When the first type is the NFET, then the DC bias voltage is less than or equal to the first voltage state of the first control signal and greater than the second voltage state of the first control signal; and when the first type is the PFET, then the DC bias voltage is greater than or equal to the first voltage state of the first control signal and less than the second voltage state of the first control signal.

[0059] In another aspect of some but not necessarily all inventive embodiments, the switch circuit comprises a first capacitor having one terminal connected to the first terminal of the transistor switch.

[0060] In yet another aspect of some but not necessarily all inventive embodiments, a second terminal of the transistor switch is an other one of the source of the transistor switch and the drain of the transistor switch, different from the first terminal of the transistor switch; and the second terminal of the transistor switch is connected to a reference voltage.

[0061] In still another aspect of some but not necessarily all inventive embodiments, a second terminal of the transistor switch is an other one of the source of the transistor switch and the drain of the transistor switch, different from the first terminal of the transistor switch, and the switch circuit comprises a third MOS transistor of the first type and a fourth MOS transistor of the second type. The third MOS transistor comprises a first non-gate terminal connected to receive the second control signal; a gate terminal connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal connected to the second terminal of the transistor switch. The fourth MOS transistor of the second type, wherein the fourth MOS transistor comprises a first non-gate terminal connected to receive the second control signal; a gate terminal connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal connected to the second terminal of the transistor switch.

[0062] In another aspect of some but not necessarily all inventive embodiments, the second voltage state of the second control signal is equal to the DC bias voltage.

[0063] In still another aspect of some but not necessarily all inventive embodiments, a capacitor bank is provided that comprises a plurality of capacitor circuits connected in parallel, wherein at least one of the capacitor circuits comprises a capacitor having a terminal connected to the first terminal of the transistor switch of the switch circuit according to any one of the previous embodiments.

[0064] In yet another aspect of some but not necessarily all inventive embodiments, the capacitor bank is comprised in an Inductor-Capacitor (LC) tank circuit that also comprises at least one inductor connected in parallel with the capacitor bank.

[0065] In still another aspect of some but not necessarily all inventive embodiments, the LC tank circuit compresses first and second connection points and is comprised in an oscillator circuit that also comprises a pair of cross-coupled transistors, wherein each of the cross-coupled transistors has an output terminal connected to a respective one of the first and second connection points of the tank circuit.

[0066] In another aspect of some but not necessarily all inventive embodiments, the oscillator circuit is comprised in a radio communication device.

[0067] In yet another aspect of some but not necessarily all inventive embodiments, the radio communication device is one of: a base station transceiver in a mobile communications system; and a user equipment for use in the mobile communications system.

[0068] In an aspect of some but not necessarily all inventive embodiments, a method of operating a transistor switch of a first type is provided, wherein the first type is selected from an NFET and a PFET; wherein the transistor switch has a source, a drain, and a gate; and wherein the gate of the transistor switch is connected to a first control signal having at least a first voltage state for turning the transistor switch on and a second voltage state for turning the transistor switch off. The method comprises turning on a first MOS transistor of the first type in response to the first control signal having the first voltage state, and while the first MOS transistor is turned on, using the first MOS transistor of the first type to supply a first DC bias voltage to a first terminal of the transistor switch in response to the first control signal having the first voltage state, wherein the first terminal of the transistor switch is one of the source of the transistor switch and the drain of the transistor switch. Additionally, the first MOS transistor is turned off in response to the first control signal having the second voltage state and while the first MOS transistor is turned off, the first MOS transistor is used to supply a second DC bias voltage to the first terminal of the transistor switch. A second MOS transistor of a second type that is complementary to the first type is used to maintain the second DC bias voltage at the first terminal of the transistor switch in response to the first control signal having the second voltage state, wherein maintaining the second DC bias voltage at the first terminal of the transistor switch comprises supplying the second DC bias voltage to a gate of the second MOS transistor and to a source of the second MOS transistor; and using a drain of the second MOS transistor to sense a deviation in voltage at the first terminal of the transistor switch and turning on the second MOS transistor in response to the deviation, wherein the deviation in voltage at the second nongate terminal of the second MOS transistor is one of: a positive deviation in voltage relative to the second DC bias voltage when the second type is a PFET; and a negative deviation in voltage relative to the second DC bias voltage when the second type is an NFET.

[0069] In yet another aspect of some but not necessarily all inventive embodiments, when the first type is the NFET, then the second DC bias voltage is less than or equal to the first voltage state of the first control signal and greater than the second voltage state of the first control signal; and when the first type is the PFET, then the second DC bias voltage is greater than or equal to the first voltage state of the first control signal and less than the second voltage state of the first control signal.

[0070] In still another aspect of some but not necessarily all inventive embodiments, operating the transistor switch comprises supplying the second DC bias voltage to a gate of the first MOS transistor and to a gate of the second MOS transistor.

[0071] In another aspect of some but not necessarily all inventive embodiments, using the first MOS transistor to supply the second DC bias voltage to the first terminal of the transistor switch comprises: supplying the second DC bias voltage to a source of the first MOS transistor; and using a drain of the first MOS transistor to sense a deviation in voltage at the first terminal of the transistor switch and turning on the first MOS transistor in response to the deviation, wherein the deviation in voltage at the drain of the first MOS transistor is one of: a negative deviation in voltage relative to the second DC bias voltage when the first type is an NFET; and a positive deviation in voltage relative to the second DC bias voltage when the first type is a PFET.

[0072] In yet another aspect of some but not necessarily all inventive embodiments, operating the transistor switch comprises generating a second control signal having at least a first voltage state that is inversely related to the first voltage state of the first control signal and a second voltage state that is inversely related to the second voltage state of the first control signal; and using the first voltage state of the second control signal as a supply source of the first DC bias voltage; and using the second voltage state of the second control signal as a supply source of the second DC bias voltage.

[0073] In another aspect of some but not necessarily all inventive embodiments, operating the transistor switch comprises causing a gate-to- source voltage of the second MOS transistor to be zero in response to the first control signal having the second voltage state.

[0074] BRIEF DESCRIPTION OF THE DRAWINGS

[0075] The objects and advantages of the invention will be understood by reading the following detailed description in conjunction with the drawings in which:

[0076] Figure 1 is a schematic diagram of a local oscillator having a cross-coupled transistor pair and an LC tank.

[0077] Figure 2A is a circuit diagram illustrating one known capacitor / switch arrangement in which the source and drain of an NFET switch are maintained at inverse levels relative to the gate voltage.

[0078] Figure 2B is a circuit diagram illustrating how a toggling of the source and drain nodes relative to a switch’s gate can be done, using one pair of NFETs each having a control signal connected to its source.

[0079] Figure 3 A is a schematic diagram of an exemplary embodiment that illustrates some inventive aspects.

[0080] Figure 3B is a schematic diagram that illustrates an alternative, single-ended embodiment in accordance with inventive aspects, in which the capacitor circuit has only one capacitor connected in series with an NFET switch transistor.

[0081] Figure 4A is a schematic diagram of a circuit for providing DC bias voltage levels at the source and drain of an NFET switch, one level for when the NFET switch is on, and another for when it is off.

[0082] Figure 4B is a schematic diagram of a circuit for providing DC bias voltage levels at the source and drain of a PFET switch, one level for when the PFET switch is on, and another for when it is off.

[0083] Figure 5 is a schematic diagram of an exemplary generic embodiment of inventive aspects, such as might be used in, to cite an example and without limitation, a radio communication device. Figure 6 is, in one respect, a flowchart of actions performed by circuitry that operates a transistor switch of a first type selected from an NFET and a PFET.

[0084] Figure 7 is a series of graphs that illustrate performance differences between conventional and inventive embodiments with respect to the drain-to-source voltage (VDS) across a transistor switch in a capacitor circuit of an LC tank when it is in its “of ’-state.

[0085] DETAILED DESCRIPTION

[0086] The various features of the invention will now be described with reference to the figures, in which like parts are identified with the same reference characters.

[0087] The various aspects of the invention will now be described in greater detail in connection with a number of exemplary embodiments. To facilitate an understanding of the invention, many aspects of the invention are described in terms of sequences of actions to be performed by elements of a computer system or other hardware capable of executing programmed instructions. It will be recognized that in each of the embodiments, the various actions could be performed by specialized circuits (e.g., analog and / or discrete logic gates interconnected to perform a specialized function), by one or more processors programmed with a suitable set of instructions, or by a combination of both. The term “circuitry configured to” perform one or more described actions is used herein to refer to any such embodiment (i.e., one or more specialized circuits alone, one or more programmed processors, or any combination of these). Moreover, the invention can additionally be considered to be embodied entirely within any form of non- transitory computer readable carrier, such as solid-state memory, magnetic disk, or optical disk containing an appropriate set of computer instructions that would cause a processor to carry out the techniques described herein. Thus, the various aspects of the invention may be embodied in many different forms, and all such forms are contemplated to be within the scope of the invention. For each of the various aspects of the invention, any such form of embodiments as described above may be referred to herein as “logic configured to” perform a described action, or alternatively as “logic that” performs a described action.

[0088] Embodiments that include one or more aspects of the invention variously relate to, and include technology for, maintaining the SOA performance of a MOS transistor switch when used for, to take an example, engaging and disengaging a capacitance in the presence of a high frequency (e.g., 20-40GHz) AC signal (e.g., in the digital capacitive frequency control of a Digitally Controlled Oscillator (DCO)) without compromising the Q-value of the capacitive frequency control. The DCO can be part of, for example, an ADPLL (All Digital Phase Locked Loop) frequency synthesizer. The technology is advantageously put to use in a frequency synthesizer that provides a wide frequency range with a high spectral purity. The frequency control can be provided using one or several controlled capacitor banks.

[0089] Various aspects of inventive embodiments enable a high ohmic, area efficient off-control of the source and drain of a transistor switch, giving a reliable DC operation of the transistor switch in both its off and on states, so that operation in the SOA is maintained in the off-state and the Q-value of both on and off-states are not degraded.

[0090] In an aspect of inventive embodiments, a DC bias having a voltage level that is complementary to the gate voltage is applied to at least one of the source and drain nodes of a transistor switch.

[0091] In another aspect of inventive embodiments, a complementary, parallel connected transistor pair (i.e., an NFET in parallel with a PFET) is provided for each of the transistor switch’s non-gate terminals (i.e., one or both of the source and drain terminals) to which an on / off state-dependent bias is to be applied. The gates of each transistor in the pair are biased at a fixed, supply voltage level that is the same as or related to the “turn on” voltage of the transistor switch (e.g., Vdd or other high voltage when the transistor switch is an NFET; Vss or other low when the transistor switch is a PFET). This permits the on / off state of each transistor in the pair to be controlled by a same control signal having a voltage state that is complementary to the gate voltage of the transistor switch, and that fluctuates between the supply voltage level and a reference voltage level (e.g., Vss when the transistor switch is an NFET; Vdd when the transistor switch is a PFET). With this arrangement, it will be recognized that a first transistor of the pair that has the same type (NFET or PFET) as that of the transistor switch will be turned on and off in states that are aligned with the on / off state of the transistor switch. At the same time, a second transistor of the pair having a type that is complementary to that of the type of the transistor switch will remain off at all times, with the “off’ state being either very sturdy (i.e., Vgs 0; this occurs when the transistor switch is on) or less so (i.e., Vgs = 0; this occurs when the transistor switch is off).

[0092] Thus, for example, in the case of an NFET as the transistor switch, a first transistor that is an NFET is paired with an always-off complementary second transistor that is a PFET. The turn on voltage of the main switch is high, so the bias voltage of the gates of the first and second transistors is also high.

[0093] Alternatively, in the case of a PFET as the transistor switch, a first transistor that is a PFET is paired with an always-off complementary second transistor that is an NFET. The turn on voltage of the main switch is low, so the bias voltage of the gates of the first and second transistors is also low.

[0094] These and other aspects of embodiments consistent with the invention are now described in further detail.

[0095] Figure 3 A is a schematic diagram of an exemplary embodiment that illustrates some inventive aspects. A capacitor circuit 301 is one of a plurality of such circuits connected in parallel to form a capacitor bank 303. The capacitor circuit 301 comprises, in series, a first capacitor Cl, a transistor switch 305, and a second capacitor C2. In this class of embodiments, the transistor switch 305 is an NFET having on / off states controlled by a first control signal 307 applied to the switch’s gate, with the first control signal 307 having a first state for turning the transistor switch 305 on, and a second state for turning the transistor switch 305 off.

[0096] In addition to its gate, the transistor switch has two non-gate terminals, one being its source and the other being its drain. A first non-gate terminal 309 of the transistor switch 305 is connected to drains of a first pair of complementary transistors (NFET and PFET pair) 313 connected in parallel, while similarly, a second non-gate terminal 311 of the transistor switch 305 is connected to the drains of a second pair of complementary transistors (NFET and PFET pair) 315 connected in parallel. The gates of all transistors that make up the first and second pairs of complementary transistors 313, 315 are connected to a DC bias level, denoted “vbias” in the figure. The value of vbias is fixed, and may for example be equal to VDD when the transistor switch 305 is an NFET as shown.

[0097] The sources of all transistors that make up the first and second pairs of complementary transistors 313, 315 are connected to a second control signal 317 having two voltage states that are complementary to the two voltage states of the first control signal 307. So, for example, when the first control signal is asserted at a high voltage level, thereby turning on the transistor switch 305, the second control signal assumes a low voltage level that turns on the NFET in each transistor pair 313, 315 because the gates of all transistors in the transistor pairs 313, 315 are tied to a high voltage level (vbias). The PFETs in the transistor pairs 313, 315 remain off under these conditions.

[0098] When the first control signal assumes a low voltage level, thereby turning off the transistor switch 305, the second control signal assumes a high voltage level (e.g., equal to or near VDD) that turns off the NFET in each transistor pair 313, 315 because the gates of all transistors in the transistor pairs 313, 315 are tied to a high voltage level, so the gate and source voltages are, or are nearly, equal (i.e., Vgs=0). Although the second control signal has changed its state to a high voltage level, the PFETs continue to remain nominally off because its gate and source voltages are, or are nearly, equal (i.e., Vgs=0).

[0099] With the NFET and PFET in each transistor pair 313, 315 biased in an “off’-state in this way,, when an AC signal is present at the non-gate terminals 309, 311 (e.g., source and drain nodes) of the transistor switch 305, a deviation in voltage that is higher than the drain voltage of a PFET at either non-gate terminal 309, 311 of the transistor switch 305 will result in the connected PFET turning on to some degree, and this will cause the DC bias voltage applied at that non-gate terminal 309, 311 to be held at, or near, the voltage level at the source of the PFET. Similarly, when the AC signal at the non-gate terminals 309, 311 (e.g., source and drain nodes) of the transistor switch 305 deviates to a lower voltage than the drain voltage of an NFET at either non-gate terminal 309, 311 of the transistor switch 305, the connected NFET turns on to some degree, and this will likewise cause the DC bias voltage applied at the non-gate terminal 309, 311 to be held at, or near, the voltage level at the source of the NFET, which is the same as the voltage level at the source of the PFET. In this way, each NFET and PFET in a transistor pair senses a respective downward and upward deviation in DC voltage at the transistor switch terminal and responds by turning on. The NFET wants to pull up the VD / VS of the switch terminal it is connected to, while the PFET wants to pull it down. The result is that they settle on the common DC bias voltage.

[0100] Figure 3B illustrates an alternative, single-ended embodiment in which the capacitor circuit has only one capacitor Cl connected in series with an NFET switch transistor 353. Since one non-gate terminal 355 of the NFET switch 353 is tied to Vss, only one complementary transistor pair 357 is required to maintain a safe bias at the other non-gate terminal 359 of the transistor switch 353. But remaining aspects are the same as described above with respect to Figure 3 A.

[0101] It is further noted that in alternative embodiments, the transistor switch is a PFET instead of an NFET as used in the above described examples. In these classes of embodiments, the connections are the same as described above, but with voltage levels essentially reversed to enable PFET-based operation. In such embodiments, the PFETs in the complementary transistor pairs operate to maintain a desirable DC bias level when the main, PFET switch is turned on, and the NFETs in the complementary transistor pairs operate to maintain a safe DC bias level when the main, PFET switch is turned off.

[0102] In the embodiments of Figures 3 A and 3B or in the complementary versions based on Figures 3A and 3B (i.e., in which the main switch is a PFET), a stable on and off bias is applied to the source and drain (or just drain, in single-ended embodiments) of the main switch. In the switch’s on stage, the DC operating point will be equal to the voltage level of the second control signal 317, which is the low voltage (e.g., Vss) for NFET switches and high voltage (e.g., VDD) for PFET switches. In the off stage, the DC operating point will be equal to the voltage level of the second control signal 317, which is the high voltage vbias (with Vss<vbias < VDD) for NFET switches, and the low voltage vbias (with VDD>vbias>Vss) for PFET switches.

[0103] In all embodiments, the second control signal 317 is an inverted signal, voltage levelwise, with respect to that of the first control signal 307 (i.e., when the first control signal is high, the second control signal is low, and vice versa). The second control signal 317 can have a limited range between its high and low levels compared to that of the first control signal 307. For example, in the case of the transistor switch being an NFET, the range of the second control signal 317 can span between Vss and the voltage, vbias, applied to the gates of the transistor pairs 313, 315. In the case of the transistor switch being a PFET the control range is between vbias and VDD, where vbias > Vss.

[0104] Further aspects of embodiments consistent with the invention will now be described with reference to a few concrete examples. Figure 4A is a schematic diagram of a circuit for providing DC bias voltage levels at the source and drain of an NFET switch 401, one level for when the NFET switch 401 is on, and another for when it is off. The NFET switch 401 is connected in series with two capacitors that are switched in and out of a capacitor bank in dependence on a signal, Z that is asserted at a high level when the two capacitors are to be switched into the capacitor bank, and asserted at a low level otherwise. The on / off state of the NFET switch 401 is controlled by a first control signal 403 supplied to the gate of the NFET switch 401.

[0105] To ensure that the first control signal 403 will have two voltage states that are Vdd (when high) and Vss (when low), the capacitor control signal Z is passed through two inverters connected in series, with the first inverter constituted by complementary MOS transistors N5 and P5, and the second inverter constituted by complementary MOS transistors N6 and P6. The output of the second inverter is the first control signal 403.

[0106] To generate a second control signal 405 having voltage states that are the inverse of those of the first control signal 403 (i.e., when the first control signal 403 has a high voltage level, the second control signal 405 has a low voltage level, and when the first control signal 403 has a low voltage level, the second control signal 405 has a high voltage level), the first control signal 403 is supplied to the input of a third inverter that is constituted by complementary MOS transistors N1 and Pl. The third inverter is configured to generate the second control signal 405 such that it can toggle between a low state equal to Vss, and a high state that is equal to Vbias n that may, but need not be equal to Vdd.

[0107] The DC bias voltage for the drain of the NFET switch 401 is supplied by a first pair of first (Tl) and second (T2) MOS transistors that are complementary to one another, while the DC bias voltage for the source of the NFET switch 401 is supplied by a second pair of third (T3) and fourth (T4) MOS transistors that are complementary to one another. The gates of the MOS transistors Tl, T2, T3, T4 are all tied to the high voltage, Vbias n, so that the on / off states of the NFET transistors Tl, T3 are controlled by the second control signal 405 applied at the respective sources of these transistors. When the NFET switch 401 is “on”, its gate voltage is high and, in this arrangement, this makes the second control signal 405 assume a low level equal to Vss. The NFET transistors Tl, T3 then turn on, and this causes Vss to be applied, from the drains of NFETs Tl, T3, to the respective drain and source of the NFET switch 401.

[0108] It will be observed that the PFET transistors T2, T4 are biased “off’ regardless of the voltage level of the second control signal 405. However, when the NFET switch 401 is off, its gate voltage is low, which causes the second control signal 405 to assume its high level (Vbias n). When the second control signal 405 has its high voltage state, the gate-to-source voltage, Vgs, of the PFET transistors T2, T4 is equal to zero, which makes these transistors sensitive to upward voltage swings applied at their drains (i.e., they can start to conduct current when there is such an upward deviation in voltage). This enables the PFET transistors T2, T4 to tie the DC bias level at the source and drain of the transistor switch 401 to, in this embodiment, Vbias_n when the NFET switch 401 is turned on.

[0109] Turning now to an embodiment involving MOS transistor types that are complementary to those just illustrated in Figure 4A, Figure 4B is a schematic diagram of a circuit for providing DC bias voltage levels at the source and drain of a PFET switch 451, one level for when the PFET switch 451 is on, and another for when it is off. The PFET switch 451 is connected in series with two capacitors that are switched in and out of a capacitor bank in dependence on a signal, Z that is asserted at a high level when the two capacitors are to be switched into the capacitor bank, and asserted at a low level otherwise. The on / off state of the PFET switch 451 is controlled by a first control signal 453 supplied to the gate of the PFET switch 451.

[0110] To ensure that the first control signal 453 will have two voltage states that are Vdd (when high) and Vss (when low), and also to provide for the fact that the first control signal 453 needs to have voltage states that are the inverse of those of the capacitor control signal Z, the capacitor control signal Z is passed through an inverter constituted by complementary MOS transistors N3 and P3. The output of the first inverter is the first control signal 453.

[0111] To generate a second control signal 455 having voltage states that are the inverse of those of the first control signal 453 (i.e., when the first control signal 453 has a high voltage level, the second control signal 455 has a low voltage level, and when the first control signal 453 has a low voltage level, the second control signal 455 has a high voltage level), the first control signal 453 is supplied to the input of a second inverter that is constituted by complementary MOS transistors N2 and P2. The second inverter is configured to generate the second control signal 455 such that it can toggle between a low state equal to Vbias_p, and a high state that is equal to Vdd. The voltage Vbias_p may, but need not be equal to Vss.

[0112] The DC bias voltage for the source of the PFET switch 451 is supplied by a first pair of complementary MOS transistors T1 and T2, while the DC bias voltage for the drain of the PFET switch 451 is supplied by a second pair of complementary MOS transistors T3 and T4. The gates of the MOS transistors Tl, T2, T3, T4 are all tied to a low voltage, Vbias_p, so that the on / off states of the PFET transistors Tl, T3 are controlled by the second control signal 455 applied at the respective sources of these transistors. When the PFET switch 451 is “on”, its gate voltage is low and, in this arrangement, this makes the second control signal 455 assume a high level equal to Vdd. The PFET transistors Tl, T3 then turn on, and this causes Vdd to be applied, from the drains of PFETs Tl, T3, to the respective source and drain of the PFET switch 451.

[0113] It will be observed that the NFET transistors T2, T4 are biased “off’ regardless of the voltage level of the second control signal 455. However, when the PFET switch 451 is off, its gate voltage is high, which causes the second control signal 455 to assume a low level equal to Vbias_p. When the second control signal 455 has its low voltage state, the gate-to-source voltage, Vgs, of the NFET transistors T2, T4 is equal to zero, which makes these transistors sensitive to downward voltage swings applied at their drains (i.e., they can start to conduct current when there is such a downward deviation in voltage). This enables the NFET transistors T2, T4 to tie the DC bias level at the source and drain of the transistor switch 451 to, in this embodiment, Vbias_p when the PFET switch 451 is turned off.

[0114] Further aspects of some but not necessarily all inventive embodiments are now described with reference to Figure 5, which is a schematic diagram of an exemplary generic embodiment, such as might be used in, to cite an example and without limitation, a radio communication device 500. Here, a switch circuit has a transistor switch 501 of a first type selected from an NFET and a PFET, wherein the transistor switch has a source, a drain, and a gate, wherein the gate of the transistor switch is connected to a first control signal 503 having at least a first voltage state for turning the transistor switch on and a second voltage state for turning the transistor switch off. For example, when the transistor switch 501 is an NFET type, then a high voltage state (e.g., Vdd) will turn it on, whereas when the transistor switch 501 is a PFET type, then a low voltage state (e.g., Vss) will turn it on).

[0115] The switch circuit also has a first MOS transistor 505 of the first type (i.e., the same as the type of the transistor switch 501). The first MOS transistor 505 comprises a first non-gate terminal 507 (i.e., a terminal that can be considered either a source or a drain) connected to receive a second control signal 509, wherein the second control signal 509 has at least a first voltage state that is inversely related to the first voltage state of the first control signal and a second voltage state that is inversely related to the second voltage state of the first control signal.

[0116] The first MOS transistor 505 also has a gate terminal 511 and a second non-gate terminal 513 (i.e., the other one of source or drain, different from the first non-gate terminal 507). The gate terminal 511 is connected to a voltage source that supplies a DC bias voltage. The second non-gate terminal 513 is connected to a first terminal 515 (e.g., the source) of the transistor switch 501 or to a second terminal 516 (e.g., the drain) of the transistor switch 501. The two alternative types of connections are illustrated in Figure 5 by means of dashed lines.

[0117] The switch circuit also has a second MOS transistor 517 of a second type that is complementary to the first type. The second MOS transistor 517 comprises a first non-gate terminal 519 connected to receive the second control signal 509. The second MOS transistor 517 also has a gate terminal 521 and a second non-gate terminal 523. The gate terminal 521 is connected to the voltage source that supplies the DC bias voltage. The second non-gate terminal 523 is connected to the first terminal 515 of the transistor switch 501.

[0118] The switch circuit is configured such that, when the first type is the NFET, then the DC bias voltage is less than or equal to the first voltage state of the first control signal 503 (i.e., the “turn-on” voltage) and greater than the second voltage state (i.e., “turn-off’ voltage of the transistor switch 501) of the first control signal 503. And when the first type is the PFET, then the DC bias voltage is greater than or equal to the first voltage state of the first control signal and less than the second voltage state of the first control signal.

[0119] Further aspects of at least some inventive embodiments will now be described with reference to Figure 6 which, in one respect, is a flowchart of actions performed by circuitry that operates a transistor switch of a first type selected from an NFET and a PFET, wherein the transistor switch has a source, a drain, and a gate, and wherein the gate of the transistor switch is reconnected to a first control signal having at least a first voltage state for turning the transistor switch on and a second voltage state for turning the transistor switch off. In other respects, the blocks depicted in Figure 6 can also be considered to represent means 600 (e.g., hardwired or programmable circuitry or other processing means) for carrying out the described actions.

[0120] As shown in the figure, operating the transistor switch includes being responsive to a current state of the first control signal (decision block 601). When the first control signal has the first voltage state (i.e., when the transistor switch is “On”), a first MOS transistor of the first type is turned on, and while the first MOS transistor is turned on, it supplies a first DC bias voltage to a first terminal of the transistor switch (step 603), wherein the first terminal of the transistor switch is one of the source of the transistor switch and the drain of the transistor switch.

[0121] When the first control signal has the second voltage state (i.e., when the transistor switch is “Off’), the first MOS transistor is turned off, and while the first MOS transistor is turned off, it is used to supply a second DC bias voltage to the first terminal of the transistor switch (step 605).

[0122] Further when the first control signal has the second voltage state, a second MOS transistor of a second type that is complementary to the first type is used to maintain the second DC bias voltage at the first terminal of the transistor switch in response to the first control signal having the second voltage state (step 607). Maintaining the second DC bias voltage at the first terminal of the transistor switch comprises supplying the second DC bias voltage to a gate of the second MOS transistor and to a source of the second MOS transistor and using a drain of the second MOS transistor to sense a deviation in voltage at the first terminal of the transistor switch and turning on the second MOS transistor in response to the deviation. The type of deviation in voltage at the drain of the second MOS transistor that triggers a response by the second MOS transistor is dependent on what type of MOS transistor it is. In particular, the deviation is either: a positive deviation in voltage relative to the second DC bias voltage when the second type is a PFET; or a negative deviation in voltage relative to the second DC bias voltage when the second type is an NFET.

[0123] In an optional aspect of some inventive embodiments, when the first control signal has the second voltage state, a first MOS transistor of the first type that is the same as that of the transistor switch is used to support maintenance of the second DC bias voltage at the first terminal of the transistor switch in response to the first control signal having the second voltage state (step 609). Maintaining the second DC bias voltage at the first terminal of the transistor switch comprises supplying the second DC bias voltage to a gate of the first MOS transistor and to a source of the first MOS transistor and using a drain of the first MOS transistor to sense a deviation in voltage at the first terminal of the transistor switch and turning on the first MOS transistor in response to the deviation. The type of deviation in voltage at the drain of the first MOS transistor that triggers a response by the first MOS transistor is dependent on what type of MOS transistor it is. In particular, the deviation is either: a negative deviation in voltage relative to the second DC bias voltage when the first type is an NFET; or a positive deviation in voltage relative to the second DC bias voltage when the first type is a PFET.

[0124] The behavior of an exemplary embodiment that employs at least some aspects of the invention is illustrated by the dashed curves in the graph of Figure 7, which shows the drain and source voltages (VD and Vs, respectively) of a transistor switch in a capacitor circuit of an LC tank when it is in its “off’ (i.e., when the capacitance of the capacitor circuit is switched out of the capacitor bank). As was mentioned earlier, the solid line curves, such as the curve 701, relate to conventional circuitry that fails to maintain a fixed DC bias at the drain and source of the transistor switch. Consequently, it can be seen that each resulting (solid line) curve has a minimum value in a region near 0.7V, so that the higher the amplitude of the AC signal across the LC tank, the higher the maximum value of VD and Vs (e.g., approximately 1.56V for the curve 701). But notably, not only is the peak value of each solid-line curve higher for a given AC signal, the DC operating point 703 becomes higher with larger signals.

[0125] By contrast, as shown by the dashed lines in Figure 7, embodiments in accordance with the invention maintain an off-state DC operating point 705 that is essentially the same off-state DC bias of VD and Vs regardless of the amplitude of the applied AC voltage in the LC tank. Consequently, peak values of the voltages VD and Vs remain much lower in inventive embodiments than peak values for comparable AC voltages applied in conventional technology. Compare, for example, the peak of the solid line curve 701 (conventional technology) with the dashed line curve 707 (derived from a model of an exemplary embodiment in which the voltage, vbias, was set to VDD).

[0126] Various embodiments constructed in accordance with inventive aspects provide a number of advantages over conventional technology. One of these is that, by maintaining the second MOS transistor (e.g., PFET when the transistor switch is an NFET) in a persistently “off’ biased state, the leakage is much smaller, and the resistance much higher, than for the first MOS transistor (in this example, an NFET). But at the same time, the second MOS transistor will open and pull down any DC voltage that is sensed as deviating higher than the gate voltage. This provides a better level of control of voltage across the transistor switch, and therefore enables SOA issues to be avoided.

[0127] Another benefit of inventive embodiments is that it does not change the on-state performance of the transistor switch. Thus, there is no tradeoff that needs to be made in this respect.

[0128] Yet another advantage of inventive embodiments is the simplicity of the circuit design, which makes it easy to set the off-state DC operating levels of the transistor switch’s source and drain by deciding on values for Vdd and for the bias voltage to be applied to the gates of the transistors in the transistor pairs.

[0129] The invention has been described with reference to particular embodiments. However, it will be readily apparent to those skilled in the art that it is possible to embody the invention in specific forms other than those of the embodiment described above.

[0130] For example, and assuming for the moment a circuit involving an NFET switch, the gate voltage at the first and second MOS transistors does not need to be VDD as shown in some exemplary embodiments. It can instead be set at a lower level (call it “Vbias2”). But in such embodiments, the source voltage of the first and second MOS transistors then needs to toggle between 0 and Vbias2. This is easily achieved by, for example, letting the inverter driving the source control voltage have Vbias2 as the local supply voltage.

[0131] Thus, the described embodiments are merely illustrative and should not be considered restrictive in any way. The scope of the invention is further illustrated by the appended claims, rather than only by the preceding description, and all variations and equivalents which fall within the range of the claims are intended to be embraced therein.

Claims

CLAIMS:

1. A switch circuit comprising: a transistor switch (305, 353, 401, 451, 501) of a first type selected from an N-channel Field Effect Transistor, NFET, and a P-channel Field Effect Transistor, PFET, wherein the transistor switch (305, 353, 401, 451, 501) has a source (311, 355, 515), a drain (309, 359, 516), and a gate (503), wherein the gate (503) of the transistor switch (305, 353, 401, 451, 501) is connected to a first control signal (307, 403, 453, 503) having at least a first voltage state for turning the transistor switch (305, 353, 401, 451, 501) on and a second voltage state for turning the transistor switch (305, 353, 401, 451, 501) off; a first MOS transistor (Tl, T3, 505) of the first type, wherein the first MOS transistor (Tl, T3, 505) comprises: a first non-gate terminal (507) connected to receive a second control signal (405, 455, 509), wherein the second control signal (405, 455, 509) has at least a first voltage state that is inversely related to the first voltage state of the first control signal (307, 403, 453, 503) and a second voltage state that is inversely related to the second voltage state of the first control signal (307, 403, 453, 503); a gate terminal (511) connected to a voltage source that supplies a DC bias voltage; and a second non-gate terminal (513) connected to a first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) that is one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501); and a second MOS transistor (T2, T4, 517) of a second type that is complementary to the first type, wherein the second MOS transistor (T2, T4, 517) comprises: a first non-gate terminal (519) connected to receive the second control signal (405, 455, 509); a gate terminal (521) connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal (523) connected to the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501), wherein:when the first type is the NFET, then the DC bias voltage is less than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and greater than the second voltage state of the first control signal (307, 403, 453, 503); and when the first type is the PFET, then the DC bias voltage is greater than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and less than the second voltage state of the first control signal (307, 403, 453, 503).

2. The switch circuit of claim 1, comprising: a first capacitor having one terminal connected to the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501).

3. The switch circuit of any one of the previous claims, wherein: a second terminal of the transistor switch (305, 353, 401, 451, 501) is an other one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501), different from the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501); and the second terminal of the transistor switch (305, 353, 401, 451, 501) is connected to a reference voltage.

4. The switch circuit of claim 1 or claim 2, wherein a second terminal of the transistor switch (305, 353, 401, 451, 501) is an other one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501), different from the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501), and wherein the switch circuit comprises: a third MOS transistor of the first type, wherein the third MOS transistor comprises: a first non-gate terminal connected to receive the second control signal (405, 455, 509); a gate terminal connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal connected to the second terminal of the transistor switch (305, 353, 401, 451, 501); and a fourth MOS transistor of the second type, wherein the fourth MOS transistor comprises:a first non-gate terminal connected to receive the second control signal (405, 455, 509); a gate terminal connected to the voltage source that supplies the DC bias voltage; and a second non-gate terminal connected to the second terminal of the transistor switch (305, 353, 401, 451, 501).

5. The switch circuit of any one of the previous claims, wherein the second voltage state of the second control signal (405, 455, 509) is equal to the DC bias voltage.

6. A capacitor bank, comprising: a plurality of capacitor circuits connected in parallel, wherein at least one of the capacitor circuits comprises a capacitor having a terminal connected to the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) of the switch circuit according to any one of the previous claims.

7. An Inductor-Capacitor (LC) tank circuit, comprising: the capacitor bank of claim 6; and at least one inductor connected in parallel with the capacitor bank.

8. An oscillator circuit, comprising: the LC tank circuit of claim 7, wherein the LC tank circuit comprises first and second connection points; and a pair of cross-coupled transistors, wherein each of the cross-coupled transistors has an output terminal connected to a respective one of the first and second connection points of the tank circuit.

9. A radio communication device, comprising the oscillator circuit of claim 8.

10. The radio communication device of claim 9, wherein the radio communication device is one of: a base station transceiver in a mobile communications system; and a user equipment for use in the mobile communications system.

11. A method of operating a transistor switch (305, 353, 401, 451, 501) of a first type selected from an N-channel Field Effect Transistor, NFET, and a P-channel Field Effect Transistor, PFET, wherein the transistor switch (305, 353, 401, 451, 501) has a source (311, 355, 515), a drain (309, 359, 516), and a gate (503), wherein the gate (503) of the transistor switch (305, 353, 401, 451, 501) is connected to a first control signal (307, 403, 453, 503) having at least a first voltage state for turning the transistor switch (305, 353, 401, 451, 501) on and a second voltage state for turning the transistor switch (305, 353, 401, 451, 501) off, wherein the method comprises: turning on a first MOS transistor (Tl, T3, 505) of the first type in response to (601) the first control signal (307, 403, 453, 503) having the first voltage state, and while the first MOS transistor (Tl, T3, 505) is turned on, using (603) the first MOS transistor (Tl, T3, 505) of the first type to supply a first DC bias voltage to a first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) in response to the first control signal (307, 403, 453, 503) having the first voltage state, wherein the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) is one of the source (311, 355, 515) of the transistor switch (305, 353, 401, 451, 501) and the drain (309, 359, 516) of the transistor switch (305, 353, 401, 451, 501); turning off the first MOS transistor (Tl, T3, 505) in response to (601) the first control signal (307, 403, 453, 503) having the second voltage state and while the first MOS transistor (Tl, T3, 505) is turned off, using (605) the first MOS transistor (Tl, T3, 505) to supply a second DC bias voltage to the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501); using (607) a second MOS transistor (T2, T4, 517) of a second type that is complementary to the first type to maintain the second DC bias voltage at the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) in response to (601) the first control signal (307, 403, 453, 503) having the second voltage state, wherein using (607) the second MOS transistor (T2, T4, 517) to maintain the second DC bias voltage at the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) comprises: supplying the second DC bias voltage to a gate (521) of the second MOS transistor (T2, T4, 517) and to a source (519) of the second MOS transistor (T2, T4, 517); and using a drain (523) of the second MOS transistor (T2, T4, 517) to sense a deviation in voltage at the first terminal (309, 311, 355, 515, 516) of the transistor switch (305,353, 401, 451, 501) and turning on the second MOS transistor (T2, T4, 517) in response to the deviation, wherein the deviation in voltage at the drain (523) of the second MOS transistor (T2, T4, 517) is one of: a positive deviation in voltage relative to the second DC bias voltage when the second type is a PFET; and a negative deviation in voltage relative to the second DC bias voltage when the second type is an NFET.

12. The method of claim 11, wherein: when the first type is the NFET, then the second DC bias voltage is less than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and greater than the second voltage state of the first control signal (307, 403, 453, 503); and when the first type is the PFET, then the second DC bias voltage is greater than or equal to the first voltage state of the first control signal (307, 403, 453, 503) and less than the second voltage state of the first control signal (307, 403, 453, 503).

13. The method of any one of claims 11 and 12, comprising: supplying the second DC bias voltage to a gate (511) of the first MOS transistor (Tl, T3, 505).

14. The method of any one of claims 11 through 13, wherein using (605) the first MOS transistor (Tl, T3, 505) to supply the second DC bias voltage to the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) comprises: supplying the second DC bias voltage to a source (507) of the first MOS transistor (Tl, T3, 505); and using (609) a drain (513) of the first MOS transistor (Tl, T3, 505) to sense a deviation in voltage at the first terminal (309, 311, 355, 515, 516) of the transistor switch (305, 353, 401, 451, 501) and turning on the first MOS transistor (Tl, T3, 505) in response to the deviation, wherein the deviation in voltage at the drain (513) of the first MOS transistor (Tl, T3, 505) is one of: a negative deviation in voltage relative to the second DC bias voltage when the first type is an NFET; and a positive deviation in voltage relative to the second DC bias voltage when the first type is a PFET.

15. The method of any one of claims 11 through 14, comprising: generating a second control signal (405, 455, 509) having at least a first voltage state that is inversely related to the first voltage state of the first control signal (307, 403, 453, 503) and a second voltage state that is inversely related to the second voltage state of the first control signal (307, 403, 453, 503); and using the first voltage state of the second control signal (405, 455, 509) as a supply source of the first DC bias voltage; and using the second voltage state of the second control signal (405, 455, 509) as a supply source of the second DC bias voltage.

16. The method of any one of claims 11 through 15, comprising: causing a gate-to- source voltage of the second MOS transistor (T2, T4, 517) to be zero in response to the first control signal (307, 403, 453, 503) having the second voltage state.

Images