Performance evaluation and structural optimization methods for high-power semiconductor laser chip, and performance evaluation system for high-power semiconductor laser chip

Abstract

Performance evaluation and structural optimization methods for a high-power semiconductor laser chip, and a performance evaluation system for a high-power semiconductor laser chip. The performance evaluation method for a high-power semiconductor laser chip comprises: providing a window on an N-side electrode of a chip to be tested (step 1); keeping the chip in an operating state (step 2); allowing a quantum well active region of the chip to generate spontaneous emission, so that the spontaneous emission is imaged outside the chip (step 3); acquiring, by means of a spectrograph, a spectrum of the spontaneous emission outside the chip and obtaining a two-dimensional distribution of a quantum well temperature of the chip in the operating state; and acquiring, by means of a CCD camera, an image of the spontaneous emission imaging outside the chip and obtaining a two-dimensional distribution of charge carriers in the quantum well of the chip in the operating state (step 4). According to the performance evaluation and structural optimization methods for a high-power semiconductor laser chip, the distributions of the temperature and the charge carrier concentration in the quantum well of the chip to be tested in the operating state in which the resolution is freely adjusted can be obtained. Operations of the methods are convenient, and implementation is simple and easy, thereby efficiently improving the accuracy of an evaluation result.

Description

Method for evaluating performance and optimizing structure of high-power semiconductor laser chip, and performance evaluation system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application No. 202410534321.3, filed on April 30, 2024, and entitled "Method for evaluating performance and optimizing structure of high-power semiconductor laser chip", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor lasers, and in particular to a method for evaluating performance and optimizing structure of high-power semiconductor laser chip, and a performance evaluation system. BACKGROUND

[0004] The development direction of high-power semiconductor laser chip is higher power conversion efficiency, higher output optical power, and higher brightness. As a highly nonlinear system of mutual coupling of photons, carriers, phonons, etc., it is very important to obtain the spatial distribution of carriers and temperature in the active region of the laser chip operating state, to evaluate the performance of the laser, and to carry out targeted structural optimization.

[0005] At present, increasing the width of the light-emitting region of the laser chip, extending the resonant length of the laser chip, and preparing a wide waveguide and long cavity semiconductor laser chip are the main means to improve the optical power. The physical size of the slow axis (lateral direction) of the high-power wide-area long-cavity semiconductor laser is much larger than the typical operating wavelength (0.8 to 2.0 μm). Under large current operation, due to the combined effect of carrier and thermal lateral diffusion, it tends to multi-mode emission in the lateral direction, thereby affecting the power efficiency and greatly reducing the lateral beam quality; due to the extreme asymmetry of the coating film, the carrier concentration and temperature are unevenly distributed along the anti-reflection film to the reflection film in the cavity length (longitudinal direction), especially under large current operation away from the threshold, the uneven distribution of carriers and temperature gradually increases, and the performance of the semiconductor laser chip degrades, and the optical output power decreases. These effects limit the further application of high-power wide-area long-cavity semiconductor lasers. Therefore, it is very important to optimize the structure of high-power wide-area long-cavity semiconductor laser chips, to further improve the output optical power, power conversion efficiency, and brightness, to obtain the temperature distribution in the active region under real operating conditions, and to obtain the carrier distribution.

[0006] Currently, there are some methods for evaluating temperature distribution and carrier distribution, including reflection method for inferring temperature by measuring cavity surface reflectivity, thermal radiation method for inferring temperature by mid-infrared imaging, and carrier concentration inference method by side spontaneous radiation. However, these methods have problems such as insufficient resolution of the test system, difficulty in obtaining two-dimensional distribution of physical quantities in the active region, and cumbersome test system. SUMMARY

[0007] To solve one or more of the above problems, the present application proposes a high-power semiconductor laser chip performance evaluation and structure optimization method and a performance evaluation system.

[0008] According to one aspect of the present application, a high-power semiconductor laser chip performance evaluation method is provided, comprising:

[0009] A window is arranged on the N-face electrode of the to-be-tested chip;

[0010] The to-be-tested chip is kept in a working state, and the quantum well active region of the to-be-tested chip generates spontaneous radiation;

[0011] The spontaneous radiation is imaged outside the to-be-tested chip by a first lens arranged in the radiation direction of the spontaneous radiation;

[0012] The spectrum of the spontaneous radiation is obtained outside the to-be-tested chip by a spectrometer, and a two-dimensional distribution of the quantum well temperature of the to-be-tested chip in the working state is obtained;

[0013] An image of the spontaneous radiation is obtained outside the to-be-tested chip by a CCD camera, and a two-dimensional distribution of the carriers in the quantum well of the to-be-tested chip in the working state is obtained.

[0014] According to a second aspect of the present application, a high-power semiconductor laser chip structure optimization method is provided, comprising:

[0015] The carrier distribution of the to-be-tested chip and the optical field distribution of the to-be-tested chip are obtained, and the longitudinal segmentation number of the N-face electrode of the current to-be-tested chip is recorded as W;

[0016] The optical field distribution of the to-be-tested chip is normalized to obtain a normalized optical field intensity, denoted as P(z);

[0017] The carrier distribution of the to-be-tested chip is normalized to obtain a normalized carrier intensity, denoted as N(z);

[0018] The mismatch degree δ is calculated according to the normalized carrier intensity N(z) and the normalized optical field intensity P(z), and the expression of the mismatch degree δ is as follows:

[0019] In the formula, z represents the normalized longitudinal position,

[0020] According to the current mismatch degree δ, it is judged whether the to-be-tested chip needs to be optimized. If the to-be-tested chip needs to be optimized, the number of segments of the N-face electrode of the to-be-tested chip is increased, W is set to W+1, and the gold wire arrangement on each segment of the N-face electrode is changed, so that the number of gold wires on each segment of the N-face electrode is proportional to the normalized light field intensity on each segment;

[0021] The above steps are repeatedly performed until it is judged according to the mismatch degree δ that the to-be-tested chip does not need to be optimized, and the optimization is completed.

[0022] The method for obtaining the carrier distribution of the to-be-tested chip is any one of the above high-power semiconductor laser chip performance evaluation methods.

[0023] According to a third aspect of the present application, a high-power semiconductor laser chip performance evaluation system is provided, which is applied to any one of the above high-power semiconductor laser chip performance evaluation methods, and comprises:

[0024] A constant temperature device is used to keep the temperature of the to-be-tested chip, so that the to-be-tested chip can work at a predetermined temperature.

[0025] A lens device comprises a first lens, a beam splitter, a second lens and a third lens. The first lens is arranged on the radiation path of the spontaneous radiation of the to-be-tested chip. The beam splitter is arranged on the exit direction of the first lens. The beam splitter is used to divide the exit light of the first lens into two beams. The second lens and the third lens are arranged on the two exit directions of the beam splitter, respectively.

[0026] A spectrometer comprises a signal acquisition element. The signal acquisition element of the spectrometer is arranged on the exit direction of the second lens.

[0027] A CCD camera is arranged on the exit direction of the third lens.

[0028] A two-dimensional displacement device is arranged on the lens device, the signal acquisition element of the spectrometer and the CCD camera. The two-dimensional displacement device can drive the lens device, the signal acquisition element of the spectrometer and the CCD camera to move. The relative position of the first lens and the to-be-tested chip is changed without changing the vertical distance between the first lens and the exit surface of the spontaneous radiation of the to-be-tested chip.

[0029] The high-power semiconductor laser chip performance evaluation and structure optimization method disclosed in the application can image the quantum well of the to-be-tested chip to the outside of the to-be-tested chip by setting a window in the N-face electrode area of the to-be-tested chip and through lens imaging, and then obtain the temperature and carrier concentration distribution of the to-be-tested chip under the working state. On the premise of not affecting the performance of the chip, the distribution of the temperature and carrier concentration in the quantum well of the to-be-tested chip under the working state with freely adjustable resolution can be obtained. The method is convenient, simple and easy to operate, reduces the inference process in the evaluation process, and the evaluation result is more accurate. At the same time, according to the concentration distribution test result of the carriers, the mismatch between the longitudinal carriers and the light field distribution is eliminated by increasing the N-face electrode segmentation and changing the N-face electrode gold wire arrangement, so as to improve the performance of the to-be-tested chip. BRIEF DESCRIPTION OF DRAWINGS

[0030] Fig. 1 is a flowchart of the high-power semiconductor laser chip performance evaluation method provided by an embodiment of the application.

[0031] Fig. 2 is a partial schematic view of the cross section of the to-be-tested chip in the light emitting direction in the high-power semiconductor laser chip performance evaluation method provided by an embodiment of the application.

[0032] Fig. 3 is a structural schematic view of the high-power semiconductor laser chip performance evaluation system provided by an embodiment of the application.

[0033] Fig. 4 is a schematic view of the cross section of the N-face electrode along the cavity length direction in the high-power semiconductor laser chip performance evaluation method provided by an embodiment of the application.

[0034] Fig. 5 is the gold wire arrangement of a conventional high-power semiconductor laser chip.

[0035] Fig. 6 is a schematic view of the longitudinal carrier and light field distribution of a conventional high-power semiconductor laser chip.

[0036] Fig. 7 is the gold wire arrangement of the high-power semiconductor laser chip optimized by the high-power semiconductor laser chip structure optimization method provided by an embodiment of the application.

[0037] Fig. 8 is a schematic view of the longitudinal carrier and light field distribution of the high-power semiconductor laser chip optimized by the high-power semiconductor laser chip structure optimization method provided by an embodiment of the application. DETAILED DESCRIPTION

[0038] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are part of the embodiments of the present application, rather than all the embodiments, and are only used to explain the present application, and are not used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0039] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "inner", "outer", "two ends", "two sides", "bottom", "top" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the elements referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "superior", "inferior", "primary", "secondary" and the like are only for descriptive purposes and can simply be used to more clearly distinguish different components, and cannot be understood as indicating or implying relative importance.

[0040] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be a fixed connection, or it can be a detachable connection, or it can be an integral connection, or it can be a mechanical connection, or it can be an electrical connection, or it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0041] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0042] Embodiment 1:

[0043] With reference to the accompanying drawings 1, the present application provides a high-power semiconductor laser chip performance evaluation method, comprising the following steps:

[0044] Step 1: Set a window on the N-face electrode of the chip to be tested;

[0045] Step 2: Keep the chip to be tested in a working state;

[0046] Step 3: Image the quantum well active region spontaneous radiation of the chip to be tested on the outside of the chip to be tested;

[0047] Step 4: obtaining the two-dimensional distribution of the quantum well temperature and the two-dimensional distribution of the carrier in the quantum well of the chip under test in the working state according to the spectrum of the spontaneous radiation and the image of the spontaneous radiation imaging.

[0048] Specifically, referring to FIG. 2 of the specification, a partial schematic view of the cross section of the chip under test in the light emitting direction is shown. The structure shown in the figure includes an N-face electrode 101, a substrate 102 and a quantum well 103.

[0049] This embodiment takes the chip under test with a GaAs base, a front cavity reflectivity of 1.5%, a back cavity reflectivity of 99%, a cavity length of 5.0 mm and an injection region width of 90 μm as an example to illustrate the method for evaluating the performance of the high-power semiconductor laser chip.

[0050] In the optional embodiment, the window provided on the N-face electrode of the chip under test in step 1 can be provided by the lift-off process. Thus, the spontaneous radiation of the quantum well of the chip under test in the working state can be imaged through the substrate by providing the window on the N-face electrode of the chip under test.

[0051] The window provided on the N-face electrode of the chip under test should meet the condition of not significantly affecting the electrical injection. In the optional embodiment, the size of the window needs to meet the following formula:

[0052] l≤0.01*L; wherein, l represents the size of the window in the cavity length direction, and L represents the cavity length.

[0053] Referring to FIG. 3 of the specification, a structural schematic view of a high-power semiconductor laser chip performance evaluation system is shown. In order to facilitate the description, a vertex of the exit surface of the spontaneous radiation of the chip under test 10 is taken as the origin O, the exit direction of the spontaneous radiation is taken as the z-axis, and the light emitting direction of the chip under test 10 is taken as the x-axis to establish a three-dimensional coordinate system.

[0054] The chip under test 10 is placed on the constant temperature device 38, which is used to maintain the temperature of the chip under test 10 so that the chip under test 10 can work at a predetermined temperature. The first lens 31, the beam splitter 32, the second lens 33, the third lens 34, the signal acquisition element 35 of the spectrometer 36 and the CCD camera 37 are all provided on the two-dimensional displacement device (not shown in the figure). The relative positions of the first lens 31, the beam splitter 32, the second lens 33, the third lens 34, the signal acquisition element 35 of the spectrometer 36 and the CCD camera 37 are fixed, and they can move in the XY plane under the driving of the two-dimensional displacement device.

[0055] When z=0, the cross-sectional view of the xy plane, i.e. the cross-sectional view of the N-face electrode along the cavity length direction can refer to the schematic diagram shown in FIG. 4 of the specification, the N-face electrode 101 includes a window 1011 and a metal region 1012. Taking a cavity length of 5.0 mm as an example, the window size can be 50 μm*400 μm, and the window position is uniformly distributed along the cavity length direction with a period of 500 μm.

[0056] In step 2, the to-be-tested chip is kept in a working state, so that the quantum well active region of the to-be-tested chip generates spontaneous radiation.

[0057] In step 3, the spontaneous radiation is imaged outside the to-be-tested chip by a first lens arranged in the direction of the spontaneous radiation, which can specifically include:

[0058] A beam splitter is arranged in the exit direction of the first lens, a second lens and a third lens are arranged in the two exit directions of the beam splitter respectively, a signal collection element of a spectrometer is arranged in the exit direction of the second lens, and a CCD camera is arranged in the exit direction of the third lens.

[0059] Therefore, by arranging the beam splitter, the second lens and the third lens, the spontaneous radiation generated by the quantum well active region of the to-be-tested chip in the working state can be simultaneously imaged to the signal collection element of the spectrometer and the CCD camera through the first lens, the beam splitter, the second lens and the third lens, which facilitates the calculation of the quantum well temperature distribution and the carrier distribution.

[0060] In step 4, according to the spectrum of the spontaneous radiation and the image of the spontaneous radiation imaging, the two-dimensional distribution of the quantum well temperature and the two-dimensional distribution of the carriers in the quantum well of the to-be-tested chip in the working state are obtained, which specifically includes:

[0061] The spectrum of the spontaneous radiation is obtained by the spectrometer outside the to-be-tested chip, and the two-dimensional distribution of the quantum well temperature of the to-be-tested chip in the working state is obtained.

[0062] The image of the spontaneous radiation imaging is obtained by the CCD camera outside the to-be-tested chip, and the two-dimensional distribution of the carriers in the quantum well of the to-be-tested chip in the working state is obtained.

[0063] The two-dimensional distribution of the quantum well temperature of the to-be-tested chip in the working state specifically includes the following steps:

[0064] The spontaneous emission spectrum peak wavelength λ0 of the to-be-tested chip working at the injection current I and the temperature T0 can be directly given by the spectrometer.

[0065] Under the condition of meeting the predetermined duty ratio and pulse requirements, the temperature of the to-be-tested chip is changed, so that the temperature of the to-be-tested chip is T1, T2,..., Tn-1 and Tn respectively, where n is a natural number not less than 2, the values of T1, T2,..., Tn-1 and Tn are different, and the unit is ℃. Under the temperature conditions of T1, T2,..., Tn-1 and Tn respectively, the relative positions of the signal acquisition element, the first lens, the beam splitter and the second lens of the spectrometer are kept unchanged, the horizontal distance between the signal acquisition element of the spectrometer and the to-be-tested chip is changed, that is, the vertical distance between the first lens and the spontaneous emission exit surface of the to-be-tested chip is kept unchanged, so that the relative position of the first lens and the to-be-tested chip changes, and the spectrometer data is recorded along the spatial position in turn, and the spontaneous emission spectrum peak wavelengths λ(T1), λ(T2),..., λ(Tn-1) and λ(Tn) of the to-be-tested chip working at different temperatures in the window are obtained respectively.

[0066] According to the least square linear regression, the spontaneous emission spectrum temperature drift coefficient δλ is calculated.

[0067] According to the spontaneous emission spectrum temperature drift coefficient δλ and the spectrum peak wavelength λ0, the two-dimensional distribution of the quantum well temperature of the to-be-tested chip working at the injection current I and the temperature T0 is obtained.

[0068] Specifically, the signal acquisition element of the spectrometer can be an optical fiber, so that the optical fiber collects the light generated by the spontaneous emission of the to-be-tested chip, and the spectral distribution of the spontaneous emission light is obtained after inputting the spectrometer.

[0069] The temperature T0 and the injection current I are pre-set parameters, the injection current I is loaded on the to-be-tested chip by an external power supply, the temperature T0 is realized by a constant temperature device, and the temperature T0 can be randomly valued on the premise of ensuring the normal working of the to-be-tested chip. The constant temperature device can be any device in the prior art that automatically opens or closes to keep the to-be-tested chip in a pre-set temperature range. The constant temperature device can include a sensitive element and a converter, the sensitive element is used to measure the change of temperature, and the converter is used to heat or cool the to-be-tested element according to the change of temperature.

[0070] The predetermined duty cycle and pulse requirement can be a low duty cycle and a short pulse, where the low duty cycle refers to one thousandth of the duty cycle, and the short pulse refers to a pulse width less than 1 μs.

[0071] Among the temperatures T1, T2, T3, …, Tn-1 and Tn, n can be a natural number greater than 2. When n = 8, the temperatures T1, T2, T3, …, T7 and T8 can be an arithmetic sequence with an initial temperature of 5°C and a step of 5°C, can be an arithmetic sequence with an initial temperature of 4°C and a step of 7°C, or can be 8 temperature points randomly selected under the premise of ensuring the normal operation of the chip to be measured. Thus, through multiple measurements, the calculation of the spontaneous emission spectrum temperature drift coefficient δλ is more accurate, and the error that can exist in a single measurement is reduced.

[0072] By changing the temperature T of the heat sink n times, n groups of corresponding spontaneous emission spectrum peak wavelengths λ(Tn) are obtained, and the n groups of observation data are substituted into the least squares formula to obtain the spectrum temperature drift coefficient δλ.

[0073] The calculation formula of the spectrum temperature drift coefficient δλ is as follows:

[0074] In the formula, λi represents the spontaneous emission spectrum peak wavelength obtained in the ith measurement, Ti represents the temperature corresponding to the ith measurement, and i is a natural number not less than 1; represents the average value of the spectrum peak wavelength in n measurements, represents the average value of the temperature in n measurements.

[0075] In an optional embodiment, according to the spontaneous emission spectrum temperature drift coefficient δλ and the spectrum peak wavelength λ(T0) corresponding to the temperature T0, the two-dimensional distribution of the quantum well temperature of the chip to be measured working at the injection current I and the temperature T0 is obtained, which specifically includes: C = δin * (λ - λ(T0)) + T0

[0076] In the formula, Tc represents the quantum well temperature, λ is the current spectrum peak wavelength obtained from the spectrometer, and λ(T0) represents the spectrum peak wavelength λ(T0) obtained at the temperature T0.

[0077] In an optional embodiment, the image of the spontaneous emission imaging is obtained by a CCD camera outside the chip to be measured, and the two-dimensional distribution of the carriers in the quantum well of the chip to be measured in the working state can include:

[0078] Keeping the injection current I of the to-be-tested chip unchanged, keeping the temperature T of the to-be-tested chip unchanged, keeping the relative positions of the signal acquisition element, the CCD camera, the first lens, the beam splitter, the second lens and the third lens of the spectrometer unchanged, keeping the vertical distance between the first lens and the spontaneous radiation exit surface of the to-be-tested chip unchanged, and acquiring the CCD image of the spontaneous radiation imaging;

[0079] The gray value of the CCD image is acquired, and the square root of the gray value is calculated to obtain the two-dimensional distribution of the carriers in the quantum well of the to-be-tested chip working under the condition that the injection current is I and the temperature is T.

[0080] Since the field of view range of the CCD camera is large enough, the CCD image is acquired at any position once the CCD camera is moved along the two-dimensional displacement device, and the CCD image of the spontaneous radiation imaging is obtained. Since the intensity of the spontaneous radiation is proportional to the square of the carrier concentration, the carrier distribution can be represented by the square root of the gray value of the CCD image, and the testing method is simple, the calculation is simple, and the calculation result is more accurate.

[0081] The high-power semiconductor laser chip performance evaluation method disclosed in the application can set a window in the N-face electrode area of the to-be-tested chip, and image the quantum well of the to-be-tested chip to the outside of the to-be-tested chip through the lens, so as to obtain the temperature and carrier concentration distribution of the to-be-tested chip under the working state. Without affecting the performance of the chip, the distribution of the temperature and carrier concentration in the quantum well of the to-be-tested chip under the working state with adjustable resolution can be obtained, which is convenient, simple and easy to operate, reduces the inference process in the evaluation process, and the evaluation result is more accurate. The evaluation of the temperature distribution and the carrier concentration distribution is the basis for evaluating the lateral thermal lens effect and the longitudinal temperature non-uniformity effect, and inhibiting the lateral carrier accumulation, the lateral carrier leakage and the longitudinal carrier non-uniformity effect, which is beneficial to the subsequent evaluation and optimization of the to-be-tested chip.

[0082] Embodiment 2:

[0083] The application embodiment further provides a high-power semiconductor laser chip structure optimization method, which comprises the following steps:

[0084] The carrier distribution of the to-be-tested chip and the optical field distribution of the to-be-tested chip are acquired, and the longitudinal segmentation number of the N-face electrode of the current to-be-tested chip is recorded as W;

[0085] The optical field distribution of the to-be-tested chip is normalized to obtain a normalized optical field intensity, denoted as P(z);

[0086] The carrier distribution of the to-be-tested chip is normalized to obtain a normalized carrier intensity, denoted as N(z);

[0087] The mismatch degree δ is calculated according to the normalized carrier intensity N(z) and the longitudinal normalized distribution P(z) of the normalized light field intensity, and the expression of the mismatch degree δ is as follows:

[0088] In the formula, z represents a normalized longitudinal position,

[0089] Whether the to-be-tested chip needs to be optimized is determined according to the current mismatch degree δ, if the to-be-tested chip needs to be optimized, the segmentation number of the N-face electrode of the to-be-tested chip is increased, W is set as W+1, and the gold wire arrangement on each segment of the N-face electrode is changed, so that the number of gold wires on each segment of the N-face electrode is proportional to the normalized light field intensity on each segment;

[0090] The foregoing steps are repeatedly executed until it is determined that the to-be-tested chip does not need to be optimized according to the mismatch degree δ, and the optimization is completed.

[0091] The method for obtaining the carrier distribution of the to-be-tested chip is any one of the high-power semiconductor laser chip performance evaluation methods in the embodiments.

[0092] Therefore, by increasing the segmentation of the N-face electrode and changing the injection current injected into each segment, the adjustment precision is increased, and the gold wire arrangement mode can be changed more finely; by changing the number of gold wires on each segment, the change of the gold wire arrangement mode is realized, so that the carrier distribution is adjusted, the difference between the carrier distribution and the light field distribution is reduced, the light field distribution and the carrier distribution are made to be approximately coincident, and the optimization effect is achieved.

[0093] The initial value of the segmentation number W of the N-face electrode can be 1 or a natural number greater than 1.

[0094] For the to-be-tested chip with a given cavity surface reflectivity, the light field distribution is fixed.

[0095] Specifically, whether the to-be-tested chip needs to be optimized is determined according to the current mismatch degree δ, including:

[0096] The value of the following formula is calculated:

[0097] In the formula, δ represents the mismatch degree, and P(z) represents the normalized light field intensity P(z).

[0098] Whether the calculated value is less than a predetermined value is determined, if the calculated value is less than the predetermined value, the to-be-tested chip does not need to be optimized, and if the calculated value is not less than the predetermined value, the to-be-tested chip needs to be optimized.

[0099] In an optional embodiment, the predetermined value can be 5%. Therefore, when the calculated value is less than 5%, it can be considered that the light field distribution and the carrier distribution are approximately coincident, and the predetermined value can be set according to the needs in actual production.

[0100] The number of segments of the N-face electrode of the to-be-tested chip can be increased by using a metal stripping method.

[0101] Specifically, FIG. 5 of the accompanying drawings shows the gold wire arrangement of a conventional high-power semiconductor laser chip, and FIG. 6 of the accompanying drawings shows a longitudinal carrier and optical field distribution diagram of the conventional high-power semiconductor laser chip. For the conventional high-power semiconductor laser chip, the number of segments of the N-face electrode is 1, the gold wire arrangement of the N-face electrode is uniform, the number of gold wires per unit length is equal, the carriers are uniformly injected along the cavity length direction, and however, the optical field is extremely asymmetrically distributed along the cavity length direction due to the asymmetry of the front and rear cavity surface coating. Therefore, the carrier distribution and the optical field distribution are severely mismatched, resulting in a decrease in device efficiency, an increase in heat generation, and an increase in temperature.

[0102] FIG. 7 of the accompanying drawings shows the gold wire arrangement of the high-power semiconductor laser chip optimized by the high-power semiconductor laser chip structure optimization method provided in the embodiment, and FIG. 8 of the accompanying drawings shows a longitudinal carrier and optical field distribution diagram of the high-power semiconductor laser chip optimized by the high-power semiconductor laser chip structure optimization method provided in the embodiment. In FIG. 6 of the accompanying drawings and FIG. 8 of the accompanying drawings, the meanings of the curves represented by the arrows are shown. As can be seen from FIG. 7 of the accompanying drawings, the greater the normalized optical field intensity, the greater the number of gold wires in the corresponding segment.

[0103] The same features of the embodiment 1 are not repeated here.

[0104] The high-power semiconductor laser chip structure optimization method provided in the embodiments of the present application judges the degree of coincidence of the carrier distribution and the optical field distribution by introducing the mismatch degree, and gradually increases the number of segments of the N-face electrode and changes the number of gold wires on each segment to reduce the difference between the optical field distribution and the carrier distribution. On the one hand, the chip efficiency is effectively improved, and the chip heat generation is reduced. On the other hand, since the more the number of segments, the more the process steps, by increasing the number of segments, changing the gold wire distribution, calculating the mismatch degree, and then increasing the number of segments and changing the gold wire distribution, the cycle steps are performed. While the mismatch degree meets the preset condition, unnecessary process steps are avoided, the optimization effect is ensured, and the optimization efficiency is improved.

[0105] Embodiment 3:

[0106] Referring to FIG. 3 of the accompanying drawings, the embodiments of the present application further provide a high-power semiconductor laser chip performance evaluation system, which is applied to any of the high-power semiconductor laser chip performance evaluation methods in embodiment 1 and comprises:

[0107] The constant temperature device 38 is used to keep the temperature of the to-be-tested chip, so that the to-be-tested chip can work at a predetermined temperature.

[0108] The lens device comprises a first lens 31, a beam splitter 32, a second lens 33 and a third lens 34, the first lens 31 is arranged on a radiation path of the spontaneous radiation of the chip 10 to be measured, the beam splitter 32 is arranged in the outgoing direction of the first lens 31, the beam splitter 32 is used to divide the outgoing light of the first lens 31 into two beams, and the second lens 33 and the third lens 34 are arranged in the outgoing directions of the two beams of the beam splitter 32 respectively;

[0109] A spectrometer 36, the signal acquisition element 35 of the spectrometer 36 is arranged in the outgoing direction of the second lens 33;

[0110] A CCD camera 37, the CCD camera 37 is arranged in the outgoing direction of the third lens 34;

[0111] A two-dimensional displacement device, the lens device, the signal acquisition element 35 of the spectrometer 36 and the CCD camera 37 are all arranged on the two-dimensional displacement device, the two-dimensional displacement device can drive the lens device, the signal acquisition element 35 of the spectrometer 36 and the CCD camera 37 to move, and the relative position of the first lens 31 and the chip 10 to be measured is changed without changing the vertical distance between the first lens 31 and the outgoing surface of the spontaneous radiation of the chip 10 to be measured.

[0112] In an optional embodiment, the second lens 33 and the third lens 34 adopt lenses with the same parameters, and the distance between the signal acquisition element 35 of the spectrometer and the second lens 33 is equal to the distance between the CCD camera 37 and the third lens 34.

[0113] The same features of the embodiment 1 are not described here.

[0114] The high-power semiconductor laser chip performance evaluation method disclosed in the application can image the quantum well of the chip to be measured to the outside of the chip to be measured through the window arranged on the N-face electrode area of the chip to be measured and the lens imaging, and then obtain the temperature and carrier concentration distribution of the chip to be measured under the working state, so that the temperature and carrier concentration distribution in the quantum well of the chip to be measured under the working state with adjustable resolution can be obtained without affecting the performance of the chip, the operation is convenient, simple and easy to implement, the inference process in the evaluation process is reduced, and the evaluation result is more accurate.

[0115] The above is only an optional embodiment of the application, and it should be pointed out that those skilled in the art can make some improvements and refinements without departing from the principles of the application, and these improvements and refinements should also be regarded as the protection scope of the application.

Claims

1. A method for evaluating performance of a high-power semiconductor laser chip, comprising: setting a window on an N-face electrode of a to-be-tested chip; keeping the to-be-tested chip in a working state, and causing a quantum well active region of the to-be-tested chip to generate spontaneous radiation; causing the spontaneous radiation to be imaged outside the to-be-tested chip by a first lens that is pre-set in a radiation direction of the spontaneous radiation; obtaining a spectrum of the spontaneous radiation outside the to-be-tested chip by a spectrometer, to obtain a two-dimensional distribution of quantum well temperature of the to-be-tested chip in the working state; obtaining an image of the spontaneous radiation imaged outside the to-be-tested chip by a CCD camera, to obtain a two-dimensional distribution of carriers in the quantum well of the to-be-tested chip in the working state; wherein the causing the spontaneous radiation to be imaged outside the to-be-tested chip by the first lens that is pre-set in the radiation path of the spontaneous radiation comprises: setting a beam splitter in an exit direction of the first lens, setting a second lens and a third lens along two exit directions of the beam splitter respectively, setting a signal acquisition element of the spectrometer in an exit direction of the second lens, and setting the CCD camera in an exit direction of the third lens; and wherein the obtaining the spectrum of the spontaneous radiation outside the to-be-tested chip by the spectrometer to obtain the two-dimensional distribution of quantum well temperature of the to-be-tested chip in the working state comprises: keeping the injected current I of the to-be-tested chip unchanged, keeping the temperature T0 of the to-be-tested chip unchanged, keeping the relative positions of the signal acquisition element of the spectrometer, the CCD camera, the first lens, the beam splitter, the second lens and the third lens unchanged, keeping a vertical distance between the first lens and an exit surface of the spontaneous radiation of the to-be-tested chip unchanged, changing the relative position of the first lens and the to-be-tested chip, sequentially recording spectrometer data, and obtaining a peak wavelength λ(T0) of the spectrum; changing the temperature of the to-be-tested chip to be T1, T2, …, Tn-1 and Tn under conditions that satisfy predetermined duty ratios and pulse requirements, wherein n is a natural number not less than 2, the values of T1, T2, …, Tn-1 and Tn are different from each other, and the unit is ℃; keeping the relative positions of the signal acquisition element of the spectrometer, the first lens, the beam splitter and the second lens unchanged, changing a horizontal distance between the signal acquisition element of the spectrometer and the to-be-tested chip, sequentially recording spectrometer data, and obtaining peak wavelengths λ(T1), λ(T2), …, λ(Tn-1) and λ(Tn) of the spectrum; calculating a spontaneous radiation spectrum temperature drift coefficient δλ according to a least square linear regression; and obtaining the two-dimensional distribution of quantum well temperature of the to-be-tested chip working at the injected current I and the temperature T0 according to the spontaneous radiation spectrum temperature drift coefficient δλ and the peak wavelength λ(T0) of the spectrum. The window is set on the N-face electrode of the to-be-tested chip by a lift-off process. 3.The method according to claim 1, wherein a size of the window satisfies the following formula: l / L≤0.

1. 4.The method according to claim 1, wherein the window has a size that satisfies the following formula: l / L≤0.

1. ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The method of claim 1, wherein the high power semiconductor laser chip performance evaluation method is characterized by, ​ ​ ​ l≤0.01*L； ​ ​ An image of the spontaneous radiation imaging is acquired by a CCD camera outside the to-be-tested chip to obtain a two-dimensional distribution of the carriers in the quantum well of the to-be-tested chip in the working state, including: The CCD image of the spontaneous radiation imaging is acquired while keeping the injection current I of the to-be-tested chip unchanged, keeping the temperature T0 of the to-be-tested chip unchanged, keeping the relative positions of the signal acquisition element, the CCD camera, the first lens, the beam splitter, the second lens and the third lens of the spectrometer unchanged, keeping the vertical distance between the first lens and the emission surface of the spontaneous radiation of the to-be-tested chip unchanged; The gray value of the CCD image is acquired, and a square root calculation is performed on the gray value to obtain the two-dimensional distribution of the carriers in the quantum well of the to-be-tested chip working at the injection current I and the temperature T0.

5. A method for high power semiconductor laser chip structure optimization, characterized by, Including: The carrier distribution of the to-be-tested chip and the light field distribution of the to-be-tested chip are acquired, and the longitudinal segmentation number of the N-face electrode of the current to-be-tested chip is recorded as W; The light field distribution of the to-be-tested chip is normalized to obtain a normalized light field intensity, denoted as P(z); The carrier distribution of the to-be-tested chip is normalized to obtain a normalized carrier intensity, denoted as N(z); The mismatch δ is calculated from the normalized carrier intensity N(z) and the normalized optical field intensity P(z), the expression for which is as follows: In the formula, z represents a normalized longitudinal position, According to the current mismatch degree δ, it is judged whether the to-be-tested chip needs to be optimized, if the to-be-tested chip needs to be optimized, the segmentation number of the N-face electrode of the to-be-tested chip is increased, so that W=W+1, and the gold wire arrangement on each segment of the N-face electrode is changed, so that the number of gold wires on each segment of the N-face electrode is proportional to the normalized light field intensity on each segment; The above steps are repeatedly executed until it is judged according to the mismatch degree δ that the to-be-tested chip does not need to be optimized, and the optimization is ended; The method for acquiring the carrier distribution of the to-be-tested chip is the high-power semiconductor laser chip performance evaluation method in any one of claims 1-4.

6. The high power semiconductor laser chip structure optimization method of claim 5, wherein, According to the current mismatch degree δ, it is judged whether the to-be-tested chip needs to be optimized, including: Calculate the value of the following formula: In the formula, δ represents the mismatch degree, and P(z) represents the normalized light field intensity P(z); It is judged whether the calculated value is less than a predetermined value, if the calculated value is less than the predetermined value, the to-be-tested chip does not need to be optimized, if the calculated value is not less than the predetermined value, the to-be-tested chip needs to be optimized.

7. A high power semiconductor laser chip performance evaluation system, characterized in that, Applied to the high-power semiconductor laser chip performance evaluation method in any one of claims 1-4, including: A constant temperature device is used to keep the temperature of the to-be-tested chip, so that the to-be-tested chip can work at a predetermined temperature; A lens device includes a first lens, a beam splitter, a second lens and a third lens, the first lens is arranged on the radiation path of the spontaneous radiation of the to-be-tested chip, the beam splitter is arranged in the emission direction of the first lens, the beam splitter is used to divide the emission light of the first lens into two beams, the second lens and the third lens are arranged in the two emission directions of the beam splitter respectively; A spectrometer includes a signal acquisition element, the signal acquisition element of the spectrometer is arranged in the emission direction of the second lens; A CCD camera is arranged in the emission direction of the third lens; A two-dimensional displacement device, the lens device, the signal collection element of the spectrometer and the CCD camera are arranged on the two-dimensional displacement device, and the two-dimensional displacement device can drive the lens device, the signal collection element of the spectrometer and the CCD camera to move, so as to change the relative position of the first lens and the chip to be measured without changing the vertical distance between the first lens and the emission surface of the spontaneous radiation of the chip to be measured.

8. The high power semiconductor laser chip performance evaluation system of claim 7, wherein, The second lens and the third lens are lenses with the same parameters, and the distance between the signal collection element of the spectrometer and the second lens is equal to the distance between the CCD camera and the third lens.

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